Quelle  sm8150.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
 * Copyright (c) 2019, Linaro Limited
 */

#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,dispcc-sm8150.h>
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
#include <dt-bindings/clock/qcom,videocc-sm8150.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm8150.h>
#include <dt-bindings/clock/qcom,sm8150-camcc.h>
#include <dt-bindings/thermal/thermal.h>

/ {
 interrupt-parent = <&intc>;

 #address-cells = <2>;
 #size-cells = <2>;

 chosen { };

 clocks {
  xo_board: xo-board {
   compatible = "fixed-clock";
   #clock-cells = <0>;
   clock-frequency = <38400000>;
   clock-output-names = "xo_board";
  };

  sleep_clk: sleep-clk {
   compatible = "fixed-clock";
   #clock-cells = <0>;
   clock-frequency = <32764>;
   clock-output-names = "sleep_clk";
  };
 };

 cpus {
  #address-cells = <2>;
  #size-cells = <0>;

  cpu0: cpu@0 {
   device_type = "cpu";
   compatible = "qcom,kryo485";
   reg = <0x0 0x0>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   capacity-dmips-mhz = <488>;
   dynamic-power-coefficient = <232>;
   next-level-cache = <&l2_0>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   power-domains = <&cpu_pd0>;
   power-domain-names = "psci";
   #cooling-cells = <2>;
   l2_0: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
    l3_0: l3-cache {
     compatible = "cache";
     cache-level = <3>;
     cache-unified;
    };
   };
  };

  cpu1: cpu@100 {
   device_type = "cpu";
   compatible = "qcom,kryo485";
   reg = <0x0 0x100>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   capacity-dmips-mhz = <488>;
   dynamic-power-coefficient = <232>;
   next-level-cache = <&l2_100>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   power-domains = <&cpu_pd1>;
   power-domain-names = "psci";
   #cooling-cells = <2>;
   l2_100: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu2: cpu@200 {
   device_type = "cpu";
   compatible = "qcom,kryo485";
   reg = <0x0 0x200>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   capacity-dmips-mhz = <488>;
   dynamic-power-coefficient = <232>;
   next-level-cache = <&l2_200>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   power-domains = <&cpu_pd2>;
   power-domain-names = "psci";
   #cooling-cells = <2>;
   l2_200: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu3: cpu@300 {
   device_type = "cpu";
   compatible = "qcom,kryo485";
   reg = <0x0 0x300>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   capacity-dmips-mhz = <488>;
   dynamic-power-coefficient = <232>;
   next-level-cache = <&l2_300>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   power-domains = <&cpu_pd3>;
   power-domain-names = "psci";
   #cooling-cells = <2>;
   l2_300: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu4: cpu@400 {
   device_type = "cpu";
   compatible = "qcom,kryo485";
   reg = <0x0 0x400>;
   clocks = <&cpufreq_hw 1>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <369>;
   next-level-cache = <&l2_400>;
   qcom,freq-domain = <&cpufreq_hw 1>;
   operating-points-v2 = <&cpu4_opp_table>;
   interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   power-domains = <&cpu_pd4>;
   power-domain-names = "psci";
   #cooling-cells = <2>;
   l2_400: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu5: cpu@500 {
   device_type = "cpu";
   compatible = "qcom,kryo485";
   reg = <0x0 0x500>;
   clocks = <&cpufreq_hw 1>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <369>;
   next-level-cache = <&l2_500>;
   qcom,freq-domain = <&cpufreq_hw 1>;
   operating-points-v2 = <&cpu4_opp_table>;
   interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   power-domains = <&cpu_pd5>;
   power-domain-names = "psci";
   #cooling-cells = <2>;
   l2_500: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu6: cpu@600 {
   device_type = "cpu";
   compatible = "qcom,kryo485";
   reg = <0x0 0x600>;
   clocks = <&cpufreq_hw 1>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <369>;
   next-level-cache = <&l2_600>;
   qcom,freq-domain = <&cpufreq_hw 1>;
   operating-points-v2 = <&cpu4_opp_table>;
   interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   power-domains = <&cpu_pd6>;
   power-domain-names = "psci";
   #cooling-cells = <2>;
   l2_600: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu7: cpu@700 {
   device_type = "cpu";
   compatible = "qcom,kryo485";
   reg = <0x0 0x700>;
   clocks = <&cpufreq_hw 2>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <421>;
   next-level-cache = <&l2_700>;
   qcom,freq-domain = <&cpufreq_hw 2>;
   operating-points-v2 = <&cpu7_opp_table>;
   interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
     <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
   power-domains = <&cpu_pd7>;
   power-domain-names = "psci";
   #cooling-cells = <2>;
   l2_700: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu-map {
   cluster0 {
    core0 {
     cpu = <&cpu0>;
    };

    core1 {
     cpu = <&cpu1>;
    };

    core2 {
     cpu = <&cpu2>;
    };

    core3 {
     cpu = <&cpu3>;
    };

    core4 {
     cpu = <&cpu4>;
    };

    core5 {
     cpu = <&cpu5>;
    };

    core6 {
     cpu = <&cpu6>;
    };

    core7 {
     cpu = <&cpu7>;
    };
   };
  };

  idle-states {
   entry-method = "psci";

   little_cpu_sleep_0: cpu-sleep-0-0 {
    compatible = "arm,idle-state";
    idle-state-name = "little-rail-power-collapse";
    arm,psci-suspend-param = <0x40000004>;
    entry-latency-us = <355>;
    exit-latency-us = <909>;
    min-residency-us = <3934>;
    local-timer-stop;
   };

   big_cpu_sleep_0: cpu-sleep-1-0 {
    compatible = "arm,idle-state";
    idle-state-name = "big-rail-power-collapse";
    arm,psci-suspend-param = <0x40000004>;
    entry-latency-us = <241>;
    exit-latency-us = <1461>;
    min-residency-us = <4488>;
    local-timer-stop;
   };
  };

  domain-idle-states {
   cluster_sleep_0: cluster-sleep-0 {
    compatible = "domain-idle-state";
    arm,psci-suspend-param = <0x4100c244>;
    entry-latency-us = <3263>;
    exit-latency-us = <6562>;
    min-residency-us = <9987>;
   };
  };
 };

 cpu0_opp_table: opp-table-cpu0 {
  compatible = "operating-points-v2";
  opp-shared;

  cpu0_opp1: opp-300000000 {
   opp-hz = /bits/ 64 <300000000>;
   opp-peak-kBps = <800000 9600000>;
  };

  cpu0_opp2: opp-403200000 {
   opp-hz = /bits/ 64 <403200000>;
   opp-peak-kBps = <800000 9600000>;
  };

  cpu0_opp3: opp-499200000 {
   opp-hz = /bits/ 64 <499200000>;
   opp-peak-kBps = <800000 12902400>;
  };

  cpu0_opp4: opp-576000000 {
   opp-hz = /bits/ 64 <576000000>;
   opp-peak-kBps = <800000 12902400>;
  };

  cpu0_opp5: opp-672000000 {
   opp-hz = /bits/ 64 <672000000>;
   opp-peak-kBps = <800000 15974400>;
  };

  cpu0_opp6: opp-768000000 {
   opp-hz = /bits/ 64 <768000000>;
   opp-peak-kBps = <1804000 19660800>;
  };

  cpu0_opp7: opp-844800000 {
   opp-hz = /bits/ 64 <844800000>;
   opp-peak-kBps = <1804000 19660800>;
  };

  cpu0_opp8: opp-940800000 {
   opp-hz = /bits/ 64 <940800000>;
   opp-peak-kBps = <1804000 22732800>;
  };

  cpu0_opp9: opp-1036800000 {
   opp-hz = /bits/ 64 <1036800000>;
   opp-peak-kBps = <1804000 22732800>;
  };

  cpu0_opp10: opp-1113600000 {
   opp-hz = /bits/ 64 <1113600000>;
   opp-peak-kBps = <2188000 25804800>;
  };

  cpu0_opp11: opp-1209600000 {
   opp-hz = /bits/ 64 <1209600000>;
   opp-peak-kBps = <2188000 31948800>;
  };

  cpu0_opp12: opp-1305600000 {
   opp-hz = /bits/ 64 <1305600000>;
   opp-peak-kBps = <3072000 31948800>;
  };

  cpu0_opp13: opp-1382400000 {
   opp-hz = /bits/ 64 <1382400000>;
   opp-peak-kBps = <3072000 31948800>;
  };

  cpu0_opp14: opp-1478400000 {
   opp-hz = /bits/ 64 <1478400000>;
   opp-peak-kBps = <3072000 31948800>;
  };

  cpu0_opp15: opp-1555200000 {
   opp-hz = /bits/ 64 <1555200000>;
   opp-peak-kBps = <3072000 40550400>;
  };

  cpu0_opp16: opp-1632000000 {
   opp-hz = /bits/ 64 <1632000000>;
   opp-peak-kBps = <3072000 40550400>;
  };

  cpu0_opp17: opp-1708800000 {
   opp-hz = /bits/ 64 <1708800000>;
   opp-peak-kBps = <3072000 43008000>;
  };

  cpu0_opp18: opp-1785600000 {
   opp-hz = /bits/ 64 <1785600000>;
   opp-peak-kBps = <3072000 43008000>;
  };
 };

 cpu4_opp_table: opp-table-cpu4 {
  compatible = "operating-points-v2";
  opp-shared;

  cpu4_opp1: opp-710400000 {
   opp-hz = /bits/ 64 <710400000>;
   opp-peak-kBps = <1804000 15974400>;
  };

  cpu4_opp2: opp-825600000 {
   opp-hz = /bits/ 64 <825600000>;
   opp-peak-kBps = <2188000 19660800>;
  };

  cpu4_opp3: opp-940800000 {
   opp-hz = /bits/ 64 <940800000>;
   opp-peak-kBps = <2188000 22732800>;
  };

  cpu4_opp4: opp-1056000000 {
   opp-hz = /bits/ 64 <1056000000>;
   opp-peak-kBps = <3072000 25804800>;
  };

  cpu4_opp5: opp-1171200000 {
   opp-hz = /bits/ 64 <1171200000>;
   opp-peak-kBps = <3072000 31948800>;
  };

  cpu4_opp6: opp-1286400000 {
   opp-hz = /bits/ 64 <1286400000>;
   opp-peak-kBps = <4068000 31948800>;
  };

  cpu4_opp7: opp-1401600000 {
   opp-hz = /bits/ 64 <1401600000>;
   opp-peak-kBps = <4068000 31948800>;
  };

  cpu4_opp8: opp-1497600000 {
   opp-hz = /bits/ 64 <1497600000>;
   opp-peak-kBps = <4068000 40550400>;
  };

  cpu4_opp9: opp-1612800000 {
   opp-hz = /bits/ 64 <1612800000>;
   opp-peak-kBps = <4068000 40550400>;
  };

  cpu4_opp10: opp-1708800000 {
   opp-hz = /bits/ 64 <1708800000>;
   opp-peak-kBps = <4068000 43008000>;
  };

  cpu4_opp11: opp-1804800000 {
   opp-hz = /bits/ 64 <1804800000>;
   opp-peak-kBps = <6220000 43008000>;
  };

  cpu4_opp12: opp-1920000000 {
   opp-hz = /bits/ 64 <1920000000>;
   opp-peak-kBps = <6220000 49152000>;
  };

  cpu4_opp13: opp-2016000000 {
   opp-hz = /bits/ 64 <2016000000>;
   opp-peak-kBps = <7216000 49152000>;
  };

  cpu4_opp14: opp-2131200000 {
   opp-hz = /bits/ 64 <2131200000>;
   opp-peak-kBps = <8368000 49152000>;
  };

  cpu4_opp15: opp-2227200000 {
   opp-hz = /bits/ 64 <2227200000>;
   opp-peak-kBps = <8368000 51609600>;
  };

  cpu4_opp16: opp-2323200000 {
   opp-hz = /bits/ 64 <2323200000>;
   opp-peak-kBps = <8368000 51609600>;
  };

  cpu4_opp17: opp-2419200000 {
   opp-hz = /bits/ 64 <2419200000>;
   opp-peak-kBps = <8368000 51609600>;
  };
 };

 cpu7_opp_table: opp-table-cpu7 {
  compatible = "operating-points-v2";
  opp-shared;

  cpu7_opp1: opp-825600000 {
   opp-hz = /bits/ 64 <825600000>;
   opp-peak-kBps = <2188000 19660800>;
  };

  cpu7_opp2: opp-940800000 {
   opp-hz = /bits/ 64 <940800000>;
   opp-peak-kBps = <2188000 22732800>;
  };

  cpu7_opp3: opp-1056000000 {
   opp-hz = /bits/ 64 <1056000000>;
   opp-peak-kBps = <3072000 25804800>;
  };

  cpu7_opp4: opp-1171200000 {
   opp-hz = /bits/ 64 <1171200000>;
   opp-peak-kBps = <3072000 31948800>;
  };

  cpu7_opp5: opp-1286400000 {
   opp-hz = /bits/ 64 <1286400000>;
   opp-peak-kBps = <4068000 31948800>;
  };

  cpu7_opp6: opp-1401600000 {
   opp-hz = /bits/ 64 <1401600000>;
   opp-peak-kBps = <4068000 31948800>;
  };

  cpu7_opp7: opp-1497600000 {
   opp-hz = /bits/ 64 <1497600000>;
   opp-peak-kBps = <4068000 40550400>;
  };

  cpu7_opp8: opp-1612800000 {
   opp-hz = /bits/ 64 <1612800000>;
   opp-peak-kBps = <4068000 40550400>;
  };

  cpu7_opp9: opp-1708800000 {
   opp-hz = /bits/ 64 <1708800000>;
   opp-peak-kBps = <4068000 43008000>;
  };

  cpu7_opp10: opp-1804800000 {
   opp-hz = /bits/ 64 <1804800000>;
   opp-peak-kBps = <6220000 43008000>;
  };

  cpu7_opp11: opp-1920000000 {
   opp-hz = /bits/ 64 <1920000000>;
   opp-peak-kBps = <6220000 49152000>;
  };

  cpu7_opp12: opp-2016000000 {
   opp-hz = /bits/ 64 <2016000000>;
   opp-peak-kBps = <7216000 49152000>;
  };

  cpu7_opp13: opp-2131200000 {
   opp-hz = /bits/ 64 <2131200000>;
   opp-peak-kBps = <8368000 49152000>;
  };

  cpu7_opp14: opp-2227200000 {
   opp-hz = /bits/ 64 <2227200000>;
   opp-peak-kBps = <8368000 51609600>;
  };

  cpu7_opp15: opp-2323200000 {
   opp-hz = /bits/ 64 <2323200000>;
   opp-peak-kBps = <8368000 51609600>;
  };

  cpu7_opp16: opp-2419200000 {
   opp-hz = /bits/ 64 <2419200000>;
   opp-peak-kBps = <8368000 51609600>;
  };

  cpu7_opp17: opp-2534400000 {
   opp-hz = /bits/ 64 <2534400000>;
   opp-peak-kBps = <8368000 51609600>;
  };

  cpu7_opp18: opp-2649600000 {
   opp-hz = /bits/ 64 <2649600000>;
   opp-peak-kBps = <8368000 51609600>;
  };

  cpu7_opp19: opp-2745600000 {
   opp-hz = /bits/ 64 <2745600000>;
   opp-peak-kBps = <8368000 51609600>;
  };

  cpu7_opp20: opp-2841600000 {
   opp-hz = /bits/ 64 <2841600000>;
   opp-peak-kBps = <8368000 51609600>;
  };
 };

 firmware {
  scm: scm {
   compatible = "qcom,scm-sm8150", "qcom,scm";
   #reset-cells = <1>;
  };
 };

 memory@80000000 {
  device_type = "memory";
  /* We expect the bootloader to fill in the size */
  reg = <0x0 0x80000000 0x0 0x0>;
 };

 pmu {
  compatible = "arm,armv8-pmuv3";
  interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 };

 psci {
  compatible = "arm,psci-1.0";
  method = "smc";

  cpu_pd0: power-domain-cpu0 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0>;
  };

  cpu_pd1: power-domain-cpu1 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0>;
  };

  cpu_pd2: power-domain-cpu2 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0>;
  };

  cpu_pd3: power-domain-cpu3 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0>;
  };

  cpu_pd4: power-domain-cpu4 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0>;
  };

  cpu_pd5: power-domain-cpu5 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0>;
  };

  cpu_pd6: power-domain-cpu6 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0>;
  };

  cpu_pd7: power-domain-cpu7 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0>;
  };

  cluster_pd: power-domain-cpu-cluster0 {
   #power-domain-cells = <0>;
   domain-idle-states = <&cluster_sleep_0>;
  };
 };

 reserved-memory {
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  hyp_mem: memory@85700000 {
   reg = <0x0 0x85700000 0x0 0x600000>;
   no-map;
  };

  xbl_mem: memory@85d00000 {
   reg = <0x0 0x85d00000 0x0 0x140000>;
   no-map;
  };

  aop_mem: memory@85f00000 {
   reg = <0x0 0x85f00000 0x0 0x20000>;
   no-map;
  };

  aop_cmd_db: memory@85f20000 {
   compatible = "qcom,cmd-db";
   reg = <0x0 0x85f20000 0x0 0x20000>;
   no-map;
  };

  smem_mem: memory@86000000 {
   reg = <0x0 0x86000000 0x0 0x200000>;
   no-map;
  };

  tz_mem: memory@86200000 {
   reg = <0x0 0x86200000 0x0 0x3900000>;
   no-map;
  };

  rmtfs_mem: memory@89b00000 {
   compatible = "qcom,rmtfs-mem";
   reg = <0x0 0x89b00000 0x0 0x200000>;
   no-map;

   qcom,client-id = <1>;
   qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
  };

  camera_mem: memory@8b700000 {
   reg = <0x0 0x8b700000 0x0 0x500000>;
   no-map;
  };

  wlan_mem: memory@8bc00000 {
   reg = <0x0 0x8bc00000 0x0 0x180000>;
   no-map;
  };

  npu_mem: memory@8bd80000 {
   reg = <0x0 0x8bd80000 0x0 0x80000>;
   no-map;
  };

  adsp_mem: memory@8be00000 {
   reg = <0x0 0x8be00000 0x0 0x1a00000>;
   no-map;
  };

  mpss_mem: memory@8d800000 {
   reg = <0x0 0x8d800000 0x0 0x9600000>;
   no-map;
  };

  venus_mem: memory@96e00000 {
   reg = <0x0 0x96e00000 0x0 0x500000>;
   no-map;
  };

  slpi_mem: memory@97300000 {
   reg = <0x0 0x97300000 0x0 0x1400000>;
   no-map;
  };

  ipa_fw_mem: memory@98700000 {
   reg = <0x0 0x98700000 0x0 0x10000>;
   no-map;
  };

  ipa_gsi_mem: memory@98710000 {
   reg = <0x0 0x98710000 0x0 0x5000>;
   no-map;
  };

  gpu_mem: memory@98715000 {
   reg = <0x0 0x98715000 0x0 0x2000>;
   no-map;
  };

  spss_mem: memory@98800000 {
   reg = <0x0 0x98800000 0x0 0x100000>;
   no-map;
  };

  cdsp_mem: memory@98900000 {
   reg = <0x0 0x98900000 0x0 0x1400000>;
   no-map;
  };

  qseecom_mem: memory@9e400000 {
   reg = <0x0 0x9e400000 0x0 0x1400000>;
   no-map;
  };
 };

 smem {
  compatible = "qcom,smem";
  memory-region = <&smem_mem>;
  hwlocks = <&tcsr_mutex 3>;
 };

 smp2p-cdsp {
  compatible = "qcom,smp2p";
  qcom,smem = <94>, <432>;

  interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;

  mboxes = <&apss_shared 6>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <5>;

  cdsp_smp2p_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  cdsp_smp2p_in: slave-kernel {
   qcom,entry-name = "slave-kernel";

   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-lpass {
  compatible = "qcom,smp2p";
  qcom,smem = <443>, <429>;

  interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;

  mboxes = <&apss_shared 10>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <2>;

  adsp_smp2p_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  adsp_smp2p_in: slave-kernel {
   qcom,entry-name = "slave-kernel";

   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-mpss {
  compatible = "qcom,smp2p";
  qcom,smem = <435>, <428>;

  interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;

  mboxes = <&apss_shared 14>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <1>;

  modem_smp2p_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  modem_smp2p_in: slave-kernel {
   qcom,entry-name = "slave-kernel";

   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-slpi {
  compatible = "qcom,smp2p";
  qcom,smem = <481>, <430>;

  interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;

  mboxes = <&apss_shared 26>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <3>;

  slpi_smp2p_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  slpi_smp2p_in: slave-kernel {
   qcom,entry-name = "slave-kernel";

   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 soc: soc@0 {
  #address-cells = <2>;
  #size-cells = <2>;
  ranges = <0 0 0 0 0x10 0>;
  dma-ranges = <0 0 0 0 0x10 0>;
  compatible = "simple-bus";

  gcc: clock-controller@100000 {
   compatible = "qcom,gcc-sm8150";
   reg = <0x0 0x00100000 0x0 0x1f0000>;
   #clock-cells = <1>;
   #reset-cells = <1>;
   #power-domain-cells = <1>;
   clock-names = "bi_tcxo",
          "sleep_clk";
   clocks = <&rpmhcc RPMH_CXO_CLK>,
     <&sleep_clk>;
  };

  gpi_dma0: dma-controller@800000 {
   compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
   reg = <0 0x00800000 0 0x60000>;
   interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
   dma-channels = <13>;
   dma-channel-mask = <0xfa>;
   iommus = <&apps_smmu 0x00d6 0x0>;
   #dma-cells = <3>;
   status = "disabled";
  };

  ethernet: ethernet@20000 {
   compatible = "qcom,sm8150-ethqos";
   reg = <0x0 0x00020000 0x0 0x10000>,
         <0x0 0x00036000 0x0 0x100>;
   reg-names = "stmmaceth", "rgmii";
   clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
   clocks = <&gcc GCC_EMAC_AXI_CLK>,
    <&gcc GCC_EMAC_SLV_AHB_CLK>,
    <&gcc GCC_EMAC_PTP_CLK>,
    <&gcc GCC_EMAC_RGMII_CLK>;
   interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "macirq", "eth_lpi";

   power-domains = <&gcc EMAC_GDSC>;
   resets = <&gcc GCC_EMAC_BCR>;

   iommus = <&apps_smmu 0x3c0 0x0>;

   snps,tso;
   rx-fifo-depth = <4096>;
   tx-fifo-depth = <4096>;

   status = "disabled";
  };

  qfprom: efuse@784000 {
   compatible = "qcom,sm8150-qfprom", "qcom,qfprom";
   reg = <0 0x00784000 0 0x8ff>;
   #address-cells = <1>;
   #size-cells = <1>;

   gpu_speed_bin: gpu-speed-bin@133 {
    reg = <0x133 0x1>;
    bits = <5 3>;
   };
  };

  qupv3_id_0: geniqup@8c0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0x0 0x008c0000 0x0 0x6000>;
   clock-names = "m-ahb", "s-ahb";
   clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
     <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
   iommus = <&apps_smmu 0xc3 0x0>;
   #address-cells = <2>;
   #size-cells = <2>;
   ranges;
   status = "disabled";

   i2c0: i2c@880000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00880000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
           <&gpi_dma0 1 0 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c0_default>;
    interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi0: spi@880000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00880000 0 0x4000>;
    reg-names = "se";
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
           <&gpi_dma0 1 0 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi0_default>;
    interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
    spi-max-frequency = <50000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c1: i2c@884000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00884000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
    dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
           <&gpi_dma0 1 1 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c1_default>;
    interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi1: spi@884000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00884000 0 0x4000>;
    reg-names = "se";
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
    dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
           <&gpi_dma0 1 1 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi1_default>;
    interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
    spi-max-frequency = <50000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c2: i2c@888000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00888000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
    dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
           <&gpi_dma0 1 2 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c2_default>;
    interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi2: spi@888000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00888000 0 0x4000>;
    reg-names = "se";
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
    dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
           <&gpi_dma0 1 2 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi2_default>;
    interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
    spi-max-frequency = <50000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c3: i2c@88c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x0088c000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
    dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
           <&gpi_dma0 1 3 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c3_default>;
    interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi3: spi@88c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x0088c000 0 0x4000>;
    reg-names = "se";
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
    dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
           <&gpi_dma0 1 3 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi3_default>;
    interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
    spi-max-frequency = <50000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c4: i2c@890000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00890000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
    dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
           <&gpi_dma0 1 4 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c4_default>;
    interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi4: spi@890000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00890000 0 0x4000>;
    reg-names = "se";
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
    dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
           <&gpi_dma0 1 4 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi4_default>;
    interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
    spi-max-frequency = <50000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c5: i2c@894000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00894000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
    dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
           <&gpi_dma0 1 5 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c5_default>;
    interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi5: spi@894000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00894000 0 0x4000>;
    reg-names = "se";
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
    dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
           <&gpi_dma0 1 5 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi5_default>;
    interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
    spi-max-frequency = <50000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c6: i2c@898000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00898000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
    dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
           <&gpi_dma0 1 6 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c6_default>;
    interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi6: spi@898000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00898000 0 0x4000>;
    reg-names = "se";
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
    dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
           <&gpi_dma0 1 6 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi6_default>;
    interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
    spi-max-frequency = <50000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c7: i2c@89c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x0089c000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
    dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
           <&gpi_dma0 1 7 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c7_default>;
    interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi7: spi@89c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x0089c000 0 0x4000>;
    reg-names = "se";
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
    dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
           <&gpi_dma0 1 7 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi7_default>;
    interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
    spi-max-frequency = <50000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };
  };

  gpi_dma1: dma-controller@a00000 {
   compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
   reg = <0 0x00a00000 0 0x60000>;
   interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
   dma-channels = <13>;
   dma-channel-mask = <0xfa>;
   iommus = <&apps_smmu 0x0616 0x0>;
   #dma-cells = <3>;
   status = "disabled";
  };

  qupv3_id_1: geniqup@ac0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0x0 0x00ac0000 0x0 0x6000>;
   clock-names = "m-ahb", "s-ahb";
   clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
     <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
   iommus = <&apps_smmu 0x603 0x0>;
   #address-cells = <2>;
   #size-cells = <2>;
   ranges;
   status = "disabled";

   i2c8: i2c@a80000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a80000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
    dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
           <&gpi_dma1 1 0 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c8_default>;
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi8: spi@a80000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a80000 0 0x4000>;
    reg-names = "se";
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
    dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
           <&gpi_dma1 1 0 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi8_default>;
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    spi-max-frequency = <50000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c9: i2c@a84000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a84000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
    dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
           <&gpi_dma1 1 1 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c9_default>;
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi9: spi@a84000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a84000 0 0x4000>;
    reg-names = "se";
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
    dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
           <&gpi_dma1 1 1 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi9_default>;
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    spi-max-frequency = <50000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart9: serial@a84000 {
    compatible = "qcom,geni-uart";
    reg = <0x0 0x00a84000 0x0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
    clock-names = "se";
    pinctrl-0 = <&qup_uart9_default>;
    pinctrl-names = "default";
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    status = "disabled";
   };

   i2c10: i2c@a88000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a88000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
    dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
           <&gpi_dma1 1 2 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c10_default>;
    interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi10: spi@a88000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a88000 0 0x4000>;
    reg-names = "se";
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
    dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
           <&gpi_dma1 1 2 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi10_default>;
    interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
    spi-max-frequency = <50000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c11: i2c@a8c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a8c000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
    dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
           <&gpi_dma1 1 3 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c11_default>;
    interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi11: spi@a8c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a8c000 0 0x4000>;
    reg-names = "se";
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
    dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
           <&gpi_dma1 1 3 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi11_default>;
    interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
    spi-max-frequency = <50000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   uart2: serial@a90000 {
    compatible = "qcom,geni-debug-uart";
    reg = <0x0 0x00a90000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
    interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
    status = "disabled";
   };

   i2c12: i2c@a90000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a90000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
    dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
           <&gpi_dma1 1 4 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c12_default>;
    interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi12: spi@a90000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a90000 0 0x4000>;
    reg-names = "se";
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
    dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
           <&gpi_dma1 1 4 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi12_default>;
    interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
    spi-max-frequency = <50000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c16: i2c@94000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00094000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
    dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
           <&gpi_dma2 1 5 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c16_default>;
    interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi16: spi@a94000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a94000 0 0x4000>;
    reg-names = "se";
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
    dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
           <&gpi_dma2 1 5 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi16_default>;
    interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
    spi-max-frequency = <50000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };
  };

  gpi_dma2: dma-controller@c00000 {
   compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
   reg = <0 0x00c00000 0 0x60000>;
   interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
   dma-channels = <13>;
   dma-channel-mask = <0xfa>;
   iommus = <&apps_smmu 0x07b6 0x0>;
   #dma-cells = <3>;
   status = "disabled";
  };

  qupv3_id_2: geniqup@cc0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0x0 0x00cc0000 0x0 0x6000>;

   clock-names = "m-ahb", "s-ahb";
   clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
     <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
   iommus = <&apps_smmu 0x7a3 0x0>;
   #address-cells = <2>;
   #size-cells = <2>;
   ranges;
   status = "disabled";

   i2c17: i2c@c80000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00c80000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
    dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
           <&gpi_dma2 1 0 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c17_default>;
    interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi17: spi@c80000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00c80000 0 0x4000>;
    reg-names = "se";
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
    dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
           <&gpi_dma2 1 0 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi17_default>;
    interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
    spi-max-frequency = <50000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c18: i2c@c84000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00c84000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
    dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
           <&gpi_dma2 1 1 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c18_default>;
    interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi18: spi@c84000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00c84000 0 0x4000>;
    reg-names = "se";
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
    dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
           <&gpi_dma2 1 1 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi18_default>;
    interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
    spi-max-frequency = <50000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c19: i2c@c88000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00c88000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
    dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
           <&gpi_dma2 1 2 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c19_default>;
    interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi19: spi@c88000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00c88000 0 0x4000>;
    reg-names = "se";
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
    dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
           <&gpi_dma2 1 2 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi19_default>;
    interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
    spi-max-frequency = <50000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c13: i2c@c8c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00c8c000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
    dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
           <&gpi_dma2 1 3 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c13_default>;
    interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi13: spi@c8c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00c8c000 0 0x4000>;
    reg-names = "se";
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
    dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
           <&gpi_dma2 1 3 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi13_default>;
    interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
    spi-max-frequency = <50000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c14: i2c@c90000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00c90000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
    dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
           <&gpi_dma2 1 4 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c14_default>;
    interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi14: spi@c90000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00c90000 0 0x4000>;
    reg-names = "se";
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
    dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
           <&gpi_dma2 1 4 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi14_default>;
    interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
    spi-max-frequency = <50000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   i2c15: i2c@c94000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00c94000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
    dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
           <&gpi_dma2 1 5 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c15_default>;
    interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };

   spi15: spi@c94000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00c94000 0 0x4000>;
    reg-names = "se";
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
    dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
           <&gpi_dma2 1 5 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi15_default>;
    interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
    spi-max-frequency = <50000000>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
   };
  };

  config_noc: interconnect@1500000 {
   compatible = "qcom,sm8150-config-noc";
   reg = <0 0x01500000 0 0x7400>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  system_noc: interconnect@1620000 {
   compatible = "qcom,sm8150-system-noc";
   reg = <0 0x01620000 0 0x19400>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  mc_virt: interconnect@163a000 {
   compatible = "qcom,sm8150-mc-virt";
   reg = <0 0x0163a000 0 0x1000>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  aggre1_noc: interconnect@16e0000 {
   compatible = "qcom,sm8150-aggre1-noc";
   reg = <0 0x016e0000 0 0xd080>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  aggre2_noc: interconnect@1700000 {
   compatible = "qcom,sm8150-aggre2-noc";
   reg = <0 0x01700000 0 0x20000>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  compute_noc: interconnect@1720000 {
   compatible = "qcom,sm8150-compute-noc";
   reg = <0 0x01720000 0 0x7000>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  mmss_noc: interconnect@1740000 {
   compatible = "qcom,sm8150-mmss-noc";
   reg = <0 0x01740000 0 0x1c100>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  system-cache-controller@9200000 {
   compatible = "qcom,sm8150-llcc";
   reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
         <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
         <0 0x09600000 0 0x50000>;
   reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
        "llcc3_base", "llcc_broadcast_base";
   interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
  };

  dma@10a2000 {
   compatible = "qcom,sm8150-dcc", "qcom,dcc";
   reg = <0x0 0x010a2000 0x0 0x1000>,
         <0x0 0x010ad000 0x0 0x3000>;
  };

  pcie0: pcie@1c00000 {
   compatible = "qcom,pcie-sm8150";
   reg = <0 0x01c00000 0 0x3000>,
         <0 0x60000000 0 0xf1d>,
         <0 0x60000f20 0 0xa8>,
         <0 0x60001000 0 0x1000>,
         <0 0x60100000 0 0x100000>;
   reg-names = "parf", "dbi", "elbi", "atu", "config";
   device_type = "pci";
   linux,pci-domain = <0>;
   bus-range = <0x00 0xff>;
   num-lanes = <1>;

   #address-cells = <3>;
   #size-cells = <2>;

   ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
     <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;

   interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "msi0",
       "msi1",
       "msi2",
       "msi3",
       "msi4",
       "msi5",
       "msi6",
       "msi7",
       "global";
   #interrupt-cells = <1>;
   interrupt-map-mask = <0 0 0 0x7>;
   interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
     <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
     <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
     <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

   clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
     <&gcc GCC_PCIE_0_AUX_CLK>,
     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
   clock-names = "pipe",
          "aux",
          "cfg",
          "bus_master",
          "bus_slave",
          "slave_q2a";

   iommu-map = <0x0   &apps_smmu 0x1d80 0x1>,
        <0x100 &apps_smmu 0x1d81 0x1>;

   resets = <&gcc GCC_PCIE_0_BCR>;
   reset-names = "pci";

   power-domains = <&gcc PCIE_0_GDSC>;

   phys = <&pcie0_phy>;
   phy-names = "pciephy";

   perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
   wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;

   pinctrl-names = "default";
   pinctrl-0 = <&pcie0_default_state>;

   status = "disabled";

   pcie@0 {
    device_type = "pci";
    reg = <0x0 0x0 0x0 0x0 0x0>;
    bus-range = <0x01 0xff>;

    #address-cells = <3>;
    #size-cells = <2>;
    ranges;
   };
  };

  pcie0_phy: phy@1c06000 {
   compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
   reg = <0 0x01c06000 0 0x1000>;
   clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_0_CLKREF_CLK>,
     <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
     <&gcc GCC_PCIE_0_PIPE_CLK>;
   clock-names = "aux",
          "cfg_ahb",
          "ref",
          "refgen",
          "pipe";

   clock-output-names = "pcie_0_pipe_clk";
   #clock-cells = <0>;

   #phy-cells = <0>;

   resets = <&gcc GCC_PCIE_0_PHY_BCR>;
   reset-names = "phy";

   assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
   assigned-clock-rates = <100000000>;

   status = "disabled";
  };

  pcie1: pcie@1c08000 {
   compatible = "qcom,pcie-sm8150";
   reg = <0 0x01c08000 0 0x3000>,
         <0 0x40000000 0 0xf1d>,
         <0 0x40000f20 0 0xa8>,
         <0 0x40001000 0 0x1000>,
         <0 0x40100000 0 0x100000>;
   reg-names = "parf", "dbi", "elbi", "atu", "config";
   device_type = "pci";
   linux,pci-domain = <1>;
   bus-range = <0x00 0xff>;
   num-lanes = <2>;

   #address-cells = <3>;
   #size-cells = <2>;

   ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
     <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;

   interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "msi0",
       "msi1",
       "msi2",
       "msi3",
       "msi4",
       "msi5",
       "msi6",
       "msi7",
       "global";
   #interrupt-cells = <1>;
   interrupt-map-mask = <0 0 0 0x7>;
   interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
     <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
     <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
     <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

   clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
     <&gcc GCC_PCIE_1_AUX_CLK>,
     <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
     <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
     <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
   clock-names = "pipe",
          "aux",
          "cfg",
          "bus_master",
          "bus_slave",
          "slave_q2a";

   assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
   assigned-clock-rates = <19200000>;

   iommu-map = <0x0   &apps_smmu 0x1e00 0x1>,
        <0x100 &apps_smmu 0x1e01 0x1>;

   resets = <&gcc GCC_PCIE_1_BCR>;
   reset-names = "pci";

   power-domains = <&gcc PCIE_1_GDSC>;

   phys = <&pcie1_phy>;
   phy-names = "pciephy";

   perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
   enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;

   pinctrl-names = "default";
   pinctrl-0 = <&pcie1_default_state>;

   status = "disabled";

   pcie@0 {
    device_type = "pci";
    reg = <0x0 0x0 0x0 0x0 0x0>;
    bus-range = <0x01 0xff>;

    #address-cells = <3>;
    #size-cells = <2>;
    ranges;
   };
  };

  pcie1_phy: phy@1c0e000 {
   compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
   reg = <0 0x01c0e000 0 0x1000>;
   clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
     <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_1_CLKREF_CLK>,
     <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
     <&gcc GCC_PCIE_1_PIPE_CLK>;
   clock-names = "aux",
          "cfg_ahb",
          "ref",
          "refgen",
          "pipe";

   clock-output-names = "pcie_1_pipe_clk";
   #clock-cells = <0>;

   #phy-cells = <0>;

   resets = <&gcc GCC_PCIE_1_PHY_BCR>;
   reset-names = "phy";

   assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
   assigned-clock-rates = <100000000>;

   status = "disabled";
  };

  ufs_mem_hc: ufshc@1d84000 {
   compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
         "jedec,ufs-2.0";
   reg = <0 0x01d84000 0 0x2500>,
         <0 0x01d90000 0 0x8000>;
   reg-names = "std", "ice";
   interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
   phys = <&ufs_mem_phy>;
   phy-names = "ufsphy";
   lanes-per-direction = <2>;
   #reset-cells = <1>;
   resets = <&gcc GCC_UFS_PHY_BCR>;
   reset-names = "rst";

   iommus = <&apps_smmu 0x300 0>;

   clock-names =
    "core_clk",
    "bus_aggr_clk",
    "iface_clk",
    "core_clk_unipro",
    "ref_clk",
    "tx_lane0_sync_clk",
    "rx_lane0_sync_clk",
    "rx_lane1_sync_clk",
    "ice_core_clk";
   clocks =
    <&gcc GCC_UFS_PHY_AXI_CLK>,
    <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
    <&gcc GCC_UFS_PHY_AHB_CLK>,
    <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
    <&rpmhcc RPMH_CXO_CLK>,
    <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
    <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
    <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
    <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
   freq-table-hz =
    <37500000 300000000>,
    <0 0>,
    <0 0>,
    <37500000 300000000>,
    <0 0>,
    <0 0>,
    <0 0>,
    <0 0>,
    <0 300000000>;

   status = "disabled";
  };

  ufs_mem_phy: phy@1d87000 {
   compatible = "qcom,sm8150-qmp-ufs-phy";
   reg = <0 0x01d87000 0 0x1000>;

   clocks = <&rpmhcc RPMH_CXO_CLK>,
     <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
     <&gcc GCC_UFS_MEM_CLKREF_CLK>;
   clock-names = "ref",
          "ref_aux",
          "qref";

   power-domains = <&gcc UFS_PHY_GDSC>;

   resets = <&ufs_mem_hc 0>;
   reset-names = "ufsphy";

   #phy-cells = <0>;

   status = "disabled";
  };

  cryptobam: dma-controller@1dc4000 {
   compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
   reg = <0 0x01dc4000 0 0x24000>;
   interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
   #dma-cells = <1>;
   qcom,ee = <0>;
   qcom,controlled-remotely;
   num-channels = <8>;
   qcom,num-ees = <2>;
   iommus = <&apps_smmu 0x502 0x0641>,
     <&apps_smmu 0x504 0x0011>,
     <&apps_smmu 0x506 0x0011>,
     <&apps_smmu 0x508 0x0011>,
     <&apps_smmu 0x512 0x0000>;
  };

  crypto: crypto@1dfa000 {
   compatible = "qcom,sm8150-qce", "qcom,qce";
   reg = <0 0x01dfa000 0 0x6000>;
   dmas = <&cryptobam 4>, <&cryptobam 5>;
   dma-names = "rx", "tx";
   iommus = <&apps_smmu 0x502 0x0641>,
     <&apps_smmu 0x504 0x0011>,
     <&apps_smmu 0x506 0x0011>,
     <&apps_smmu 0x508 0x0011>,
     <&apps_smmu 0x512 0x0000>;
   interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
   interconnect-names = "memory";
  };

  tcsr_mutex: hwlock@1f40000 {
   compatible = "qcom,tcsr-mutex";
   reg = <0x0 0x01f40000 0x0 0x20000>;
   #hwlock-cells = <1>;
  };

  tcsr_regs_1: syscon@1f60000 {
   compatible = "qcom,sm8150-tcsr", "syscon";
   reg = <0x0 0x01f60000 0x0 0x20000>;
  };

  remoteproc_slpi: remoteproc@2400000 {
   compatible = "qcom,sm8150-slpi-pas";
   reg = <0x0 0x02400000 0x0 0x4040>;

   interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
           <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
           <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
           <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
           <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
   interrupt-names = "wdog", "fatal", "ready",
       "handover", "stop-ack";

   clocks = <&rpmhcc RPMH_CXO_CLK>;
   clock-names = "xo";

   power-domains = <&rpmhpd SM8150_LCX>,
     <&rpmhpd SM8150_LMX>;
   power-domain-names = "lcx", "lmx";

   memory-region = <&slpi_mem>;

   qcom,qmp = <&aoss_qmp>;

   qcom,smem-states = <&slpi_smp2p_out 0>;
   qcom,smem-state-names = "stop";

   status = "disabled";

   glink-edge {
    interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
    label = "dsps";
    qcom,remote-pid = <3>;
    mboxes = <&apss_shared 24>;

    fastrpc {
     compatible = "qcom,fastrpc";
     qcom,glink-channels = "fastrpcglink-apps-dsp";
     label = "sdsp";
     qcom,non-secure-domain;
     #address-cells = <1>;
     #size-cells = <0>;

     compute-cb@1 {
      compatible = "qcom,fastrpc-compute-cb";
      reg = <1>;
      iommus = <&apps_smmu 0x05a1 0x0>;
     };

     compute-cb@2 {
      compatible = "qcom,fastrpc-compute-cb";
      reg = <2>;
      iommus = <&apps_smmu 0x05a2 0x0>;
     };

     compute-cb@3 {
      compatible = "qcom,fastrpc-compute-cb";
      reg = <3>;
      iommus = <&apps_smmu 0x05a3 0x0>;
      /* note: shared-cb = <4> in downstream */
     };
    };
   };
  };

  gpu: gpu@2c00000 {
   compatible = "qcom,adreno-640.1", "qcom,adreno";
   reg = <0 0x02c00000 0 0x40000>;
   reg-names = "kgsl_3d0_reg_memory";

   interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;

   iommus = <&adreno_smmu 0 0x401>;

   operating-points-v2 = <&gpu_opp_table>;

   qcom,gmu = <&gmu>;

   nvmem-cells = <&gpu_speed_bin>;
   nvmem-cell-names = "speed_bin";
   #cooling-cells = <2>;

   status = "disabled";

   zap-shader {
    memory-region = <&gpu_mem>;
   };

   gpu_opp_table: opp-table {
    compatible = "operating-points-v2";

    opp-675000000 {
     opp-hz = /bits/ 64 <675000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
     opp-supported-hw = <0x2>;
    };

    opp-585000000 {
     opp-hz = /bits/ 64 <585000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
     opp-supported-hw = <0x3>;
    };

    opp-499200000 {
     opp-hz = /bits/ 64 <499200000>;
     opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
     opp-supported-hw = <0x3>;
    };

    opp-427000000 {
     opp-hz = /bits/ 64 <427000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
     opp-supported-hw = <0x3>;
    };

    opp-345000000 {
     opp-hz = /bits/ 64 <345000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
     opp-supported-hw = <0x3>;
    };

    opp-257000000 {
     opp-hz = /bits/ 64 <257000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
     opp-supported-hw = <0x3>;
    };
   };
  };

  gmu: gmu@2c6a000 {
   compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";

   reg = <0 0x02c6a000 0 0x30000>,
         <0 0x0b290000 0 0x10000>,
         <0 0x0b490000 0 0x10000>;
   reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";

   interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "hfi", "gmu";

   clocks = <&gpucc GPU_CC_AHB_CLK>,
     <&gpucc GPU_CC_CX_GMU_CLK>,
     <&gpucc GPU_CC_CXO_CLK>,
     <&gcc GCC_DDRSS_GPU_AXI_CLK>,
     <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
   clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";

   power-domains = <&gpucc GPU_CX_GDSC>,
     <&gpucc GPU_GX_GDSC>;
   power-domain-names = "cx", "gx";

   iommus = <&adreno_smmu 5 0x400>;

   operating-points-v2 = <&gmu_opp_table>;

   status = "disabled";

   gmu_opp_table: opp-table {
    compatible = "operating-points-v2";

    opp-200000000 {
     opp-hz = /bits/ 64 <200000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
    };
   };
  };

  gpucc: clock-controller@2c90000 {
   compatible = "qcom,sm8150-gpucc";
   reg = <0 0x02c90000 0 0x9000>;
   clocks = <&rpmhcc RPMH_CXO_CLK>,
     <&gcc GCC_GPU_GPLL0_CLK_SRC>,
     <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
   clock-names = "bi_tcxo",
          "gcc_gpu_gpll0_clk_src",
          "gcc_gpu_gpll0_div_clk_src";
   #clock-cells = <1>;
   #reset-cells = <1>;
   #power-domain-cells = <1>;
  };

  adreno_smmu: iommu@2ca0000 {
   compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu",
         "qcom,smmu-500", "arm,mmu-500";
   reg = <0 0x02ca0000 0 0x10000>;
   #iommu-cells = <2>;
   #global-interrupts = <1>;
   interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
    <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
    <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
    <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
    <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
    <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
    <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
    <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
    <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
   clocks = <&gpucc GPU_CC_AHB_CLK>,
     <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
     <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
   clock-names = "ahb", "bus", "iface";

   power-domains = <&gpucc GPU_CX_GDSC>;
  };

  tlmm: pinctrl@3100000 {
   compatible = "qcom,sm8150-pinctrl";
   reg = <0x0 0x03100000 0x0 0x300000>,
         <0x0 0x03500000 0x0 0x300000>,
         <0x0 0x03900000 0x0 0x300000>,
         <0x0 0x03D00000 0x0 0x300000>;
   reg-names = "west", "east", "north", "south";
   interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
   gpio-ranges = <&tlmm 0 0 176>;
   gpio-controller;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
   wakeup-parent = <&pdc>;

   qup_i2c0_default: qup-i2c0-default-state {
    pins = "gpio0", "gpio1";
    function = "qup0";
    drive-strength = <0x02>;
    bias-disable;
   };

   qup_spi0_default: qup-spi0-default-state {
    pins = "gpio0", "gpio1", "gpio2", "gpio3";
    function = "qup0";
    drive-strength = <6>;
    bias-disable;
   };

   qup_i2c1_default: qup-i2c1-default-state {
    pins = "gpio114", "gpio115";
    function = "qup1";
    drive-strength = <2>;
    bias-disable;
   };

   qup_spi1_default: qup-spi1-default-state {
    pins = "gpio114", "gpio115", "gpio116", "gpio117";
    function = "qup1";
    drive-strength = <6>;
    bias-disable;
   };

   qup_i2c2_default: qup-i2c2-default-state {
    pins = "gpio126", "gpio127";
    function = "qup2";
    drive-strength = <2>;
    bias-disable;
   };

   qup_spi2_default: qup-spi2-default-state {
    pins = "gpio126", "gpio127", "gpio128", "gpio129";
    function = "qup2";
    drive-strength = <6>;
    bias-disable;
   };

   qup_i2c3_default: qup-i2c3-default-state {
    pins = "gpio144", "gpio145";
    function = "qup3";
    drive-strength = <2>;
    bias-disable;
   };

   qup_spi3_default: qup-spi3-default-state {
    pins = "gpio144", "gpio145", "gpio146", "gpio147";
    function = "qup3";
    drive-strength = <6>;
    bias-disable;
   };

   qup_i2c4_default: qup-i2c4-default-state {
    pins = "gpio51", "gpio52";
    function = "qup4";
    drive-strength = <2>;
    bias-disable;
   };

   qup_spi4_default: qup-spi4-default-state {
    pins = "gpio51", "gpio52", "gpio53", "gpio54";
    function = "qup4";
    drive-strength = <6>;
    bias-disable;
   };

   qup_i2c5_default: qup-i2c5-default-state {
    pins = "gpio121", "gpio122";
    function = "qup5";
    drive-strength = <2>;
    bias-disable;
   };

   qup_spi5_default: qup-spi5-default-state {
    pins = "gpio119", "gpio120", "gpio121", "gpio122";
    function = "qup5";
    drive-strength = <6>;
    bias-disable;
   };

   qup_i2c6_default: qup-i2c6-default-state {
    pins = "gpio6", "gpio7";
    function = "qup6";
    drive-strength = <2>;
    bias-disable;
   };

   qup_spi6_default: qup-spi6-default-state {
    pins = "gpio4", "gpio5", "gpio6", "gpio7";
    function = "qup6";
    drive-strength = <6>;
    bias-disable;
   };

   qup_i2c7_default: qup-i2c7-default-state {
    pins = "gpio98", "gpio99";
    function = "qup7";
    drive-strength = <2>;
    bias-disable;
   };

   qup_spi7_default: qup-spi7-default-state {
    pins = "gpio98", "gpio99", "gpio100", "gpio101";
    function = "qup7";
    drive-strength = <6>;
    bias-disable;
   };

   qup_i2c8_default: qup-i2c8-default-state {
    pins = "gpio88", "gpio89";
    function = "qup8";
    drive-strength = <2>;
    bias-disable;
   };

   qup_spi8_default: qup-spi8-default-state {
    pins = "gpio88", "gpio89", "gpio90", "gpio91";
    function = "qup8";
    drive-strength = <6>;
    bias-disable;
   };

   qup_i2c9_default: qup-i2c9-default-state {
    pins = "gpio39", "gpio40";
    function = "qup9";
    drive-strength = <2>;
    bias-disable;
   };

   qup_spi9_default: qup-spi9-default-state {
    pins = "gpio39", "gpio40", "gpio41", "gpio42";
    function = "qup9";
    drive-strength = <6>;
    bias-disable;
   };

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