/* * Resolve the IPA the hard way using the guest VA. * * Stage-1 translation already validated the memory access * rights. As such, we can use the EL1 translation regime, and * don't have to distinguish between EL0 and EL1 access. * * We do need to save/restore PAR_EL1 though, as we haven't * saved the guest context yet, and we may return early...
*/
par = read_sysreg_par();
ret = system_supports_poe() ? __kvm_at(OP_AT_S1E1A, far) :
__kvm_at(OP_AT_S1E1R, far); if (!ret)
tmp = read_sysreg_par(); else
tmp = SYS_PAR_EL1_F; /* back to the guest */
write_sysreg(par, par_el1);
if (unlikely(tmp & SYS_PAR_EL1_F)) returnfalse; /* Translation failed, back to guest */
/* Convert PAR to HPFAR format */
*hpfar = PAR_TO_HPFAR(tmp); returntrue;
}
/* * Checks for the conditions when HPFAR_EL2 is written, per ARM ARM R_FKLWR.
*/ staticinlinebool __hpfar_valid(u64 esr)
{ /* * CPUs affected by ARM erratum #834220 may incorrectly report a * stage-2 translation fault when a stage-1 permission fault occurs. * * Re-walk the page tables to determine if a stage-1 fault actually * occurred.
*/ if (cpus_have_final_cap(ARM64_WORKAROUND_834220) &&
esr_fsc_is_translation_fault(esr)) returnfalse;
if (esr_fsc_is_translation_fault(esr) || esr_fsc_is_access_flag_fault(esr)) returntrue;
if ((esr & ESR_ELx_S1PTW) && esr_fsc_is_permission_fault(esr)) returntrue;
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