/* * Convert a physical memory address into a IO memory address. * For us this is trivially a type cast.
*/ #define iomem(a) ((void __iomem *) (a))
/* * The non-MMU m68k and ColdFire IO and memory mapped hardware access * functions have always worked in CPU native endian. We need to define * that behavior here first before we include asm-generic/io.h.
*/ #define __raw_readb(addr) \
({ u8 __v = (*(__force volatile u8 *) (addr)); __v; }) #define __raw_readw(addr) \
({ u16 __v = (*(__force volatile u16 *) (addr)); __v; }) #define __raw_readl(addr) \
({ u32 __v = (*(__force volatile u32 *) (addr)); __v; })
#ifdefined(CONFIG_COLDFIRE) /* * For ColdFire platforms we may need to do some extra checks for what * type of address range we are accessing. Include the ColdFire platform * definitions so we can figure out if need to do something special.
*/ #include <asm/byteorder.h> #include <asm/coldfire.h> #include <asm/mcfsim.h> #endif/* CONFIG_COLDFIRE */
#ifdefined(IOMEMBASE) /* * The ColdFire SoC internal peripherals are mapped into virtual address * space using the ACR registers of the cache control unit. This means we * are using a 1:1 physical:virtual mapping for them. We can quickly * determine if we are accessing an internal peripheral device given the * physical or vitrual address using the same range check. This check logic * applies just the same of there is no MMU but something like a PCI bus * is present.
*/ staticint __cf_internalio(unsignedlong addr)
{ return (addr >= IOMEMBASE) && (addr <= IOMEMBASE + IOMEMSIZE - 1);
}
/* * We need to treat built-in peripherals and bus based address ranges * differently. Local built-in peripherals (and the ColdFire SoC parts * have quite a lot of them) are always native endian - which is big * endian on m68k/ColdFire. Bus based address ranges, like the PCI bus, * are accessed little endian - so we need to byte swap those.
*/ #define readw readw staticinline u16 readw(constvolatilevoid __iomem *addr)
{ if (cf_internalio(addr)) return __raw_readw(addr); return swab16(__raw_readw(addr));
}
#ifdefined(CONFIG_PCI) /* * Support for PCI bus access uses the asm-generic access functions. * We need to supply the base address and masks for the normal memory * and IO address space mappings.
*/ #define PCI_MEM_PA 0xf0000000 /* Host physical address */ #define PCI_MEM_BA 0xf0000000 /* Bus physical address */ #define PCI_MEM_SIZE 0x08000000 /* 128 MB */ #define PCI_MEM_MASK (PCI_MEM_SIZE - 1)
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