Quelle  loongson64-2k1000.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: GPL-2.0

/dts-v1/;

#include <dt-bindings/interrupt-controller/irq.h>

/ {
 compatible = "loongson,loongson2k1000";

 #address-cells = <2>;
 #size-cells = <2>;

 cpus {
  #address-cells = <1>;
  #size-cells = <0>;

  cpu0: cpu@0 {
   device_type = "cpu";
   compatible = "loongson,gs264";
   reg = <0x0>;
   #clock-cells = <1>;
   clocks = <&cpu_clk>;
  };
 };

 cpu_clk: cpu_clk {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <800000000>;
 };

 cpuintc: interrupt-controller {
  #address-cells = <0>;
  #interrupt-cells = <1>;
  interrupt-controller;
  compatible = "mti,cpu-interrupt-controller";
 };

 package0: bus@10000000 {
  compatible = "simple-bus";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* ioports */
   0 0x40000000 0 0x40000000 0 0x40000000
   0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>;

  isa@18000000 {
   compatible = "isa";
   #size-cells = <1>;
   #address-cells = <2>;
   ranges = <1 0x0 0x0 0x18000000 0x4000>;
  };

  pm: reset-controller@1fe07000 {
   compatible = "loongson,ls2k-pm";
   reg = <0 0x1fe07000 0 0x422>;
  };

  liointc0: interrupt-controller@1fe11400 {
   compatible = "loongson,liointc-2.0";
   reg = <0 0x1fe11400 0 0x40>,
    <0 0x1fe11040 0 0x8>,
    <0 0x1fe11140 0 0x8>;
   reg-names = "main", "isr0", "isr1";

   interrupt-controller;
   #interrupt-cells = <2>;

   interrupt-parent = <&cpuintc>;
   interrupts = <2>;
   interrupt-names = "int0";

   loongson,parent_int_map = <0xffffffff>, /* int0 */
      <0x00000000>, /* int1 */
      <0x00000000>, /* int2 */
      <0x00000000>; /* int3 */
  };

  liointc1: interrupt-controller@1fe11440 {
   compatible = "loongson,liointc-2.0";
   reg = <0 0x1fe11440 0 0x40>,
    <0 0x1fe11048 0 0x8>,
    <0 0x1fe11148 0 0x8>;
   reg-names = "main", "isr0", "isr1";

   interrupt-controller;
   #interrupt-cells = <2>;

   interrupt-parent = <&cpuintc>;
   interrupts = <3>;
   interrupt-names = "int1";

   loongson,parent_int_map = <0x00000000>, /* int0 */
      <0xffffffff>, /* int1 */
      <0x00000000>, /* int2 */
      <0x00000000>; /* int3 */
  };

  rtc0: rtc@1fe07800 {
   compatible = "loongson,ls2k1000-rtc";
   reg = <0 0x1fe07800 0 0x78>;
   interrupt-parent = <&liointc1>;
   interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
  };

  uart0: serial@1fe00000 {
   compatible = "ns16550a";
   reg = <0 0x1fe00000 0 0x8>;
   clock-frequency = <125000000>;
   interrupt-parent = <&liointc0>;
   interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
   no-loopback-test;
  };

  pci@1a000000 {
   compatible = "loongson,ls2k-pci";
   device_type = "pci";
   #address-cells = <3>;
   #size-cells = <2>;

   reg = <0 0x1a000000 0 0x02000000>,
    <0xfe 0x00000000 0 0x20000000>;

   ranges = <0x01000000 0x0 0x00000000 0x0 0x18000000  0x0 0x00010000>,
     <0x02000000 0x0 0x40000000 0x0 0x40000000  0x0 0x40000000>;

   gmac@3,0 {
    compatible = "pci0014,7a03.0",
         "pci0014,7a03",
         "pciclass0c0320",
         "pciclass0c03";

    reg = <0x1800 0x0 0x0 0x0 0x0>;
    interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
          <13 IRQ_TYPE_LEVEL_HIGH>;
    interrupt-names = "macirq", "eth_lpi";
    interrupt-parent = <&liointc0>;
    phy-mode = "rgmii-id";
    phy-handle = <&phy1>;
    mdio {
     #address-cells = <1>;
     #size-cells = <0>;
     compatible = "snps,dwmac-mdio";
     phy0: ethernet-phy@0 {
      reg = <0>;
     };
    };
   };

   gmac@3,1 {
    compatible = "pci0014,7a03.0",
         "pci0014,7a03",
         "pciclass0c0320",
         "pciclass0c03",
         "loongson, pci-gmac";

    reg = <0x1900 0x0 0x0 0x0 0x0>;
    interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
          <15 IRQ_TYPE_LEVEL_HIGH>;
    interrupt-names = "macirq", "eth_lpi";
    interrupt-parent = <&liointc0>;
    phy-mode = "rgmii-id";
    phy-handle = <&phy1>;
    mdio {
     #address-cells = <1>;
     #size-cells = <0>;
     compatible = "snps,dwmac-mdio";
     phy1: ethernet-phy@1 {
      reg = <0>;
     };
    };
   };

   ehci@4,1 {
    compatible = "pci0014,7a14.0",
         "pci0014,7a14",
         "pciclass0c0320",
         "pciclass0c03";

    reg = <0x2100 0x0 0x0 0x0 0x0>;
    interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
    interrupt-parent = <&liointc1>;
   };

   ohci@4,2 {
    compatible = "pci0014,7a24.0",
         "pci0014,7a24",
         "pciclass0c0310",
         "pciclass0c03";

    reg = <0x2200 0x0 0x0 0x0 0x0>;
    interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
    interrupt-parent = <&liointc1>;
   };

   sata@8,0 {
    compatible = "pci0014,7a08.0",
         "pci0014,7a08",
         "pciclass010601",
         "pciclass0106";

    reg = <0x4000 0x0 0x0 0x0 0x0>;
    interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
    interrupt-parent = <&liointc0>;
   };

   pcie@9,0 {
    compatible = "pci0014,7a19.0",
         "pci0014,7a19",
         "pciclass060400",
         "pciclass0604";

    reg = <0x4800 0x0 0x0 0x0 0x0>;
    #address-cells = <3>;
    #size-cells = <2>;
    device_type = "pci";
    #interrupt-cells = <1>;
    interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
    interrupt-parent = <&liointc1>;
    interrupt-map-mask = <0 0 0 0>;
    interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_HIGH>;
    ranges;
    external-facing;
   };

   pcie@a,0 {
    compatible = "pci0014,7a09.0",
         "pci0014,7a09",
         "pciclass060400",
         "pciclass0604";

    reg = <0x5000 0x0 0x0 0x0 0x0>;
    #address-cells = <3>;
    #size-cells = <2>;
    device_type = "pci";
    #interrupt-cells = <1>;
    interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
    interrupt-parent = <&liointc1>;
    interrupt-map-mask = <0 0 0 0>;
    interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_HIGH>;
    ranges;
    external-facing;
   };

   pcie@b,0 {
    compatible = "pci0014,7a09.0",
         "pci0014,7a09",
         "pciclass060400",
         "pciclass0604";

    reg = <0x5800 0x0 0x0 0x0 0x0>;
    #address-cells = <3>;
    #size-cells = <2>;
    device_type = "pci";
    #interrupt-cells = <1>;
    interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
    interrupt-parent = <&liointc1>;
    interrupt-map-mask = <0 0 0 0>;
    interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_HIGH>;
    ranges;
    external-facing;
   };

   pcie@c,0 {
    compatible = "pci0014,7a09.0",
         "pci0014,7a09",
         "pciclass060400",
         "pciclass0604";

    reg = <0x6000 0x0 0x0 0x0 0x0>;
    #address-cells = <3>;
    #size-cells = <2>;
    device_type = "pci";
    #interrupt-cells = <1>;
    interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
    interrupt-parent = <&liointc1>;
    interrupt-map-mask = <0 0 0 0>;
    interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_HIGH>;
    ranges;
    external-facing;
   };

   pcie@d,0 {
    compatible = "pci0014,7a19.0",
         "pci0014,7a19",
         "pciclass060400",
         "pciclass0604";

    reg = <0x6800 0x0 0x0 0x0 0x0>;
    #address-cells = <3>;
    #size-cells = <2>;
    device_type = "pci";
    #interrupt-cells = <1>;
    interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
    interrupt-parent = <&liointc1>;
    interrupt-map-mask = <0 0 0 0>;
    interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_HIGH>;
    ranges;
    external-facing;
   };

   pcie@e,0 {
    compatible = "pci0014,7a09.0",
         "pci0014,7a09",
         "pciclass060400",
         "pciclass0604";

    reg = <0x7000 0x0 0x0 0x0 0x0>;
    #address-cells = <3>;
    #size-cells = <2>;
    device_type = "pci";
    #interrupt-cells = <1>;
    interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
    interrupt-parent = <&liointc1>;
    interrupt-map-mask = <0 0 0 0>;
    interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_HIGH>;
    ranges;
    external-facing;
   };

  };
 };
};