/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * OpenRISC head.S * * Linux architectural port borrowing liberally from similar works of * others. All original copyrights apply as per the original source * declaration. * * Modifications for the OpenRISC architecture: * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com> * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
*/
/* * DSCR: this is a common hook for handling exceptions. it will save * the needed registers, set up stack and pointer to current * then jump to the handler while enabling MMU * * PRMS: handler - a function to jump to. it has to save the * remaining registers to kernel stack, call * appropriate arch-independant exception handler * and finaly jump to ret_from_except * * PREQ: unchanged state from the time exception happened * * POST: SAVED the following registers original value * to the new created exception frame pointed to by r1 * * r1 - ksp pointing to the new (exception) frame * r4 - EEAR exception EA * r10 - current pointing to current_thread_info struct * r12 - syscall 0, since we didn't come from syscall * r30 - handler address of the handler we'll jump to * * handler has to save remaining registers to the exception * ksp frame *before* tainting them! * * NOTE: this function is not reentrant per se. reentrancy is guaranteed * by processor disabling all exceptions/interrupts when exception * accours. * * OPTM: no need to make it so wasteful to extract ksp when in user mode
*/
#define EXCEPTION_HANDLE(handler) \
EXCEPTION_T_STORE_GPR30 ;\
l.mfspr r30,r0,SPR_ESR_BASE ;\
l.andi r30,r30,SPR_SR_SM ;\
l.sfeqi r30,0 ;\
EXCEPTION_T_STORE_GPR10 ;\
l.bnf 2f /* kernel_mode */ ;\
EXCEPTION_T_STORE_SP /* delay slot */ ;\
1: /* user_mode: */ ;\
GET_CURRENT_THREAD_INFO ;\
tophys (r30,r10) ;\
l.lwz r1,(TI_KSP)(r30) ;\ /* fall through */ ;\
2: /* kernel_mode: */ ;\ /* create new stack frame, save only needed gprs */ ;\ /* r1: KSP, r10: current, r4: EEAR, r31: __pa(KSP) */ ;\ /* r12: temp, syscall indicator */ ;\
l.addi r1,r1,-(INT_FRAME_SIZE) ;\ /* r1 is KSP, r30 is __pa(KSP) */ ;\
tophys (r30,r1) ;\
l.sw PT_GPR12(r30),r12 ;\ /* r4 use for tmp before EA */ ;\
l.mfspr r12,r0,SPR_EPCR_BASE ;\
l.sw PT_PC(r30),r12 ;\
l.mfspr r12,r0,SPR_ESR_BASE ;\
l.sw PT_SR(r30),r12 ;\ /* save r30 */ ;\
EXCEPTION_T_LOAD_GPR30(r12) ;\
l.sw PT_GPR30(r30),r12 ;\ /* save r10 as was prior to exception */ ;\
EXCEPTION_T_LOAD_GPR10(r12) ;\
l.sw PT_GPR10(r30),r12 ;\ /* save PT_SP as was prior to exception */ ;\
EXCEPTION_T_LOAD_SP(r12) ;\
l.sw PT_SP(r30),r12 ;\ /* save exception r4, set r4 = EA */ ;\
l.sw PT_GPR4(r30),r4 ;\
l.mfspr r4,r0,SPR_EEAR_BASE ;\ /* r12 == 1 if we come from syscall */ ;\
CLEAR_GPR(r12) ;\ /* ----- turn on MMU ----- */ ;\ /* Carry DSX into exception SR */ ;\
l.mfspr r30,r0,SPR_SR ;\
l.andi r30,r30,SPR_SR_DSX ;\
l.ori r30,r30,(EXCEPTION_SR) ;\
l.mtspr r0,r30,SPR_ESR_BASE ;\ /* r30: EA address of handler */ ;\
LOAD_SYMBOL_2_GPR(r30,handler) ;\
l.mtspr r0,r30,SPR_EPCR_BASE ;\
l.rfe
/* ---[ 0x100: RESET exception ]----------------------------------------- */
.org 0x100 /* Jump to .init code at _start which lives in the .head section * and will be discarded after boot.
*/
LOAD_SYMBOL_2_GPR(r15, _start)
tophys (r13,r15) /* MMU disabled */
l.jr r13
l.nop
/* This early stuff belongs in the .init.text section, but some of the functions below definitely
* don't... */
__INIT
.global _start
_start: /* Init r0 to zero as per spec */
CLEAR_GPR(r0)
/* save kernel parameters */
l.or r25,r0,r3 /* pointer to fdt */
/* * ensure a deterministic start
*/
l.ori r3,r0,0x1
l.mtspr r0,r3,SPR_SR
/* * Start the TTCR as early as possible, so that the RNG can make use of * measurements of boot time from the earliest opportunity. Especially * important is that the TTCR does not return zero by the time we reach * random_init().
*/
l.movhi r3,hi(SPR_TTMR_CR)
l.mtspr r0,r3,SPR_TTMR
_flush_tlb: /* * I N V A L I D A T E T L B e n t r i e s
*/
LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0))
LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0))
l.addi r7,r0,128 /* Maximum number of sets */
1:
l.mtspr r5,r0,0x0
l.mtspr r6,r0,0x0
#ifdef CONFIG_SMP
secondary_wait: /* Doze the cpu until we are asked to run */ /* If we dont have power management skip doze */
l.mfspr r25,r0,SPR_UPR
l.andi r25,r25,SPR_UPR_PMP
l.sfeq r25,r0
l.bf secondary_check_release
l.nop
secondary_check_release: /* * Check if we actually got the release signal, if not go-back to * sleep.
*/
l.mfspr r25,r0,SPR_COREID
LOAD_SYMBOL_2_GPR(r3, secondary_release)
tophys(r4, r3)
l.lwz r3,0(r4)
l.sfeq r25,r3
l.bnf secondary_wait
l.nop /* fall through to secondary_init */
secondary_init: /* * set up initial ksp and current
*/
LOAD_SYMBOL_2_GPR(r10, secondary_thread_info)
tophys (r30,r10)
l.lwz r10,0(r30)
l.addi r1,r10,THREAD_SIZE
tophys (r30,r10)
l.sw TI_KSP(r30),r1
l.jal _ic_enable
l.nop
l.jal _dc_enable
l.nop
l.jal _flush_tlb
l.nop
/* * enable dmmu & immu
*/
l.mfspr r30,r0,SPR_SR
l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
l.or r30,r30,r28 /* * This is a bit tricky, we need to switch over from physical addresses * to virtual addresses on the fly. * To do that, we first set up ESR with the IME and DME bits set. * Then EPCR is set to secondary_start and then a l.rfe is issued to * "jump" to that.
*/
l.mtspr r0,r30,SPR_ESR_BASE
LOAD_SYMBOL_2_GPR(r30, secondary_start)
l.mtspr r0,r30,SPR_EPCR_BASE
l.rfe
/* for SMP we'd have (this is a bit subtle, CC must be always set * for SMP, but since we have _PAGE_PRESENT bit always defined * we can just modify the mask)
*/
#define DTLB_SMP_CONVERT_MASK 0x3fb
#define ITLB_SMP_CONVERT_MASK 0x3b
/* ---[ boot dtlb miss handler ]----------------------------------------- */
boot_dtlb_miss_handler:
/* mask for DTLB_MR register: - (0) sets V (valid) bit, * - (31-12) sets bits belonging to VPN (31-12)
*/
#define DTLB_MR_MASK 0xfffff001
/* mask for DTLB_TR register: - (2) sets CI (cache inhibit) bit, * - (4) sets A (access) bit, * - (5) sets D (dirty) bit, * - (8) sets SRE (superuser read) bit * - (9) sets SWE (superuser write) bit * - (31-12) sets bits belonging to VPN (31-12)
*/
#define DTLB_TR_MASK 0xfffff332
/* These are for masking out the VPN/PPN value from the MR/TR registers...
* it's not the same as the PFN */
#define VPN_MASK 0xfffff000
#define PPN_MASK 0xfffff000
EXCEPTION_STORE_GPR6
#if 0
l.mfspr r6,r0,SPR_ESR_BASE //
l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
l.sfeqi r6,0 // r6 == 0x1 --> SM
l.bf exit_with_no_dtranslation //
l.nop
#endif
/* this could be optimized by moving storing of * non r6 registers here, and jumping r6 restore * if not in supervisor mode
*/
/* set up DTLB with no translation for EA <= 0xbfffffff */
LOAD_SYMBOL_2_GPR(r6,0xbfffffff)
l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xbfffffff >= EA)
l.bf 1f // goto out
l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
tophys(r3,r4) // r3 <- PA
1:
l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
l.movhi r5,hi(DTLB_TR_MASK) // r5 <- ffff:0000.x000
l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK
l.and r5,r5,r3 // r5 <- PPN :PPN .x330 - we have DTLBTR entry
l.mtspr r2,r5,SPR_DTLBTR_BASE(0) // set DTLBTR
/* * set up ITLB with no translation for EA <= 0x0fffffff * * we need this for head.S mapping (EA = PA). if we move all functions * which run with mmu enabled into entry.S, we might be able to eliminate this. *
*/
LOAD_SYMBOL_2_GPR(r6,0x0fffffff)
l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xb0ffffff >= EA)
l.bf 1f // goto out
l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
tophys(r3,r4) // r3 <- PA
1:
l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
l.movhi r5,hi(ITLB_TR_MASK) // r5 <- ffff:0000.x000
l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK
l.and r5,r5,r3 // r5 <- PPN :PPN .x050 - we have ITLBTR entry
l.mtspr r2,r5,SPR_ITLBTR_BASE(0) // set ITLBTR
/* ====================================================================== */ /* * Stuff below here shouldn't go into .head section... maybe this stuff * can be moved to entry.S ???
*/
/* ==============================================[ DTLB miss handler ]=== */
/* * Comments: * Exception handlers are entered with MMU off so the following handler * needs to use physical addressing *
*/
.text
ENTRY(dtlb_miss_handler)
EXCEPTION_STORE_GPR2
EXCEPTION_STORE_GPR3
EXCEPTION_STORE_GPR4 /* * get EA of the miss
*/
l.mfspr r2,r0,SPR_EEAR_BASE /* * pmd = (pmd_t *)(current_pgd + pgd_index(daddr));
*/
GET_CURRENT_PGD(r3,r4) // r3 is current_pgd, r4 is temp
l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
l.slli r4,r4,0x2 // to get address << 2
l.add r3,r4,r3 // r4 is pgd_index(daddr) /* * if (pmd_none(*pmd)) * goto pmd_none:
*/
tophys (r4,r3)
l.lwz r3,0x0(r4) // get *pmd value
l.sfne r3,r0
l.bnf d_pmd_none
l.addi r3,r0,0xffffe000 // PAGE_MASK
/* ==============================================[ ITLB miss handler ]=== */
ENTRY(itlb_miss_handler)
EXCEPTION_STORE_GPR2
EXCEPTION_STORE_GPR3
EXCEPTION_STORE_GPR4 /* * get EA of the miss
*/
l.mfspr r2,r0,SPR_EEAR_BASE
/* * pmd = (pmd_t *)(current_pgd + pgd_index(daddr)); *
*/
GET_CURRENT_PGD(r3,r4) // r3 is current_pgd, r5 is temp
l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
l.slli r4,r4,0x2 // to get address << 2
l.add r3,r4,r3 // r4 is pgd_index(daddr) /* * if (pmd_none(*pmd)) * goto pmd_none:
*/
tophys (r4,r3)
l.lwz r3,0x0(r4) // get *pmd value
l.sfne r3,r0
l.bnf i_pmd_none
l.addi r3,r0,0xffffe000 // PAGE_MASK
/* * __PHX__ :: fixme * we should not just blindly set executable flags, * but it does help with ping. the clean way would be to find out * (and fix it) why stack doesn't have execution permissions
*/
/* =================================================[ debugging aids ]=== */
/* * DESC: Prints ASCII character stored in r7 * * PRMS: r7 - a 32-bit value with an ASCII character in the first byte * position. * * PREQ: The UART at UART_BASE_ADD has to be initialized * * POST: internally used but restores: * r4 - to store UART_BASE_ADD * r5 - for loading OFF_TXFULL / THRE,TEMT * r6 - for storing bitmask (SERIAL_8250)
*/
ENTRY(_emergency_putc)
EMERGENCY_PRINT_STORE_GPR4
EMERGENCY_PRINT_STORE_GPR5
EMERGENCY_PRINT_STORE_GPR6
/* * DSCR: prints a string referenced by r3. * * PRMS: r3 - address of the first character of null * terminated string to be printed * * PREQ: UART at UART_BASE_ADD has to be initialized * * POST: caller should be aware that r3, r9 are changed
*/
ENTRY(_emergency_print)
EMERGENCY_PRINT_STORE_GPR7
EMERGENCY_PRINT_STORE_GPR9
/* Load character to r7, check for null terminator */
2: l.lbz r7,0(r3)
l.sfeqi r7,0x0
l.bf 9f
l.nop
/* * DSCR: prints a number in r3 in hex. * * PRMS: r3 - a 32-bit unsigned integer * * PREQ: UART at UART_BASE_ADD has to be initialized * * POST: caller should be aware that r3, r9 are changed
*/
ENTRY(_emergency_print_nr)
EMERGENCY_PRINT_STORE_GPR7
EMERGENCY_PRINT_STORE_GPR8
EMERGENCY_PRINT_STORE_GPR9
/* * This should be used for debugging only. * It messes up the Linux early serial output * somehow, so use it sparingly and essentially * only if you need to debug something that goes wrong * before Linux gets the early serial going. * * Furthermore, you'll have to make sure you set the * UART_DEVISOR correctly according to the system * clock rate. * *
*/
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