Quelle  k1.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
 */

#include <dt-bindings/clock/spacemit,k1-syscon.h>

/dts-v1/;
/ {
 #address-cells = <2>;
 #size-cells = <2>;
 model = "SpacemiT K1";
 compatible = "spacemit,k1";

 cpus {
  #address-cells = <1>;
  #size-cells = <0>;
  timebase-frequency = <24000000>;

  cpu-map {
   cluster0 {
    core0 {
     cpu = <&cpu_0>;
    };
    core1 {
     cpu = <&cpu_1>;
    };
    core2 {
     cpu = <&cpu_2>;
    };
    core3 {
     cpu = <&cpu_3>;
    };
   };

   cluster1 {
    core0 {
     cpu = <&cpu_4>;
    };
    core1 {
     cpu = <&cpu_5>;
    };
    core2 {
     cpu = <&cpu_6>;
    };
    core3 {
     cpu = <&cpu_7>;
    };
   };
  };

  cpu_0: cpu@0 {
   compatible = "spacemit,x60", "riscv";
   device_type = "cpu";
   reg = <0>;
   riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
   riscv,isa-base = "rv64i";
   riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
            "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
            "zifencei", "zihintpause", "zihpm", "zfh", "zba",
            "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
            "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
   riscv,cbom-block-size = <64>;
   riscv,cbop-block-size = <64>;
   riscv,cboz-block-size = <64>;
   i-cache-block-size = <64>;
   i-cache-size = <32768>;
   i-cache-sets = <128>;
   d-cache-block-size = <64>;
   d-cache-size = <32768>;
   d-cache-sets = <128>;
   next-level-cache = <&cluster0_l2_cache>;
   mmu-type = "riscv,sv39";

   cpu0_intc: interrupt-controller {
    compatible = "riscv,cpu-intc";
    interrupt-controller;
    #interrupt-cells = <1>;
   };
  };

  cpu_1: cpu@1 {
   compatible = "spacemit,x60", "riscv";
   device_type = "cpu";
   reg = <1>;
   riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
   riscv,isa-base = "rv64i";
   riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
            "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
            "zifencei", "zihintpause", "zihpm", "zfh", "zba",
            "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
            "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
   riscv,cbom-block-size = <64>;
   riscv,cbop-block-size = <64>;
   riscv,cboz-block-size = <64>;
   i-cache-block-size = <64>;
   i-cache-size = <32768>;
   i-cache-sets = <128>;
   d-cache-block-size = <64>;
   d-cache-size = <32768>;
   d-cache-sets = <128>;
   next-level-cache = <&cluster0_l2_cache>;
   mmu-type = "riscv,sv39";

   cpu1_intc: interrupt-controller {
    compatible = "riscv,cpu-intc";
    interrupt-controller;
    #interrupt-cells = <1>;
   };
  };

  cpu_2: cpu@2 {
   compatible = "spacemit,x60", "riscv";
   device_type = "cpu";
   reg = <2>;
   riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
   riscv,isa-base = "rv64i";
   riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
            "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
            "zifencei", "zihintpause", "zihpm", "zfh", "zba",
            "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
            "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
   riscv,cbom-block-size = <64>;
   riscv,cbop-block-size = <64>;
   riscv,cboz-block-size = <64>;
   i-cache-block-size = <64>;
   i-cache-size = <32768>;
   i-cache-sets = <128>;
   d-cache-block-size = <64>;
   d-cache-size = <32768>;
   d-cache-sets = <128>;
   next-level-cache = <&cluster0_l2_cache>;
   mmu-type = "riscv,sv39";

   cpu2_intc: interrupt-controller {
    compatible = "riscv,cpu-intc";
    interrupt-controller;
    #interrupt-cells = <1>;
   };
  };

  cpu_3: cpu@3 {
   compatible = "spacemit,x60", "riscv";
   device_type = "cpu";
   reg = <3>;
   riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
   riscv,isa-base = "rv64i";
   riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
            "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
            "zifencei", "zihintpause", "zihpm", "zfh", "zba",
            "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
            "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
   riscv,cbom-block-size = <64>;
   riscv,cbop-block-size = <64>;
   riscv,cboz-block-size = <64>;
   i-cache-block-size = <64>;
   i-cache-size = <32768>;
   i-cache-sets = <128>;
   d-cache-block-size = <64>;
   d-cache-size = <32768>;
   d-cache-sets = <128>;
   next-level-cache = <&cluster0_l2_cache>;
   mmu-type = "riscv,sv39";

   cpu3_intc: interrupt-controller {
    compatible = "riscv,cpu-intc";
    interrupt-controller;
    #interrupt-cells = <1>;
   };
  };

  cpu_4: cpu@4 {
   compatible = "spacemit,x60", "riscv";
   device_type = "cpu";
   reg = <4>;
   riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
   riscv,isa-base = "rv64i";
   riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
            "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
            "zifencei", "zihintpause", "zihpm", "zfh", "zba",
            "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
            "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
   riscv,cbom-block-size = <64>;
   riscv,cbop-block-size = <64>;
   riscv,cboz-block-size = <64>;
   i-cache-block-size = <64>;
   i-cache-size = <32768>;
   i-cache-sets = <128>;
   d-cache-block-size = <64>;
   d-cache-size = <32768>;
   d-cache-sets = <128>;
   next-level-cache = <&cluster1_l2_cache>;
   mmu-type = "riscv,sv39";

   cpu4_intc: interrupt-controller {
    compatible = "riscv,cpu-intc";
    interrupt-controller;
    #interrupt-cells = <1>;
   };
  };

  cpu_5: cpu@5 {
   compatible = "spacemit,x60", "riscv";
   device_type = "cpu";
   reg = <5>;
   riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
   riscv,isa-base = "rv64i";
   riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
            "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
            "zifencei", "zihintpause", "zihpm", "zfh", "zba",
            "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
            "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
   riscv,cbom-block-size = <64>;
   riscv,cbop-block-size = <64>;
   riscv,cboz-block-size = <64>;
   i-cache-block-size = <64>;
   i-cache-size = <32768>;
   i-cache-sets = <128>;
   d-cache-block-size = <64>;
   d-cache-size = <32768>;
   d-cache-sets = <128>;
   next-level-cache = <&cluster1_l2_cache>;
   mmu-type = "riscv,sv39";

   cpu5_intc: interrupt-controller {
    compatible = "riscv,cpu-intc";
    interrupt-controller;
    #interrupt-cells = <1>;
   };
  };

  cpu_6: cpu@6 {
   compatible = "spacemit,x60", "riscv";
   device_type = "cpu";
   reg = <6>;
   riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
   riscv,isa-base = "rv64i";
   riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
            "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
            "zifencei", "zihintpause", "zihpm", "zfh", "zba",
            "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
            "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
   riscv,cbom-block-size = <64>;
   riscv,cbop-block-size = <64>;
   riscv,cboz-block-size = <64>;
   i-cache-block-size = <64>;
   i-cache-size = <32768>;
   i-cache-sets = <128>;
   d-cache-block-size = <64>;
   d-cache-size = <32768>;
   d-cache-sets = <128>;
   next-level-cache = <&cluster1_l2_cache>;
   mmu-type = "riscv,sv39";

   cpu6_intc: interrupt-controller {
    compatible = "riscv,cpu-intc";
    interrupt-controller;
    #interrupt-cells = <1>;
   };
  };

  cpu_7: cpu@7 {
   compatible = "spacemit,x60", "riscv";
   device_type = "cpu";
   reg = <7>;
   riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
   riscv,isa-base = "rv64i";
   riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
            "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
            "zifencei", "zihintpause", "zihpm", "zfh", "zba",
            "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
            "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
   riscv,cbom-block-size = <64>;
   riscv,cbop-block-size = <64>;
   riscv,cboz-block-size = <64>;
   i-cache-block-size = <64>;
   i-cache-size = <32768>;
   i-cache-sets = <128>;
   d-cache-block-size = <64>;
   d-cache-size = <32768>;
   d-cache-sets = <128>;
   next-level-cache = <&cluster1_l2_cache>;
   mmu-type = "riscv,sv39";

   cpu7_intc: interrupt-controller {
    compatible = "riscv,cpu-intc";
    interrupt-controller;
    #interrupt-cells = <1>;
   };
  };

  cluster0_l2_cache: l2-cache0 {
   compatible = "cache";
   cache-block-size = <64>;
   cache-level = <2>;
   cache-size = <524288>;
   cache-sets = <512>;
   cache-unified;
  };

  cluster1_l2_cache: l2-cache1 {
   compatible = "cache";
   cache-block-size = <64>;
   cache-level = <2>;
   cache-size = <524288>;
   cache-sets = <512>;
   cache-unified;
  };
 };

 clocks {
  vctcxo_1m: clock-1m {
   compatible = "fixed-clock";
   clock-frequency = <1000000>;
   clock-output-names = "vctcxo_1m";
   #clock-cells = <0>;
  };

  vctcxo_24m: clock-24m {
   compatible = "fixed-clock";
   clock-frequency = <24000000>;
   clock-output-names = "vctcxo_24m";
   #clock-cells = <0>;
  };

  vctcxo_3m: clock-3m {
   compatible = "fixed-clock";
   clock-frequency = <3000000>;
   clock-output-names = "vctcxo_3m";
   #clock-cells = <0>;
  };

  osc_32k: clock-32k {
   compatible = "fixed-clock";
   clock-frequency = <32000>;
   clock-output-names = "osc_32k";
   #clock-cells = <0>;
  };
 };

 soc {
  compatible = "simple-bus";
  interrupt-parent = <&plic>;
  #address-cells = <2>;
  #size-cells = <2>;
  dma-noncoherent;
  ranges;

  syscon_rcpu: system-controller@c0880000 {
   compatible = "spacemit,k1-syscon-rcpu";
   reg = <0x0 0xc0880000 0x0 0x2048>;
   #reset-cells = <1>;
  };

  syscon_rcpu2: system-controller@c0888000 {
   compatible = "spacemit,k1-syscon-rcpu2";
   reg = <0x0 0xc0888000 0x0 0x28>;
   #reset-cells = <1>;
  };

  syscon_apbc: system-controller@d4015000 {
   compatible = "spacemit,k1-syscon-apbc";
   reg = <0x0 0xd4015000 0x0 0x1000>;
   clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
     <&vctcxo_24m>;
   clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
          "vctcxo_24m";
   #clock-cells = <1>;
   #reset-cells = <1>;
  };

  gpio: gpio@d4019000 {
   compatible = "spacemit,k1-gpio";
   reg = <0x0 0xd4019000 0x0 0x100>;
   clocks = <&syscon_apbc CLK_GPIO>,
     <&syscon_apbc CLK_GPIO_BUS>;
   clock-names = "core", "bus";
   gpio-controller;
   #gpio-cells = <3>;
   interrupts = <58>;
   interrupt-parent = <&plic>;
   interrupt-controller;
   #interrupt-cells = <3>;
   gpio-ranges = <&pinctrl 0 0 0 32>,
          <&pinctrl 1 0 32 32>,
          <&pinctrl 2 0 64 32>,
          <&pinctrl 3 0 96 32>;
  };

  pwm0: pwm@d401a000 {
   compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
   reg = <0x0 0xd401a000 0x0 0x10>;
   #pwm-cells = <3>;
   clocks = <&syscon_apbc CLK_PWM0>;
   resets = <&syscon_apbc RESET_PWM0>;
   status = "disabled";
  };

  pwm1: pwm@d401a400 {
   compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
   reg = <0x0 0xd401a400 0x0 0x10>;
   #pwm-cells = <3>;
   clocks = <&syscon_apbc CLK_PWM1>;
   resets = <&syscon_apbc RESET_PWM1>;
   status = "disabled";
  };

  pwm2: pwm@d401a800 {
   compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
   reg = <0x0 0xd401a800 0x0 0x10>;
   #pwm-cells = <3>;
   clocks = <&syscon_apbc CLK_PWM2>;
   resets = <&syscon_apbc RESET_PWM2>;
   status = "disabled";
  };

  pwm3: pwm@d401ac00 {
   compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
   reg = <0x0 0xd401ac00 0x0 0x10>;
   #pwm-cells = <3>;
   clocks = <&syscon_apbc CLK_PWM3>;
   resets = <&syscon_apbc RESET_PWM3>;
   status = "disabled";
  };

  pwm4: pwm@d401b000 {
   compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
   reg = <0x0 0xd401b000 0x0 0x10>;
   #pwm-cells = <3>;
   clocks = <&syscon_apbc CLK_PWM4>;
   resets = <&syscon_apbc RESET_PWM4>;
   status = "disabled";
  };

  pwm5: pwm@d401b400 {
   compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
   reg = <0x0 0xd401b400 0x0 0x10>;
   #pwm-cells = <3>;
   clocks = <&syscon_apbc CLK_PWM5>;
   resets = <&syscon_apbc RESET_PWM5>;
   status = "disabled";
  };

  pwm6: pwm@d401b800 {
   compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
   reg = <0x0 0xd401b800 0x0 0x10>;
   #pwm-cells = <3>;
   clocks = <&syscon_apbc CLK_PWM6>;
   resets = <&syscon_apbc RESET_PWM6>;
   status = "disabled";
  };

  pwm7: pwm@d401bc00 {
   compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
   reg = <0x0 0xd401bc00 0x0 0x10>;
   #pwm-cells = <3>;
   clocks = <&syscon_apbc CLK_PWM7>;
   resets = <&syscon_apbc RESET_PWM7>;
   status = "disabled";
  };

  pinctrl: pinctrl@d401e000 {
   compatible = "spacemit,k1-pinctrl";
   reg = <0x0 0xd401e000 0x0 0x400>;
   clocks = <&syscon_apbc CLK_AIB>,
     <&syscon_apbc CLK_AIB_BUS>;
   clock-names = "func", "bus";
  };

  pwm8: pwm@d4020000 {
   compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
   reg = <0x0 0xd4020000 0x0 0x10>;
   #pwm-cells = <3>;
   clocks = <&syscon_apbc CLK_PWM8>;
   resets = <&syscon_apbc RESET_PWM8>;
   status = "disabled";
  };

  pwm9: pwm@d4020400 {
   compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
   reg = <0x0 0xd4020400 0x0 0x10>;
   #pwm-cells = <3>;
   clocks = <&syscon_apbc CLK_PWM9>;
   resets = <&syscon_apbc RESET_PWM9>;
   status = "disabled";
  };

  pwm10: pwm@d4020800 {
   compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
   reg = <0x0 0xd4020800 0x0 0x10>;
   #pwm-cells = <3>;
   clocks = <&syscon_apbc CLK_PWM10>;
   resets = <&syscon_apbc RESET_PWM10>;
   status = "disabled";
  };

  pwm11: pwm@d4020c00 {
   compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
   reg = <0x0 0xd4020c00 0x0 0x10>;
   #pwm-cells = <3>;
   clocks = <&syscon_apbc CLK_PWM11>;
   resets = <&syscon_apbc RESET_PWM11>;
   status = "disabled";
  };

  pwm12: pwm@d4021000 {
   compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
   reg = <0x0 0xd4021000 0x0 0x10>;
   #pwm-cells = <3>;
   clocks = <&syscon_apbc CLK_PWM12>;
   resets = <&syscon_apbc RESET_PWM12>;
   status = "disabled";
  };

  pwm13: pwm@d4021400 {
   compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
   reg = <0x0 0xd4021400 0x0 0x10>;
   #pwm-cells = <3>;
   clocks = <&syscon_apbc CLK_PWM13>;
   resets = <&syscon_apbc RESET_PWM13>;
   status = "disabled";
  };

  pwm14: pwm@d4021800 {
   compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
   reg = <0x0 0xd4021800 0x0 0x10>;
   #pwm-cells = <3>;
   clocks = <&syscon_apbc CLK_PWM14>;
   resets = <&syscon_apbc RESET_PWM14>;
   status = "disabled";
  };

  pwm15: pwm@d4021c00 {
   compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
   reg = <0x0 0xd4021c00 0x0 0x10>;
   #pwm-cells = <3>;
   clocks = <&syscon_apbc CLK_PWM15>;
   resets = <&syscon_apbc RESET_PWM15>;
   status = "disabled";
  };

  pwm16: pwm@d4022000 {
   compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
   reg = <0x0 0xd4022000 0x0 0x10>;
   #pwm-cells = <3>;
   clocks = <&syscon_apbc CLK_PWM16>;
   resets = <&syscon_apbc RESET_PWM16>;
   status = "disabled";
  };

  pwm17: pwm@d4022400 {
   compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
   reg = <0x0 0xd4022400 0x0 0x10>;
   #pwm-cells = <3>;
   clocks = <&syscon_apbc CLK_PWM17>;
   resets = <&syscon_apbc RESET_PWM17>;
   status = "disabled";
  };

  pwm18: pwm@d4022800 {
   compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
   reg = <0x0 0xd4022800 0x0 0x10>;
   #pwm-cells = <3>;
   clocks = <&syscon_apbc CLK_PWM18>;
   resets = <&syscon_apbc RESET_PWM18>;
   status = "disabled";
  };

  pwm19: pwm@d4022c00 {
   compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
   reg = <0x0 0xd4022c00 0x0 0x10>;
   #pwm-cells = <3>;
   clocks = <&syscon_apbc CLK_PWM19>;
   resets = <&syscon_apbc RESET_PWM19>;
   status = "disabled";
  };

  syscon_mpmu: system-controller@d4050000 {
   compatible = "spacemit,k1-syscon-mpmu";
   reg = <0x0 0xd4050000 0x0 0x209c>;
   clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
     <&vctcxo_24m>;
   clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
          "vctcxo_24m";
   #clock-cells = <1>;
   #power-domain-cells = <1>;
   #reset-cells = <1>;
  };

  pll: clock-controller@d4090000 {
   compatible = "spacemit,k1-pll";
   reg = <0x0 0xd4090000 0x0 0x1000>;
   clocks = <&vctcxo_24m>;
   spacemit,mpmu = <&syscon_mpmu>;
   #clock-cells = <1>;
  };

  syscon_apmu: system-controller@d4282800 {
   compatible = "spacemit,k1-syscon-apmu";
   reg = <0x0 0xd4282800 0x0 0x400>;
   clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
     <&vctcxo_24m>;
   clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
          "vctcxo_24m";
   #clock-cells = <1>;
   #power-domain-cells = <1>;
   #reset-cells = <1>;
  };

  plic: interrupt-controller@e0000000 {
   compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
   reg = <0x0 0xe0000000 0x0 0x4000000>;
   interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
           <&cpu1_intc 11>, <&cpu1_intc 9>,
           <&cpu2_intc 11>, <&cpu2_intc 9>,
           <&cpu3_intc 11>, <&cpu3_intc 9>,
           <&cpu4_intc 11>, <&cpu4_intc 9>,
           <&cpu5_intc 11>, <&cpu5_intc 9>,
           <&cpu6_intc 11>, <&cpu6_intc 9>,
           <&cpu7_intc 11>, <&cpu7_intc 9>;
   interrupt-controller;
   #address-cells = <0>;
   #interrupt-cells = <1>;
   riscv,ndev = <159>;
  };

  clint: timer@e4000000 {
   compatible = "spacemit,k1-clint", "sifive,clint0";
   reg = <0x0 0xe4000000 0x0 0x10000>;
   interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
           <&cpu1_intc 3>, <&cpu1_intc 7>,
           <&cpu2_intc 3>, <&cpu2_intc 7>,
           <&cpu3_intc 3>, <&cpu3_intc 7>,
           <&cpu4_intc 3>, <&cpu4_intc 7>,
           <&cpu5_intc 3>, <&cpu5_intc 7>,
           <&cpu6_intc 3>, <&cpu6_intc 7>,
           <&cpu7_intc 3>, <&cpu7_intc 7>;
  };

  syscon_apbc2: system-controller@f0610000 {
   compatible = "spacemit,k1-syscon-apbc2";
   reg = <0x0 0xf0610000 0x0 0x20>;
   #reset-cells = <1>;
  };

  camera-bus {
   compatible = "simple-bus";
   ranges;
   #address-cells = <2>;
   #size-cells = <2>;
   dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
         <0x0 0x80000000 0x1 0x00000000 0x1 0x80000000>;
  };

  dma-bus {
   compatible = "simple-bus";
   ranges;
   #address-cells = <2>;
   #size-cells = <2>;
   dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
         <0x1 0x00000000 0x1 0x80000000 0x3 0x00000000>;

   uart0: serial@d4017000 {
    compatible = "spacemit,k1-uart",
          "intel,xscale-uart";
    reg = <0x0 0xd4017000 0x0 0x100>;
    clocks = <&syscon_apbc CLK_UART0>,
      <&syscon_apbc CLK_UART0_BUS>;
    clock-names = "core", "bus";
    interrupts = <42>;
    reg-shift = <2>;
    reg-io-width = <4>;
    status = "disabled";
   };

   uart2: serial@d4017100 {
    compatible = "spacemit,k1-uart",
          "intel,xscale-uart";
    reg = <0x0 0xd4017100 0x0 0x100>;
    clocks = <&syscon_apbc CLK_UART2>,
      <&syscon_apbc CLK_UART2_BUS>;
    clock-names = "core", "bus";
    interrupts = <44>;
    reg-shift = <2>;
    reg-io-width = <4>;
    status = "disabled";
   };

   uart3: serial@d4017200 {
    compatible = "spacemit,k1-uart",
          "intel,xscale-uart";
    reg = <0x0 0xd4017200 0x0 0x100>;
    clocks = <&syscon_apbc CLK_UART3>,
      <&syscon_apbc CLK_UART3_BUS>;
    clock-names = "core", "bus";
    interrupts = <45>;
    reg-shift = <2>;
    reg-io-width = <4>;
    status = "disabled";
   };

   uart4: serial@d4017300 {
    compatible = "spacemit,k1-uart",
          "intel,xscale-uart";
    reg = <0x0 0xd4017300 0x0 0x100>;
    clocks = <&syscon_apbc CLK_UART4>,
      <&syscon_apbc CLK_UART4_BUS>;
    clock-names = "core", "bus";
    interrupts = <46>;
    reg-shift = <2>;
    reg-io-width = <4>;
    status = "disabled";
   };

   uart5: serial@d4017400 {
    compatible = "spacemit,k1-uart",
          "intel,xscale-uart";
    reg = <0x0 0xd4017400 0x0 0x100>;
    clocks = <&syscon_apbc CLK_UART5>,
      <&syscon_apbc CLK_UART5_BUS>;
    clock-names = "core", "bus";
    interrupts = <47>;
    reg-shift = <2>;
    reg-io-width = <4>;
    status = "disabled";
   };

   uart6: serial@d4017500 {
    compatible = "spacemit,k1-uart",
          "intel,xscale-uart";
    reg = <0x0 0xd4017500 0x0 0x100>;
    clocks = <&syscon_apbc CLK_UART6>,
      <&syscon_apbc CLK_UART6_BUS>;
    clock-names = "core", "bus";
    interrupts = <48>;
    reg-shift = <2>;
    reg-io-width = <4>;
    status = "disabled";
   };

   uart7: serial@d4017600 {
    compatible = "spacemit,k1-uart",
          "intel,xscale-uart";
    reg = <0x0 0xd4017600 0x0 0x100>;
    clocks = <&syscon_apbc CLK_UART7>,
      <&syscon_apbc CLK_UART7_BUS>;
    clock-names = "core", "bus";
    interrupts = <49>;
    reg-shift = <2>;
    reg-io-width = <4>;
    status = "disabled";
   };

   uart8: serial@d4017700 {
    compatible = "spacemit,k1-uart",
          "intel,xscale-uart";
    reg = <0x0 0xd4017700 0x0 0x100>;
    clocks = <&syscon_apbc CLK_UART8>,
      <&syscon_apbc CLK_UART8_BUS>;
    clock-names = "core", "bus";
    interrupts = <50>;
    reg-shift = <2>;
    reg-io-width = <4>;
    status = "disabled";
   };

   uart9: serial@d4017800 {
    compatible = "spacemit,k1-uart",
          "intel,xscale-uart";
    reg = <0x0 0xd4017800 0x0 0x100>;
    clocks = <&syscon_apbc CLK_UART9>,
      <&syscon_apbc CLK_UART9_BUS>;
    clock-names = "core", "bus";
    interrupts = <51>;
    reg-shift = <2>;
    reg-io-width = <4>;
    status = "disabled";
   };

   sec_uart1: serial@f0612000 {
    compatible = "spacemit,k1-uart",
          "intel,xscale-uart";
    reg = <0x0 0xf0612000 0x0 0x100>;
    interrupts = <43>;
    clock-frequency = <14857000>;
    reg-shift = <2>;
    reg-io-width = <4>;
    status = "reserved"; /* for TEE usage */
   };
  };

  multimedia-bus {
   compatible = "simple-bus";
   ranges;
   #address-cells = <2>;
   #size-cells = <2>;
   dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
         <0x0 0x80000000 0x1 0x00000000 0x3 0x80000000>;
  };

  network-bus {
   compatible = "simple-bus";
   ranges;
   #address-cells = <2>;
   #size-cells = <2>;
   dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
         <0x0 0x80000000 0x1 0x00000000 0x0 0x80000000>;
  };

  pcie-bus {
   compatible = "simple-bus";
   ranges;
   #address-cells = <2>;
   #size-cells = <2>;
   dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
         <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>;
  };

  storage-bus {
   compatible = "simple-bus";
   ranges;
   #address-cells = <2>;
   #size-cells = <2>;
   dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;

   emmc: mmc@d4281000 {
    compatible = "spacemit,k1-sdhci";
    reg = <0x0 0xd4281000 0x0 0x200>;
    clocks = <&syscon_apmu CLK_SDH_AXI>,
      <&syscon_apmu CLK_SDH2>;
    clock-names = "core", "io";
    interrupts = <101>;
    status = "disabled";
   };
  };
 };
};