Quelle  uv_mmrs.h   Sprache: C

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * HPE UV MMR definitions
 *
 * (C) Copyright 2020 Hewlett Packard Enterprise Development LP
 * Copyright (C) 2007-2016 Silicon Graphics, Inc. All rights reserved.
 */

#ifndef _ASM_X86_UV_UV_MMRS_H
#define _ASM_X86_UV_UV_MMRS_H

/*
 * This file contains MMR definitions for all UV hubs types.
 *
 * To minimize coding differences between hub types, the symbols are
 * grouped by architecture types.
 *
 * UVH  - definitions common to all UV hub types.
 * UVXH - definitions common to UVX class (2, 3, 4).
 * UVYH - definitions common to UVY class (5).
 * UV5H - definitions specific to UV type 5 hub.
 * UV4AH - definitions specific to UV type 4A hub.
 * UV4H - definitions specific to UV type 4 hub.
 * UV3H - definitions specific to UV type 3 hub.
 * UV2H - definitions specific to UV type 2 hub.
 *
 * If the MMR exists on all hub types but have different addresses,
 * use a conditional operator to define the value at runtime.  Any
 * that are not defined are blank.
 * (UV4A variations only generated if different from uv4)
 * #define UVHxxx (
 * is_uv(UV5) ? UV5Hxxx value :
 * is_uv(UV4A) ? UV4AHxxx value :
 * is_uv(UV4) ? UV4Hxxx value :
 * is_uv(UV3) ? UV3Hxxx value :
 * is_uv(UV2) ? UV2Hxxx value :
 * <ucv> or <undef value>)
 *
 * Class UVX has UVs (2|3|4|4A).
 * Class UVY has UVs (5).
 *
 * union uvh_xxx {
 * unsigned long       v;
 * struct uvh_xxx_s {  # Common fields only
 * } s;
 * struct uv5h_xxx_s {  # Full UV5 definition (*)
 * } s5;
 * struct uv4ah_xxx_s {  # Full UV4A definition (*)
 * } s4a;
 * struct uv4h_xxx_s {  # Full UV4 definition (*)
 * } s4;
 * struct uv3h_xxx_s {  # Full UV3 definition (*)
 * } s3;
 * struct uv2h_xxx_s {  # Full UV2 definition (*)
 * } s2;
 * };
 * (* - if present and different than the common struct)
 *
 * Only essential differences are enumerated. For example, if the address is
 * the same for all UV's, only a single #define is generated. Likewise,
 * if the contents is the same for all hubs, only the "s" structure is
 * generated.
 *
 * (GEN Flags: undefs=function)
 */

 /* UV bit masks */
#define UV2 (1 << 0)
#define UV3 (1 << 1)
#define UV4 (1 << 2)
#define UV4A (1 << 3)
#define UV5 (1 << 4)
#define UVX (UV2|UV3|UV4)
#define UVY (UV5)
#define UV_ANY (~0)




#define UV_MMR_ENABLE  (1UL << 63)

#define UV1_HUB_PART_NUMBER 0x88a5
#define UV2_HUB_PART_NUMBER 0x8eb8
#define UV2_HUB_PART_NUMBER_X 0x1111
#define UV3_HUB_PART_NUMBER 0x9578
#define UV3_HUB_PART_NUMBER_X 0x4321
#define UV4_HUB_PART_NUMBER 0x99a1
#define UV5_HUB_PART_NUMBER 0xa171

/* Error function to catch undefined references */
extern unsigned long uv_undefined(char *str);

/* ========================================================================= */
/*                           UVH_EVENT_OCCURRED0                             */
/* ========================================================================= */
#define UVH_EVENT_OCCURRED0 0x70000UL

/* UVH common defines*/
#define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT  0
#define UVH_EVENT_OCCURRED0_LB_HCERR_MASK  0x0000000000000001UL

/* UVXH common defines */
#define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT  2
#define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK  0x0000000000000004UL
#define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT  3
#define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK  0x0000000000000008UL
#define UVXH_EVENT_OCCURRED0_LH1_HCERR_SHFT  4
#define UVXH_EVENT_OCCURRED0_LH1_HCERR_MASK  0x0000000000000010UL
#define UVXH_EVENT_OCCURRED0_GR0_HCERR_SHFT  5
#define UVXH_EVENT_OCCURRED0_GR0_HCERR_MASK  0x0000000000000020UL
#define UVXH_EVENT_OCCURRED0_GR1_HCERR_SHFT  6
#define UVXH_EVENT_OCCURRED0_GR1_HCERR_MASK  0x0000000000000040UL
#define UVXH_EVENT_OCCURRED0_NI0_HCERR_SHFT  7
#define UVXH_EVENT_OCCURRED0_NI0_HCERR_MASK  0x0000000000000080UL
#define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT  8
#define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK  0x0000000000000100UL
#define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT  9
#define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK  0x0000000000000200UL
#define UVXH_EVENT_OCCURRED0_RH_AOERR0_SHFT  11
#define UVXH_EVENT_OCCURRED0_RH_AOERR0_MASK  0x0000000000000800UL
#define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT  12
#define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK  0x0000000000001000UL
#define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT  13
#define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK  0x0000000000002000UL
#define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT  14
#define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK  0x0000000000004000UL
#define UVXH_EVENT_OCCURRED0_GR1_AOERR0_SHFT  15
#define UVXH_EVENT_OCCURRED0_GR1_AOERR0_MASK  0x0000000000008000UL
#define UVXH_EVENT_OCCURRED0_XB_AOERR0_SHFT  16
#define UVXH_EVENT_OCCURRED0_XB_AOERR0_MASK  0x0000000000010000UL

/* UVYH common defines */
#define UVYH_EVENT_OCCURRED0_KT_HCERR_SHFT  1
#define UVYH_EVENT_OCCURRED0_KT_HCERR_MASK  0x0000000000000002UL
#define UVYH_EVENT_OCCURRED0_RH0_HCERR_SHFT  2
#define UVYH_EVENT_OCCURRED0_RH0_HCERR_MASK  0x0000000000000004UL
#define UVYH_EVENT_OCCURRED0_RH1_HCERR_SHFT  3
#define UVYH_EVENT_OCCURRED0_RH1_HCERR_MASK  0x0000000000000008UL
#define UVYH_EVENT_OCCURRED0_LH0_HCERR_SHFT  4
#define UVYH_EVENT_OCCURRED0_LH0_HCERR_MASK  0x0000000000000010UL
#define UVYH_EVENT_OCCURRED0_LH1_HCERR_SHFT  5
#define UVYH_EVENT_OCCURRED0_LH1_HCERR_MASK  0x0000000000000020UL
#define UVYH_EVENT_OCCURRED0_LH2_HCERR_SHFT  6
#define UVYH_EVENT_OCCURRED0_LH2_HCERR_MASK  0x0000000000000040UL
#define UVYH_EVENT_OCCURRED0_LH3_HCERR_SHFT  7
#define UVYH_EVENT_OCCURRED0_LH3_HCERR_MASK  0x0000000000000080UL
#define UVYH_EVENT_OCCURRED0_XB_HCERR_SHFT  8
#define UVYH_EVENT_OCCURRED0_XB_HCERR_MASK  0x0000000000000100UL
#define UVYH_EVENT_OCCURRED0_RDM_HCERR_SHFT  9
#define UVYH_EVENT_OCCURRED0_RDM_HCERR_MASK  0x0000000000000200UL
#define UVYH_EVENT_OCCURRED0_NI0_HCERR_SHFT  10
#define UVYH_EVENT_OCCURRED0_NI0_HCERR_MASK  0x0000000000000400UL
#define UVYH_EVENT_OCCURRED0_NI1_HCERR_SHFT  11
#define UVYH_EVENT_OCCURRED0_NI1_HCERR_MASK  0x0000000000000800UL
#define UVYH_EVENT_OCCURRED0_LB_AOERR0_SHFT  12
#define UVYH_EVENT_OCCURRED0_LB_AOERR0_MASK  0x0000000000001000UL
#define UVYH_EVENT_OCCURRED0_KT_AOERR0_SHFT  13
#define UVYH_EVENT_OCCURRED0_KT_AOERR0_MASK  0x0000000000002000UL
#define UVYH_EVENT_OCCURRED0_RH0_AOERR0_SHFT  14
#define UVYH_EVENT_OCCURRED0_RH0_AOERR0_MASK  0x0000000000004000UL
#define UVYH_EVENT_OCCURRED0_RH1_AOERR0_SHFT  15
#define UVYH_EVENT_OCCURRED0_RH1_AOERR0_MASK  0x0000000000008000UL
#define UVYH_EVENT_OCCURRED0_LH0_AOERR0_SHFT  16
#define UVYH_EVENT_OCCURRED0_LH0_AOERR0_MASK  0x0000000000010000UL
#define UVYH_EVENT_OCCURRED0_LH1_AOERR0_SHFT  17
#define UVYH_EVENT_OCCURRED0_LH1_AOERR0_MASK  0x0000000000020000UL
#define UVYH_EVENT_OCCURRED0_LH2_AOERR0_SHFT  18
#define UVYH_EVENT_OCCURRED0_LH2_AOERR0_MASK  0x0000000000040000UL
#define UVYH_EVENT_OCCURRED0_LH3_AOERR0_SHFT  19
#define UVYH_EVENT_OCCURRED0_LH3_AOERR0_MASK  0x0000000000080000UL
#define UVYH_EVENT_OCCURRED0_XB_AOERR0_SHFT  20
#define UVYH_EVENT_OCCURRED0_XB_AOERR0_MASK  0x0000000000100000UL
#define UVYH_EVENT_OCCURRED0_RDM_AOERR0_SHFT  21
#define UVYH_EVENT_OCCURRED0_RDM_AOERR0_MASK  0x0000000000200000UL
#define UVYH_EVENT_OCCURRED0_RT0_AOERR0_SHFT  22
#define UVYH_EVENT_OCCURRED0_RT0_AOERR0_MASK  0x0000000000400000UL
#define UVYH_EVENT_OCCURRED0_RT1_AOERR0_SHFT  23
#define UVYH_EVENT_OCCURRED0_RT1_AOERR0_MASK  0x0000000000800000UL
#define UVYH_EVENT_OCCURRED0_NI0_AOERR0_SHFT  24
#define UVYH_EVENT_OCCURRED0_NI0_AOERR0_MASK  0x0000000001000000UL
#define UVYH_EVENT_OCCURRED0_NI1_AOERR0_SHFT  25
#define UVYH_EVENT_OCCURRED0_NI1_AOERR0_MASK  0x0000000002000000UL
#define UVYH_EVENT_OCCURRED0_LB_AOERR1_SHFT  26
#define UVYH_EVENT_OCCURRED0_LB_AOERR1_MASK  0x0000000004000000UL
#define UVYH_EVENT_OCCURRED0_KT_AOERR1_SHFT  27
#define UVYH_EVENT_OCCURRED0_KT_AOERR1_MASK  0x0000000008000000UL
#define UVYH_EVENT_OCCURRED0_RH0_AOERR1_SHFT  28
#define UVYH_EVENT_OCCURRED0_RH0_AOERR1_MASK  0x0000000010000000UL
#define UVYH_EVENT_OCCURRED0_RH1_AOERR1_SHFT  29
#define UVYH_EVENT_OCCURRED0_RH1_AOERR1_MASK  0x0000000020000000UL
#define UVYH_EVENT_OCCURRED0_LH0_AOERR1_SHFT  30
#define UVYH_EVENT_OCCURRED0_LH0_AOERR1_MASK  0x0000000040000000UL
#define UVYH_EVENT_OCCURRED0_LH1_AOERR1_SHFT  31
#define UVYH_EVENT_OCCURRED0_LH1_AOERR1_MASK  0x0000000080000000UL
#define UVYH_EVENT_OCCURRED0_LH2_AOERR1_SHFT  32
#define UVYH_EVENT_OCCURRED0_LH2_AOERR1_MASK  0x0000000100000000UL
#define UVYH_EVENT_OCCURRED0_LH3_AOERR1_SHFT  33
#define UVYH_EVENT_OCCURRED0_LH3_AOERR1_MASK  0x0000000200000000UL
#define UVYH_EVENT_OCCURRED0_XB_AOERR1_SHFT  34
#define UVYH_EVENT_OCCURRED0_XB_AOERR1_MASK  0x0000000400000000UL
#define UVYH_EVENT_OCCURRED0_RDM_AOERR1_SHFT  35
#define UVYH_EVENT_OCCURRED0_RDM_AOERR1_MASK  0x0000000800000000UL
#define UVYH_EVENT_OCCURRED0_RT0_AOERR1_SHFT  36
#define UVYH_EVENT_OCCURRED0_RT0_AOERR1_MASK  0x0000001000000000UL
#define UVYH_EVENT_OCCURRED0_RT1_AOERR1_SHFT  37
#define UVYH_EVENT_OCCURRED0_RT1_AOERR1_MASK  0x0000002000000000UL
#define UVYH_EVENT_OCCURRED0_NI0_AOERR1_SHFT  38
#define UVYH_EVENT_OCCURRED0_NI0_AOERR1_MASK  0x0000004000000000UL
#define UVYH_EVENT_OCCURRED0_NI1_AOERR1_SHFT  39
#define UVYH_EVENT_OCCURRED0_NI1_AOERR1_MASK  0x0000008000000000UL
#define UVYH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 40
#define UVYH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000010000000000UL
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT  41
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK  0x0000020000000000UL
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT  42
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK  0x0000040000000000UL
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT  43
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK  0x0000080000000000UL
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT  44
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK  0x0000100000000000UL
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT  45
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK  0x0000200000000000UL
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT  46
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK  0x0000400000000000UL
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT  47
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK  0x0000800000000000UL
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT  48
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK  0x0001000000000000UL
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT  49
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK  0x0002000000000000UL
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT  50
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK  0x0004000000000000UL
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT  51
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK  0x0008000000000000UL
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT  52
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK  0x0010000000000000UL
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT  53
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK  0x0020000000000000UL
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT  54
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK  0x0040000000000000UL
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT  55
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK  0x0080000000000000UL
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT  56
#define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK  0x0100000000000000UL
#define UVYH_EVENT_OCCURRED0_L1_NMI_INT_SHFT  57
#define UVYH_EVENT_OCCURRED0_L1_NMI_INT_MASK  0x0200000000000000UL
#define UVYH_EVENT_OCCURRED0_STOP_CLOCK_SHFT  58
#define UVYH_EVENT_OCCURRED0_STOP_CLOCK_MASK  0x0400000000000000UL
#define UVYH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT  59
#define UVYH_EVENT_OCCURRED0_ASIC_TO_L1_MASK  0x0800000000000000UL
#define UVYH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT  60
#define UVYH_EVENT_OCCURRED0_L1_TO_ASIC_MASK  0x1000000000000000UL
#define UVYH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 61
#define UVYH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x2000000000000000UL

/* UV4 unique defines */
#define UV4H_EVENT_OCCURRED0_KT_HCERR_SHFT  1
#define UV4H_EVENT_OCCURRED0_KT_HCERR_MASK  0x0000000000000002UL
#define UV4H_EVENT_OCCURRED0_KT_AOERR0_SHFT  10
#define UV4H_EVENT_OCCURRED0_KT_AOERR0_MASK  0x0000000000000400UL
#define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_SHFT  17
#define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_MASK  0x0000000000020000UL
#define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_SHFT  18
#define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_MASK  0x0000000000040000UL
#define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_SHFT  19
#define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_MASK  0x0000000000080000UL
#define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_SHFT  20
#define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_MASK  0x0000000000100000UL
#define UV4H_EVENT_OCCURRED0_NI0_AOERR0_SHFT  21
#define UV4H_EVENT_OCCURRED0_NI0_AOERR0_MASK  0x0000000000200000UL
#define UV4H_EVENT_OCCURRED0_NI1_AOERR0_SHFT  22
#define UV4H_EVENT_OCCURRED0_NI1_AOERR0_MASK  0x0000000000400000UL
#define UV4H_EVENT_OCCURRED0_LB_AOERR1_SHFT  23
#define UV4H_EVENT_OCCURRED0_LB_AOERR1_MASK  0x0000000000800000UL
#define UV4H_EVENT_OCCURRED0_KT_AOERR1_SHFT  24
#define UV4H_EVENT_OCCURRED0_KT_AOERR1_MASK  0x0000000001000000UL
#define UV4H_EVENT_OCCURRED0_RH_AOERR1_SHFT  25
#define UV4H_EVENT_OCCURRED0_RH_AOERR1_MASK  0x0000000002000000UL
#define UV4H_EVENT_OCCURRED0_LH0_AOERR1_SHFT  26
#define UV4H_EVENT_OCCURRED0_LH0_AOERR1_MASK  0x0000000004000000UL
#define UV4H_EVENT_OCCURRED0_LH1_AOERR1_SHFT  27
#define UV4H_EVENT_OCCURRED0_LH1_AOERR1_MASK  0x0000000008000000UL
#define UV4H_EVENT_OCCURRED0_GR0_AOERR1_SHFT  28
#define UV4H_EVENT_OCCURRED0_GR0_AOERR1_MASK  0x0000000010000000UL
#define UV4H_EVENT_OCCURRED0_GR1_AOERR1_SHFT  29
#define UV4H_EVENT_OCCURRED0_GR1_AOERR1_MASK  0x0000000020000000UL
#define UV4H_EVENT_OCCURRED0_XB_AOERR1_SHFT  30
#define UV4H_EVENT_OCCURRED0_XB_AOERR1_MASK  0x0000000040000000UL
#define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_SHFT  31
#define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_MASK  0x0000000080000000UL
#define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_SHFT  32
#define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_MASK  0x0000000100000000UL
#define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_SHFT  33
#define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_MASK  0x0000000200000000UL
#define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_SHFT  34
#define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_MASK  0x0000000400000000UL
#define UV4H_EVENT_OCCURRED0_NI0_AOERR1_SHFT  35
#define UV4H_EVENT_OCCURRED0_NI0_AOERR1_MASK  0x0000000800000000UL
#define UV4H_EVENT_OCCURRED0_NI1_AOERR1_SHFT  36
#define UV4H_EVENT_OCCURRED0_NI1_AOERR1_MASK  0x0000001000000000UL
#define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 37
#define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000002000000000UL
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT  38
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK  0x0000004000000000UL
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT  39
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK  0x0000008000000000UL
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT  40
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK  0x0000010000000000UL
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT  41
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK  0x0000020000000000UL
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT  42
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK  0x0000040000000000UL
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT  43
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK  0x0000080000000000UL
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT  44
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK  0x0000100000000000UL
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT  45
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK  0x0000200000000000UL
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT  46
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK  0x0000400000000000UL
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT  47
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK  0x0000800000000000UL
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT  48
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK  0x0001000000000000UL
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT  49
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK  0x0002000000000000UL
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT  50
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK  0x0004000000000000UL
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT  51
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK  0x0008000000000000UL
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT  52
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK  0x0010000000000000UL
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT  53
#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK  0x0020000000000000UL
#define UV4H_EVENT_OCCURRED0_L1_NMI_INT_SHFT  54
#define UV4H_EVENT_OCCURRED0_L1_NMI_INT_MASK  0x0040000000000000UL
#define UV4H_EVENT_OCCURRED0_STOP_CLOCK_SHFT  55
#define UV4H_EVENT_OCCURRED0_STOP_CLOCK_MASK  0x0080000000000000UL
#define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT  56
#define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_MASK  0x0100000000000000UL
#define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT  57
#define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_MASK  0x0200000000000000UL
#define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 58
#define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0400000000000000UL
#define UV4H_EVENT_OCCURRED0_IPI_INT_SHFT  59
#define UV4H_EVENT_OCCURRED0_IPI_INT_MASK  0x0800000000000000UL
#define UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT  60
#define UV4H_EVENT_OCCURRED0_EXTIO_INT0_MASK  0x1000000000000000UL
#define UV4H_EVENT_OCCURRED0_EXTIO_INT1_SHFT  61
#define UV4H_EVENT_OCCURRED0_EXTIO_INT1_MASK  0x2000000000000000UL
#define UV4H_EVENT_OCCURRED0_EXTIO_INT2_SHFT  62
#define UV4H_EVENT_OCCURRED0_EXTIO_INT2_MASK  0x4000000000000000UL
#define UV4H_EVENT_OCCURRED0_EXTIO_INT3_SHFT  63
#define UV4H_EVENT_OCCURRED0_EXTIO_INT3_MASK  0x8000000000000000UL

/* UV3 unique defines */
#define UV3H_EVENT_OCCURRED0_QP_HCERR_SHFT  1
#define UV3H_EVENT_OCCURRED0_QP_HCERR_MASK  0x0000000000000002UL
#define UV3H_EVENT_OCCURRED0_QP_AOERR0_SHFT  10
#define UV3H_EVENT_OCCURRED0_QP_AOERR0_MASK  0x0000000000000400UL
#define UV3H_EVENT_OCCURRED0_RT_AOERR0_SHFT  17
#define UV3H_EVENT_OCCURRED0_RT_AOERR0_MASK  0x0000000000020000UL
#define UV3H_EVENT_OCCURRED0_NI0_AOERR0_SHFT  18
#define UV3H_EVENT_OCCURRED0_NI0_AOERR0_MASK  0x0000000000040000UL
#define UV3H_EVENT_OCCURRED0_NI1_AOERR0_SHFT  19
#define UV3H_EVENT_OCCURRED0_NI1_AOERR0_MASK  0x0000000000080000UL
#define UV3H_EVENT_OCCURRED0_LB_AOERR1_SHFT  20
#define UV3H_EVENT_OCCURRED0_LB_AOERR1_MASK  0x0000000000100000UL
#define UV3H_EVENT_OCCURRED0_QP_AOERR1_SHFT  21
#define UV3H_EVENT_OCCURRED0_QP_AOERR1_MASK  0x0000000000200000UL
#define UV3H_EVENT_OCCURRED0_RH_AOERR1_SHFT  22
#define UV3H_EVENT_OCCURRED0_RH_AOERR1_MASK  0x0000000000400000UL
#define UV3H_EVENT_OCCURRED0_LH0_AOERR1_SHFT  23
#define UV3H_EVENT_OCCURRED0_LH0_AOERR1_MASK  0x0000000000800000UL
#define UV3H_EVENT_OCCURRED0_LH1_AOERR1_SHFT  24
#define UV3H_EVENT_OCCURRED0_LH1_AOERR1_MASK  0x0000000001000000UL
#define UV3H_EVENT_OCCURRED0_GR0_AOERR1_SHFT  25
#define UV3H_EVENT_OCCURRED0_GR0_AOERR1_MASK  0x0000000002000000UL
#define UV3H_EVENT_OCCURRED0_GR1_AOERR1_SHFT  26
#define UV3H_EVENT_OCCURRED0_GR1_AOERR1_MASK  0x0000000004000000UL
#define UV3H_EVENT_OCCURRED0_XB_AOERR1_SHFT  27
#define UV3H_EVENT_OCCURRED0_XB_AOERR1_MASK  0x0000000008000000UL
#define UV3H_EVENT_OCCURRED0_RT_AOERR1_SHFT  28
#define UV3H_EVENT_OCCURRED0_RT_AOERR1_MASK  0x0000000010000000UL
#define UV3H_EVENT_OCCURRED0_NI0_AOERR1_SHFT  29
#define UV3H_EVENT_OCCURRED0_NI0_AOERR1_MASK  0x0000000020000000UL
#define UV3H_EVENT_OCCURRED0_NI1_AOERR1_SHFT  30
#define UV3H_EVENT_OCCURRED0_NI1_AOERR1_MASK  0x0000000040000000UL
#define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31
#define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT  32
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK  0x0000000100000000UL
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT  33
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK  0x0000000200000000UL
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT  34
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK  0x0000000400000000UL
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT  35
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK  0x0000000800000000UL
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT  36
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK  0x0000001000000000UL
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT  37
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK  0x0000002000000000UL
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT  38
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK  0x0000004000000000UL
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT  39
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK  0x0000008000000000UL
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT  40
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK  0x0000010000000000UL
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT  41
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK  0x0000020000000000UL
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT  42
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK  0x0000040000000000UL
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT  43
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK  0x0000080000000000UL
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT  44
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK  0x0000100000000000UL
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT  45
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK  0x0000200000000000UL
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT  46
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK  0x0000400000000000UL
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT  47
#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK  0x0000800000000000UL
#define UV3H_EVENT_OCCURRED0_L1_NMI_INT_SHFT  48
#define UV3H_EVENT_OCCURRED0_L1_NMI_INT_MASK  0x0001000000000000UL
#define UV3H_EVENT_OCCURRED0_STOP_CLOCK_SHFT  49
#define UV3H_EVENT_OCCURRED0_STOP_CLOCK_MASK  0x0002000000000000UL
#define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT  50
#define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_MASK  0x0004000000000000UL
#define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT  51
#define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_MASK  0x0008000000000000UL
#define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52
#define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL
#define UV3H_EVENT_OCCURRED0_IPI_INT_SHFT  53
#define UV3H_EVENT_OCCURRED0_IPI_INT_MASK  0x0020000000000000UL
#define UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT  54
#define UV3H_EVENT_OCCURRED0_EXTIO_INT0_MASK  0x0040000000000000UL
#define UV3H_EVENT_OCCURRED0_EXTIO_INT1_SHFT  55
#define UV3H_EVENT_OCCURRED0_EXTIO_INT1_MASK  0x0080000000000000UL
#define UV3H_EVENT_OCCURRED0_EXTIO_INT2_SHFT  56
#define UV3H_EVENT_OCCURRED0_EXTIO_INT2_MASK  0x0100000000000000UL
#define UV3H_EVENT_OCCURRED0_EXTIO_INT3_SHFT  57
#define UV3H_EVENT_OCCURRED0_EXTIO_INT3_MASK  0x0200000000000000UL
#define UV3H_EVENT_OCCURRED0_PROFILE_INT_SHFT  58
#define UV3H_EVENT_OCCURRED0_PROFILE_INT_MASK  0x0400000000000000UL

/* UV2 unique defines */
#define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT  1
#define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK  0x0000000000000002UL
#define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT  10
#define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK  0x0000000000000400UL
#define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT  17
#define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK  0x0000000000020000UL
#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT  18
#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK  0x0000000000040000UL
#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT  19
#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK  0x0000000000080000UL
#define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT  20
#define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK  0x0000000000100000UL
#define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT  21
#define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK  0x0000000000200000UL
#define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT  22
#define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK  0x0000000000400000UL
#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT  23
#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK  0x0000000000800000UL
#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT  24
#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK  0x0000000001000000UL
#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT  25
#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK  0x0000000002000000UL
#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT  26
#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK  0x0000000004000000UL
#define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT  27
#define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK  0x0000000008000000UL
#define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT  28
#define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK  0x0000000010000000UL
#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT  29
#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK  0x0000000020000000UL
#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT  30
#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK  0x0000000040000000UL
#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31
#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT  32
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK  0x0000000100000000UL
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT  33
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK  0x0000000200000000UL
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT  34
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK  0x0000000400000000UL
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT  35
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK  0x0000000800000000UL
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT  36
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK  0x0000001000000000UL
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT  37
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK  0x0000002000000000UL
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT  38
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK  0x0000004000000000UL
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT  39
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK  0x0000008000000000UL
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT  40
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK  0x0000010000000000UL
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT  41
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK  0x0000020000000000UL
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT  42
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK  0x0000040000000000UL
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT  43
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK  0x0000080000000000UL
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT  44
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK  0x0000100000000000UL
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT  45
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK  0x0000200000000000UL
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT  46
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK  0x0000400000000000UL
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT  47
#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK  0x0000800000000000UL
#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT  48
#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK  0x0001000000000000UL
#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT  49
#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK  0x0002000000000000UL
#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT  50
#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK  0x0004000000000000UL
#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT  51
#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK  0x0008000000000000UL
#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52
#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL
#define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT  53
#define UV2H_EVENT_OCCURRED0_IPI_INT_MASK  0x0020000000000000UL
#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT  54
#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK  0x0040000000000000UL
#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT  55
#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK  0x0080000000000000UL
#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT  56
#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK  0x0100000000000000UL
#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT  57
#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK  0x0200000000000000UL
#define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT  58
#define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK  0x0400000000000000UL

#define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK (    \
 is_uv(UV4) ? 0x1000000000000000UL :    \
 is_uv(UV3) ? 0x0040000000000000UL :    \
 is_uv(UV2) ? 0x0040000000000000UL :    \
 0)
#define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT (    \
 is_uv(UV4) ? 60 :      \
 is_uv(UV3) ? 54 :      \
 is_uv(UV2) ? 54 :      \
 -1)

union uvh_event_occurred0_u {
 unsigned long v;

 /* UVH common struct */
 struct uvh_event_occurred0_s {
  unsigned long lb_hcerr:1;   /* RW */
  unsigned long rsvd_1_63:63;
 } s;

 /* UVXH common struct */
 struct uvxh_event_occurred0_s {
  unsigned long lb_hcerr:1;   /* RW */
  unsigned long rsvd_1:1;
  unsigned long rh_hcerr:1;   /* RW */
  unsigned long lh0_hcerr:1;   /* RW */
  unsigned long lh1_hcerr:1;   /* RW */
  unsigned long gr0_hcerr:1;   /* RW */
  unsigned long gr1_hcerr:1;   /* RW */
  unsigned long ni0_hcerr:1;   /* RW */
  unsigned long ni1_hcerr:1;   /* RW */
  unsigned long lb_aoerr0:1;   /* RW */
  unsigned long rsvd_10:1;
  unsigned long rh_aoerr0:1;   /* RW */
  unsigned long lh0_aoerr0:1;   /* RW */
  unsigned long lh1_aoerr0:1;   /* RW */
  unsigned long gr0_aoerr0:1;   /* RW */
  unsigned long gr1_aoerr0:1;   /* RW */
  unsigned long xb_aoerr0:1;   /* RW */
  unsigned long rsvd_17_63:47;
 } sx;

 /* UVYH common struct */
 struct uvyh_event_occurred0_s {
  unsigned long lb_hcerr:1;   /* RW */
  unsigned long kt_hcerr:1;   /* RW */
  unsigned long rh0_hcerr:1;   /* RW */
  unsigned long rh1_hcerr:1;   /* RW */
  unsigned long lh0_hcerr:1;   /* RW */
  unsigned long lh1_hcerr:1;   /* RW */
  unsigned long lh2_hcerr:1;   /* RW */
  unsigned long lh3_hcerr:1;   /* RW */
  unsigned long xb_hcerr:1;   /* RW */
  unsigned long rdm_hcerr:1;   /* RW */
  unsigned long ni0_hcerr:1;   /* RW */
  unsigned long ni1_hcerr:1;   /* RW */
  unsigned long lb_aoerr0:1;   /* RW */
  unsigned long kt_aoerr0:1;   /* RW */
  unsigned long rh0_aoerr0:1;   /* RW */
  unsigned long rh1_aoerr0:1;   /* RW */
  unsigned long lh0_aoerr0:1;   /* RW */
  unsigned long lh1_aoerr0:1;   /* RW */
  unsigned long lh2_aoerr0:1;   /* RW */
  unsigned long lh3_aoerr0:1;   /* RW */
  unsigned long xb_aoerr0:1;   /* RW */
  unsigned long rdm_aoerr0:1;   /* RW */
  unsigned long rt0_aoerr0:1;   /* RW */
  unsigned long rt1_aoerr0:1;   /* RW */
  unsigned long ni0_aoerr0:1;   /* RW */
  unsigned long ni1_aoerr0:1;   /* RW */
  unsigned long lb_aoerr1:1;   /* RW */
  unsigned long kt_aoerr1:1;   /* RW */
  unsigned long rh0_aoerr1:1;   /* RW */
  unsigned long rh1_aoerr1:1;   /* RW */
  unsigned long lh0_aoerr1:1;   /* RW */
  unsigned long lh1_aoerr1:1;   /* RW */
  unsigned long lh2_aoerr1:1;   /* RW */
  unsigned long lh3_aoerr1:1;   /* RW */
  unsigned long xb_aoerr1:1;   /* RW */
  unsigned long rdm_aoerr1:1;   /* RW */
  unsigned long rt0_aoerr1:1;   /* RW */
  unsigned long rt1_aoerr1:1;   /* RW */
  unsigned long ni0_aoerr1:1;   /* RW */
  unsigned long ni1_aoerr1:1;   /* RW */
  unsigned long system_shutdown_int:1;  /* RW */
  unsigned long lb_irq_int_0:1;   /* RW */
  unsigned long lb_irq_int_1:1;   /* RW */
  unsigned long lb_irq_int_2:1;   /* RW */
  unsigned long lb_irq_int_3:1;   /* RW */
  unsigned long lb_irq_int_4:1;   /* RW */
  unsigned long lb_irq_int_5:1;   /* RW */
  unsigned long lb_irq_int_6:1;   /* RW */
  unsigned long lb_irq_int_7:1;   /* RW */
  unsigned long lb_irq_int_8:1;   /* RW */
  unsigned long lb_irq_int_9:1;   /* RW */
  unsigned long lb_irq_int_10:1;  /* RW */
  unsigned long lb_irq_int_11:1;  /* RW */
  unsigned long lb_irq_int_12:1;  /* RW */
  unsigned long lb_irq_int_13:1;  /* RW */
  unsigned long lb_irq_int_14:1;  /* RW */
  unsigned long lb_irq_int_15:1;  /* RW */
  unsigned long l1_nmi_int:1;   /* RW */
  unsigned long stop_clock:1;   /* RW */
  unsigned long asic_to_l1:1;   /* RW */
  unsigned long l1_to_asic:1;   /* RW */
  unsigned long la_seq_trigger:1;  /* RW */
  unsigned long rsvd_62_63:2;
 } sy;

 /* UV5 unique struct */
 struct uv5h_event_occurred0_s {
  unsigned long lb_hcerr:1;   /* RW */
  unsigned long kt_hcerr:1;   /* RW */
  unsigned long rh0_hcerr:1;   /* RW */
  unsigned long rh1_hcerr:1;   /* RW */
  unsigned long lh0_hcerr:1;   /* RW */
  unsigned long lh1_hcerr:1;   /* RW */
  unsigned long lh2_hcerr:1;   /* RW */
  unsigned long lh3_hcerr:1;   /* RW */
  unsigned long xb_hcerr:1;   /* RW */
  unsigned long rdm_hcerr:1;   /* RW */
  unsigned long ni0_hcerr:1;   /* RW */
  unsigned long ni1_hcerr:1;   /* RW */
  unsigned long lb_aoerr0:1;   /* RW */
  unsigned long kt_aoerr0:1;   /* RW */
  unsigned long rh0_aoerr0:1;   /* RW */
  unsigned long rh1_aoerr0:1;   /* RW */
  unsigned long lh0_aoerr0:1;   /* RW */
  unsigned long lh1_aoerr0:1;   /* RW */
  unsigned long lh2_aoerr0:1;   /* RW */
  unsigned long lh3_aoerr0:1;   /* RW */
  unsigned long xb_aoerr0:1;   /* RW */
  unsigned long rdm_aoerr0:1;   /* RW */
  unsigned long rt0_aoerr0:1;   /* RW */
  unsigned long rt1_aoerr0:1;   /* RW */
  unsigned long ni0_aoerr0:1;   /* RW */
  unsigned long ni1_aoerr0:1;   /* RW */
  unsigned long lb_aoerr1:1;   /* RW */
  unsigned long kt_aoerr1:1;   /* RW */
  unsigned long rh0_aoerr1:1;   /* RW */
  unsigned long rh1_aoerr1:1;   /* RW */
  unsigned long lh0_aoerr1:1;   /* RW */
  unsigned long lh1_aoerr1:1;   /* RW */
  unsigned long lh2_aoerr1:1;   /* RW */
  unsigned long lh3_aoerr1:1;   /* RW */
  unsigned long xb_aoerr1:1;   /* RW */
  unsigned long rdm_aoerr1:1;   /* RW */
  unsigned long rt0_aoerr1:1;   /* RW */
  unsigned long rt1_aoerr1:1;   /* RW */
  unsigned long ni0_aoerr1:1;   /* RW */
  unsigned long ni1_aoerr1:1;   /* RW */
  unsigned long system_shutdown_int:1;  /* RW */
  unsigned long lb_irq_int_0:1;   /* RW */
  unsigned long lb_irq_int_1:1;   /* RW */
  unsigned long lb_irq_int_2:1;   /* RW */
  unsigned long lb_irq_int_3:1;   /* RW */
  unsigned long lb_irq_int_4:1;   /* RW */
  unsigned long lb_irq_int_5:1;   /* RW */
  unsigned long lb_irq_int_6:1;   /* RW */
  unsigned long lb_irq_int_7:1;   /* RW */
  unsigned long lb_irq_int_8:1;   /* RW */
  unsigned long lb_irq_int_9:1;   /* RW */
  unsigned long lb_irq_int_10:1;  /* RW */
  unsigned long lb_irq_int_11:1;  /* RW */
  unsigned long lb_irq_int_12:1;  /* RW */
  unsigned long lb_irq_int_13:1;  /* RW */
  unsigned long lb_irq_int_14:1;  /* RW */
  unsigned long lb_irq_int_15:1;  /* RW */
  unsigned long l1_nmi_int:1;   /* RW */
  unsigned long stop_clock:1;   /* RW */
  unsigned long asic_to_l1:1;   /* RW */
  unsigned long l1_to_asic:1;   /* RW */
  unsigned long la_seq_trigger:1;  /* RW */
  unsigned long rsvd_62_63:2;
 } s5;

 /* UV4 unique struct */
 struct uv4h_event_occurred0_s {
  unsigned long lb_hcerr:1;   /* RW */
  unsigned long kt_hcerr:1;   /* RW */
  unsigned long rh_hcerr:1;   /* RW */
  unsigned long lh0_hcerr:1;   /* RW */
  unsigned long lh1_hcerr:1;   /* RW */
  unsigned long gr0_hcerr:1;   /* RW */
  unsigned long gr1_hcerr:1;   /* RW */
  unsigned long ni0_hcerr:1;   /* RW */
  unsigned long ni1_hcerr:1;   /* RW */
  unsigned long lb_aoerr0:1;   /* RW */
  unsigned long kt_aoerr0:1;   /* RW */
  unsigned long rh_aoerr0:1;   /* RW */
  unsigned long lh0_aoerr0:1;   /* RW */
  unsigned long lh1_aoerr0:1;   /* RW */
  unsigned long gr0_aoerr0:1;   /* RW */
  unsigned long gr1_aoerr0:1;   /* RW */
  unsigned long xb_aoerr0:1;   /* RW */
  unsigned long rtq0_aoerr0:1;   /* RW */
  unsigned long rtq1_aoerr0:1;   /* RW */
  unsigned long rtq2_aoerr0:1;   /* RW */
  unsigned long rtq3_aoerr0:1;   /* RW */
  unsigned long ni0_aoerr0:1;   /* RW */
  unsigned long ni1_aoerr0:1;   /* RW */
  unsigned long lb_aoerr1:1;   /* RW */
  unsigned long kt_aoerr1:1;   /* RW */
  unsigned long rh_aoerr1:1;   /* RW */
  unsigned long lh0_aoerr1:1;   /* RW */
  unsigned long lh1_aoerr1:1;   /* RW */
  unsigned long gr0_aoerr1:1;   /* RW */
  unsigned long gr1_aoerr1:1;   /* RW */
  unsigned long xb_aoerr1:1;   /* RW */
  unsigned long rtq0_aoerr1:1;   /* RW */
  unsigned long rtq1_aoerr1:1;   /* RW */
  unsigned long rtq2_aoerr1:1;   /* RW */
  unsigned long rtq3_aoerr1:1;   /* RW */
  unsigned long ni0_aoerr1:1;   /* RW */
  unsigned long ni1_aoerr1:1;   /* RW */
  unsigned long system_shutdown_int:1;  /* RW */
  unsigned long lb_irq_int_0:1;   /* RW */
  unsigned long lb_irq_int_1:1;   /* RW */
  unsigned long lb_irq_int_2:1;   /* RW */
  unsigned long lb_irq_int_3:1;   /* RW */
  unsigned long lb_irq_int_4:1;   /* RW */
  unsigned long lb_irq_int_5:1;   /* RW */
  unsigned long lb_irq_int_6:1;   /* RW */
  unsigned long lb_irq_int_7:1;   /* RW */
  unsigned long lb_irq_int_8:1;   /* RW */
  unsigned long lb_irq_int_9:1;   /* RW */
  unsigned long lb_irq_int_10:1;  /* RW */
  unsigned long lb_irq_int_11:1;  /* RW */
  unsigned long lb_irq_int_12:1;  /* RW */
  unsigned long lb_irq_int_13:1;  /* RW */
  unsigned long lb_irq_int_14:1;  /* RW */
  unsigned long lb_irq_int_15:1;  /* RW */
  unsigned long l1_nmi_int:1;   /* RW */
  unsigned long stop_clock:1;   /* RW */
  unsigned long asic_to_l1:1;   /* RW */
  unsigned long l1_to_asic:1;   /* RW */
  unsigned long la_seq_trigger:1;  /* RW */
  unsigned long ipi_int:1;   /* RW */
  unsigned long extio_int0:1;   /* RW */
  unsigned long extio_int1:1;   /* RW */
  unsigned long extio_int2:1;   /* RW */
  unsigned long extio_int3:1;   /* RW */
 } s4;

 /* UV3 unique struct */
 struct uv3h_event_occurred0_s {
  unsigned long lb_hcerr:1;   /* RW */
  unsigned long qp_hcerr:1;   /* RW */
  unsigned long rh_hcerr:1;   /* RW */
  unsigned long lh0_hcerr:1;   /* RW */
  unsigned long lh1_hcerr:1;   /* RW */
  unsigned long gr0_hcerr:1;   /* RW */
  unsigned long gr1_hcerr:1;   /* RW */
  unsigned long ni0_hcerr:1;   /* RW */
  unsigned long ni1_hcerr:1;   /* RW */
  unsigned long lb_aoerr0:1;   /* RW */
  unsigned long qp_aoerr0:1;   /* RW */
  unsigned long rh_aoerr0:1;   /* RW */
  unsigned long lh0_aoerr0:1;   /* RW */
  unsigned long lh1_aoerr0:1;   /* RW */
  unsigned long gr0_aoerr0:1;   /* RW */
  unsigned long gr1_aoerr0:1;   /* RW */
  unsigned long xb_aoerr0:1;   /* RW */
  unsigned long rt_aoerr0:1;   /* RW */
  unsigned long ni0_aoerr0:1;   /* RW */
  unsigned long ni1_aoerr0:1;   /* RW */
  unsigned long lb_aoerr1:1;   /* RW */
  unsigned long qp_aoerr1:1;   /* RW */
  unsigned long rh_aoerr1:1;   /* RW */
  unsigned long lh0_aoerr1:1;   /* RW */
  unsigned long lh1_aoerr1:1;   /* RW */
  unsigned long gr0_aoerr1:1;   /* RW */
  unsigned long gr1_aoerr1:1;   /* RW */
  unsigned long xb_aoerr1:1;   /* RW */
  unsigned long rt_aoerr1:1;   /* RW */
  unsigned long ni0_aoerr1:1;   /* RW */
  unsigned long ni1_aoerr1:1;   /* RW */
  unsigned long system_shutdown_int:1;  /* RW */
  unsigned long lb_irq_int_0:1;   /* RW */
  unsigned long lb_irq_int_1:1;   /* RW */
  unsigned long lb_irq_int_2:1;   /* RW */
  unsigned long lb_irq_int_3:1;   /* RW */
  unsigned long lb_irq_int_4:1;   /* RW */
  unsigned long lb_irq_int_5:1;   /* RW */
  unsigned long lb_irq_int_6:1;   /* RW */
  unsigned long lb_irq_int_7:1;   /* RW */
  unsigned long lb_irq_int_8:1;   /* RW */
  unsigned long lb_irq_int_9:1;   /* RW */
  unsigned long lb_irq_int_10:1;  /* RW */
  unsigned long lb_irq_int_11:1;  /* RW */
  unsigned long lb_irq_int_12:1;  /* RW */
  unsigned long lb_irq_int_13:1;  /* RW */
  unsigned long lb_irq_int_14:1;  /* RW */
  unsigned long lb_irq_int_15:1;  /* RW */
  unsigned long l1_nmi_int:1;   /* RW */
  unsigned long stop_clock:1;   /* RW */
  unsigned long asic_to_l1:1;   /* RW */
  unsigned long l1_to_asic:1;   /* RW */
  unsigned long la_seq_trigger:1;  /* RW */
  unsigned long ipi_int:1;   /* RW */
  unsigned long extio_int0:1;   /* RW */
  unsigned long extio_int1:1;   /* RW */
  unsigned long extio_int2:1;   /* RW */
  unsigned long extio_int3:1;   /* RW */
  unsigned long profile_int:1;   /* RW */
  unsigned long rsvd_59_63:5;
 } s3;

 /* UV2 unique struct */
 struct uv2h_event_occurred0_s {
  unsigned long lb_hcerr:1;   /* RW */
  unsigned long qp_hcerr:1;   /* RW */
  unsigned long rh_hcerr:1;   /* RW */
  unsigned long lh0_hcerr:1;   /* RW */
  unsigned long lh1_hcerr:1;   /* RW */
  unsigned long gr0_hcerr:1;   /* RW */
  unsigned long gr1_hcerr:1;   /* RW */
  unsigned long ni0_hcerr:1;   /* RW */
  unsigned long ni1_hcerr:1;   /* RW */
  unsigned long lb_aoerr0:1;   /* RW */
  unsigned long qp_aoerr0:1;   /* RW */
  unsigned long rh_aoerr0:1;   /* RW */
  unsigned long lh0_aoerr0:1;   /* RW */
  unsigned long lh1_aoerr0:1;   /* RW */
  unsigned long gr0_aoerr0:1;   /* RW */
  unsigned long gr1_aoerr0:1;   /* RW */
  unsigned long xb_aoerr0:1;   /* RW */
  unsigned long rt_aoerr0:1;   /* RW */
  unsigned long ni0_aoerr0:1;   /* RW */
  unsigned long ni1_aoerr0:1;   /* RW */
  unsigned long lb_aoerr1:1;   /* RW */
  unsigned long qp_aoerr1:1;   /* RW */
  unsigned long rh_aoerr1:1;   /* RW */
  unsigned long lh0_aoerr1:1;   /* RW */
  unsigned long lh1_aoerr1:1;   /* RW */
  unsigned long gr0_aoerr1:1;   /* RW */
  unsigned long gr1_aoerr1:1;   /* RW */
  unsigned long xb_aoerr1:1;   /* RW */
  unsigned long rt_aoerr1:1;   /* RW */
  unsigned long ni0_aoerr1:1;   /* RW */
  unsigned long ni1_aoerr1:1;   /* RW */
  unsigned long system_shutdown_int:1;  /* RW */
  unsigned long lb_irq_int_0:1;   /* RW */
  unsigned long lb_irq_int_1:1;   /* RW */
  unsigned long lb_irq_int_2:1;   /* RW */
  unsigned long lb_irq_int_3:1;   /* RW */
  unsigned long lb_irq_int_4:1;   /* RW */
  unsigned long lb_irq_int_5:1;   /* RW */
  unsigned long lb_irq_int_6:1;   /* RW */
  unsigned long lb_irq_int_7:1;   /* RW */
  unsigned long lb_irq_int_8:1;   /* RW */
  unsigned long lb_irq_int_9:1;   /* RW */
  unsigned long lb_irq_int_10:1;  /* RW */
  unsigned long lb_irq_int_11:1;  /* RW */
  unsigned long lb_irq_int_12:1;  /* RW */
  unsigned long lb_irq_int_13:1;  /* RW */
  unsigned long lb_irq_int_14:1;  /* RW */
  unsigned long lb_irq_int_15:1;  /* RW */
  unsigned long l1_nmi_int:1;   /* RW */
  unsigned long stop_clock:1;   /* RW */
  unsigned long asic_to_l1:1;   /* RW */
  unsigned long l1_to_asic:1;   /* RW */
  unsigned long la_seq_trigger:1;  /* RW */
  unsigned long ipi_int:1;   /* RW */
  unsigned long extio_int0:1;   /* RW */
  unsigned long extio_int1:1;   /* RW */
  unsigned long extio_int2:1;   /* RW */
  unsigned long extio_int3:1;   /* RW */
  unsigned long profile_int:1;   /* RW */
  unsigned long rsvd_59_63:5;
 } s2;
};

/* ========================================================================= */
/*                        UVH_EVENT_OCCURRED0_ALIAS                          */
/* ========================================================================= */
#define UVH_EVENT_OCCURRED0_ALIAS 0x70008UL


/* ========================================================================= */
/*                           UVH_EVENT_OCCURRED1                             */
/* ========================================================================= */
#define UVH_EVENT_OCCURRED1 0x70080UL



/* UVYH common defines */
#define UVYH_EVENT_OCCURRED1_IPI_INT_SHFT  0
#define UVYH_EVENT_OCCURRED1_IPI_INT_MASK  0x0000000000000001UL
#define UVYH_EVENT_OCCURRED1_EXTIO_INT0_SHFT  1
#define UVYH_EVENT_OCCURRED1_EXTIO_INT0_MASK  0x0000000000000002UL
#define UVYH_EVENT_OCCURRED1_EXTIO_INT1_SHFT  2
#define UVYH_EVENT_OCCURRED1_EXTIO_INT1_MASK  0x0000000000000004UL
#define UVYH_EVENT_OCCURRED1_EXTIO_INT2_SHFT  3
#define UVYH_EVENT_OCCURRED1_EXTIO_INT2_MASK  0x0000000000000008UL
#define UVYH_EVENT_OCCURRED1_EXTIO_INT3_SHFT  4
#define UVYH_EVENT_OCCURRED1_EXTIO_INT3_MASK  0x0000000000000010UL
#define UVYH_EVENT_OCCURRED1_PROFILE_INT_SHFT  5
#define UVYH_EVENT_OCCURRED1_PROFILE_INT_MASK  0x0000000000000020UL
#define UVYH_EVENT_OCCURRED1_BAU_DATA_SHFT  6
#define UVYH_EVENT_OCCURRED1_BAU_DATA_MASK  0x0000000000000040UL
#define UVYH_EVENT_OCCURRED1_PROC_GENERAL_SHFT  7
#define UVYH_EVENT_OCCURRED1_PROC_GENERAL_MASK  0x0000000000000080UL
#define UVYH_EVENT_OCCURRED1_XH_TLB_INT0_SHFT  8
#define UVYH_EVENT_OCCURRED1_XH_TLB_INT0_MASK  0x0000000000000100UL
#define UVYH_EVENT_OCCURRED1_XH_TLB_INT1_SHFT  9
#define UVYH_EVENT_OCCURRED1_XH_TLB_INT1_MASK  0x0000000000000200UL
#define UVYH_EVENT_OCCURRED1_XH_TLB_INT2_SHFT  10
#define UVYH_EVENT_OCCURRED1_XH_TLB_INT2_MASK  0x0000000000000400UL
#define UVYH_EVENT_OCCURRED1_XH_TLB_INT3_SHFT  11
#define UVYH_EVENT_OCCURRED1_XH_TLB_INT3_MASK  0x0000000000000800UL
#define UVYH_EVENT_OCCURRED1_XH_TLB_INT4_SHFT  12
#define UVYH_EVENT_OCCURRED1_XH_TLB_INT4_MASK  0x0000000000001000UL
#define UVYH_EVENT_OCCURRED1_XH_TLB_INT5_SHFT  13
#define UVYH_EVENT_OCCURRED1_XH_TLB_INT5_MASK  0x0000000000002000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT0_SHFT  14
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT0_MASK  0x0000000000004000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT1_SHFT  15
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT1_MASK  0x0000000000008000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT2_SHFT  16
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT2_MASK  0x0000000000010000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT3_SHFT  17
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT3_MASK  0x0000000000020000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT4_SHFT  18
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT4_MASK  0x0000000000040000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT5_SHFT  19
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT5_MASK  0x0000000000080000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT6_SHFT  20
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT6_MASK  0x0000000000100000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT7_SHFT  21
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT7_MASK  0x0000000000200000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT8_SHFT  22
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT8_MASK  0x0000000000400000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT9_SHFT  23
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT9_MASK  0x0000000000800000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT10_SHFT  24
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT10_MASK  0x0000000001000000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT11_SHFT  25
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT11_MASK  0x0000000002000000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT12_SHFT  26
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT12_MASK  0x0000000004000000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT13_SHFT  27
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT13_MASK  0x0000000008000000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT14_SHFT  28
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT14_MASK  0x0000000010000000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT15_SHFT  29
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT15_MASK  0x0000000020000000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT16_SHFT  30
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT16_MASK  0x0000000040000000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT17_SHFT  31
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT17_MASK  0x0000000080000000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT18_SHFT  32
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT18_MASK  0x0000000100000000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT19_SHFT  33
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT19_MASK  0x0000000200000000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT20_SHFT  34
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT20_MASK  0x0000000400000000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT21_SHFT  35
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT21_MASK  0x0000000800000000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT22_SHFT  36
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT22_MASK  0x0000001000000000UL
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT23_SHFT  37
#define UVYH_EVENT_OCCURRED1_RDM_TLB_INT23_MASK  0x0000002000000000UL

/* UV4 unique defines */
#define UV4H_EVENT_OCCURRED1_PROFILE_INT_SHFT  0
#define UV4H_EVENT_OCCURRED1_PROFILE_INT_MASK  0x0000000000000001UL
#define UV4H_EVENT_OCCURRED1_BAU_DATA_SHFT  1
#define UV4H_EVENT_OCCURRED1_BAU_DATA_MASK  0x0000000000000002UL
#define UV4H_EVENT_OCCURRED1_PROC_GENERAL_SHFT  2
#define UV4H_EVENT_OCCURRED1_PROC_GENERAL_MASK  0x0000000000000004UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT0_SHFT  3
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT0_MASK  0x0000000000000008UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT1_SHFT  4
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT1_MASK  0x0000000000000010UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT2_SHFT  5
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT2_MASK  0x0000000000000020UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT3_SHFT  6
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT3_MASK  0x0000000000000040UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT4_SHFT  7
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT4_MASK  0x0000000000000080UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT5_SHFT  8
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT5_MASK  0x0000000000000100UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT6_SHFT  9
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT6_MASK  0x0000000000000200UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT7_SHFT  10
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT7_MASK  0x0000000000000400UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT8_SHFT  11
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT8_MASK  0x0000000000000800UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT9_SHFT  12
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT9_MASK  0x0000000000001000UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT10_SHFT  13
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT10_MASK  0x0000000000002000UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT11_SHFT  14
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT11_MASK  0x0000000000004000UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT12_SHFT  15
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT12_MASK  0x0000000000008000UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT13_SHFT  16
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT13_MASK  0x0000000000010000UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT14_SHFT  17
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT14_MASK  0x0000000000020000UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT15_SHFT  18
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT15_MASK  0x0000000000040000UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT16_SHFT  19
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT16_MASK  0x0000000000080000UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT17_SHFT  20
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT17_MASK  0x0000000000100000UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT18_SHFT  21
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT18_MASK  0x0000000000200000UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT19_SHFT  22
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT19_MASK  0x0000000000400000UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT20_SHFT  23
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT20_MASK  0x0000000000800000UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT21_SHFT  24
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT21_MASK  0x0000000001000000UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT22_SHFT  25
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT22_MASK  0x0000000002000000UL
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT23_SHFT  26
#define UV4H_EVENT_OCCURRED1_GR0_TLB_INT23_MASK  0x0000000004000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT0_SHFT  27
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT0_MASK  0x0000000008000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT1_SHFT  28
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT1_MASK  0x0000000010000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT2_SHFT  29
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT2_MASK  0x0000000020000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT3_SHFT  30
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT3_MASK  0x0000000040000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT4_SHFT  31
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT4_MASK  0x0000000080000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT5_SHFT  32
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT5_MASK  0x0000000100000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT6_SHFT  33
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT6_MASK  0x0000000200000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT7_SHFT  34
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT7_MASK  0x0000000400000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT8_SHFT  35
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT8_MASK  0x0000000800000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT9_SHFT  36
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT9_MASK  0x0000001000000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT10_SHFT  37
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT10_MASK  0x0000002000000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT11_SHFT  38
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT11_MASK  0x0000004000000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT12_SHFT  39
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT12_MASK  0x0000008000000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT13_SHFT  40
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT13_MASK  0x0000010000000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT14_SHFT  41
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT14_MASK  0x0000020000000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT15_SHFT  42
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT15_MASK  0x0000040000000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT16_SHFT  43
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT16_MASK  0x0000080000000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT17_SHFT  44
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT17_MASK  0x0000100000000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT18_SHFT  45
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT18_MASK  0x0000200000000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT19_SHFT  46
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT19_MASK  0x0000400000000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT20_SHFT  47
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT20_MASK  0x0000800000000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT21_SHFT  48
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT21_MASK  0x0001000000000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT22_SHFT  49
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT22_MASK  0x0002000000000000UL
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT23_SHFT  50
#define UV4H_EVENT_OCCURRED1_GR1_TLB_INT23_MASK  0x0004000000000000UL

/* UV3 unique defines */
#define UV3H_EVENT_OCCURRED1_BAU_DATA_SHFT  0
#define UV3H_EVENT_OCCURRED1_BAU_DATA_MASK  0x0000000000000001UL
#define UV3H_EVENT_OCCURRED1_POWER_MANAGEMENT_REQ_SHFT 1
#define UV3H_EVENT_OCCURRED1_POWER_MANAGEMENT_REQ_MASK 0x0000000000000002UL
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT0_SHFT 2
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT0_MASK 0x0000000000000004UL
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT1_SHFT 3
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT1_MASK 0x0000000000000008UL
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT2_SHFT 4
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT2_MASK 0x0000000000000010UL
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT3_SHFT 5
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT3_MASK 0x0000000000000020UL
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT4_SHFT 6
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT4_MASK 0x0000000000000040UL
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT5_SHFT 7
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT5_MASK 0x0000000000000080UL
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT6_SHFT 8
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT6_MASK 0x0000000000000100UL
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT7_SHFT 9
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT7_MASK 0x0000000000000200UL
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT8_SHFT 10
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT8_MASK 0x0000000000000400UL
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT9_SHFT 11
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT9_MASK 0x0000000000000800UL
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT10_SHFT 12
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT10_MASK 0x0000000000001000UL
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT11_SHFT 13
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT11_MASK 0x0000000000002000UL
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT12_SHFT 14
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT12_MASK 0x0000000000004000UL
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT13_SHFT 15
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT13_MASK 0x0000000000008000UL
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT14_SHFT 16
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT14_MASK 0x0000000000010000UL
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT15_SHFT 17
#define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT15_MASK 0x0000000000020000UL
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT0_SHFT  18
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT0_MASK  0x0000000000040000UL
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT1_SHFT  19
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT1_MASK  0x0000000000080000UL
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT2_SHFT  20
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT2_MASK  0x0000000000100000UL
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT3_SHFT  21
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT3_MASK  0x0000000000200000UL
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT4_SHFT  22
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT4_MASK  0x0000000000400000UL
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT5_SHFT  23
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT5_MASK  0x0000000000800000UL
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT6_SHFT  24
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT6_MASK  0x0000000001000000UL
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT7_SHFT  25
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT7_MASK  0x0000000002000000UL
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT8_SHFT  26
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT8_MASK  0x0000000004000000UL
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT9_SHFT  27
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT9_MASK  0x0000000008000000UL
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT10_SHFT  28
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT10_MASK  0x0000000010000000UL
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT11_SHFT  29
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT11_MASK  0x0000000020000000UL
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT12_SHFT  30
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT12_MASK  0x0000000040000000UL
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT13_SHFT  31
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT13_MASK  0x0000000080000000UL
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT14_SHFT  32
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT14_MASK  0x0000000100000000UL
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT15_SHFT  33
#define UV3H_EVENT_OCCURRED1_GR0_TLB_INT15_MASK  0x0000000200000000UL
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT0_SHFT  34
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT0_MASK  0x0000000400000000UL
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT1_SHFT  35
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT1_MASK  0x0000000800000000UL
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT2_SHFT  36
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT2_MASK  0x0000001000000000UL
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT3_SHFT  37
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT3_MASK  0x0000002000000000UL
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT4_SHFT  38
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT4_MASK  0x0000004000000000UL
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT5_SHFT  39
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT5_MASK  0x0000008000000000UL
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT6_SHFT  40
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT6_MASK  0x0000010000000000UL
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT7_SHFT  41
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT7_MASK  0x0000020000000000UL
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT8_SHFT  42
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT8_MASK  0x0000040000000000UL
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT9_SHFT  43
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT9_MASK  0x0000080000000000UL
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT10_SHFT  44
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT10_MASK  0x0000100000000000UL
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT11_SHFT  45
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT11_MASK  0x0000200000000000UL
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT12_SHFT  46
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT12_MASK  0x0000400000000000UL
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT13_SHFT  47
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT13_MASK  0x0000800000000000UL
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT14_SHFT  48
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT14_MASK  0x0001000000000000UL
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT15_SHFT  49
#define UV3H_EVENT_OCCURRED1_GR1_TLB_INT15_MASK  0x0002000000000000UL
#define UV3H_EVENT_OCCURRED1_RTC_INTERVAL_INT_SHFT 50
#define UV3H_EVENT_OCCURRED1_RTC_INTERVAL_INT_MASK 0x0004000000000000UL
#define UV3H_EVENT_OCCURRED1_BAU_DASHBOARD_INT_SHFT 51
#define UV3H_EVENT_OCCURRED1_BAU_DASHBOARD_INT_MASK 0x0008000000000000UL

/* UV2 unique defines */
#define UV2H_EVENT_OCCURRED1_BAU_DATA_SHFT  0
#define UV2H_EVENT_OCCURRED1_BAU_DATA_MASK  0x0000000000000001UL
#define UV2H_EVENT_OCCURRED1_POWER_MANAGEMENT_REQ_SHFT 1
#define UV2H_EVENT_OCCURRED1_POWER_MANAGEMENT_REQ_MASK 0x0000000000000002UL
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT0_SHFT 2
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT0_MASK 0x0000000000000004UL
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT1_SHFT 3
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT1_MASK 0x0000000000000008UL
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT2_SHFT 4
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT2_MASK 0x0000000000000010UL
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT3_SHFT 5
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT3_MASK 0x0000000000000020UL
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT4_SHFT 6
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT4_MASK 0x0000000000000040UL
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT5_SHFT 7
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT5_MASK 0x0000000000000080UL
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT6_SHFT 8
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT6_MASK 0x0000000000000100UL
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT7_SHFT 9
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT7_MASK 0x0000000000000200UL
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT8_SHFT 10
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT8_MASK 0x0000000000000400UL
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT9_SHFT 11
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT9_MASK 0x0000000000000800UL
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT10_SHFT 12
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT10_MASK 0x0000000000001000UL
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT11_SHFT 13
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT11_MASK 0x0000000000002000UL
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT12_SHFT 14
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT12_MASK 0x0000000000004000UL
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT13_SHFT 15
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT13_MASK 0x0000000000008000UL
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT14_SHFT 16
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT14_MASK 0x0000000000010000UL
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT15_SHFT 17
#define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT15_MASK 0x0000000000020000UL
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT0_SHFT  18
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT0_MASK  0x0000000000040000UL
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT1_SHFT  19
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT1_MASK  0x0000000000080000UL
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT2_SHFT  20
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT2_MASK  0x0000000000100000UL
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT3_SHFT  21
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT3_MASK  0x0000000000200000UL
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT4_SHFT  22
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT4_MASK  0x0000000000400000UL
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT5_SHFT  23
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT5_MASK  0x0000000000800000UL
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT6_SHFT  24
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT6_MASK  0x0000000001000000UL
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT7_SHFT  25
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT7_MASK  0x0000000002000000UL
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT8_SHFT  26
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT8_MASK  0x0000000004000000UL
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT9_SHFT  27
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT9_MASK  0x0000000008000000UL
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT10_SHFT  28
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT10_MASK  0x0000000010000000UL
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT11_SHFT  29
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT11_MASK  0x0000000020000000UL
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT12_SHFT  30
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT12_MASK  0x0000000040000000UL
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT13_SHFT  31
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT13_MASK  0x0000000080000000UL
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT14_SHFT  32
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT14_MASK  0x0000000100000000UL
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT15_SHFT  33
#define UV2H_EVENT_OCCURRED1_GR0_TLB_INT15_MASK  0x0000000200000000UL
#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT0_SHFT  34
#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT0_MASK  0x0000000400000000UL
#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT1_SHFT  35
#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT1_MASK  0x0000000800000000UL
#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT2_SHFT  36
#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT2_MASK  0x0000001000000000UL
#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT3_SHFT  37
#define UV2H_EVENT_OCCURRED1_GR1_TLB_INT3_MASK  0x0000002000000000UL
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