// SPDX-License-Identifier: GPL-2.0-only /* * pata_cmd640.c - CMD640 PCI PATA for new ATA layer * (C) 2007 Red Hat Inc * * Based upon * linux/drivers/ide/pci/cmd640.c Version 1.02 Sep 01, 1996 * * Copyright (C) 1995-1996 Linus Torvalds & authors (see driver) * * This drives only the PCI version of the controller. If you have a * VLB one then we have enough docs to support it but you can write * your own code.
*/
/* The second channel has shared timings and the setup timing is
messy to switch to merge it for worst case */ if (ap->port_no && pair) { struct ata_timing p;
ata_timing_compute(pair, pair->pio_mode, &p, T, 1);
ata_timing_merge(&p, &t, &t, ATA_TIMING_SETUP);
}
/* Make the timings fit */ if (t.recover > 16) {
t.active += t.recover - 16;
t.recover = 16;
} if (t.active > 16)
t.active = 16;
/* Now convert the clocks into values we can actually stuff into
the chip */
if (t.recover > 1)
t.recover--; /* 640B only */ else
t.recover = 15;
/* Load active/recovery */
pci_write_config_byte(pdev, arttim + 1, (t.active << 4) | t.recover);
} else { /* Save the shared timings for channel, they will be loaded by qc_issue. Reloading the setup time is expensive so we
keep a merged one loaded */
pci_read_config_byte(pdev, ARTIM23, ®);
reg &= 0x3F;
reg |= t.setup;
pci_write_config_byte(pdev, ARTIM23, reg);
timing->reg58[adev->devno] = (t.active << 4) | t.recover;
}
}
/** * cmd640_qc_issue - command preparation hook * @qc: Command to be issued * * Channel 1 has shared timings. We must reprogram the * clock each drive 2/3 switch we do.
*/
/** * cmd640_port_start - port setup * @ap: ATA port being set up * * The CMD640 needs to maintain private data structures so we * allocate space here.
*/
/* CMD640 detected, commiserations */
pci_write_config_byte(pdev, 0x5B, 0x00); /* PIO0 command cycles */
pci_write_config_byte(pdev, CMDTIM, 0); /* 512 byte bursts (sector) */
pci_write_config_byte(pdev, BRST, 0x40); /* * A reporter a long time ago * Had problems with the data fifo * So don't run the risk * Of putting crap on the disk * For its better just to go slow
*/ /* Do channel 0 */
pci_read_config_byte(pdev, CNTRL, &ctrl);
pci_write_config_byte(pdev, CNTRL, ctrl | 0xC0); /* Ditto for channel 1 */
pci_read_config_byte(pdev, ARTIM23, &ctrl);
ctrl |= 0x0C;
pci_write_config_byte(pdev, ARTIM23, ctrl);
}
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