#define ENI_ZEROES_SIZE 4 /* need that many DMA-able zero bytes */
struct eni_free { void __iomem *start; /* counting in bytes */ int order;
};
struct eni_tx { void __iomem *send; /* base, 0 if unused */ int prescaler; /* shaping prescaler */ int resolution; /* shaping divider */ unsignedlong tx_pos; /* current TX write position */ unsignedlong words; /* size of TX queue */ int index; /* TX channel number */ int reserved; /* reserved peak cell rate */ int shaping; /* shaped peak cell rate */ struct sk_buff_head backlog; /* queue of waiting TX buffers */
};
struct eni_vcc { int (*rx)(struct atm_vcc *vcc); /* RX function, NULL if none */ void __iomem *recv; /* receive buffer */ unsignedlong words; /* its size in words */ unsignedlong descr; /* next descriptor (RX) */ unsignedlong rx_pos; /* current RX descriptor pos */ struct eni_tx *tx; /* TXer, NULL if none */ int rxing; /* number of pending PDUs */ int servicing; /* number of waiting VCs (0 or 1) */ int txing; /* number of pending TX bytes */
ktime_t timestamp; /* for RX timing */ struct atm_vcc *next; /* next pending RX */ struct sk_buff *last; /* last PDU being DMAed (used to carry
discard information) */
};
struct eni_dev { /*-------------------------------- spinlock */
spinlock_t lock; /* sync with interrupt */ struct tasklet_struct task; /* tasklet for interrupt work */
u32 events; /* pending events */ /*-------------------------------- base pointers into Midway address
space */ void __iomem *ioaddr; void __iomem *phy; /* PHY interface chip registers */ void __iomem *reg; /* register base */ void __iomem *ram; /* RAM base */ void __iomem *vci; /* VCI table */ void __iomem *rx_dma; /* RX DMA queue */ void __iomem *tx_dma; /* TX DMA queue */ void __iomem *service; /* service list */ /*-------------------------------- TX part */ struct eni_tx tx[NR_CHAN]; /* TX channels */ struct eni_tx *ubr; /* UBR channel */ struct sk_buff_head tx_queue; /* PDUs currently being TX DMAed*/
wait_queue_head_t tx_wait; /* for close */ int tx_bw; /* remaining bandwidth */
u32 dma[TX_DMA_BUF*2]; /* DMA request scratch area */ struct eni_zero { /* aligned "magic" zeroes */
u32 *addr;
dma_addr_t dma;
} zero; int tx_mult; /* buffer size multiplier (percent) */ /*-------------------------------- RX part */
u32 serv_read; /* host service read index */ struct atm_vcc *fast,*last_fast;/* queues of VCCs with pending PDUs */ struct atm_vcc *slow,*last_slow; struct atm_vcc **rx_map; /* for fast lookups */ struct sk_buff_head rx_queue; /* PDUs currently being RX-DMAed */
wait_queue_head_t rx_wait; /* for close */ int rx_mult; /* buffer size multiplier (percent) */ /*-------------------------------- statistics */ unsignedlong lost; /* number of lost cells (RX) */ /*-------------------------------- memory management */ unsignedlong base_diff; /* virtual-real base address */ int free_len; /* free list length */ struct eni_free *free_list; /* free list */ int free_list_size; /* maximum size of free list */ /*-------------------------------- ENI links */ struct atm_dev *more; /* other ENI devices */ /*-------------------------------- general information */ int mem; /* RAM on board (in bytes) */ int asic; /* PCI interface type, 0 for FPGA */ unsignedint irq; /* IRQ */ struct pci_dev *pci_dev; /* PCI stuff */
};
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