/* Clock type, used to tell common block what it's part of */ enum bcm_clk_type {
bcm_clk_none, /* undefined clock type */
bcm_clk_bus,
bcm_clk_core,
bcm_clk_peri
};
/* * CCU policy control for clocks. Clocks can be enabled or disabled * based on the CCU policy in effect. One bit in each policy mask * register (one per CCU policy) represents whether the clock is * enabled when that policy is effect or not. The CCU policy engine * must be stopped to update these bits, and must be restarted again * afterward.
*/ struct bcm_clk_policy {
u32 offset; /* first policy mask register offset */
u32 bit; /* bit used in all mask registers */
};
/* * Gating control and status is managed by a 32-bit gate register. * * There are several types of gating available: * - (no gate) * A clock with no gate is assumed to be always enabled. * - hardware-only gating (auto-gating) * Enabling or disabling clocks with this type of gate is * managed automatically by the hardware. Such clocks can be * considered by the software to be enabled. The current status * of auto-gated clocks can be read from the gate status bit. * - software-only gating * Auto-gating is not available for this type of clock. * Instead, software manages whether it's enabled by setting or * clearing the enable bit. The current gate status of a gate * under software control can be read from the gate status bit. * To ensure a change to the gating status is complete, the * status bit can be polled to verify that the gate has entered * the desired state. * - selectable hardware or software gating * Gating for this type of clock can be configured to be either * under software or hardware control. Which type is in use is * determined by the hw_sw_sel bit of the gate register.
*/ struct bcm_clk_gate {
u32 offset; /* gate register offset */
u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */
u32 en_bit; /* 0: disable; 1: enable */
u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
u32 flags; /* BCM_CLK_GATE_FLAGS_* below */
};
/* * Gate flags: * HW means this gate can be auto-gated * SW means the state of this gate can be software controlled * NO_DISABLE means this gate is (only) enabled if under software control * SW_MANAGED means the status of this gate is under software control * ENABLED means this software-managed gate is *supposed* to be enabled
*/ #define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */ #define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */ #define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */ #define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */ #define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */ #define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */
/* * Gate initialization macros. * * Any gate initially under software control will be enabled.
*/
/* * Each clock can have zero, one, or two dividers which change the * output rate of the clock. Each divider can be either fixed or * variable. If there are two dividers, they are the "pre-divider" * and the "regular" or "downstream" divider. If there is only one, * there is no pre-divider. * * A fixed divider is any non-zero (positive) value, and it * indicates how the input rate is affected by the divider. * * The value of a variable divider is maintained in a sub-field of a * 32-bit divider register. The position of the field in the * register is defined by its offset and width. The value recorded * in this field is always 1 less than the value it represents. * * In addition, a variable divider can indicate that some subset * of its bits represent a "fractional" part of the divider. Such * bits comprise the low-order portion of the divider field, and can * be viewed as representing the portion of the divider that lies to * the right of the decimal point. Most variable dividers have zero * fractional bits. Variable dividers with non-zero fraction width * still record a value 1 less than the value they represent; the * added 1 does *not* affect the low-order bit in this case, it * affects the bits above the fractional part only. (Often in this * code a divider field value is distinguished from the value it * represents by referring to the latter as a "divisor".) * * In order to avoid dealing with fractions, divider arithmetic is * performed using "scaled" values. A scaled value is one that's * been left-shifted by the fractional width of a divider. Dividing * a scaled value by a scaled divisor produces the desired quotient * without loss of precision and without any other special handling * for fractions. * * The recorded value of a variable divider can be modified. To * modify either divider (or both), a clock must be enabled (i.e., * using its gate). In addition, a trigger register (described * below) must be used to commit the change, and polled to verify * the change is complete.
*/ struct bcm_clk_div { union { struct { /* variable divider */
u32 offset; /* divider register offset */
u32 shift; /* field shift */
u32 width; /* field width */
u32 frac_width; /* field fraction width */
/* A divider with an integral divisor */ #define DIVIDER(_offset, _shift, _width) \
{ \
.u.s.offset = (_offset), \
.u.s.shift = (_shift), \
.u.s.width = (_width), \
.u.s.scaled_div = BAD_SCALED_DIV_VALUE, \
.flags = FLAG(DIV, EXISTS), \
}
/* A divider whose divisor has an integer and fractional part */ #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \
{ \
.u.s.offset = (_offset), \
.u.s.shift = (_shift), \
.u.s.width = (_width), \
.u.s.frac_width = (_frac_width), \
.u.s.scaled_div = BAD_SCALED_DIV_VALUE, \
.flags = FLAG(DIV, EXISTS), \
}
/* * Clocks may have multiple "parent" clocks. If there is more than * one, a selector must be specified to define which of the parent * clocks is currently in use. The selected clock is indicated in a * sub-field of a 32-bit selector register. The range of * representable selector values typically exceeds the number of * available parent clocks. Occasionally the reset value of a * selector field is explicitly set to a (specific) value that does * not correspond to a defined input clock. * * We register all known parent clocks with the common clock code * using a packed array (i.e., no empty slots) of (parent) clock * names, and refer to them later using indexes into that array. * We maintain an array of selector values indexed by common clock * index values in order to map between these common clock indexes * and the selector values used by the hardware. * * Like dividers, a selector can be modified, but to do so a clock * must be enabled, and a trigger must be used to commit the change.
*/ struct bcm_clk_sel {
u32 offset; /* selector register offset */
u32 shift; /* field shift */
u32 width; /* field width */
u32 parent_count; /* number of entries in parent_sel[] */
u32 *parent_sel; /* array of parent selector values */
u8 clk_index; /* current selected index in parent_sel[] */
};
/* * Making changes to a variable divider or a selector for a clock * requires the use of a trigger. A trigger is defined by a single * bit within a register. To signal a change, a 1 is written into * that bit. To determine when the change has been completed, that * trigger bit is polled; the read value will be 1 while the change * is in progress, and 0 when it is complete. * * Occasionally a clock will have more than one trigger. In this * case, the "pre-trigger" will be used when changing a clock's * selector and/or its pre-divider.
*/ struct bcm_clk_trig {
u32 offset; /* trigger register offset */
u32 bit; /* trigger bit */
u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */
};
/* * Trigger flags: * EXISTS means this trigger exists
*/ #define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */
/* * CCU policy control. To enable software update of the policy * tables the CCU policy engine must be stopped by setting the * software update enable bit (LVM_EN). After an update the engine * is restarted using the GO bit and either the GO_ATL or GO_AC bit.
*/ struct bcm_lvm_en {
u32 offset; /* LVM_EN register offset */
u32 bit; /* POLICY_CONFIG_EN bit in register */
};
/* * Each CCU defines a mapped area of memory containing registers * used to manage clocks implemented by the CCU. Access to memory * within the CCU's space is serialized by a spinlock. Before any * (other) address can be written, a special access "password" value * must be written to its WR_ACCESS register (located at the base * address of the range). We keep track of the name of each CCU as * it is set up, and maintain them in a list.
*/ struct ccu_data { void __iomem *base; /* base of mapped address space */
spinlock_t lock; /* serialization lock */ bool write_enabled; /* write access is currently enabled */ struct ccu_policy policy; struct device_node *node;
size_t clk_num; constchar *name;
u32 range; /* byte range of address space */ struct kona_clk kona_clks[]; /* must be last */
};
/* Initialization for common fields in a Kona ccu_data structure */ #define KONA_CCU_COMMON(_prefix, _name, _ccuname) \
.name = #_name "_ccu", \
.lock = __SPIN_LOCK_UNLOCKED(_name ## _ccu_data.lock), \
.clk_num = _prefix ## _ ## _ccuname ## _CCU_CLOCK_COUNT
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