// SPDX-License-Identifier: GPL-2.0 /* * Driver for Silicon Labs Si5340 , Si5341 , Si5342 , Si5344 and Si5345 * Copyright ( C ) 2019 Topic Embedded Products * Author : Mike Looijmans < mike . looijmans @ topic . nl > * * The Si5341 has 10 outputs and 5 synthesizers . * The Si5340 is a smaller version of the Si5341 with only 4 outputs . * The Si5345 is similar to the Si5341 , with the addition of fractional input * dividers and automatic input selection . * The Si5342 and Si5344 are smaller versions of the Si5345 . #include <linux/clk.h>#include <linux/clk-provider.h>#include <linux/delay.h>#include <linux/gcd.h>#include <linux/math64.h>#include <linux/i2c.h>#include <linux/module.h>#include <linux/regmap.h>#include <linux/regulator/consumer.h>#include <linux/slab.h>#include <linux/unaligned.h>#define SI5341_NUM_INPUTS 4 #define SI5340_MAX_NUM_OUTPUTS 4 #define SI5341_MAX_NUM_OUTPUTS 10 #define SI5342_MAX_NUM_OUTPUTS 2 #define SI5344_MAX_NUM_OUTPUTS 4 #define SI5345_MAX_NUM_OUTPUTS 10 #define SI5340_NUM_SYNTH 4 #define SI5341_NUM_SYNTH 5 #define SI5342_NUM_SYNTH 2 #define SI5344_NUM_SYNTH 4 #define SI5345_NUM_SYNTH 5 /* Range of the synthesizer fractional divider */ #define SI5341_SYNTH_N_MIN 10 #define SI5341_SYNTH_N_MAX 4095 /* The chip can get its input clock from 3 input pins or an XTAL */ /* There is one PLL running at 13500–14256 MHz */ #define SI5341_PLL_VCO_MIN 13500000000 ull#define SI5341_PLL_VCO_MAX 14256000000 ull/* The 5 frequency synthesizers obtain their input from the PLL */ struct clk_si5341_synth {struct clk_hw hw;struct clk_si5341 *data;#define to_clk_si5341_synth(_hw) \struct clk_si5341_synth, hw)/* The output stages can be connected to any synth (full mux) */ struct clk_si5341_output {struct clk_hw hw;struct clk_si5341 *data;struct regulator *vddo_reg;#define to_clk_si5341_output(_hw) \struct clk_si5341_output, hw)struct clk_si5341 {struct clk_hw hw;struct regmap *regmap;struct i2c_client *i2c_client;struct clk_si5341_synth synth[SI5341_NUM_SYNTH];struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS];struct clk *input_clk[SI5341_NUM_INPUTS];const char *input_clk_name[SI5341_NUM_INPUTS];const u16 *reg_output_offset;const u16 *reg_rdiv_offset;/* 13500–14256 MHz */ bool xaxb_ext_clk;bool iovdd_33;#define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw)struct clk_si5341_output_config {bool synth_master;bool always_on;#define SI5341_PAGE 0 x0001#define SI5341_PN_BASE 0 x0002#define SI5341_DEVICE_REV 0 x0005#define SI5341_STATUS 0 x000C#define SI5341_LOS 0 x000D#define SI5341_STATUS_STICKY 0 x0011#define SI5341_LOS_STICKY 0 x0012#define SI5341_SOFT_RST 0 x001C#define SI5341_IN_SEL 0 x0021#define SI5341_DEVICE_READY 0 x00FE#define SI5341_XAXB_CFG 0 x090E#define SI5341_IO_VDD_SEL 0 x0943#define SI5341_IN_EN 0 x0949#define SI5341_INX_TO_PFD_EN 0 x094A/* Status bits */ #define SI5341_STATUS_SYSINCAL BIT(0 )#define SI5341_STATUS_LOSXAXB BIT(1 )#define SI5341_STATUS_LOSREF BIT(2 )#define SI5341_STATUS_LOL BIT(3 )/* Input selection */ #define SI5341_IN_SEL_MASK 0 x06#define SI5341_IN_SEL_SHIFT 1 #define SI5341_IN_SEL_REGCTRL 0 x01#define SI5341_INX_TO_PFD_SHIFT 4 /* XTAL config bits */ #define SI5341_XAXB_CFG_EXTCLK_EN BIT(0 )#define SI5341_XAXB_CFG_PDNB BIT(1 )/* Input dividers (48-bit) */ #define SI5341_IN_PDIV(x) (0 x0208 + ((x) * 10 ))#define SI5341_IN_PSET(x) (0 x020E + ((x) * 10 ))#define SI5341_PX_UPD 0 x0230/* PLL configuration */ #define SI5341_PLL_M_NUM 0 x0235#define SI5341_PLL_M_DEN 0 x023B/* Output configuration */ #define SI5341_OUT_CONFIG(output) \#define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1 )#define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2 )#define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3 )#define SI5341_OUT_R_REG(output) \#define SI5341_OUT_MUX_VDD_SEL_MASK 0 x38/* Synthesize N divider */ #define SI5341_SYNTH_N_NUM(x) (0 x0302 + ((x) * 11 ))#define SI5341_SYNTH_N_DEN(x) (0 x0308 + ((x) * 11 ))#define SI5341_SYNTH_N_UPD(x) (0 x030C + ((x) * 11 ))/* Synthesizer output enable, phase bypass, power mode */ #define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0 x0A03#define SI5341_SYNTH_N_PIBYP 0 x0A04#define SI5341_SYNTH_N_PDNB 0 x0A05#define SI5341_SYNTH_N_CLK_DIS 0 x0B4A#define SI5341_REGISTER_MAX 0 xBFF/* SI5341_OUT_CONFIG bits */ #define SI5341_OUT_CFG_PDN BIT(0 )#define SI5341_OUT_CFG_OE BIT(1 )#define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2 )/* Static configuration (to be moved to firmware) */ struct si5341_reg_default {static const char * const si5341_input_clock_names[] = {"in0" , "in1" , "in2" , "xtal" /* Output configuration registers 0..9 are not quite logically organized */ /* Also for si5345 */ static const u16 si5341_reg_output_offset[] = {0 x0108,0 x010D,0 x0112,0 x0117,0 x011C,0 x0121,0 x0126,0 x012B,0 x0130,0 x013A,/* for si5340, si5342 and si5344 */ static const u16 si5340_reg_output_offset[] = {0 x0112,0 x0117,0 x0126,0 x012B,/* The location of the R divider registers */ static const u16 si5341_reg_rdiv_offset[] = {0 x024A,0 x024D,0 x0250,0 x0253,0 x0256,0 x0259,0 x025C,0 x025F,0 x0262,0 x0268,static const u16 si5340_reg_rdiv_offset[] = {0 x0250,0 x0253,0 x025C,0 x025F,/* * Programming sequence from ClockBuilder , settings to initialize the system * using only the XTAL input , without pre - divider . * This also contains settings that aren ' t mentioned anywhere in the datasheet . * The " known " settings like synth and output configuration are done later . static const struct si5341_reg_default si5341_reg_defaults[] = {0 x0017, 0 x3A }, /* INT mask (disable interrupts) */ 0 x0018, 0 xFF }, /* INT mask */ 0 x0021, 0 x0F }, /* Select XTAL as input */ 0 x0022, 0 x00 }, /* Not in datasheet */ 0 x002B, 0 x02 }, /* SPI config */ 0 x002C, 0 x20 }, /* LOS enable for XTAL */ 0 x002D, 0 x00 }, /* LOS timing */ 0 x002E, 0 x00 },0 x002F, 0 x00 },0 x0030, 0 x00 },0 x0031, 0 x00 },0 x0032, 0 x00 },0 x0033, 0 x00 },0 x0034, 0 x00 },0 x0035, 0 x00 },0 x0036, 0 x00 },0 x0037, 0 x00 },0 x0038, 0 x00 }, /* LOS setting (thresholds) */ 0 x0039, 0 x00 },0 x003A, 0 x00 },0 x003B, 0 x00 },0 x003C, 0 x00 },0 x003D, 0 x00 }, /* LOS setting (thresholds) end */ 0 x0041, 0 x00 }, /* LOS0_DIV_SEL */ 0 x0042, 0 x00 }, /* LOS1_DIV_SEL */ 0 x0043, 0 x00 }, /* LOS2_DIV_SEL */ 0 x0044, 0 x00 }, /* LOS3_DIV_SEL */ 0 x009E, 0 x00 }, /* Not in datasheet */ 0 x0102, 0 x01 }, /* Enable outputs */ 0 x013F, 0 x00 }, /* Not in datasheet */ 0 x0140, 0 x00 }, /* Not in datasheet */ 0 x0141, 0 x40 }, /* OUT LOS */ 0 x0202, 0 x00 }, /* XAXB_FREQ_OFFSET (=0)*/ 0 x0203, 0 x00 },0 x0204, 0 x00 },0 x0205, 0 x00 },0 x0206, 0 x00 }, /* PXAXB (2^x) */ 0 x0208, 0 x00 }, /* Px divider setting (usually 0) */ 0 x0209, 0 x00 },0 x020A, 0 x00 },0 x020B, 0 x00 },0 x020C, 0 x00 },0 x020D, 0 x00 },0 x020E, 0 x00 },0 x020F, 0 x00 },0 x0210, 0 x00 },0 x0211, 0 x00 },0 x0212, 0 x00 },0 x0213, 0 x00 },0 x0214, 0 x00 },0 x0215, 0 x00 },0 x0216, 0 x00 },0 x0217, 0 x00 },0 x0218, 0 x00 },0 x0219, 0 x00 },0 x021A, 0 x00 },0 x021B, 0 x00 },0 x021C, 0 x00 },0 x021D, 0 x00 },0 x021E, 0 x00 },0 x021F, 0 x00 },0 x0220, 0 x00 },0 x0221, 0 x00 },0 x0222, 0 x00 },0 x0223, 0 x00 },0 x0224, 0 x00 },0 x0225, 0 x00 },0 x0226, 0 x00 },0 x0227, 0 x00 },0 x0228, 0 x00 },0 x0229, 0 x00 },0 x022A, 0 x00 },0 x022B, 0 x00 },0 x022C, 0 x00 },0 x022D, 0 x00 },0 x022E, 0 x00 },0 x022F, 0 x00 }, /* Px divider setting (usually 0) end */ 0 x026B, 0 x00 }, /* DESIGN_ID (ASCII string) */ 0 x026C, 0 x00 },0 x026D, 0 x00 },0 x026E, 0 x00 },0 x026F, 0 x00 },0 x0270, 0 x00 },0 x0271, 0 x00 },0 x0272, 0 x00 }, /* DESIGN_ID (ASCII string) end */ 0 x0339, 0 x1F }, /* N_FSTEP_MSK */ 0 x033B, 0 x00 }, /* Nx_FSTEPW (Frequency step) */ 0 x033C, 0 x00 },0 x033D, 0 x00 },0 x033E, 0 x00 },0 x033F, 0 x00 },0 x0340, 0 x00 },0 x0341, 0 x00 },0 x0342, 0 x00 },0 x0343, 0 x00 },0 x0344, 0 x00 },0 x0345, 0 x00 },0 x0346, 0 x00 },0 x0347, 0 x00 },0 x0348, 0 x00 },0 x0349, 0 x00 },0 x034A, 0 x00 },0 x034B, 0 x00 },0 x034C, 0 x00 },0 x034D, 0 x00 },0 x034E, 0 x00 },0 x034F, 0 x00 },0 x0350, 0 x00 },0 x0351, 0 x00 },0 x0352, 0 x00 },0 x0353, 0 x00 },0 x0354, 0 x00 },0 x0355, 0 x00 },0 x0356, 0 x00 },0 x0357, 0 x00 },0 x0358, 0 x00 }, /* Nx_FSTEPW (Frequency step) end */ 0 x0359, 0 x00 }, /* Nx_DELAY */ 0 x035A, 0 x00 },0 x035B, 0 x00 },0 x035C, 0 x00 },0 x035D, 0 x00 },0 x035E, 0 x00 },0 x035F, 0 x00 },0 x0360, 0 x00 },0 x0361, 0 x00 },0 x0362, 0 x00 }, /* Nx_DELAY end */ 0 x0802, 0 x00 }, /* Not in datasheet */ 0 x0803, 0 x00 }, /* Not in datasheet */ 0 x0804, 0 x00 }, /* Not in datasheet */ 0 x090E, 0 x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */ 0 x091C, 0 x04 }, /* ZDM_EN=4 (Normal mode) */ 0 x0949, 0 x00 }, /* IN_EN (disable input clocks) */ 0 x094A, 0 x00 }, /* INx_TO_PFD_EN (disabled) */ 0 x0A02, 0 x00 }, /* Not in datasheet */ 0 x0B44, 0 x0F }, /* PDIV_ENB (datasheet does not mention what it is) */ 0 x0B57, 0 x10 }, /* VCO_RESET_CALCODE (not described in datasheet) */ 0 x0B58, 0 x05 }, /* VCO_RESET_CALCODE (not described in datasheet) */ /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */ static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg,int err;10 ];10 );if (err < 0 )return err;5 ] & 0 x0f) << 8 | r[4 ]) << 32 ) |6 ]);return 0 ;static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg,10 ];/* Shift left as far as possible without overflowing */ while (!(n_num & BIT_ULL(43 )) && !(n_den & BIT(31 ))) {1 ;1 ;/* 44 bits (6 bytes) numerator */ 4 ] = (n_num >> 32 ) & 0 xff;5 ] = (n_num >> 40 ) & 0 x0f;/* 32 bits denominator */ 6 ]);/* Program the fraction */ return regmap_bulk_write(regmap, reg, r, sizeof (r));/* VCO, we assume it runs at a constant frequency */ static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw,unsigned long parent_rate)struct clk_si5341 *data = to_clk_si5341(hw);int err;unsigned int shift;/* Assume that PDIV is not being used, just read the PLL setting */ if (err < 0 )return 0 ;if (!m_num || !m_den)return 0 ;/* * Though m_num is 64 - bit , only the upper bits are actually used . While * calculating m_num and m_den , they are shifted as far as possible to * the left . To avoid 96 - bit division here , we just shift them back so * we can do with just 64 bits . 0 ;while (res & 0 xffff00000000ULL) {1 ;/* We cannot return the actual frequency in 32 bit, store it locally */ /* Report kHz since the value is out of range */ 1000 );return (unsigned long )res;static int si5341_clk_get_selected_input(struct clk_si5341 *data)int err;if (err < 0 )return err;return (val & SI5341_IN_SEL_MASK) >> SI5341_IN_SEL_SHIFT;static u8 si5341_clk_get_parent(struct clk_hw *hw)struct clk_si5341 *data = to_clk_si5341(hw);int res = si5341_clk_get_selected_input(data);if (res < 0 )return 0 ; /* Apparently we cannot report errors */ return res;static int si5341_clk_reparent(struct clk_si5341 *data, u8 index)int err;/* Enable register-based input selection */ if (err < 0 )return err;if (index < 3 ) {/* Enable input buffer for selected input */ 0 x07, BIT(index));if (err < 0 )return err;/* Enables the input to phase detector */ 0 x7 << SI5341_INX_TO_PFD_SHIFT,if (err < 0 )return err;/* Power down XTAL oscillator and buffer */ 0 );if (err < 0 )return err;/* * Set the P divider to " 1 " . There ' s no explanation in the * datasheet of these registers , but the clockbuilder software * programs a " 1 " when the input is being used . 1 );if (err < 0 )return err;1 );if (err < 0 )return err;/* Set update PDIV bit */ if (err < 0 )return err;else {/* Disable all input buffers */ 0 x07, 0 );if (err < 0 )return err;/* Disable input to phase detector */ 0 x7 << SI5341_INX_TO_PFD_SHIFT, 0 );if (err < 0 )return err;/* Power up XTAL oscillator and buffer, select clock mode */ 0 ));if (err < 0 )return err;return 0 ;static int si5341_clk_set_parent(struct clk_hw *hw, u8 index)struct clk_si5341 *data = to_clk_si5341(hw);return si5341_clk_reparent(data, index);static const struct clk_ops si5341_clk_ops = {/* Synthesizers, there are 5 synthesizers that connect to any of the outputs */ /* The synthesizer is on if all power and enable bits are set */ static int si5341_synth_clk_is_on(struct clk_hw *hw)struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);int err;if (err < 0 )return 0 ;if (!(val & BIT(index)))return 0 ;if (err < 0 )return 0 ;if (!(val & BIT(index)))return 0 ;/* This bit must be 0 for the synthesizer to receive clock input */ if (err < 0 )return 0 ;return !(val & BIT(index));static void si5341_synth_clk_unprepare(struct clk_hw *hw)struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);/* In range 0..5 */ /* Disable output */ 0 );/* Power down */ 0 );/* Disable clock input to synth (set to 1 to disable) */ static int si5341_synth_clk_prepare(struct clk_hw *hw)struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);int err;/* Power up */ if (err < 0 )return err;/* Enable clock input to synth (set bit to 0 to enable) */ 0 );if (err < 0 )return err;/* Enable output */ return regmap_update_bits(synth->data->regmap,/* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */ static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,unsigned long parent_rate)struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);int err;if (err < 0 )return err;/* Check for bogus/uninitialized settings */ if (!n_num || !n_den)return 0 ;/* * n_num and n_den are shifted left as much as possible , so to prevent * overflow in 64 - bit math , we shift n_den 4 bits to the right 4 ;/* Now we need to do 64-bit division: f/n_num */ /* And compensate for the 4 bits we dropped */ 4 ));return f;static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate,unsigned long *parent_rate)struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);/* The synthesizer accuracy is such that anything in range will work */ if (rate < f)return f;if (rate > f)return f;return rate;static int si5341_synth_program(struct clk_si5341_synth *synth,bool is_integer)int err;0 );if (err < 0 )return err;return regmap_write(synth->data->regmap,0 x01);static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,unsigned long parent_rate)struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);bool is_integer;/* see if there's an integer solution */ 0 );if (is_integer) {/* Integer divider equal to n_num */ 1 ;else {/* Calculate a fractional solution */ "%s(%u): n=0x%llx d=0x%x %s\n" , __func__,"int" : "frac" );return si5341_synth_program(synth, n_num, n_den, is_integer);static const struct clk_ops si5341_synth_clk_ops = {static int si5341_output_clk_is_on(struct clk_hw *hw)struct clk_si5341_output *output = to_clk_si5341_output(hw);int err;if (err < 0 )return err;/* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */ return (val & 0 x03) == SI5341_OUT_CFG_OE;/* Disables and then powers down the output */ static void si5341_output_clk_unprepare(struct clk_hw *hw)struct clk_si5341_output *output = to_clk_si5341_output(hw);0 );/* Powers up and then enables the output */ static int si5341_output_clk_prepare(struct clk_hw *hw)struct clk_si5341_output *output = to_clk_si5341_output(hw);int err;0 );if (err < 0 )return err;return regmap_update_bits(output->data->regmap,static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,unsigned long parent_rate)struct clk_si5341_output *output = to_clk_si5341_output(hw);int err;3 ];if (err < 0 )return err;/* If SI5341_OUT_CFG_RDIV_FORCE2 is set, r_divider is 2 */ if (val & SI5341_OUT_CFG_RDIV_FORCE2)return parent_rate / 2 ;3 );if (err < 0 )return err;/* Calculate value as 24-bit integer*/ 2 ] << 16 | r[1 ] << 8 | r[0 ];/* If Rx_REG is zero, the divider is disabled, so return a "0" rate */ if (!r_divider)return 0 ;/* Divider is 2*(Rx_REG+1) */ 1 ;1 ;return parent_rate / r_divider;static int si5341_output_clk_determine_rate(struct clk_hw *hw,struct clk_rate_request *req)unsigned long rate = req->rate;unsigned long r;if (!rate)return 0 ;1 ;/* If rate is an even divisor, no changes to parent required */ if (r && !(r % rate))return 0 ;if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {if (rate > 200000000 ) {/* minimum r-divider is 2 */ 2 ;else {/* Take a parent frequency near 400 MHz */ 400000000 u / rate) & ~1 ;else {/* We cannot change our parent's rate, report what we can do */ 1 );return 0 ;static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,unsigned long parent_rate)struct clk_si5341_output *output = to_clk_si5341_output(hw);int err;3 ];if (!rate)return -EINVAL;/* Frequency divider is (r_div + 1) * 2 */ 1 ;if (r_div <= 1 )0 ;else if (r_div >= BIT(24 ))24 ) - 1 ;else /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */ 0 ) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0 );if (err < 0 )return err;/* Always write Rx_REG, because a zero value disables the divider */ 0 ] = r_div ? (r_div & 0 xff) : 1 ;1 ] = (r_div >> 8 ) & 0 xff;2 ] = (r_div >> 16 ) & 0 xff;return regmap_bulk_write(output->data->regmap,3 );static int si5341_output_reparent(struct clk_si5341_output *output, u8 index)return regmap_update_bits(output->data->regmap,0 x07, index);static int si5341_output_set_parent(struct clk_hw *hw, u8 index)struct clk_si5341_output *output = to_clk_si5341_output(hw);if (index >= output->data->num_synth)return -EINVAL;return si5341_output_reparent(output, index);static u8 si5341_output_get_parent(struct clk_hw *hw)struct clk_si5341_output *output = to_clk_si5341_output(hw);return val & 0 x7;static const struct clk_ops si5341_output_clk_ops = {/* * The chip can be bought in a pre - programmed version , or one can program the * NVM in the chip to boot up in a preset mode . This routine tries to determine * if that ' s the case , or if we need to reset and program everything from * scratch . Returns negative error , or true / false . static int si5341_is_programmed_already(struct clk_si5341 *data)int err;4 ];/* Read the PLL divider value, it must have a non-zero value */ if (err < 0 )return err;return !!get_unaligned_le32(r);static struct clk_hw *struct of_phandle_args *clkspec, void *_data)struct clk_si5341 *data = _data;unsigned int idx = clkspec->args[1 ];unsigned int group = clkspec->args[0 ];switch (group) {case 0 :if (idx >= data->num_outputs) {"invalid output index %u\n" , idx);return ERR_PTR(-EINVAL);return &data->clk[idx].hw;case 1 :if (idx >= data->num_synth) {"invalid synthesizer index %u\n" , idx);return ERR_PTR(-EINVAL);return &data->synth[idx].hw;case 2 :if (idx > 0 ) {"invalid PLL index %u\n" , idx);return ERR_PTR(-EINVAL);return &data->hw;default :"invalid group %u\n" , group);return ERR_PTR(-EINVAL);static int si5341_probe_chip_id(struct clk_si5341 *data)int err;4 ];if (err < 0 ) {"Failed to read chip ID\n" );return err;"Chip: %x Grade: %u Rev: %u\n" ,2 ], reg[3 ]);switch (model) {case 0 x5340:break ;case 0 x5341:break ;case 0 x5342:break ;case 0 x5344:break ;case 0 x5345:break ;default :"Model '%x' not supported\n" ,return -EINVAL;return 0 ;/* Read active settings into the regmap cache for later reference */ static int si5341_read_settings(struct clk_si5341 *data)int err;10 ];10 );if (err < 0 )return err;3 );if (err < 0 )return err;1 );if (err < 0 )return err;for (i = 0 ; i < data->num_synth; ++i) {10 );if (err < 0 )return err;for (i = 0 ; i < data->num_outputs; ++i) {4 );if (err < 0 )return err;3 );if (err < 0 )return err;return 0 ;static int si5341_write_multiple(struct clk_si5341 *data,const struct si5341_reg_default *values, unsigned int num_values)unsigned int i;int res;for (i = 0 ; i < num_values; ++i) {if (res < 0 ) {"Failed to write %#x:%#x\n" ,return res;return 0 ;static const struct si5341_reg_default si5341_preamble[] = {0 x0B25, 0 x00 },0 x0502, 0 x01 },0 x0505, 0 x03 },0 x0957, 0 x17 },0 x0B4E, 0 x1A },static const struct si5341_reg_default si5345_preamble[] = {0 x0B25, 0 x00 },0 x0540, 0 x01 },static int si5341_send_preamble(struct clk_si5341 *data)int res;/* For revision 2 and up, the values are slightly different */ if (res < 0 )return res;/* Write "preamble" as specified by datasheet */ 0 xB24, revision < 2 ? 0 xD8 : 0 xC0);if (res < 0 )return res;/* The si5342..si5345 require a different preamble */ if (data->chip_id > 0 x5341)else if (res < 0 )return res;/* Datasheet specifies a 300ms wait after sending the preamble */ 300 );return 0 ;/* Perform a soft reset and write post-amble */ static int si5341_finalize_defaults(struct clk_si5341 *data)int res;1 : 0 );if (res < 0 )return res;if (res < 0 )return res;"%s rev=%u\n" , __func__, revision);0 x01);if (res < 0 )return res;/* The si5342..si5345 have an additional post-amble */ if (data->chip_id > 0 x5341) {0 x540, 0 x0);if (res < 0 )return res;/* Datasheet does not explain these nameless registers */ 0 xB24, revision < 2 ? 0 xDB : 0 xC3);if (res < 0 )return res;0 x0B25, 0 x02);if (res < 0 )return res;return 0 ;static const struct regmap_range si5341_regmap_volatile_range[] = {0 x000C, 0 x0012), /* Status */ 0 x001C, 0 x001E), /* reset, finc/fdec */ 0 x00E2, 0 x00FE), /* NVM, interrupts, device ready */ /* Update bits for P divider and synth config */ 0 ), SI5341_SYNTH_N_UPD(0 )),1 ), SI5341_SYNTH_N_UPD(1 )),2 ), SI5341_SYNTH_N_UPD(2 )),3 ), SI5341_SYNTH_N_UPD(3 )),4 ), SI5341_SYNTH_N_UPD(4 )),static const struct regmap_access_table si5341_regmap_volatile = {/* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */ static const struct regmap_range_cfg si5341_regmap_ranges[] = {0 ,0 xff,0 ,0 ,256 ,static int si5341_wait_device_ready(struct i2c_client *client)int count;/* Datasheet warns: Any attempt to read or write any register other * than DEVICE_READY before DEVICE_READY reads as 0 x0F may corrupt the * NVM programming and may corrupt the register contents , as they are * read from NVM . Note that this includes accesses to the PAGE register . * Also : DEVICE_READY is available on every register page , so no page * change is needed to read it . * Do this outside regmap to avoid automatic PAGE register access . * May take up to 300 ms to complete . for (count = 0 ; count < 15 ; ++count) {if (result < 0 )return result;if (result == 0 x0F)return 0 ;20 );"timeout waiting for DEVICE_READY\n" );return -EIO;static const struct regmap_config si5341_regmap_config = {8 ,8 ,static int si5341_dt_parse_dt(struct clk_si5341 *data,struct clk_si5341_output_config *config)struct device_node *child;struct device_node *np = data->i2c_client->dev.of_node;0 , sizeof (struct clk_si5341_output_config) *if (of_property_read_u32(child, "reg" , &num)) {"missing reg property of %s\n" ,goto put_child;if (num >= SI5341_MAX_NUM_OUTPUTS) {"invalid clkout %d\n" , num);goto put_child;if (!of_property_read_u32(child, "silabs,format" , &val)) {/* Set cm and ampl conservatively to 3v3 settings */ switch (val) {case 1 : /* normal differential */ 0 x33;break ;case 2 : /* low-power differential */ 0 x13;break ;case 4 : /* LVCMOS */ 0 x33;/* Set SI recommended impedance for LVCMOS */ 0 xc0;break ;default :"invalid silabs,format %u for %u\n" ,goto put_child;0 x07;0 x07;/* Always enable the SYNC feature */ 0 x08;if (!of_property_read_u32(child, "silabs,common-mode" , &val)) {if (val > 0 xf) {"invalid silabs,common-mode %u\n" ,goto put_child;0 xf0;0 x0f;if (!of_property_read_u32(child, "silabs,amplitude" , &val)) {if (val > 0 xf) {"invalid silabs,amplitude %u\n" ,goto put_child;0 x0f;4 ) & 0 xf0;if (of_property_read_bool(child, "silabs,disable-high" ))0 x10;"silabs,synth-master" );"always-on" );0 x08;if (data->clk[num].vddo_reg) {int vdd = regulator_get_voltage(data->clk[num].vddo_reg);switch (vdd) {case 3300000 :0 << 4 ;break ;case 1800000 :1 << 4 ;break ;case 2500000 :2 << 4 ;break ;default :"unsupported vddo voltage %d for %s\n" ,goto put_child;else {/* chip seems to default to 2.5V when not set */ "no regulator set, defaulting vdd_sel to 2.5V for %s\n" ,2 << 4 ;return 0 ;return -EINVAL;/* * If not pre - configured , calculate and set the PLL configuration manually . * For low - jitter performance , the PLL should be set such that the synthesizers * only need integer division . * Without any user guidance , we ' ll set the PLL to 14 GHz , which still allows * the chip to generate any frequency on its outputs , but jitter performance * may be sub - optimal . static int si5341_initialize_pll(struct clk_si5341 *data)struct device_node *np = data->i2c_client->dev.of_node;0 ;0 ;int sel;if (of_property_read_u32(np, "silabs,pll-m-num" , &m_num)) {"PLL configuration requires silabs,pll-m-num\n" );if (of_property_read_u32(np, "silabs,pll-m-den" , &m_den)) {"PLL configuration requires silabs,pll-m-den\n" );if (!m_num || !m_den) {"PLL configuration invalid, assume 14GHz\n" );if (sel < 0 )return sel;10 ;1400000000 ;return si5341_encode_44_32(data->regmap,static int si5341_clk_select_active_input(struct clk_si5341 *data)int res;int err;int i;if (res < 0 )return res;/* If the current register setting is invalid, pick the first input */ if (!data->input_clk[res]) {"Input %d not connected, rerouting\n" , res);for (i = 0 ; i < SI5341_NUM_INPUTS; ++i) {if (data->input_clk[i]) {break ;if (res < 0 ) {"No clock input available\n" );return res;/* Make sure the selected clock is also enabled and routed */ if (err < 0 )return err;if (err < 0 )return err;return res;static ssize_t input_present_show(struct device *dev,struct device_attribute *attr,char *buf)struct clk_si5341 *data = dev_get_drvdata(dev);int res = regmap_read(data->regmap, SI5341_STATUS, &status);if (res < 0 )return res;return sysfs_emit(buf, "%d\n" , res);static DEVICE_ATTR_RO(input_present);static ssize_t input_present_sticky_show(struct device *dev,struct device_attribute *attr,char *buf)struct clk_si5341 *data = dev_get_drvdata(dev);int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status);if (res < 0 )return res;return sysfs_emit(buf, "%d\n" , res);static DEVICE_ATTR_RO(input_present_sticky);static ssize_t pll_locked_show(struct device *dev,struct device_attribute *attr,char *buf)struct clk_si5341 *data = dev_get_drvdata(dev);int res = regmap_read(data->regmap, SI5341_STATUS, &status);if (res < 0 )return res;return sysfs_emit(buf, "%d\n" , res);static DEVICE_ATTR_RO(pll_locked);static ssize_t pll_locked_sticky_show(struct device *dev,struct device_attribute *attr,char *buf)struct clk_si5341 *data = dev_get_drvdata(dev);int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status);if (res < 0 )return res;return sysfs_emit(buf, "%d\n" , res);static DEVICE_ATTR_RO(pll_locked_sticky);static ssize_t clear_sticky_store(struct device *dev,struct device_attribute *attr,const char *buf, size_t count)struct clk_si5341 *data = dev_get_drvdata(dev);long val;if (kstrtol(buf, 10 , &val))return -EINVAL;if (val) {int res = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0 );if (res < 0 )return res;return count;static DEVICE_ATTR_WO(clear_sticky);static const struct attribute *si5341_attributes[] = {static int si5341_probe(struct i2c_client *client)struct clk_si5341 *data;struct clk_init_data init;struct clk *input;const char *root_clock_name;const char *synth_clock_names[SI5341_NUM_SYNTH] = { NULL };int err;unsigned int i;struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];bool initialization_required;sizeof (*data), GFP_KERNEL);if (!data)return -ENOMEM;/* Must be done before otherwise touching hardware */ if (err)return err;for (i = 0 ; i < SI5341_NUM_INPUTS; ++i) {if (IS_ERR(input)) {if (PTR_ERR(input) == -EPROBE_DEFER)return -EPROBE_DEFER;else {for (i = 0 ; i < SI5341_MAX_NUM_OUTPUTS; ++i) {char reg_name[10 ];sizeof (reg_name), "vddo%d" , i);if (IS_ERR(data->clk[i].vddo_reg)) {if (err == -ENODEV)continue ;goto cleanup;else {if (err) {"failed to enable %s regulator: %d\n" ,goto cleanup;if (err)goto cleanup;if (of_property_read_string(client->dev.of_node, "clock-output-names" ,if (IS_ERR(data->regmap)) {goto cleanup;if (err < 0 )goto cleanup;if (of_property_read_bool(client->dev.of_node, "silabs,reprogram" )) {true ;else {if (err < 0 )goto cleanup;"silabs,xaxb-ext-clk" );"silabs,iovdd-33" );if (initialization_required) {/* Populate the regmap cache in preparation for "cache only" */ if (err < 0 )goto cleanup;if (err < 0 )goto cleanup;/* * We intend to send all ' final ' register values in a single * transaction . So cache all register writes until we ' re done * configuring . true );/* Write the configuration pairs from the firmware blob */ if (err < 0 )goto cleanup;/* Input must be up and running at this point */ if (err < 0 )goto cleanup;if (initialization_required) {/* PLL configuration is required */ if (err < 0 )goto cleanup;/* Register the PLL */ 0 ;if (err) {"clock registration failed\n" );goto cleanup;1 ;for (i = 0 ; i < data->num_synth; ++i) {"%s.N%u" , client->dev.of_node->name, i);if (!synth_clock_names[i]) {goto free_clk_names;if (err) {"synth N%u registration failed\n" , i);goto free_clk_names;for (i = 0 ; i < data->num_outputs; ++i) {"%s.%d" ,if (!init.name) {goto free_clk_names;0 ;if (config[i].out_format_drv_bits & 0 x07) {/* clock framework made a copy of the name */ if (err) {"output %u registration failed\n" , i);goto free_clk_names;if (config[i].always_on)if (err) {"unable to add clk provider\n" );goto free_clk_names;if (initialization_required) {/* Synchronize */ false );if (err < 0 )goto free_clk_names;if (err < 0 )goto free_clk_names;/* wait for device to report input clock present and PLL lock */ 10000 , 250000 );if (err) {"Error waiting for input clock or PLL lock\n" );goto free_clk_names;/* clear sticky alarm bits from initialization */ 0 );if (err) {"unable to clear sticky status\n" );goto free_clk_names;if (err)"unable to create sysfs files\n" );/* Free the names, clk framework makes copies */ for (i = 0 ; i < data->num_synth; ++i)void *)synth_clock_names[i]);if (err) {for (i = 0 ; i < SI5341_MAX_NUM_OUTPUTS; ++i) {if (data->clk[i].vddo_reg)return err;static void si5341_remove(struct i2c_client *client)struct clk_si5341 *data = i2c_get_clientdata(client);int i;for (i = 0 ; i < SI5341_MAX_NUM_OUTPUTS; ++i) {if (data->clk[i].vddo_reg)static const struct i2c_device_id si5341_id[] = {"si5340" , 0 },"si5341" , 1 },"si5342" , 2 },"si5344" , 4 },"si5345" , 5 },static const struct of_device_id clk_si5341_of_match[] = {"silabs,si5340" },"silabs,si5341" },"silabs,si5342" },"silabs,si5344" },"silabs,si5345" },static struct i2c_driver si5341_driver = {"si5341" ,"Mike Looijmans <mike.looijmans@topic.nl>" );"Si5341 driver" );"GPL" );
Messung V0.5 in Prozent C=93 H=90 G=91
¤ Dauer der Verarbeitung: 0.23 Sekunden
(vorverarbeitet am 2026-09-27)
¤ *© Formatika GbR, Deutschland
