// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2014 MediaTek Inc. * Author: James Liao <jamesjj.liao@mediatek.com> #include <linux/clk-provider.h>#include <linux/mod_devicetable.h>#include <linux/platform_device.h>#include "clk-gate.h" #include "clk-mtk.h" #include <dt-bindings/clock/mt8173-clk.h>static const struct mtk_gate_regs mm0_cg_regs = {static const struct mtk_gate_regs mm1_cg_regs = {#define GATE_MM0(_id, _name, _parent, _shift) \#define GATE_MM1(_id, _name, _parent, _shift) \static const struct mtk_gate mt8173_mm_clks[] = {"mm_dummy" ),/* MM0 */ "mm_smi_common" , "mm_sel" , 0),"mm_smi_larb0" , "mm_sel" , 1),"mm_cam_mdp" , "mm_sel" , 2),"mm_mdp_rdma0" , "mm_sel" , 3),"mm_mdp_rdma1" , "mm_sel" , 4),"mm_mdp_rsz0" , "mm_sel" , 5),"mm_mdp_rsz1" , "mm_sel" , 6),"mm_mdp_rsz2" , "mm_sel" , 7),"mm_mdp_tdshp0" , "mm_sel" , 8),"mm_mdp_tdshp1" , "mm_sel" , 9),"mm_mdp_wdma" , "mm_sel" , 11),"mm_mdp_wrot0" , "mm_sel" , 12),"mm_mdp_wrot1" , "mm_sel" , 13),"mm_fake_eng" , "mm_sel" , 14),"mm_mutex_32k" , "rtc_sel" , 15),"mm_disp_ovl0" , "mm_sel" , 16),"mm_disp_ovl1" , "mm_sel" , 17),"mm_disp_rdma0" , "mm_sel" , 18),"mm_disp_rdma1" , "mm_sel" , 19),"mm_disp_rdma2" , "mm_sel" , 20),"mm_disp_wdma0" , "mm_sel" , 21),"mm_disp_wdma1" , "mm_sel" , 22),"mm_disp_color0" , "mm_sel" , 23),"mm_disp_color1" , "mm_sel" , 24),"mm_disp_aal" , "mm_sel" , 25),"mm_disp_gamma" , "mm_sel" , 26),"mm_disp_ufoe" , "mm_sel" , 27),"mm_disp_split0" , "mm_sel" , 28),"mm_disp_split1" , "mm_sel" , 29),"mm_disp_merge" , "mm_sel" , 30),"mm_disp_od" , "mm_sel" , 31),/* MM1 */ "mm_disp_pwm0mm" , "mm_sel" , 0),"mm_disp_pwm026m" , "pwm_sel" , 1),"mm_disp_pwm1mm" , "mm_sel" , 2),"mm_disp_pwm126m" , "pwm_sel" , 3),"mm_dsi0_engine" , "mm_sel" , 4),"mm_dsi0_digital" , "dsi0_dig" , 5),"mm_dsi1_engine" , "mm_sel" , 6),"mm_dsi1_digital" , "dsi1_dig" , 7),"mm_dpi_pixel" , "dpi0_sel" , 8),"mm_dpi_engine" , "mm_sel" , 9),"mm_dpi1_pixel" , "lvds_pxl" , 10),"mm_dpi1_engine" , "mm_sel" , 11),"mm_hdmi_pixel" , "dpi0_sel" , 12),"mm_hdmi_pllck" , "hdmi_sel" , 13),"mm_hdmi_audio" , "apll1" , 14),"mm_hdmi_spdif" , "apll2" , 15),"mm_lvds_pixel" , "lvds_pxl" , 16),"mm_lvds_cts" , "lvds_cts" , 17),"mm_smi_larb4" , "mm_sel" , 18),"mm_hdmi_hdcp" , "hdcp_sel" , 19),"mm_hdmi_hdcp24m" , "hdcp_24m_sel" , 20),static const struct mtk_clk_desc mm_desc = {static const struct platform_device_id clk_mt8173_mm_id_table[] = {"clk-mt8173-mm" , .driver_data = (kernel_ulong_t)&mm_desc },/* sentinel */ } static struct platform_driver clk_mt8173_mm_drv = {"clk-mt8173-mm" ,"MediaTek MT8173 MultiMedia clocks driver" );"GPL" );
Messung V0.5 C=96 H=100 G=97
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