// SPDX-License-Identifier: GPL-2.0-only /* * Amlogic C3 Peripherals Clock Controller Driver * * Copyright (c) 2023 Amlogic, inc. * Author: Chuan Liu <chuan.liu@amlogic.com> #include <linux/clk-provider.h>#include <linux/platform_device.h>#include "clk-regmap.h" #include "clk-dualdiv.h" #include "meson-clkc-utils.h" #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h>#define RTC_BY_OSCIN_CTRL0 0x8#define RTC_BY_OSCIN_CTRL1 0xc#define RTC_CTRL 0x10#define SYS_CLK_EN0_REG0 0x44#define SYS_CLK_EN0_REG1 0x48#define SYS_CLK_EN0_REG2 0x4c#define CLK12_24_CTRL 0xa8#define AXI_CLK_EN0 0xac#define VDIN_MEAS_CLK_CTRL 0xf8#define VAPB_CLK_CTRL 0xfc#define MIPIDSI_PHY_CLK_CTRL 0x104#define GE2D_CLK_CTRL 0x10c#define ISP0_CLK_CTRL 0x110#define DEWARPA_CLK_CTRL 0x114#define VOUTENC_CLK_CTRL 0x118#define VDEC_CLK_CTRL 0x140#define VDEC3_CLK_CTRL 0x148#define TS_CLK_CTRL 0x158#define ETH_CLK_CTRL 0x164#define NAND_CLK_CTRL 0x168#define SD_EMMC_CLK_CTRL 0x16c#define SPICC_CLK_CTRL 0x174#define GEN_CLK_CTRL 0x178#define SAR_CLK_CTRL0 0x17c#define PWM_CLK_AB_CTRL 0x180#define PWM_CLK_CD_CTRL 0x184#define PWM_CLK_EF_CTRL 0x188#define PWM_CLK_GH_CTRL 0x18c#define PWM_CLK_IJ_CTRL 0x190#define PWM_CLK_KL_CTRL 0x194#define PWM_CLK_MN_CTRL 0x198#define VC9000E_CLK_CTRL 0x19c#define SPIFC_CLK_CTRL 0x1a0#define NNA_CLK_CTRL 0x220static struct clk_regmap rtc_xtal_clkin = {struct clk_regmap_gate_data) {struct clk_init_data) {"rtc_xtal_clkin" ,const struct clk_parent_data) {"oscin" ,static const struct meson_clk_dualdiv_param rtc_32k_div_table[] = {/* sentinel */ } static struct clk_regmap rtc_32k_div = {struct meson_clk_dualdiv_data) {struct clk_init_data) {"rtc_32k_div" ,const struct clk_hw *[]) {static const struct clk_parent_data rtc_32k_mux_parent_data[] = {static struct clk_regmap rtc_32k_mux = {struct clk_regmap_mux_data) {struct clk_init_data) {"rtc_32k_mux" ,static struct clk_regmap rtc_32k = {struct clk_regmap_gate_data) {struct clk_init_data) {"rtc_32k" ,const struct clk_hw *[]) {static const struct clk_parent_data rtc_clk_mux_parent_data[] = {"oscin" },"pad_osc" }static struct clk_regmap rtc_clk = {struct clk_regmap_mux_data) {struct clk_init_data) {"rtc_clk" ,#define C3_CLK_GATE(_name, _reg, _bit, _fw_name, _ops, _flags) \struct clk_regmap _name = { \struct clk_regmap_gate_data){ \struct clk_init_data) { \#_ name, \const struct clk_parent_data) { \#_ fw_name, \#define C3_SYS_GATE(_name, _reg, _bit, _flags) \#define C3_SYS_GATE_RO(_name, _reg, _bit) \static C3_SYS_GATE(sys_reset_ctrl, SYS_CLK_EN0_REG0, 1, 0);static C3_SYS_GATE(sys_pwr_ctrl, SYS_CLK_EN0_REG0, 3, 0);static C3_SYS_GATE(sys_pad_ctrl, SYS_CLK_EN0_REG0, 4, 0);static C3_SYS_GATE(sys_ctrl, SYS_CLK_EN0_REG0, 5, 0);static C3_SYS_GATE(sys_ts_pll, SYS_CLK_EN0_REG0, 6, 0);/* * NOTE: sys_dev_arb provides the clock to the ETH and SPICC arbiters that * access the AXI bus. static C3_SYS_GATE(sys_dev_arb, SYS_CLK_EN0_REG0, 7, 0);/* * FIXME: sys_mmc_pclk provides the clock for the DDR PHY, DDR will only be * initialized in bl2, and this clock should not be touched in linux. static C3_SYS_GATE_RO(sys_mmc_pclk, SYS_CLK_EN0_REG0, 8);/* * NOTE: sys_cpu_ctrl provides the clock for CPU controller. After clock is * disabled, cpu_clk and other key CPU-related configurations cannot take effect. static C3_SYS_GATE(sys_cpu_ctrl, SYS_CLK_EN0_REG0, 11, CLK_IS_CRITICAL);static C3_SYS_GATE(sys_jtag_ctrl, SYS_CLK_EN0_REG0, 12, 0);static C3_SYS_GATE(sys_ir_ctrl, SYS_CLK_EN0_REG0, 13, 0);/* * NOTE: sys_irq_ctrl provides the clock for IRQ controller. The IRQ controller * collects and distributes the interrupt signal to the GIC, PWR_CTRL, and * AOCPU. If the clock is disabled, interrupt-related functions will occurs an * exception. static C3_SYS_GATE(sys_irq_ctrl, SYS_CLK_EN0_REG0, 14, CLK_IS_CRITICAL);static C3_SYS_GATE(sys_msr_clk, SYS_CLK_EN0_REG0, 15, 0);static C3_SYS_GATE(sys_rom, SYS_CLK_EN0_REG0, 16, 0);static C3_SYS_GATE(sys_uart_f, SYS_CLK_EN0_REG0, 17, 0);static C3_SYS_GATE(sys_cpu_apb, SYS_CLK_EN0_REG0, 18, 0);static C3_SYS_GATE(sys_rsa, SYS_CLK_EN0_REG0, 19, 0);static C3_SYS_GATE(sys_sar_adc, SYS_CLK_EN0_REG0, 20, 0);static C3_SYS_GATE(sys_startup, SYS_CLK_EN0_REG0, 21, 0);static C3_SYS_GATE(sys_secure, SYS_CLK_EN0_REG0, 22, 0);static C3_SYS_GATE(sys_spifc, SYS_CLK_EN0_REG0, 23, 0);static C3_SYS_GATE(sys_nna, SYS_CLK_EN0_REG0, 25, 0);static C3_SYS_GATE(sys_eth_mac, SYS_CLK_EN0_REG0, 26, 0);/* * FIXME: sys_gic provides the clock for GIC(Generic Interrupt Controller). * After clock is disabled, The GIC cannot work properly. At present, the driver * used by our GIC is the public driver in kernel, and there is no management * clock in the driver. static C3_SYS_GATE(sys_gic, SYS_CLK_EN0_REG0, 27, CLK_IS_CRITICAL);static C3_SYS_GATE(sys_rama, SYS_CLK_EN0_REG0, 28, 0);/* * NOTE: sys_big_nic provides the clock to the control bus of the NIC(Network * Interface Controller) between multiple devices(CPU, DDR, RAM, ROM, GIC, * SPIFC, CAPU, JTAG, EMMC, SDIO, sec_top, USB, Audio, ETH, SPICC) in the * system. After clock is disabled, The NIC cannot work. static C3_SYS_GATE(sys_big_nic, SYS_CLK_EN0_REG0, 29, CLK_IS_CRITICAL);static C3_SYS_GATE(sys_ramb, SYS_CLK_EN0_REG0, 30, 0);static C3_SYS_GATE(sys_audio_pclk, SYS_CLK_EN0_REG0, 31, 0);static C3_SYS_GATE(sys_pwm_kl, SYS_CLK_EN0_REG1, 0, 0);static C3_SYS_GATE(sys_pwm_ij, SYS_CLK_EN0_REG1, 1, 0);static C3_SYS_GATE(sys_usb, SYS_CLK_EN0_REG1, 2, 0);static C3_SYS_GATE(sys_sd_emmc_a, SYS_CLK_EN0_REG1, 3, 0);static C3_SYS_GATE(sys_sd_emmc_c, SYS_CLK_EN0_REG1, 4, 0);static C3_SYS_GATE(sys_pwm_ab, SYS_CLK_EN0_REG1, 5, 0);static C3_SYS_GATE(sys_pwm_cd, SYS_CLK_EN0_REG1, 6, 0);static C3_SYS_GATE(sys_pwm_ef, SYS_CLK_EN0_REG1, 7, 0);static C3_SYS_GATE(sys_pwm_gh, SYS_CLK_EN0_REG1, 8, 0);static C3_SYS_GATE(sys_spicc_1, SYS_CLK_EN0_REG1, 9, 0);static C3_SYS_GATE(sys_spicc_0, SYS_CLK_EN0_REG1, 10, 0);static C3_SYS_GATE(sys_uart_a, SYS_CLK_EN0_REG1, 11, 0);static C3_SYS_GATE(sys_uart_b, SYS_CLK_EN0_REG1, 12, 0);static C3_SYS_GATE(sys_uart_c, SYS_CLK_EN0_REG1, 13, 0);static C3_SYS_GATE(sys_uart_d, SYS_CLK_EN0_REG1, 14, 0);static C3_SYS_GATE(sys_uart_e, SYS_CLK_EN0_REG1, 15, 0);static C3_SYS_GATE(sys_i2c_m_a, SYS_CLK_EN0_REG1, 16, 0);static C3_SYS_GATE(sys_i2c_m_b, SYS_CLK_EN0_REG1, 17, 0);static C3_SYS_GATE(sys_i2c_m_c, SYS_CLK_EN0_REG1, 18, 0);static C3_SYS_GATE(sys_i2c_m_d, SYS_CLK_EN0_REG1, 19, 0);static C3_SYS_GATE(sys_i2c_s_a, SYS_CLK_EN0_REG1, 20, 0);static C3_SYS_GATE(sys_rtc, SYS_CLK_EN0_REG1, 21, 0);static C3_SYS_GATE(sys_ge2d, SYS_CLK_EN0_REG1, 22, 0);static C3_SYS_GATE(sys_isp, SYS_CLK_EN0_REG1, 23, 0);static C3_SYS_GATE(sys_gpv_isp_nic, SYS_CLK_EN0_REG1, 24, 0);static C3_SYS_GATE(sys_gpv_cve_nic, SYS_CLK_EN0_REG1, 25, 0);static C3_SYS_GATE(sys_mipi_dsi_host, SYS_CLK_EN0_REG1, 26, 0);static C3_SYS_GATE(sys_mipi_dsi_phy, SYS_CLK_EN0_REG1, 27, 0);static C3_SYS_GATE(sys_eth_phy, SYS_CLK_EN0_REG1, 28, 0);static C3_SYS_GATE(sys_acodec, SYS_CLK_EN0_REG1, 29, 0);static C3_SYS_GATE(sys_dwap, SYS_CLK_EN0_REG1, 30, 0);static C3_SYS_GATE(sys_dos, SYS_CLK_EN0_REG1, 31, 0);static C3_SYS_GATE(sys_cve, SYS_CLK_EN0_REG2, 0, 0);static C3_SYS_GATE(sys_vout, SYS_CLK_EN0_REG2, 1, 0);static C3_SYS_GATE(sys_vc9000e, SYS_CLK_EN0_REG2, 2, 0);static C3_SYS_GATE(sys_pwm_mn, SYS_CLK_EN0_REG2, 3, 0);static C3_SYS_GATE(sys_sd_emmc_b, SYS_CLK_EN0_REG2, 4, 0);#define C3_AXI_GATE(_name, _reg, _bit, _flags) \/* * NOTE: axi_sys_nic provides the clock to the AXI bus of the system NIC. After * clock is disabled, The NIC cannot work. static C3_AXI_GATE(axi_sys_nic, AXI_CLK_EN0, 2, CLK_IS_CRITICAL);static C3_AXI_GATE(axi_isp_nic, AXI_CLK_EN0, 3, 0);static C3_AXI_GATE(axi_cve_nic, AXI_CLK_EN0, 4, 0);static C3_AXI_GATE(axi_ramb, AXI_CLK_EN0, 5, 0);static C3_AXI_GATE(axi_rama, AXI_CLK_EN0, 6, 0);/* * NOTE: axi_cpu_dmc provides the clock to the AXI bus where the CPU accesses * the DDR. After clock is disabled, The CPU will not have access to the DDR. static C3_AXI_GATE(axi_cpu_dmc, AXI_CLK_EN0, 7, CLK_IS_CRITICAL);static C3_AXI_GATE(axi_nic, AXI_CLK_EN0, 8, 0);static C3_AXI_GATE(axi_dma, AXI_CLK_EN0, 9, 0);/* * NOTE: axi_mux_nic provides the clock to the NIC's AXI bus for NN(Neural * Network) and other devices(CPU, EMMC, SDIO, sec_top, USB, Audio, ETH, SPICC) * to access RAM space. static C3_AXI_GATE(axi_mux_nic, AXI_CLK_EN0, 10, 0);static C3_AXI_GATE(axi_cve, AXI_CLK_EN0, 12, 0);/* * NOTE: axi_dev1_dmc provides the clock for the peripherals(EMMC, SDIO, * sec_top, USB, Audio, ETH, SPICC) to access the AXI bus of the DDR. static C3_AXI_GATE(axi_dev1_dmc, AXI_CLK_EN0, 13, 0);static C3_AXI_GATE(axi_dev0_dmc, AXI_CLK_EN0, 14, 0);static C3_AXI_GATE(axi_dsp_dmc, AXI_CLK_EN0, 15, 0);/* * clk_12_24m model * * |------| |-----| clk_12m_24m |-----| * xtal---->| gate |---->| div |------------>| pad | * |------| |-----| |-----| static struct clk_regmap clk_12_24m_in = {struct clk_regmap_gate_data) {struct clk_init_data) {"clk_12_24m_in" ,const struct clk_parent_data) {"xtal_24m" ,static struct clk_regmap clk_12_24m = {struct clk_regmap_div_data) {struct clk_init_data) {"clk_12_24m" ,const struct clk_hw *[]) {/* Fix me: set value 0 will div by 2 like value 1 */ static struct clk_regmap fclk_25m_div = {struct clk_regmap_div_data) {struct clk_init_data) {"fclk_25m_div" ,const struct clk_parent_data) {"fix" ,static struct clk_regmap fclk_25m = {struct clk_regmap_gate_data) {struct clk_init_data) {"fclk_25m" ,const struct clk_hw *[]) {/* * Channel 3(ddr_dpll_pt_clk) is manged by the DDR module; channel 12(cts_msr_clk) * is manged by clock measures module. Their hardware are out of clock tree. * Channel 4 8 9 10 11 13 14 15 16 18 are not connected. static u32 gen_parent_table[] = { 0, 1, 2, 5, 6, 7, 17, 19, 20, 21, 22, 23, 24};static const struct clk_parent_data gen_parent_data[] = {"oscin" },"sysplldiv16" },"gp0" },"gp1" },"hifi" },"cpudiv16" },"fdiv2" },"fdiv2p5" },"fdiv3" },"fdiv4" },"fdiv5" },"fdiv7" }static struct clk_regmap gen_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"gen_sel" ,static struct clk_regmap gen_div = {struct clk_regmap_div_data) {struct clk_init_data) {"gen_div" ,const struct clk_hw *[]) {static struct clk_regmap gen = {struct clk_regmap_gate_data) {struct clk_init_data) {"gen" ,const struct clk_hw *[]) {static const struct clk_parent_data saradc_parent_data[] = {"oscin" },"sysclk" }static struct clk_regmap saradc_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"saradc_sel" ,static struct clk_regmap saradc_div = {struct clk_regmap_div_data) {struct clk_init_data) {"saradc_div" ,const struct clk_hw *[]) {static struct clk_regmap saradc = {struct clk_regmap_gate_data) {struct clk_init_data) {"saradc" ,const struct clk_hw *[]) {static const struct clk_parent_data pwm_parent_data[] = {"oscin" },"gp1" },"fdiv4" },"fdiv3" }#define AML_PWM_CLK_MUX(_name, _reg, _shift) { \struct clk_regmap_mux_data) { \struct clk_init_data) { \#_ name "_sel" , \#define AML_PWM_CLK_DIV(_name, _reg, _shift) { \struct clk_regmap_div_data) { \struct clk_init_data) { \#_ name "_div" , \const char *[]) { #_ name "_sel" },\#define AML_PWM_CLK_GATE(_name, _reg, _bit) { \struct clk_regmap_gate_data) { \struct clk_init_data) { \#_ name, \const char *[]) { #_ name "_div" },\static struct clk_regmap pwm_a_sel =static struct clk_regmap pwm_a_div =static struct clk_regmap pwm_a =static struct clk_regmap pwm_b_sel =static struct clk_regmap pwm_b_div =static struct clk_regmap pwm_b =static struct clk_regmap pwm_c_sel =static struct clk_regmap pwm_c_div =static struct clk_regmap pwm_c =static struct clk_regmap pwm_d_sel =static struct clk_regmap pwm_d_div =static struct clk_regmap pwm_d =static struct clk_regmap pwm_e_sel =static struct clk_regmap pwm_e_div =static struct clk_regmap pwm_e =static struct clk_regmap pwm_f_sel =static struct clk_regmap pwm_f_div =static struct clk_regmap pwm_f =static struct clk_regmap pwm_g_sel =static struct clk_regmap pwm_g_div =static struct clk_regmap pwm_g =static struct clk_regmap pwm_h_sel =static struct clk_regmap pwm_h_div =static struct clk_regmap pwm_h =static struct clk_regmap pwm_i_sel =static struct clk_regmap pwm_i_div =static struct clk_regmap pwm_i =static struct clk_regmap pwm_j_sel =static struct clk_regmap pwm_j_div =static struct clk_regmap pwm_j =static struct clk_regmap pwm_k_sel =static struct clk_regmap pwm_k_div =static struct clk_regmap pwm_k =static struct clk_regmap pwm_l_sel =static struct clk_regmap pwm_l_div =static struct clk_regmap pwm_l =static struct clk_regmap pwm_m_sel =static struct clk_regmap pwm_m_div =static struct clk_regmap pwm_m =static struct clk_regmap pwm_n_sel =static struct clk_regmap pwm_n_div =static struct clk_regmap pwm_n =static const struct clk_parent_data spicc_parent_data[] = {"oscin" },"sysclk" },"fdiv4" },"fdiv3" },"fdiv2" },"fdiv5" },"fdiv7" },"gp1" }static struct clk_regmap spicc_a_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"spicc_a_sel" ,static struct clk_regmap spicc_a_div = {struct clk_regmap_div_data) {struct clk_init_data) {"spicc_a_div" ,const struct clk_hw *[]) {static struct clk_regmap spicc_a = {struct clk_regmap_gate_data) {struct clk_init_data) {"spicc_a" ,const struct clk_hw *[]) {static struct clk_regmap spicc_b_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"spicc_b_sel" ,static struct clk_regmap spicc_b_div = {struct clk_regmap_div_data) {struct clk_init_data) {"spicc_b_div" ,const struct clk_hw *[]) {static struct clk_regmap spicc_b = {struct clk_regmap_gate_data) {struct clk_init_data) {"spicc_b" ,const struct clk_hw *[]) {static const struct clk_parent_data spifc_parent_data[] = {"gp0" },"fdiv2" },"fdiv3" },"fdiv2p5" },"hifi" },"fdiv4" },"fdiv5" },"fdiv7" }static struct clk_regmap spifc_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"spifc_sel" ,static struct clk_regmap spifc_div = {struct clk_regmap_div_data) {struct clk_init_data) {"spifc_div" ,const struct clk_hw *[]) {static struct clk_regmap spifc = {struct clk_regmap_gate_data) {struct clk_init_data) {"spifc" ,const struct clk_hw *[]) {static const struct clk_parent_data emmc_parent_data[] = {"oscin" },"fdiv2" },"fdiv3" },"hifi" },"fdiv2p5" },"fdiv4" },"gp1" },"gp0" }static struct clk_regmap sd_emmc_a_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"sd_emmc_a_sel" ,static struct clk_regmap sd_emmc_a_div = {struct clk_regmap_div_data) {struct clk_init_data) {"sd_emmc_a_div" ,const struct clk_hw *[]) {static struct clk_regmap sd_emmc_a = {struct clk_regmap_gate_data) {struct clk_init_data) {"sd_emmc_a" ,const struct clk_hw *[]) {static struct clk_regmap sd_emmc_b_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"sd_emmc_b_sel" ,static struct clk_regmap sd_emmc_b_div = {struct clk_regmap_div_data) {struct clk_init_data) {"sd_emmc_b_div" ,const struct clk_hw *[]) {static struct clk_regmap sd_emmc_b = {struct clk_regmap_gate_data) {struct clk_init_data) {"sd_emmc_b" ,const struct clk_hw *[]) {static struct clk_regmap sd_emmc_c_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"sd_emmc_c_sel" ,static struct clk_regmap sd_emmc_c_div = {struct clk_regmap_div_data) {struct clk_init_data) {"sd_emmc_c_div" ,const struct clk_hw *[]) {static struct clk_regmap sd_emmc_c = {struct clk_regmap_gate_data) {struct clk_init_data) {"sd_emmc_c" ,const struct clk_hw *[]) {static struct clk_regmap ts_div = {struct clk_regmap_div_data) {struct clk_init_data) {"ts_div" ,const struct clk_parent_data) {"oscin" ,static struct clk_regmap ts = {struct clk_regmap_gate_data) {struct clk_init_data) {"ts" ,const struct clk_hw *[]) {static const struct clk_parent_data eth_parent = {"fdiv2" ,static struct clk_fixed_factor eth_125m_div = {struct clk_init_data) {"eth_125m_div" ,static struct clk_regmap eth_125m = {struct clk_regmap_gate_data) {struct clk_init_data) {"eth_125m" ,const struct clk_hw *[]) {static struct clk_regmap eth_rmii_div = {struct clk_regmap_div_data) {struct clk_init_data) {"eth_rmii_div" ,static struct clk_regmap eth_rmii = {struct clk_regmap_gate_data) {struct clk_init_data) {"eth_rmii" ,const struct clk_hw *[]) {static const struct clk_parent_data mipi_dsi_meas_parent_data[] = {"oscin" },"fdiv4" },"fdiv3" },"fdiv5" },"gp1" },"gp0" },"fdiv2" },"fdiv7" }static struct clk_regmap mipi_dsi_meas_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"mipi_dsi_meas_sel" ,static struct clk_regmap mipi_dsi_meas_div = {struct clk_regmap_div_data) {struct clk_init_data) {"mipi_dsi_meas_div" ,const struct clk_hw *[]) {static struct clk_regmap mipi_dsi_meas = {struct clk_regmap_gate_data) {struct clk_init_data) {"mipi_dsi_meas" ,const struct clk_hw *[]) {static const struct clk_parent_data dsi_phy_parent_data[] = {"gp1" },"gp0" },"hifi" },"fdiv3" },"fdiv2" },"fdiv2p5" },"fdiv4" },"fdiv7" }static struct clk_regmap dsi_phy_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"dsi_phy_sel" ,static struct clk_regmap dsi_phy_div = {struct clk_regmap_div_data) {struct clk_init_data) {"dsi_phy_div" ,const struct clk_hw *[]) {static struct clk_regmap dsi_phy = {struct clk_regmap_gate_data) {struct clk_init_data) {"dsi_phy" ,const struct clk_hw *[]) {static const struct clk_parent_data vout_mclk_parent_data[] = {"fdiv2p5" },"fdiv3" },"fdiv4" },"fdiv5" },"gp0" },"hifi" },"gp1" },"fdiv7" }static struct clk_regmap vout_mclk_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"vout_mclk_sel" ,static struct clk_regmap vout_mclk_div = {struct clk_regmap_div_data) {struct clk_init_data) {"vout_mclk_div" ,const struct clk_hw *[]) {static struct clk_regmap vout_mclk = {struct clk_regmap_gate_data) {struct clk_init_data) {"vout_mclk" ,const struct clk_hw *[]) {static const struct clk_parent_data vout_enc_parent_data[] = {"gp1" },"fdiv3" },"fdiv4" },"fdiv5" },"gp0" },"hifi" },"fdiv2p5" },"fdiv7" }static struct clk_regmap vout_enc_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"vout_enc_sel" ,static struct clk_regmap vout_enc_div = {struct clk_regmap_div_data) {struct clk_init_data) {"vout_enc_div" ,const struct clk_hw *[]) {static struct clk_regmap vout_enc = {struct clk_regmap_gate_data) {struct clk_init_data) {"vout_enc" ,const struct clk_hw *[]) {static const struct clk_parent_data hcodec_pre_parent_data[] = {"fdiv2p5" },"fdiv3" },"fdiv4" },"fdiv5" },"fdiv7" },"hifi" },"gp0" },"oscin" }static struct clk_regmap hcodec_0_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"hcodec_0_sel" ,static struct clk_regmap hcodec_0_div = {struct clk_regmap_div_data) {struct clk_init_data) {"hcodec_0_div" ,const struct clk_hw *[]) {static struct clk_regmap hcodec_0 = {struct clk_regmap_gate_data) {struct clk_init_data) {"hcodec_0" ,const struct clk_hw *[]) {static struct clk_regmap hcodec_1_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"hcodec_1_sel" ,static struct clk_regmap hcodec_1_div = {struct clk_regmap_div_data) {struct clk_init_data) {"hcodec_1_div" ,const struct clk_hw *[]) {static struct clk_regmap hcodec_1 = {struct clk_regmap_gate_data) {struct clk_init_data) {"hcodec_1" ,const struct clk_hw *[]) {static const struct clk_parent_data hcodec_parent_data[] = {static struct clk_regmap hcodec = {struct clk_regmap_mux_data) {struct clk_init_data) {"hcodec" ,static const struct clk_parent_data vc9000e_parent_data[] = {"oscin" },"fdiv4" },"fdiv3" },"fdiv5" },"fdiv7" },"fdiv2p5" },"hifi" },"gp0" }static struct clk_regmap vc9000e_aclk_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"vc9000e_aclk_sel" ,static struct clk_regmap vc9000e_aclk_div = {struct clk_regmap_div_data) {struct clk_init_data) {"vc9000e_aclk_div" ,const struct clk_hw *[]) {static struct clk_regmap vc9000e_aclk = {struct clk_regmap_gate_data) {struct clk_init_data) {"vc9000e_aclk" ,const struct clk_hw *[]) {static struct clk_regmap vc9000e_core_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"vc9000e_core_sel" ,static struct clk_regmap vc9000e_core_div = {struct clk_regmap_div_data) {struct clk_init_data) {"vc9000e_core_div" ,const struct clk_hw *[]) {static struct clk_regmap vc9000e_core = {struct clk_regmap_gate_data) {struct clk_init_data) {"vc9000e_core" ,const struct clk_hw *[]) {static const struct clk_parent_data csi_phy_parent_data[] = {"fdiv2p5" },"fdiv3" },"fdiv4" },"fdiv5" },"gp0" },"hifi" },"gp1" },"oscin" }static struct clk_regmap csi_phy0_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"csi_phy0_sel" ,static struct clk_regmap csi_phy0_div = {struct clk_regmap_div_data) {struct clk_init_data) {"csi_phy0_div" ,const struct clk_hw *[]) {static struct clk_regmap csi_phy0 = {struct clk_regmap_gate_data) {struct clk_init_data) {"csi_phy0" ,const struct clk_hw *[]) {static const struct clk_parent_data dewarpa_parent_data[] = {"fdiv2p5" },"fdiv3" },"fdiv4" },"fdiv5" },"gp0" },"hifi" },"gp1" },"fdiv7" }static struct clk_regmap dewarpa_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"dewarpa_sel" ,static struct clk_regmap dewarpa_div = {struct clk_regmap_div_data) {struct clk_init_data) {"dewarpa_div" ,const struct clk_hw *[]) {static struct clk_regmap dewarpa = {struct clk_regmap_gate_data) {struct clk_init_data) {"dewarpa" ,const struct clk_hw *[]) {static const struct clk_parent_data isp_parent_data[] = {"fdiv2p5" },"fdiv3" },"fdiv4" },"fdiv5" },"gp0" },"hifi" },"gp1" },"oscin" }static struct clk_regmap isp0_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"isp0_sel" ,static struct clk_regmap isp0_div = {struct clk_regmap_div_data) {struct clk_init_data) {"isp0_div" ,const struct clk_hw *[]) {static struct clk_regmap isp0 = {struct clk_regmap_gate_data) {struct clk_init_data) {"isp0" ,const struct clk_hw *[]) {static const struct clk_parent_data nna_core_parent_data[] = {"oscin" },"fdiv2p5" },"fdiv4" },"fdiv3" },"fdiv5" },"fdiv2" },"gp1" },"hifi" }static struct clk_regmap nna_core_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"nna_core_sel" ,static struct clk_regmap nna_core_div = {struct clk_regmap_div_data) {struct clk_init_data) {"nna_core_div" ,const struct clk_hw *[]) {static struct clk_regmap nna_core = {struct clk_regmap_gate_data) {struct clk_init_data) {"nna_core" ,const struct clk_hw *[]) {static const struct clk_parent_data ge2d_parent_data[] = {"oscin" },"fdiv2p5" },"fdiv3" },"fdiv4" },"hifi" },"fdiv5" },"gp0" },static struct clk_regmap ge2d_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"ge2d_sel" ,static struct clk_regmap ge2d_div = {struct clk_regmap_div_data) {struct clk_init_data) {"ge2d_div" ,const struct clk_hw *[]) {static struct clk_regmap ge2d = {struct clk_regmap_gate_data) {struct clk_init_data) {"ge2d" ,const struct clk_hw *[]) {static const struct clk_parent_data vapb_parent_data[] = {"fdiv2p5" },"fdiv3" },"fdiv4" },"fdiv5" },"gp0" },"hifi" },"gp1" },"oscin" },static struct clk_regmap vapb_sel = {struct clk_regmap_mux_data) {struct clk_init_data) {"vapb_sel" ,static struct clk_regmap vapb_div = {struct clk_regmap_div_data) {struct clk_init_data) {"vapb_div" ,const struct clk_hw *[]) {static struct clk_regmap vapb = {struct clk_regmap_gate_data) {struct clk_init_data) {"vapb" ,const struct clk_hw *[]) {static struct clk_hw *c3_periphs_hw_clks[] = {static const struct regmap_config clkc_regmap_config = {static struct meson_clk_hw_data c3_periphs_clks = {static int c3_peripherals_probe(struct platform_device *pdev)struct device *dev = &pdev->dev;struct regmap *regmap;void __iomem *base;int clkid, ret;if (IS_ERR(base))return PTR_ERR(base);if (IS_ERR(regmap))return PTR_ERR(regmap);for (clkid = 0; clkid < c3_periphs_clks.num; clkid++) {/* array might be sparse */ if (!c3_periphs_clks.hws[clkid])continue ;if (ret) {"Clock registration failed\n" );return ret;return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get,static const struct of_device_id c3_peripherals_clkc_match_table[] = {"amlogic,c3-peripherals-clkc" ,/* sentinel */ } static struct platform_driver c3_peripherals_driver = {"c3-peripherals-clkc" ,"Amlogic C3 Peripherals Clock Controller driver" );"Chuan Liu <chuan.liu@amlogic.com>" );"GPL" );"CLK_MESON" );
Messung V0.5 in Prozent C=100 H=100 G=100
¤ Dauer der Verarbeitung: 0.21 Sekunden
(vorverarbeitet am 2026-04-29)
¤ *© Formatika GbR, Deutschland
