// SPDX-License-Identifier: (GPL-2.0-only OR MIT) /* * Amlogic S4 Peripherals Clock Controller Driver * * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved * Author: Yu Tu <yu.tu@amlogic.com> #include <linux/clk-provider.h>#include <linux/of_device.h>#include <linux/platform_device.h>#include "clk-regmap.h" #include "vid-pll-div.h" #include "clk-dualdiv.h" #include "meson-clkc-utils.h" #include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>#define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x008#define CLKCTRL_RTC_BY_OSCIN_CTRL1 0x00c#define CLKCTRL_RTC_CTRL 0x010#define CLKCTRL_SYS_CLK_CTRL0 0x040#define CLKCTRL_SYS_CLK_EN0_REG0 0x044#define CLKCTRL_SYS_CLK_EN0_REG1 0x048#define CLKCTRL_SYS_CLK_EN0_REG2 0x04c#define CLKCTRL_SYS_CLK_EN0_REG3 0x050#define CLKCTRL_CECA_CTRL0 0x088#define CLKCTRL_CECA_CTRL1 0x08c#define CLKCTRL_CECB_CTRL0 0x090#define CLKCTRL_CECB_CTRL1 0x094#define CLKCTRL_SC_CLK_CTRL 0x098#define CLKCTRL_CLK12_24_CTRL 0x0a8#define CLKCTRL_VID_CLK_CTRL 0x0c0#define CLKCTRL_VID_CLK_CTRL2 0x0c4#define CLKCTRL_VID_CLK_DIV 0x0c8#define CLKCTRL_VIID_CLK_DIV 0x0cc#define CLKCTRL_VIID_CLK_CTRL 0x0d0#define CLKCTRL_HDMI_CLK_CTRL 0x0e0#define CLKCTRL_VID_PLL_CLK_DIV 0x0e4#define CLKCTRL_VPU_CLK_CTRL 0x0e8#define CLKCTRL_VPU_CLKB_CTRL 0x0ec#define CLKCTRL_VPU_CLKC_CTRL 0x0f0#define CLKCTRL_VID_LOCK_CLK_CTRL 0x0f4#define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8#define CLKCTRL_VAPBCLK_CTRL 0x0fc#define CLKCTRL_HDCP22_CTRL 0x100#define CLKCTRL_VDEC_CLK_CTRL 0x140#define CLKCTRL_VDEC2_CLK_CTRL 0x144#define CLKCTRL_VDEC3_CLK_CTRL 0x148#define CLKCTRL_VDEC4_CLK_CTRL 0x14c#define CLKCTRL_TS_CLK_CTRL 0x158#define CLKCTRL_MALI_CLK_CTRL 0x15c#define CLKCTRL_NAND_CLK_CTRL 0x168#define CLKCTRL_SD_EMMC_CLK_CTRL 0x16c#define CLKCTRL_SPICC_CLK_CTRL 0x174#define CLKCTRL_GEN_CLK_CTRL 0x178#define CLKCTRL_SAR_CLK_CTRL 0x17c#define CLKCTRL_PWM_CLK_AB_CTRL 0x180#define CLKCTRL_PWM_CLK_CD_CTRL 0x184#define CLKCTRL_PWM_CLK_EF_CTRL 0x188#define CLKCTRL_PWM_CLK_GH_CTRL 0x18c#define CLKCTRL_PWM_CLK_IJ_CTRL 0x190#define CLKCTRL_DEMOD_CLK_CTRL 0x200static struct clk_regmap s4_rtc_32k_by_oscin_clkin = {struct clk_regmap_gate_data){struct clk_init_data) {"rtc_32k_by_oscin_clkin" ,const struct clk_parent_data []) {"xtal" , }static const struct meson_clk_dualdiv_param s4_32k_div_table[] = {static struct clk_regmap s4_rtc_32k_by_oscin_div = {struct meson_clk_dualdiv_data){struct clk_init_data){"rtc_32k_by_oscin_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_rtc_32k_by_oscin_sel = {struct clk_regmap_mux_data) {struct clk_init_data){"rtc_32k_by_oscin_sel" ,const struct clk_hw *[]) {static struct clk_regmap s4_rtc_32k_by_oscin = {struct clk_regmap_gate_data){struct clk_init_data) {"rtc_32k_by_oscin" ,const struct clk_hw *[]) {static struct clk_regmap s4_rtc_clk = {struct clk_regmap_mux_data) {struct clk_init_data){"rtc_clk_sel" ,const struct clk_hw *[]) {/* The index 5 is AXI_CLK, which is dedicated to AXI. So skip it. */ static u32 mux_table_sys_ab_clk_sel[] = { 0, 1, 2, 3, 4, 6, 7 };static const struct clk_parent_data sys_ab_clk_parent_data[] = {"xtal" },"fclk_div2" },"fclk_div3" },"fclk_div4" },"fclk_div5" },"fclk_div7" },/* * This clock is initialized by ROMcode. * The chip was changed SYS CLK for security reasons. SYS CLK registers are not writable * in the kernel phase. Write of SYS related register will cause the system to crash. * Meanwhile, these clock won't ever change at runtime. * For the above reasons, we can only use ro_ops for SYS related clocks. static struct clk_regmap s4_sysclk_b_sel = {struct clk_regmap_mux_data){struct clk_init_data){"sysclk_b_sel" ,static struct clk_regmap s4_sysclk_b_div = {struct clk_regmap_div_data){struct clk_init_data){"sysclk_b_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_sysclk_b = {struct clk_regmap_gate_data){struct clk_init_data) {"sysclk_b" ,const struct clk_hw *[]) {static struct clk_regmap s4_sysclk_a_sel = {struct clk_regmap_mux_data){struct clk_init_data){"sysclk_a_sel" ,static struct clk_regmap s4_sysclk_a_div = {struct clk_regmap_div_data){struct clk_init_data){"sysclk_a_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_sysclk_a = {struct clk_regmap_gate_data){struct clk_init_data) {"sysclk_a" ,const struct clk_hw *[]) {static struct clk_regmap s4_sys_clk = {struct clk_regmap_mux_data){struct clk_init_data){"sys_clk" ,const struct clk_hw *[]) {static struct clk_regmap s4_ceca_32k_clkin = {struct clk_regmap_gate_data){struct clk_init_data) {"ceca_32k_clkin" ,const struct clk_parent_data []) {"xtal" , }static struct clk_regmap s4_ceca_32k_div = {struct meson_clk_dualdiv_data){struct clk_init_data){"ceca_32k_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_ceca_32k_sel_pre = {struct clk_regmap_mux_data) {struct clk_init_data){"ceca_32k_sel_pre" ,const struct clk_hw *[]) {static struct clk_regmap s4_ceca_32k_sel = {struct clk_regmap_mux_data) {struct clk_init_data){"ceca_32k_sel" ,const struct clk_hw *[]) {static struct clk_regmap s4_ceca_32k_clkout = {struct clk_regmap_gate_data){struct clk_init_data){"ceca_32k_clkout" ,const struct clk_hw *[]) {static struct clk_regmap s4_cecb_32k_clkin = {struct clk_regmap_gate_data){struct clk_init_data) {"cecb_32k_clkin" ,const struct clk_parent_data []) {"xtal" , }static struct clk_regmap s4_cecb_32k_div = {struct meson_clk_dualdiv_data){struct clk_init_data){"cecb_32k_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_cecb_32k_sel_pre = {struct clk_regmap_mux_data) {struct clk_init_data){"cecb_32k_sel_pre" ,const struct clk_hw *[]) {static struct clk_regmap s4_cecb_32k_sel = {struct clk_regmap_mux_data) {struct clk_init_data){"cecb_32k_sel" ,const struct clk_hw *[]) {static struct clk_regmap s4_cecb_32k_clkout = {struct clk_regmap_gate_data){struct clk_init_data){"cecb_32k_clkout" ,const struct clk_hw *[]) {static const struct clk_parent_data s4_sc_parent_data[] = {"fclk_div4" },"fclk_div3" },"fclk_div5" },"xtal" , }static struct clk_regmap s4_sc_clk_mux = {struct clk_regmap_mux_data){struct clk_init_data) {"sc_clk_mux" ,static struct clk_regmap s4_sc_clk_div = {struct clk_regmap_div_data){struct clk_init_data) {"sc_clk_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_sc_clk_gate = {struct clk_regmap_gate_data){struct clk_init_data){"sc_clk_gate" ,const struct clk_hw *[]) {static struct clk_regmap s4_12_24M_clk_gate = {struct clk_regmap_gate_data){struct clk_init_data) {"12_24m_gate" ,const struct clk_parent_data []) {"xtal" , }static struct clk_fixed_factor s4_12M_clk_div = {struct clk_init_data){"12M" ,const struct clk_hw *[]) {static struct clk_regmap s4_12_24M_clk = {struct clk_regmap_mux_data){struct clk_init_data) {"12_24m" ,const struct clk_hw *[]) {/* Video Clocks */ static struct clk_regmap s4_vid_pll_div = {struct meson_vid_pll_div_data){struct clk_init_data) {"vid_pll_div" ,/* * TODO meson_vid_pll_div_ro_ops to meson_vid_pll_div_ops const struct clk_parent_data []) {"hdmi_pll" , }static struct clk_regmap s4_vid_pll_sel = {struct clk_regmap_mux_data){struct clk_init_data){"vid_pll_sel" ,const struct clk_parent_data []) {"hdmi_pll" , }static struct clk_regmap s4_vid_pll = {struct clk_regmap_gate_data){struct clk_init_data) {"vid_pll" ,const struct clk_hw *[]) {static const struct clk_parent_data s4_vclk_parent_data[] = {"gp0_pll" , },"hifi_pll" , },"mpll1" , },"fclk_div3" , },"fclk_div4" , },"fclk_div5" , },"fclk_div7" , },static struct clk_regmap s4_vclk_sel = {struct clk_regmap_mux_data){struct clk_init_data){"vclk_sel" ,static struct clk_regmap s4_vclk2_sel = {struct clk_regmap_mux_data){struct clk_init_data){"vclk2_sel" ,static struct clk_regmap s4_vclk_input = {struct clk_regmap_gate_data){struct clk_init_data) {"vclk_input" ,const struct clk_hw *[]) { &s4_vclk_sel.hw },static struct clk_regmap s4_vclk2_input = {struct clk_regmap_gate_data){struct clk_init_data) {"vclk2_input" ,const struct clk_hw *[]) { &s4_vclk2_sel.hw },static struct clk_regmap s4_vclk_div = {struct clk_regmap_div_data){struct clk_init_data){"vclk_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_vclk2_div = {struct clk_regmap_div_data){struct clk_init_data){"vclk2_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_vclk = {struct clk_regmap_gate_data){struct clk_init_data) {"vclk" ,const struct clk_hw *[]) { &s4_vclk_div.hw },static struct clk_regmap s4_vclk2 = {struct clk_regmap_gate_data){struct clk_init_data) {"vclk2" ,const struct clk_hw *[]) { &s4_vclk2_div.hw },static struct clk_regmap s4_vclk_div1 = {struct clk_regmap_gate_data){struct clk_init_data) {"vclk_div1" ,const struct clk_hw *[]) { &s4_vclk.hw },static struct clk_regmap s4_vclk_div2_en = {struct clk_regmap_gate_data){struct clk_init_data) {"vclk_div2_en" ,const struct clk_hw *[]) { &s4_vclk.hw },static struct clk_regmap s4_vclk_div4_en = {struct clk_regmap_gate_data){struct clk_init_data) {"vclk_div4_en" ,const struct clk_hw *[]) { &s4_vclk.hw },static struct clk_regmap s4_vclk_div6_en = {struct clk_regmap_gate_data){struct clk_init_data) {"vclk_div6_en" ,const struct clk_hw *[]) { &s4_vclk.hw },static struct clk_regmap s4_vclk_div12_en = {struct clk_regmap_gate_data){struct clk_init_data) {"vclk_div12_en" ,const struct clk_hw *[]) { &s4_vclk.hw },static struct clk_regmap s4_vclk2_div1 = {struct clk_regmap_gate_data){struct clk_init_data) {"vclk2_div1" ,const struct clk_hw *[]) { &s4_vclk2.hw },static struct clk_regmap s4_vclk2_div2_en = {struct clk_regmap_gate_data){struct clk_init_data) {"vclk2_div2_en" ,const struct clk_hw *[]) { &s4_vclk2.hw },static struct clk_regmap s4_vclk2_div4_en = {struct clk_regmap_gate_data){struct clk_init_data) {"vclk2_div4_en" ,const struct clk_hw *[]) { &s4_vclk2.hw },static struct clk_regmap s4_vclk2_div6_en = {struct clk_regmap_gate_data){struct clk_init_data) {"vclk2_div6_en" ,const struct clk_hw *[]) { &s4_vclk2.hw },static struct clk_regmap s4_vclk2_div12_en = {struct clk_regmap_gate_data){struct clk_init_data) {"vclk2_div12_en" ,const struct clk_hw *[]) { &s4_vclk2.hw },static struct clk_fixed_factor s4_vclk_div2 = {struct clk_init_data){"vclk_div2" ,const struct clk_hw *[]) {static struct clk_fixed_factor s4_vclk_div4 = {struct clk_init_data){"vclk_div4" ,const struct clk_hw *[]) {static struct clk_fixed_factor s4_vclk_div6 = {struct clk_init_data){"vclk_div6" ,const struct clk_hw *[]) {static struct clk_fixed_factor s4_vclk_div12 = {struct clk_init_data){"vclk_div12" ,const struct clk_hw *[]) {static struct clk_fixed_factor s4_vclk2_div2 = {struct clk_init_data){"vclk2_div2" ,const struct clk_hw *[]) {static struct clk_fixed_factor s4_vclk2_div4 = {struct clk_init_data){"vclk2_div4" ,const struct clk_hw *[]) {static struct clk_fixed_factor s4_vclk2_div6 = {struct clk_init_data){"vclk2_div6" ,const struct clk_hw *[]) {static struct clk_fixed_factor s4_vclk2_div12 = {struct clk_init_data){"vclk2_div12" ,const struct clk_hw *[]) {/* The 5,6,7 indexes corresponds to no real clock, so there are not used. */ static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };static const struct clk_hw *s4_cts_parent_hws[] = {static struct clk_regmap s4_cts_enci_sel = {struct clk_regmap_mux_data){struct clk_init_data){"cts_enci_sel" ,static struct clk_regmap s4_cts_encp_sel = {struct clk_regmap_mux_data){struct clk_init_data){"cts_encp_sel" ,static struct clk_regmap s4_cts_vdac_sel = {struct clk_regmap_mux_data){struct clk_init_data){"cts_vdac_sel" ,/* The 5,6,7 indexes corresponds to no real clock, so there are not used. */ static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };static const struct clk_hw *s4_cts_hdmi_tx_parent_hws[] = {static struct clk_regmap s4_hdmi_tx_sel = {struct clk_regmap_mux_data){struct clk_init_data){"hdmi_tx_sel" ,static struct clk_regmap s4_cts_enci = {struct clk_regmap_gate_data){struct clk_init_data) {"cts_enci" ,const struct clk_hw *[]) {static struct clk_regmap s4_cts_encp = {struct clk_regmap_gate_data){struct clk_init_data) {"cts_encp" ,const struct clk_hw *[]) {static struct clk_regmap s4_cts_vdac = {struct clk_regmap_gate_data){struct clk_init_data) {"cts_vdac" ,const struct clk_hw *[]) {static struct clk_regmap s4_hdmi_tx = {struct clk_regmap_gate_data){struct clk_init_data) {"hdmi_tx" ,const struct clk_hw *[]) {/* HDMI Clocks */ static const struct clk_parent_data s4_hdmi_parent_data[] = {"xtal" , },"fclk_div4" , },"fclk_div3" , },"fclk_div5" , }static struct clk_regmap s4_hdmi_sel = {struct clk_regmap_mux_data){struct clk_init_data){"hdmi_sel" ,static struct clk_regmap s4_hdmi_div = {struct clk_regmap_div_data){struct clk_init_data){"hdmi_div" ,const struct clk_hw *[]) { &s4_hdmi_sel.hw },static struct clk_regmap s4_hdmi = {struct clk_regmap_gate_data){struct clk_init_data) {"hdmi" ,const struct clk_hw *[]) { &s4_hdmi_div.hw },static struct clk_regmap s4_ts_clk_div = {struct clk_regmap_div_data){struct clk_init_data){"ts_clk_div" ,const struct clk_parent_data) {"xtal" ,static struct clk_regmap s4_ts_clk_gate = {struct clk_regmap_gate_data){struct clk_init_data){"ts_clk" ,const struct clk_hw *[]) {/* * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) * muxed by a glitch-free switch. The CCF can manage this glitch-free * mux because it does top-to-bottom updates the each clock tree and * switches to the "inactive" one when CLK_SET_RATE_GATE is set. static const struct clk_parent_data s4_mali_0_1_parent_data[] = {"xtal" , },"gp0_pll" , },"hifi_pll" , },"fclk_div2p5" , },"fclk_div3" , },"fclk_div4" , },"fclk_div5" , },"fclk_div7" , }static struct clk_regmap s4_mali_0_sel = {struct clk_regmap_mux_data){struct clk_init_data){"mali_0_sel" ,/* * Don't request the parent to change the rate because * all GPU frequencies can be derived from the fclk_* * clocks and one special GP0_PLL setting. This is * important because we need the HIFI PLL clock for audio. static struct clk_regmap s4_mali_0_div = {struct clk_regmap_div_data){struct clk_init_data){"mali_0_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_mali_0 = {struct clk_regmap_gate_data){struct clk_init_data){"mali_0" ,const struct clk_hw *[]) {static struct clk_regmap s4_mali_1_sel = {struct clk_regmap_mux_data){struct clk_init_data){"mali_1_sel" ,static struct clk_regmap s4_mali_1_div = {struct clk_regmap_div_data){struct clk_init_data){"mali_1_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_mali_1 = {struct clk_regmap_gate_data){struct clk_init_data){"mali_1" ,const struct clk_hw *[]) {static const struct clk_hw *s4_mali_parent_hws[] = {static struct clk_regmap s4_mali_mux = {struct clk_regmap_mux_data){struct clk_init_data){"mali" ,/* VDEC clocks */ static const struct clk_parent_data s4_dec_parent_data[] = {"fclk_div2p5" , },"fclk_div3" , },"fclk_div4" , },"fclk_div5" , },"fclk_div7" , },"hifi_pll" , },"gp0_pll" , },"xtal" , }static struct clk_regmap s4_vdec_p0_mux = {struct clk_regmap_mux_data){struct clk_init_data) {"vdec_p0_mux" ,static struct clk_regmap s4_vdec_p0_div = {struct clk_regmap_div_data){struct clk_init_data) {"vdec_p0_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_vdec_p0 = {struct clk_regmap_gate_data){struct clk_init_data){"vdec_p0" ,const struct clk_hw *[]) {static struct clk_regmap s4_vdec_p1_mux = {struct clk_regmap_mux_data){struct clk_init_data) {"vdec_p1_mux" ,static struct clk_regmap s4_vdec_p1_div = {struct clk_regmap_div_data){struct clk_init_data) {"vdec_p1_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_vdec_p1 = {struct clk_regmap_gate_data){struct clk_init_data){"vdec_p1" ,const struct clk_hw *[]) {static const struct clk_hw *s4_vdec_mux_parent_hws[] = {static struct clk_regmap s4_vdec_mux = {struct clk_regmap_mux_data){struct clk_init_data) {"vdec_mux" ,static struct clk_regmap s4_hevcf_p0_mux = {struct clk_regmap_mux_data){struct clk_init_data) {"hevcf_p0_mux" ,static struct clk_regmap s4_hevcf_p0_div = {struct clk_regmap_div_data){struct clk_init_data) {"hevcf_p0_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_hevcf_p0 = {struct clk_regmap_gate_data){struct clk_init_data){"hevcf_p0_gate" ,const struct clk_hw *[]) {static struct clk_regmap s4_hevcf_p1_mux = {struct clk_regmap_mux_data){struct clk_init_data) {"hevcf_p1_mux" ,static struct clk_regmap s4_hevcf_p1_div = {struct clk_regmap_div_data){struct clk_init_data) {"hevcf_p1_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_hevcf_p1 = {struct clk_regmap_gate_data){struct clk_init_data){"hevcf_p1" ,const struct clk_hw *[]) {static const struct clk_hw *s4_hevcf_mux_parent_hws[] = {static struct clk_regmap s4_hevcf_mux = {struct clk_regmap_mux_data){struct clk_init_data) {"hevcf" ,/* VPU Clock */ static const struct clk_parent_data s4_vpu_parent_data[] = {"fclk_div3" , },"fclk_div4" , },"fclk_div5" , },"fclk_div7" , },"mpll1" , },"hifi_pll" , },"gp0_pll" , },static struct clk_regmap s4_vpu_0_sel = {struct clk_regmap_mux_data){struct clk_init_data){"vpu_0_sel" ,static struct clk_regmap s4_vpu_0_div = {struct clk_regmap_div_data){struct clk_init_data){"vpu_0_div" ,const struct clk_hw *[]) { &s4_vpu_0_sel.hw },static struct clk_regmap s4_vpu_0 = {struct clk_regmap_gate_data){struct clk_init_data) {"vpu_0" ,const struct clk_hw *[]) { &s4_vpu_0_div.hw },static struct clk_regmap s4_vpu_1_sel = {struct clk_regmap_mux_data){struct clk_init_data){"vpu_1_sel" ,static struct clk_regmap s4_vpu_1_div = {struct clk_regmap_div_data){struct clk_init_data){"vpu_1_div" ,const struct clk_hw *[]) { &s4_vpu_1_sel.hw },static struct clk_regmap s4_vpu_1 = {struct clk_regmap_gate_data){struct clk_init_data) {"vpu_1" ,const struct clk_hw *[]) { &s4_vpu_1_div.hw },static struct clk_regmap s4_vpu = {struct clk_regmap_mux_data){struct clk_init_data){"vpu" ,const struct clk_hw *[]) {static const struct clk_parent_data vpu_clkb_tmp_parent_data[] = {"fclk_div4" , },"fclk_div5" , },"fclk_div7" , }static struct clk_regmap s4_vpu_clkb_tmp_mux = {struct clk_regmap_mux_data){struct clk_init_data) {"vpu_clkb_tmp_mux" ,static struct clk_regmap s4_vpu_clkb_tmp_div = {struct clk_regmap_div_data){struct clk_init_data) {"vpu_clkb_tmp_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_vpu_clkb_tmp = {struct clk_regmap_gate_data){struct clk_init_data){"vpu_clkb_tmp" ,const struct clk_hw *[]) {static struct clk_regmap s4_vpu_clkb_div = {struct clk_regmap_div_data){struct clk_init_data) {"vpu_clkb_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_vpu_clkb = {struct clk_regmap_gate_data){struct clk_init_data){"vpu_clkb" ,const struct clk_hw *[]) {static const struct clk_parent_data s4_vpu_clkc_parent_data[] = {"fclk_div4" , },"fclk_div3" , },"fclk_div5" , },"fclk_div7" , },"mpll1" , },"mpll2" , },"gp0_pll" , },static struct clk_regmap s4_vpu_clkc_p0_mux = {struct clk_regmap_mux_data){struct clk_init_data) {"vpu_clkc_p0_mux" ,static struct clk_regmap s4_vpu_clkc_p0_div = {struct clk_regmap_div_data){struct clk_init_data) {"vpu_clkc_p0_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_vpu_clkc_p0 = {struct clk_regmap_gate_data){struct clk_init_data){"vpu_clkc_p0" ,const struct clk_hw *[]) {static struct clk_regmap s4_vpu_clkc_p1_mux = {struct clk_regmap_mux_data){struct clk_init_data) {"vpu_clkc_p1_mux" ,static struct clk_regmap s4_vpu_clkc_p1_div = {struct clk_regmap_div_data){struct clk_init_data) {"vpu_clkc_p1_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_vpu_clkc_p1 = {struct clk_regmap_gate_data){struct clk_init_data){"vpu_clkc_p1" ,const struct clk_hw *[]) {static const struct clk_hw *s4_vpu_mux_parent_hws[] = {static struct clk_regmap s4_vpu_clkc_mux = {struct clk_regmap_mux_data){struct clk_init_data) {"vpu_clkc_mux" ,/* VAPB Clock */ static const struct clk_parent_data s4_vapb_parent_data[] = {"fclk_div4" , },"fclk_div3" , },"fclk_div5" , },"fclk_div7" , },"mpll1" , },"mpll2" , },"fclk_div2p5" , },static struct clk_regmap s4_vapb_0_sel = {struct clk_regmap_mux_data){struct clk_init_data){"vapb_0_sel" ,static struct clk_regmap s4_vapb_0_div = {struct clk_regmap_div_data){struct clk_init_data){"vapb_0_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_vapb_0 = {struct clk_regmap_gate_data){struct clk_init_data) {"vapb_0" ,const struct clk_hw *[]) {static struct clk_regmap s4_vapb_1_sel = {struct clk_regmap_mux_data){struct clk_init_data){"vapb_1_sel" ,static struct clk_regmap s4_vapb_1_div = {struct clk_regmap_div_data){struct clk_init_data){"vapb_1_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_vapb_1 = {struct clk_regmap_gate_data){struct clk_init_data) {"vapb_1" ,const struct clk_hw *[]) {static struct clk_regmap s4_vapb = {struct clk_regmap_mux_data){struct clk_init_data){"vapb_sel" ,const struct clk_hw *[]) {static struct clk_regmap s4_ge2d_gate = {struct clk_regmap_gate_data){struct clk_init_data) {"ge2d_clk" ,const struct clk_hw *[]) { &s4_vapb.hw },static const struct clk_parent_data s4_esmclk_parent_data[] = {"fclk_div7" , },"fclk_div4" , },"fclk_div3" , },"fclk_div5" , },static struct clk_regmap s4_hdcp22_esmclk_mux = {struct clk_regmap_mux_data){struct clk_init_data) {"hdcp22_esmclk_mux" ,static struct clk_regmap s4_hdcp22_esmclk_div = {struct clk_regmap_div_data){struct clk_init_data) {"hdcp22_esmclk_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_hdcp22_esmclk_gate = {struct clk_regmap_gate_data){struct clk_init_data){"hdcp22_esmclk_gate" ,const struct clk_hw *[]) {static const struct clk_parent_data s4_skpclk_parent_data[] = {"xtal" , },"fclk_div4" , },"fclk_div3" , },"fclk_div5" , },static struct clk_regmap s4_hdcp22_skpclk_mux = {struct clk_regmap_mux_data){struct clk_init_data) {"hdcp22_skpclk_mux" ,static struct clk_regmap s4_hdcp22_skpclk_div = {struct clk_regmap_div_data){struct clk_init_data) {"hdcp22_skpclk_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_hdcp22_skpclk_gate = {struct clk_regmap_gate_data){struct clk_init_data){"hdcp22_skpclk_gate" ,const struct clk_hw *[]) {static const struct clk_parent_data s4_vdin_parent_data[] = {"xtal" , },"fclk_div4" , },"fclk_div3" , },"fclk_div5" , },static struct clk_regmap s4_vdin_meas_mux = {struct clk_regmap_mux_data){struct clk_init_data) {"vdin_meas_mux" ,static struct clk_regmap s4_vdin_meas_div = {struct clk_regmap_div_data){struct clk_init_data) {"vdin_meas_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_vdin_meas_gate = {struct clk_regmap_gate_data){struct clk_init_data){"vdin_meas_gate" ,const struct clk_hw *[]) {/* EMMC/NAND clock */ static const struct clk_parent_data s4_sd_emmc_clk0_parent_data[] = {"xtal" , },"fclk_div2" , },"fclk_div3" , },"hifi_pll" , },"fclk_div2p5" , },"mpll2" , },"mpll3" , },"gp0_pll" , },static struct clk_regmap s4_sd_emmc_c_clk0_sel = {struct clk_regmap_mux_data){struct clk_init_data) {"sd_emmc_c_clk0_sel" ,static struct clk_regmap s4_sd_emmc_c_clk0_div = {struct clk_regmap_div_data){struct clk_init_data) {"sd_emmc_c_clk0_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_sd_emmc_c_clk0 = {struct clk_regmap_gate_data){struct clk_init_data){"sd_emmc_c_clk0" ,const struct clk_hw *[]) {static struct clk_regmap s4_sd_emmc_a_clk0_sel = {struct clk_regmap_mux_data){struct clk_init_data) {"sd_emmc_a_clk0_sel" ,static struct clk_regmap s4_sd_emmc_a_clk0_div = {struct clk_regmap_div_data){struct clk_init_data) {"sd_emmc_a_clk0_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_sd_emmc_a_clk0 = {struct clk_regmap_gate_data){struct clk_init_data){"sd_emmc_a_clk0" ,const struct clk_hw *[]) {static struct clk_regmap s4_sd_emmc_b_clk0_sel = {struct clk_regmap_mux_data){struct clk_init_data) {"sd_emmc_b_clk0_sel" ,static struct clk_regmap s4_sd_emmc_b_clk0_div = {struct clk_regmap_div_data){struct clk_init_data) {"sd_emmc_b_clk0_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_sd_emmc_b_clk0 = {struct clk_regmap_gate_data){struct clk_init_data){"sd_emmc_b_clk0" ,const struct clk_hw *[]) {/* SPICC Clock */ static const struct clk_parent_data s4_spicc_parent_data[] = {"xtal" , },"fclk_div4" , },"fclk_div3" , },"fclk_div2" , },"fclk_div5" , },"fclk_div7" , },static struct clk_regmap s4_spicc0_mux = {struct clk_regmap_mux_data){struct clk_init_data) {"spicc0_mux" ,static struct clk_regmap s4_spicc0_div = {struct clk_regmap_div_data){struct clk_init_data) {"spicc0_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_spicc0_gate = {struct clk_regmap_gate_data){struct clk_init_data){"spicc0" ,const struct clk_hw *[]) {/* PWM Clock */ static const struct clk_parent_data s4_pwm_parent_data[] = {"xtal" , },"fclk_div4" , },"fclk_div3" , },static struct clk_regmap s4_pwm_a_mux = {struct clk_regmap_mux_data) {struct clk_init_data){"pwm_a_mux" ,static struct clk_regmap s4_pwm_a_div = {struct clk_regmap_div_data) {struct clk_init_data){"pwm_a_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_pwm_a_gate = {struct clk_regmap_gate_data) {struct clk_init_data){"pwm_a_gate" ,const struct clk_hw *[]) {static struct clk_regmap s4_pwm_b_mux = {struct clk_regmap_mux_data) {struct clk_init_data){"pwm_b_mux" ,static struct clk_regmap s4_pwm_b_div = {struct clk_regmap_div_data) {struct clk_init_data){"pwm_b_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_pwm_b_gate = {struct clk_regmap_gate_data) {struct clk_init_data){"pwm_b_gate" ,const struct clk_hw *[]) {static struct clk_regmap s4_pwm_c_mux = {struct clk_regmap_mux_data) {struct clk_init_data){"pwm_c_mux" ,static struct clk_regmap s4_pwm_c_div = {struct clk_regmap_div_data) {struct clk_init_data){"pwm_c_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_pwm_c_gate = {struct clk_regmap_gate_data) {struct clk_init_data){"pwm_c_gate" ,const struct clk_hw *[]) {static struct clk_regmap s4_pwm_d_mux = {struct clk_regmap_mux_data) {struct clk_init_data){"pwm_d_mux" ,static struct clk_regmap s4_pwm_d_div = {struct clk_regmap_div_data) {struct clk_init_data){"pwm_d_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_pwm_d_gate = {struct clk_regmap_gate_data) {struct clk_init_data){"pwm_d_gate" ,const struct clk_hw *[]) {static struct clk_regmap s4_pwm_e_mux = {struct clk_regmap_mux_data) {struct clk_init_data){"pwm_e_mux" ,static struct clk_regmap s4_pwm_e_div = {struct clk_regmap_div_data) {struct clk_init_data){"pwm_e_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_pwm_e_gate = {struct clk_regmap_gate_data) {struct clk_init_data){"pwm_e_gate" ,const struct clk_hw *[]) {static struct clk_regmap s4_pwm_f_mux = {struct clk_regmap_mux_data) {struct clk_init_data){"pwm_f_mux" ,static struct clk_regmap s4_pwm_f_div = {struct clk_regmap_div_data) {struct clk_init_data){"pwm_f_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_pwm_f_gate = {struct clk_regmap_gate_data) {struct clk_init_data){"pwm_f_gate" ,const struct clk_hw *[]) {static struct clk_regmap s4_pwm_g_mux = {struct clk_regmap_mux_data) {struct clk_init_data){"pwm_g_mux" ,static struct clk_regmap s4_pwm_g_div = {struct clk_regmap_div_data) {struct clk_init_data){"pwm_g_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_pwm_g_gate = {struct clk_regmap_gate_data) {struct clk_init_data){"pwm_g_gate" ,const struct clk_hw *[]) {static struct clk_regmap s4_pwm_h_mux = {struct clk_regmap_mux_data) {struct clk_init_data){"pwm_h_mux" ,static struct clk_regmap s4_pwm_h_div = {struct clk_regmap_div_data) {struct clk_init_data){"pwm_h_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_pwm_h_gate = {struct clk_regmap_gate_data) {struct clk_init_data){"pwm_h_gate" ,const struct clk_hw *[]) {static struct clk_regmap s4_pwm_i_mux = {struct clk_regmap_mux_data) {struct clk_init_data){"pwm_i_mux" ,static struct clk_regmap s4_pwm_i_div = {struct clk_regmap_div_data) {struct clk_init_data){"pwm_i_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_pwm_i_gate = {struct clk_regmap_gate_data) {struct clk_init_data){"pwm_i_gate" ,const struct clk_hw *[]) {static struct clk_regmap s4_pwm_j_mux = {struct clk_regmap_mux_data) {struct clk_init_data){"pwm_j_mux" ,static struct clk_regmap s4_pwm_j_div = {struct clk_regmap_div_data) {struct clk_init_data){"pwm_j_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_pwm_j_gate = {struct clk_regmap_gate_data) {struct clk_init_data){"pwm_j_gate" ,const struct clk_hw *[]) {static struct clk_regmap s4_saradc_mux = {struct clk_regmap_mux_data) {struct clk_init_data){"saradc_mux" ,const struct clk_parent_data []) {"xtal" , },static struct clk_regmap s4_saradc_div = {struct clk_regmap_div_data) {struct clk_init_data){"saradc_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_saradc_gate = {struct clk_regmap_gate_data) {struct clk_init_data){"saradc_clk" ,const struct clk_hw *[]) {/* * gen clk is designed for debug/monitor some internal clock quality. Some of the * corresponding clock sources are not described in the clock tree and internal clock * for debug, so they are skipped. static u32 s4_gen_clk_mux_table[] = { 0, 4, 5, 7, 19, 21, 22,static const struct clk_parent_data s4_gen_clk_parent_data[] = {"xtal" , },"gp0_pll" , },"hifi_pll" , },"fclk_div2" , },"fclk_div3" , },"fclk_div4" , },"fclk_div5" , },"fclk_div7" , },"mpll0" , },"mpll1" , },"mpll2" , },"mpll3" , },static struct clk_regmap s4_gen_clk_sel = {struct clk_regmap_mux_data){struct clk_init_data){"gen_clk_sel" ,/* * Because the GEN clock can be connected to an external pad * and may be set up directly from the device tree. Don't * really want to automatically reparent. static struct clk_regmap s4_gen_clk_div = {struct clk_regmap_div_data){struct clk_init_data){"gen_clk_div" ,const struct clk_hw *[]) {static struct clk_regmap s4_gen_clk = {struct clk_regmap_gate_data){struct clk_init_data) {"gen_clk" ,const struct clk_hw *[]) {#define MESON_GATE(_name, _reg, _bit) \static MESON_GATE(s4_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0);static MESON_GATE(s4_dos, CLKCTRL_SYS_CLK_EN0_REG0, 1);static MESON_GATE(s4_ethphy, CLKCTRL_SYS_CLK_EN0_REG0, 4);static MESON_GATE(s4_mali, CLKCTRL_SYS_CLK_EN0_REG0, 6);static MESON_GATE(s4_aocpu, CLKCTRL_SYS_CLK_EN0_REG0, 13);static MESON_GATE(s4_aucpu, CLKCTRL_SYS_CLK_EN0_REG0, 14);static MESON_GATE(s4_cec, CLKCTRL_SYS_CLK_EN0_REG0, 16);static MESON_GATE(s4_sdemmca, CLKCTRL_SYS_CLK_EN0_REG0, 24);static MESON_GATE(s4_sdemmcb, CLKCTRL_SYS_CLK_EN0_REG0, 25);static MESON_GATE(s4_nand, CLKCTRL_SYS_CLK_EN0_REG0, 26);static MESON_GATE(s4_smartcard, CLKCTRL_SYS_CLK_EN0_REG0, 27);static MESON_GATE(s4_acodec, CLKCTRL_SYS_CLK_EN0_REG0, 28);static MESON_GATE(s4_spifc, CLKCTRL_SYS_CLK_EN0_REG0, 29);static MESON_GATE(s4_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 30);static MESON_GATE(s4_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 31);static MESON_GATE(s4_audio, CLKCTRL_SYS_CLK_EN0_REG1, 0);static MESON_GATE(s4_eth, CLKCTRL_SYS_CLK_EN0_REG1, 3);static MESON_GATE(s4_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 5);static MESON_GATE(s4_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 6);static MESON_GATE(s4_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 7);static MESON_GATE(s4_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 8);static MESON_GATE(s4_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 9);static MESON_GATE(s4_aififo, CLKCTRL_SYS_CLK_EN0_REG1, 11);static MESON_GATE(s4_ts_ddr, CLKCTRL_SYS_CLK_EN0_REG1, 15);static MESON_GATE(s4_ts_pll, CLKCTRL_SYS_CLK_EN0_REG1, 16);static MESON_GATE(s4_g2d, CLKCTRL_SYS_CLK_EN0_REG1, 20);static MESON_GATE(s4_spicc0, CLKCTRL_SYS_CLK_EN0_REG1, 21);static MESON_GATE(s4_usb, CLKCTRL_SYS_CLK_EN0_REG1, 26);static MESON_GATE(s4_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 30);static MESON_GATE(s4_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 31);static MESON_GATE(s4_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG2, 0);static MESON_GATE(s4_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG2, 1);static MESON_GATE(s4_i2c_m_e, CLKCTRL_SYS_CLK_EN0_REG2, 2);static MESON_GATE(s4_hdmitx_apb, CLKCTRL_SYS_CLK_EN0_REG2, 4);static MESON_GATE(s4_i2c_s_a, CLKCTRL_SYS_CLK_EN0_REG2, 5);static MESON_GATE(s4_usb1_to_ddr, CLKCTRL_SYS_CLK_EN0_REG2, 8);static MESON_GATE(s4_hdcp22, CLKCTRL_SYS_CLK_EN0_REG2, 10);static MESON_GATE(s4_mmc_apb, CLKCTRL_SYS_CLK_EN0_REG2, 11);static MESON_GATE(s4_rsa, CLKCTRL_SYS_CLK_EN0_REG2, 18);static MESON_GATE(s4_cpu_debug, CLKCTRL_SYS_CLK_EN0_REG2, 19);static MESON_GATE(s4_vpu_intr, CLKCTRL_SYS_CLK_EN0_REG2, 25);static MESON_GATE(s4_demod, CLKCTRL_SYS_CLK_EN0_REG2, 27);static MESON_GATE(s4_sar_adc, CLKCTRL_SYS_CLK_EN0_REG2, 28);static MESON_GATE(s4_gic, CLKCTRL_SYS_CLK_EN0_REG2, 30);static MESON_GATE(s4_pwm_ab, CLKCTRL_SYS_CLK_EN0_REG3, 7);static MESON_GATE(s4_pwm_cd, CLKCTRL_SYS_CLK_EN0_REG3, 8);static MESON_GATE(s4_pwm_ef, CLKCTRL_SYS_CLK_EN0_REG3, 9);static MESON_GATE(s4_pwm_gh, CLKCTRL_SYS_CLK_EN0_REG3, 10);static MESON_GATE(s4_pwm_ij, CLKCTRL_SYS_CLK_EN0_REG3, 11);/* Array of all clocks provided by this provider */ static struct clk_hw *s4_periphs_hw_clks[] = {static const struct regmap_config clkc_regmap_config = {static struct meson_clk_hw_data s4_periphs_clks = {static int meson_s4_periphs_probe(struct platform_device *pdev)struct device *dev = &pdev->dev;struct regmap *regmap;void __iomem *base;int ret, i;if (IS_ERR(base))return dev_err_probe(dev, PTR_ERR(base),"can't ioremap resource\n" );if (IS_ERR(regmap))return dev_err_probe(dev, PTR_ERR(regmap),"can't init regmap mmio region\n" );for (i = 0; i < s4_periphs_clks.num; i++) {/* array might be sparse */ if (!s4_periphs_clks.hws[i])continue ;if (ret)return dev_err_probe(dev, ret,"clock[%d] registration failed\n" , i);return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &s4_periphs_clks);static const struct of_device_id clkc_match_table[] = {"amlogic,s4-peripherals-clkc" ,static struct platform_driver s4_driver = {"s4-periphs-clkc" ,"Amlogic S4 Peripherals Clock Controller driver" );"Yu Tu <yu.tu@amlogic.com>" );"GPL" );"CLK_MESON" );
Messung V0.5 in Prozent C=100 H=99 G=99
¤ Dauer der Verarbeitung: 0.34 Sekunden
(vorverarbeitet am 2026-04-29)
¤ *© Formatika GbR, Deutschland
