// SPDX-License-Identifier: GPL-2.0 /* * r8a779h0 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2023 Renesas Electronics Corp. * * Based on r8a779g0-cpg-mssr.c #include <linux/bitfield.h>#include <linux/clk.h>#include <linux/clk-provider.h>#include <linux/device.h>#include <linux/err.h>#include <linux/kernel.h>#include <linux/soc/renesas/rcar-rst.h>#include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h>#include "renesas-cpg-mssr.h" #include "rcar-gen4-cpg.h" enum clk_ids {/* Core Clock Outputs exported to DT */ /* External Input Clocks */ /* Internal Core Clocks */ /* Module Clocks */ static const struct cpg_core_clk r8a779h0_core_clks[] __initconst = {/* External Clock Inputs */ "extal" , CLK_EXTAL),"extalr" , CLK_EXTALR),/* Internal Core Clocks */ ".main" , CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),".pll1" , 1 , CLK_PLL1, CLK_MAIN),".pll2" , 2 , CLK_PLL2, CLK_MAIN),".pll3" , 3 , CLK_PLL3, CLK_MAIN),".pll4" , 4 , CLK_PLL4, CLK_MAIN),".pll5" , CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),".pll6" , 6 , CLK_PLL6, CLK_MAIN),".pll1_div2" , CLK_PLL1_DIV2, CLK_PLL1, 2 , 1 ),".pll3_div2" , CLK_PLL3_DIV2, CLK_PLL3, 2 , 1 ),".pll4_div2" , CLK_PLL4_DIV2, CLK_PLL4, 2 , 1 ),".pll4_div5" , CLK_PLL4_DIV5, CLK_PLL4, 5 , 1 ),".pll5_div2" , CLK_PLL5_DIV2, CLK_PLL5, 2 , 1 ),".pll5_div4" , CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2 , 1 ),".pll6_div2" , CLK_PLL6_DIV2, CLK_PLL6, 2 , 1 ),".s0" , CLK_S0, CLK_PLL1_DIV2, 2 , 1 ),".s0_vio" , CLK_S0_VIO, CLK_PLL1_DIV2, 2 , 1 ),".s0_vc" , CLK_S0_VC, CLK_PLL1_DIV2, 2 , 1 ),".s0_hsc" , CLK_S0_HSC, CLK_PLL1_DIV2, 2 , 1 ),".sasyncper" , CLK_SASYNCPER, CLK_PLL5_DIV4, 3 , 1 ),".sv_vip" , CLK_SV_VIP, CLK_PLL1, 5 , 1 ),".sv_ir" , CLK_SV_IR, CLK_PLL1, 5 , 1 ),".impasrc" , CLK_IMPASRC, CLK_PLL1_DIV2, 2 , 1 ),".impbsrc" , CLK_IMPBSRC, CLK_PLL1, 4 , 1 ),".viosrc" , CLK_VIOSRC, CLK_PLL1, 6 , 1 ),".vcsrc" , CLK_VCSRC, CLK_PLL1, 6 , 1 ),".sdsrc" , CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),".rpcsrc" , CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),".oco" , CLK_OCO, 32768 ),/* Core Clock Outputs */ "zc0" , R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2, 4 , 0 ),"zc1" , R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2, 4 , 8 ),"zc2" , R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2, 4 , 32 ),"zc3" , R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2, 4 , 40 ),"s0d2" , R8A779H0_CLK_S0D2, CLK_S0, 2 , 1 ),"s0d3" , R8A779H0_CLK_S0D3, CLK_S0, 3 , 1 ),"s0d4" , R8A779H0_CLK_S0D4, CLK_S0, 4 , 1 ),"cl16m" , R8A779H0_CLK_CL16M, CLK_S0, 48 , 1 ),"s0d2_rt" , R8A779H0_CLK_S0D2_RT, CLK_S0, 2 , 1 ),"s0d3_rt" , R8A779H0_CLK_S0D3_RT, CLK_S0, 3 , 1 ),"s0d4_rt" , R8A779H0_CLK_S0D4_RT, CLK_S0, 4 , 1 ),"s0d6_rt" , R8A779H0_CLK_S0D6_RT, CLK_S0, 6 , 1 ),"cl16m_rt" , R8A779H0_CLK_CL16M_RT, CLK_S0, 48 , 1 ),"s0d2_per" , R8A779H0_CLK_S0D2_PER, CLK_S0, 2 , 1 ),"s0d3_per" , R8A779H0_CLK_S0D3_PER, CLK_S0, 3 , 1 ),"s0d4_per" , R8A779H0_CLK_S0D4_PER, CLK_S0, 4 , 1 ),"s0d6_per" , R8A779H0_CLK_S0D6_PER, CLK_S0, 6 , 1 ),"s0d12_per" , R8A779H0_CLK_S0D12_PER, CLK_S0, 12 , 1 ),"s0d24_per" , R8A779H0_CLK_S0D24_PER, CLK_S0, 24 , 1 ),"cl16m_per" , R8A779H0_CLK_CL16M_PER, CLK_S0, 48 , 1 ),"s0d2_mm" , R8A779H0_CLK_S0D2_MM, CLK_S0, 2 , 1 ),"s0d4_mm" , R8A779H0_CLK_S0D4_MM, CLK_S0, 4 , 1 ),"cl16m_mm" , R8A779H0_CLK_CL16M_MM, CLK_S0, 48 , 1 ),"s0d2_u3dg" , R8A779H0_CLK_S0D2_U3DG, CLK_S0, 2 , 1 ),"s0d4_u3dg" , R8A779H0_CLK_S0D4_U3DG, CLK_S0, 4 , 1 ),"s0d1_vio" , R8A779H0_CLK_S0D1_VIO, CLK_S0_VIO, 1 , 1 ),"s0d2_vio" , R8A779H0_CLK_S0D2_VIO, CLK_S0_VIO, 2 , 1 ),"s0d4_vio" , R8A779H0_CLK_S0D4_VIO, CLK_S0_VIO, 4 , 1 ),"s0d8_vio" , R8A779H0_CLK_S0D8_VIO, CLK_S0_VIO, 8 , 1 ),"s0d1_vc" , R8A779H0_CLK_S0D1_VC, CLK_S0_VC, 1 , 1 ),"s0d2_vc" , R8A779H0_CLK_S0D2_VC, CLK_S0_VC, 2 , 1 ),"s0d4_vc" , R8A779H0_CLK_S0D4_VC, CLK_S0_VC, 4 , 1 ),"s0d1_hsc" , R8A779H0_CLK_S0D1_HSC, CLK_S0_HSC, 1 , 1 ),"s0d2_hsc" , R8A779H0_CLK_S0D2_HSC, CLK_S0_HSC, 2 , 1 ),"s0d4_hsc" , R8A779H0_CLK_S0D4_HSC, CLK_S0_HSC, 4 , 1 ),"s0d8_hsc" , R8A779H0_CLK_S0D8_HSC, CLK_S0_HSC, 8 , 1 ),"cl16m_hsc" , R8A779H0_CLK_CL16M_HSC, CLK_S0_HSC, 48 , 1 ),"sasyncrt" , R8A779H0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48 , 1 ),"sasyncperd1" , R8A779H0_CLK_SASYNCPERD1, CLK_SASYNCPER, 1 , 1 ),"sasyncperd2" , R8A779H0_CLK_SASYNCPERD2, CLK_SASYNCPER, 2 , 1 ),"sasyncperd4" , R8A779H0_CLK_SASYNCPERD4, CLK_SASYNCPER, 4 , 1 ),"svd1_vip" , R8A779H0_CLK_SVD1_VIP, CLK_SV_VIP, 1 , 1 ),"svd2_vip" , R8A779H0_CLK_SVD2_VIP, CLK_SV_VIP, 2 , 1 ),"svd1_ir" , R8A779H0_CLK_SVD1_IR, CLK_SV_IR, 1 , 1 ),"svd2_ir" , R8A779H0_CLK_SVD2_IR, CLK_SV_IR, 2 , 1 ),"cbfusa" , R8A779H0_CLK_CBFUSA, CLK_EXTAL, 2 , 1 ),"cpex" , R8A779H0_CLK_CPEX, CLK_EXTAL, 2 , 1 ),"cp" , R8A779H0_CLK_CP, CLK_EXTAL, 2 , 1 ),"impad1" , R8A779H0_CLK_IMPAD1, CLK_IMPASRC, 1 , 1 ),"impad4" , R8A779H0_CLK_IMPAD4, CLK_IMPASRC, 4 , 1 ),"impb" , R8A779H0_CLK_IMPB, CLK_IMPBSRC, 1 , 1 ),"viobusd1" , R8A779H0_CLK_VIOBUSD1, CLK_VIOSRC, 1 , 1 ),"viobusd2" , R8A779H0_CLK_VIOBUSD2, CLK_VIOSRC, 2 , 1 ),"vcbusd1" , R8A779H0_CLK_VCBUSD1, CLK_VCSRC, 1 , 1 ),"vcbusd2" , R8A779H0_CLK_VCBUSD2, CLK_VCSRC, 2 , 1 ),"canfd" , R8A779H0_CLK_CANFD, CLK_PLL5_DIV4, CPG_CANFDCKCR),"csi" , R8A779H0_CLK_CSI, CLK_PLL5_DIV4, CPG_CSICKCR),"dsiref" , R8A779H0_CLK_DSIREF, CLK_PLL5_DIV4, 48 , 1 ),"dsiext" , R8A779H0_CLK_DSIEXT, CLK_PLL5_DIV4, CPG_DSIEXTCKCR),"mso" , R8A779H0_CLK_MSO, CLK_PLL5_DIV4, CPG_MSOCKCR),"sd0h" , R8A779H0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR),"sd0" , R8A779H0_CLK_SD0, R8A779H0_CLK_SD0H, CPG_SD0CKCR),"rpc" , R8A779H0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),"rpcd2" , R8A779H0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779H0_CLK_RPC),"osc" , R8A779H0_CLK_OSC, CLK_EXTAL, 8 ),"r" , R8A779H0_CLK_R, 29 , CLK_EXTALR, 1 , CLK_OCO, 1 ),static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = {"isp0" , 16 , R8A779H0_CLK_S0D2_VIO),"avb0:rgmii0" , 211 , R8A779H0_CLK_S0D8_HSC),"avb1:rgmii1" , 212 , R8A779H0_CLK_S0D8_HSC),"avb2:rgmii2" , 213 , R8A779H0_CLK_S0D8_HSC),"canfd0" , 328 , R8A779H0_CLK_SASYNCPERD2),"csi40" , 331 , R8A779H0_CLK_CSI),"csi41" , 400 , R8A779H0_CLK_CSI),"dis0" , 411 , R8A779H0_CLK_VIOBUSD2),"dsitxlink0" , 415 , R8A779H0_CLK_VIOBUSD2),"fcpvd0" , 508 , R8A779H0_CLK_VIOBUSD2),"hscif0" , 514 , R8A779H0_CLK_SASYNCPERD1),"hscif1" , 515 , R8A779H0_CLK_SASYNCPERD1),"hscif2" , 516 , R8A779H0_CLK_SASYNCPERD1),"hscif3" , 517 , R8A779H0_CLK_SASYNCPERD1),"i2c0" , 518 , R8A779H0_CLK_S0D6_PER),"i2c1" , 519 , R8A779H0_CLK_S0D6_PER),"i2c2" , 520 , R8A779H0_CLK_S0D6_PER),"i2c3" , 521 , R8A779H0_CLK_S0D6_PER),"irqc" , 611 , R8A779H0_CLK_CL16M),"ispcs0" , 612 , R8A779H0_CLK_S0D2_VIO),"ispcs1" , 613 , R8A779H0_CLK_S0D2_VIO),"msi0" , 618 , R8A779H0_CLK_MSO),"msi1" , 619 , R8A779H0_CLK_MSO),"msi2" , 620 , R8A779H0_CLK_MSO),"msi3" , 621 , R8A779H0_CLK_MSO),"msi4" , 622 , R8A779H0_CLK_MSO),"msi5" , 623 , R8A779H0_CLK_MSO),"pcie0" , 624 , R8A779H0_CLK_S0D2_HSC),"pwm" , 628 , R8A779H0_CLK_SASYNCPERD4),"rpc-if" , 629 , R8A779H0_CLK_RPCD2),"scif0" , 702 , R8A779H0_CLK_SASYNCPERD4),"scif1" , 703 , R8A779H0_CLK_SASYNCPERD4),"scif3" , 704 , R8A779H0_CLK_SASYNCPERD4),"scif4" , 705 , R8A779H0_CLK_SASYNCPERD4),"sdhi0" , 706 , R8A779H0_CLK_SD0),"sydm1" , 709 , R8A779H0_CLK_S0D6_PER),"sydm2" , 710 , R8A779H0_CLK_S0D6_PER),"tmu0" , 713 , R8A779H0_CLK_SASYNCRT),"tmu1" , 714 , R8A779H0_CLK_SASYNCPERD2),"tmu2" , 715 , R8A779H0_CLK_SASYNCPERD2),"tmu3" , 716 , R8A779H0_CLK_SASYNCPERD2),"tmu4" , 717 , R8A779H0_CLK_SASYNCPERD2),"vin00" , 730 , R8A779H0_CLK_S0D4_VIO),"vin01" , 731 , R8A779H0_CLK_S0D4_VIO),"vin02" , 800 , R8A779H0_CLK_S0D4_VIO),"vin03" , 801 , R8A779H0_CLK_S0D4_VIO),"vin04" , 802 , R8A779H0_CLK_S0D4_VIO),"vin05" , 803 , R8A779H0_CLK_S0D4_VIO),"vin06" , 804 , R8A779H0_CLK_S0D4_VIO),"vin07" , 805 , R8A779H0_CLK_S0D4_VIO),"vin10" , 806 , R8A779H0_CLK_S0D4_VIO),"vin11" , 807 , R8A779H0_CLK_S0D4_VIO),"vin12" , 808 , R8A779H0_CLK_S0D4_VIO),"vin13" , 809 , R8A779H0_CLK_S0D4_VIO),"vin14" , 810 , R8A779H0_CLK_S0D4_VIO),"vin15" , 811 , R8A779H0_CLK_S0D4_VIO),"vin16" , 812 , R8A779H0_CLK_S0D4_VIO),"vin17" , 813 , R8A779H0_CLK_S0D4_VIO),"vspd0" , 830 , R8A779H0_CLK_VIOBUSD2),"wdt1:wdt0" , 907 , R8A779H0_CLK_R),"cmt0" , 910 , R8A779H0_CLK_R),"cmt1" , 911 , R8A779H0_CLK_R),"cmt2" , 912 , R8A779H0_CLK_R),"cmt3" , 913 , R8A779H0_CLK_R),"pfc0" , 915 , R8A779H0_CLK_CP),"pfc1" , 916 , R8A779H0_CLK_CP),"pfc2" , 917 , R8A779H0_CLK_CP),"tsc2:tsc1" , 919 , R8A779H0_CLK_CL16M),"vspx0" , 1028 , R8A779H0_CLK_S0D1_VIO),"fcpvx0" , 1100 , R8A779H0_CLK_S0D1_VIO),"ssiu" , 2926 , R8A779H0_CLK_S0D6_PER),"ssi" , 2927 , R8A779H0_CLK_S0D6_PER),/* * CPG Clock Data /* * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC * 14 13 (MHz) * ------------------------------------------------------------------------ * 0 0 16.66 / 1 x192 x240 x192 x240 x192 x168 /16 * 0 1 20 / 1 x160 x200 x160 x200 x160 x140 /19 * 1 0 Prohibited setting * 1 1 33.33 / 2 x192 x240 x192 x240 x192 x168 /32 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14 )) >> 13 ) | \13 )) >> 13 ))static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4 ] __initconst = {/* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */ 1 , 192 , 1 , 192 , 1 , 16 , },1 , 160 , 1 , 160 , 1 , 19 , },0 , 0 , 0 , 0 , 0 , 0 , },2 , 192 , 1 , 192 , 1 , 32 , },static int __init r8a779h0_cpg_mssr_init(struct device *dev)const struct rcar_gen4_cpg_pll_config *cpg_pll_config;int error;if (error)return error;if (!cpg_pll_config->extal_div) {"Prohibited setting (cpg_mode=0x%x)\n" , cpg_mode);return -EINVAL;return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);const struct cpg_mssr_info r8a779h0_cpg_mssr_info __initconst = {/* Core Clocks */ /* Module Clocks */ 30 * 32 ,/* Callbacks */
Messung V0.5 in Prozent C=92 H=95 G=93
¤ Dauer der Verarbeitung: 0.15 Sekunden
(vorverarbeitet am 2026-06-06)
¤ *© Formatika GbR, Deutschland
