// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2021 Rockchip Electronics Co. Ltd. * Author: Elaine Zhang <zhangqing@rock-chips.com> #include <linux/clk-provider.h>#include <linux/module.h>#include <linux/of.h>#include <linux/of_address.h>#include <linux/platform_device.h>#include <linux/syscore_ops.h>#include <dt-bindings/clock/rk3568-cru.h>#include "clk.h" #define RK3568_GRF_SOC_STATUS0 0 x580enum rk3568_pmu_plls {enum rk3568_plls {static struct rockchip_pll_rate_table rk3568_pll_rates[] = {/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 2208000000 , 1 , 92 , 1 , 1 , 1 , 0 ),2184000000 , 1 , 91 , 1 , 1 , 1 , 0 ),2160000000 , 1 , 90 , 1 , 1 , 1 , 0 ),2088000000 , 1 , 87 , 1 , 1 , 1 , 0 ),2064000000 , 1 , 86 , 1 , 1 , 1 , 0 ),2040000000 , 1 , 85 , 1 , 1 , 1 , 0 ),2016000000 , 1 , 84 , 1 , 1 , 1 , 0 ),1992000000 , 1 , 83 , 1 , 1 , 1 , 0 ),1920000000 , 1 , 80 , 1 , 1 , 1 , 0 ),1896000000 , 1 , 79 , 1 , 1 , 1 , 0 ),1800000000 , 1 , 75 , 1 , 1 , 1 , 0 ),1704000000 , 1 , 71 , 1 , 1 , 1 , 0 ),1608000000 , 1 , 67 , 1 , 1 , 1 , 0 ),1600000000 , 3 , 200 , 1 , 1 , 1 , 0 ),1584000000 , 1 , 132 , 2 , 1 , 1 , 0 ),1560000000 , 1 , 130 , 2 , 1 , 1 , 0 ),1536000000 , 1 , 128 , 2 , 1 , 1 , 0 ),1512000000 , 1 , 126 , 2 , 1 , 1 , 0 ),1488000000 , 1 , 124 , 2 , 1 , 1 , 0 ),1464000000 , 1 , 122 , 2 , 1 , 1 , 0 ),1440000000 , 1 , 120 , 2 , 1 , 1 , 0 ),1416000000 , 1 , 118 , 2 , 1 , 1 , 0 ),1400000000 , 3 , 350 , 2 , 1 , 1 , 0 ),1392000000 , 1 , 116 , 2 , 1 , 1 , 0 ),1368000000 , 1 , 114 , 2 , 1 , 1 , 0 ),1344000000 , 1 , 112 , 2 , 1 , 1 , 0 ),1320000000 , 1 , 110 , 2 , 1 , 1 , 0 ),1296000000 , 1 , 108 , 2 , 1 , 1 , 0 ),1272000000 , 1 , 106 , 2 , 1 , 1 , 0 ),1248000000 , 1 , 104 , 2 , 1 , 1 , 0 ),1200000000 , 1 , 100 , 2 , 1 , 1 , 0 ),1188000000 , 1 , 99 , 2 , 1 , 1 , 0 ),1104000000 , 1 , 92 , 2 , 1 , 1 , 0 ),1100000000 , 3 , 275 , 2 , 1 , 1 , 0 ),1008000000 , 1 , 84 , 2 , 1 , 1 , 0 ),1000000000 , 3 , 250 , 2 , 1 , 1 , 0 ),912000000 , 1 , 76 , 2 , 1 , 1 , 0 ),816000000 , 1 , 68 , 2 , 1 , 1 , 0 ),800000000 , 3 , 200 , 2 , 1 , 1 , 0 ),724000000 , 3 , 181 , 2 , 1 , 1 , 0 ),700000000 , 3 , 350 , 4 , 1 , 1 , 0 ),696000000 , 1 , 116 , 4 , 1 , 1 , 0 ),600000000 , 1 , 100 , 4 , 1 , 1 , 0 ),594000000 , 1 , 99 , 4 , 1 , 1 , 0 ),500000000 , 1 , 125 , 6 , 1 , 1 , 0 ),408000000 , 1 , 68 , 2 , 2 , 1 , 0 ),312000000 , 1 , 78 , 6 , 1 , 1 , 0 ),297000000 , 2 , 99 , 4 , 1 , 1 , 0 ),292500000 , 1 , 195 , 4 , 4 , 1 , 0 ),241500000 , 2 , 161 , 4 , 2 , 1 , 0 ),216000000 , 1 , 72 , 4 , 2 , 1 , 0 ),200000000 , 1 , 100 , 3 , 4 , 1 , 0 ),148500000 , 1 , 99 , 4 , 4 , 1 , 0 ),135000000 , 2 , 45 , 4 , 1 , 1 , 0 ),132000000 , 1 , 66 , 6 , 2 , 1 , 0 ),128000000 , 1 , 16 , 3 , 1 , 1 , 0 ),126400000 , 1 , 79 , 5 , 3 , 1 , 0 ),119000000 , 3 , 119 , 4 , 2 , 1 , 0 ),115200000 , 1 , 24 , 5 , 1 , 1 , 0 ),108000000 , 2 , 45 , 5 , 1 , 1 , 0 ),101000000 , 1 , 101 , 6 , 4 , 1 , 0 ),100000000 , 1 , 150 , 6 , 6 , 1 , 0 ),96000000 , 1 , 96 , 6 , 4 , 1 , 0 ),78750000 , 4 , 315 , 6 , 4 , 1 , 0 ),74250000 , 2 , 99 , 4 , 4 , 1 , 0 ),33300000 , 4 , 111 , 5 , 4 , 1 , 0 ),/* sentinel */ }, #define RK3568_DIV_ATCLK_CORE_MASK 0 x1f#define RK3568_DIV_ATCLK_CORE_SHIFT 0 #define RK3568_DIV_GICCLK_CORE_MASK 0 x1f#define RK3568_DIV_GICCLK_CORE_SHIFT 8 #define RK3568_DIV_PCLK_CORE_MASK 0 x1f#define RK3568_DIV_PCLK_CORE_SHIFT 0 #define RK3568_DIV_PERIPHCLK_CORE_MASK 0 x1f#define RK3568_DIV_PERIPHCLK_CORE_SHIFT 8 #define RK3568_DIV_ACLK_CORE_MASK 0 x1f#define RK3568_DIV_ACLK_CORE_SHIFT 8 #define RK3568_DIV_SCLK_CORE_MASK 0 xf#define RK3568_DIV_SCLK_CORE_SHIFT 0 #define RK3568_MUX_SCLK_CORE_MASK 0 x3#define RK3568_MUX_SCLK_CORE_SHIFT 8 #define RK3568_MUX_SCLK_CORE_NPLL_MASK 0 x1#define RK3568_MUX_SCLK_CORE_NPLL_SHIFT 15 #define RK3568_MUX_CLK_CORE_APLL_MASK 0 x1#define RK3568_MUX_CLK_CORE_APLL_SHIFT 7 #define RK3568_MUX_CLK_PVTPLL_MASK 0 x1#define RK3568_MUX_CLK_PVTPLL_SHIFT 15 #define RK3568_CLKSEL1(_sclk_core) \2 ), \1 , RK3568_DIV_SCLK_CORE_MASK, \#define RK3568_CLKSEL2(_aclk_core) \5 ), \#define RK3568_CLKSEL3(_atclk_core, _gic_core) \3 ), \#define RK3568_CLKSEL4(_pclk_core, _periph_core) \4 ), \#define RK3568_CPUCLK_RATE(_prate, _sclk, _acore, _atcore, _gicclk, _pclk, _periph) \## U, \static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = {1800000000 , 0 , 1 , 7 , 7 , 7 , 7 ),1704000000 , 0 , 1 , 7 , 7 , 7 , 7 ),1608000000 , 0 , 1 , 5 , 5 , 5 , 5 ),1584000000 , 0 , 1 , 5 , 5 , 5 , 5 ),1560000000 , 0 , 1 , 5 , 5 , 5 , 5 ),1536000000 , 0 , 1 , 5 , 5 , 5 , 5 ),1512000000 , 0 , 1 , 5 , 5 , 5 , 5 ),1488000000 , 0 , 1 , 5 , 5 , 5 , 5 ),1464000000 , 0 , 1 , 5 , 5 , 5 , 5 ),1440000000 , 0 , 1 , 5 , 5 , 5 , 5 ),1416000000 , 0 , 1 , 5 , 5 , 5 , 5 ),1392000000 , 0 , 1 , 5 , 5 , 5 , 5 ),1368000000 , 0 , 1 , 5 , 5 , 5 , 5 ),1344000000 , 0 , 1 , 5 , 5 , 5 , 5 ),1320000000 , 0 , 1 , 5 , 5 , 5 , 5 ),1296000000 , 0 , 1 , 5 , 5 , 5 , 5 ),1272000000 , 0 , 1 , 5 , 5 , 5 , 5 ),1248000000 , 0 , 1 , 5 , 5 , 5 , 5 ),1224000000 , 0 , 1 , 5 , 5 , 5 , 5 ),1200000000 , 0 , 1 , 3 , 3 , 3 , 3 ),1104000000 , 0 , 1 , 3 , 3 , 3 , 3 ),1008000000 , 0 , 1 , 3 , 3 , 3 , 3 ),912000000 , 0 , 1 , 3 , 3 , 3 , 3 ),816000000 , 0 , 1 , 3 , 3 , 3 , 3 ),696000000 , 0 , 1 , 3 , 3 , 3 , 3 ),600000000 , 0 , 1 , 3 , 3 , 3 , 3 ),408000000 , 0 , 1 , 3 , 3 , 3 , 3 ),312000000 , 0 , 1 , 3 , 3 , 3 , 3 ),216000000 , 0 , 1 , 3 , 3 , 3 , 3 ),96000000 , 0 , 1 , 3 , 3 , 3 , 3 ),static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = {0 ] = RK3568_CLKSEL_CON(0 ),0 ] = 0 ,0 ] = 0 x1f,1 ] = RK3568_CLKSEL_CON(0 ),1 ] = 8 ,1 ] = 0 x1f,2 ] = RK3568_CLKSEL_CON(1 ),2 ] = 0 ,2 ] = 0 x1f,3 ] = RK3568_CLKSEL_CON(1 ),3 ] = 8 ,3 ] = 0 x1f,4 ,1 ,0 ,6 ,0 x1,"xin24m" };"xin24m" , "usb480m_phy" , "clk_rtc_32k" };"clk_usbphy0_480m" , "clk_usbphy1_480m" };"apll" , "gpll" };"clk_i2s0_8ch_tx_src" , "clk_i2s0_8ch_tx_frac" , "i2s0_mclkin" , "xin_osc0_half" };"clk_i2s0_8ch_rx_src" , "clk_i2s0_8ch_rx_frac" , "i2s0_mclkin" , "xin_osc0_half" };"clk_i2s1_8ch_tx_src" , "clk_i2s1_8ch_tx_frac" , "i2s1_mclkin" , "xin_osc0_half" };"clk_i2s1_8ch_rx_src" , "clk_i2s1_8ch_rx_frac" , "i2s1_mclkin" , "xin_osc0_half" };"clk_i2s2_2ch_src" , "clk_i2s2_2ch_frac" , "i2s2_mclkin" , "xin_osc0_half " };"clk_i2s3_2ch_tx_src" , "clk_i2s3_2ch_tx_frac" , "i2s3_mclkin" , "xin_osc0_half" };"clk_i2s3_2ch_rx_src" , "clk_i2s3_2ch_rx_frac" , "i2s3_mclkin" , "xin_osc0_half" };"mclk_spdif_8ch_src" , "mclk_spdif_8ch_frac" };"sclk_audpwm_src" , "sclk_audpwm_frac" };"clk_uart1_src" , "clk_uart1_frac" , "xin24m" };"clk_uart2_src" , "clk_uart2_frac" , "xin24m" };"clk_uart3_src" , "clk_uart3_frac" , "xin24m" };"clk_uart4_src" , "clk_uart4_frac" , "xin24m" };"clk_uart5_src" , "clk_uart5_frac" , "xin24m" };"clk_uart6_src" , "clk_uart6_frac" , "xin24m" };"clk_uart7_src" , "clk_uart7_frac" , "xin24m" };"clk_uart8_src" , "clk_uart8_frac" , "xin24m" };"clk_uart9_src" , "clk_uart9_frac" , "xin24m" };"sclk_uart0_div" , "sclk_uart0_frac" , "xin24m" };"clk_32k_pvtm" , "xin32k" , "clk_rtc32k_frac" };"mpll" , "gpll" , "cpll" , "npll" };"gpll" , "cpll" , "npll" };"npll" , "gpll" };"cpll" , "gpll" };"gpll" , "cpll" };"gpll" , "cpll" , "npll" , "vpll" };"apll" , "gpll" , "npll" };"sclk_core_src" , "npll" };"gpll_150m" , "gpll_100m" , "gpll_75m" , "xin24m" };"clk_gpu_src" , "gpu_pvtpll_out" };"clk_npu_src" , "dummy" };"clk_npu_pre_ndft" , "npu_pvtpll_out" };"dpll" , "gpll" , "cpll" };"clk_ddrphy1x_src" , "dpll" };"gpll_200m" , "gpll_150m" , "gpll_100m" , "xin24m" };"gpll_100m" , "gpll_75m" , "cpll_50m" };"clk_i2s0_8ch_tx" , "xin_osc0_half" };"clk_i2s0_8ch_rx" , "xin_osc0_half" };"clk_i2s1_8ch_tx" , "xin_osc0_half" };"clk_i2s1_8ch_rx" , "xin_osc0_half" };"clk_i2s2_2ch" , "xin_osc0_half" };"clk_i2s3_2ch_tx" , "xin_osc0_half" };"clk_i2s3_2ch_rx" , "xin_osc0_half" };"gpll_300m" , "cpll_250m" , "gpll_200m" , "gpll_100m" };"gpll_200m" , "gpll_100m" , "xin24m" , "cpll_100m" };"gpll_200m" , "gpll_150m" , "gpll_100m" };"gpll_300m" , "gpll_200m" , "gpll_100m" };"gpll_200m" , "gpll_150m" , "cpll_100m" , "xin24m" };"xin24m" , "cpll_50m" , "gpll_75m" , "gpll_100m" , "cpll_125m" , "gpll_150m" };"gpll_200m" , "gpll_150m" , "cpll_125m" };"xin24m" , "gpll_200m" , "gpll_150m" , "cpll_100m" , "cpll_50m" , "clk_osc0_div_375k" };"gpll_400m" , "gpll_300m" , "gpll_200m" , "xin24m" };"gpll_200m" , "cpll_125m" };"gpll_300m" , "gpll_200m" , "gpll_100m" , "xin24m" };"xin24m" , "gpll_400m" , "gpll_300m" , "cpll_100m" , "cpll_50m" , "clk_osc0_div_750k" };"cpll_125m" , "cpll_50m" , "cpll_25m" , "xin24m" };"cpll_62p5" , "gpll_100m" , "cpll_50m" , "xin24m" };"cpll_333m" , "gpll_300m" , "gpll_200m" };"cpll" , "gpll" , "hpll" };"gpll" , "usb480m" , "xin24m" , "xin24m" };"gpll_300m" , "cpll_250m" , "gpll_100m" , "xin24m" };"cpll" , "gpll" , "hpll" , "vpll" };"hpll" , "vpll" , "gpll" , "cpll" };"gpll_400m" , "cpll_333m" , "gpll_200m" };"gpll_100m" , "gpll_75m" , "cpll_50m" , "xin24m" };"xin24m" , "gpll_100m" , "cpll_100m" };"gpll" , "cpll" , "usb480m" };"gpll_100m" , "xin24m" , "cpll_100m" };"gpll_200m" , "xin24m" , "cpll_100m" };"xin24m" , "clk_rtc_32k" };"cpll_500m" , "gpll_400m" , "gpll_300m" , "xin24m" };"gpll_400m" , "gpll_300m" , "gpll_200m" , "xin24m" };"xin24m" , "cpll_100m" };"ppll" , "usb480m" , "cpll" , "gpll" };"clk_ref24m" , "xin_osc0_usbphy0_g" };"clk_ref24m" , "xin_osc0_usbphy1_g" };"clk_ref24m" , "xin_osc0_mipidsiphy0_g" };"clk_ref24m" , "xin_osc0_mipidsiphy1_g" };"clk_wifi_osc0" , "clk_wifi_div" };"clk_pciephy0_osc0" , "clk_pciephy0_div" };"clk_pciephy1_osc0" , "clk_pciephy1_div" };"clk_pciephy2_osc0" , "clk_pciephy2_div" };"clk_mac0_2top" , "gmac0_clkin" };"clk_gmac0" , "clk_gmac0" , "clk_gmac0_tx_div50" , "clk_gmac0_tx_div5" };"clk_gmac0_rx_div20" , "clk_gmac0_rx_div2" };"clk_gmac0_rgmii_speed" , "clk_gmac0_rmii_speed" , "clk_gmac0_xpcs_mii" };"clk_mac1_2top" , "gmac1_clkin" };"clk_gmac1" , "clk_gmac1" , "clk_gmac1_tx_div50" , "clk_gmac1_tx_div5" };"clk_gmac1_rx_div20" , "clk_gmac1_rx_div2" };"clk_gmac1_rgmii_speed" , "clk_gmac1_rmii_speed" , "clk_gmac1_xpcs_mii" };"hpll" , "hpll_ph0" };"ppll" , "gpll" };"cpll_125m" , "cpll_50m" , "cpll_25m" , "ppll" };"xin24m" , "clk_pdpmu" };"gpll" , "cpll" };"gpll" , "cpll" , "dummy_npll" , "dummy_vpll" };static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = {"ppll" , mux_pll_p,0 , RK3568_PMU_PLL_CON(0 ),0 , 4 , 0 , rk3568_pll_rates),"hpll" , mux_pll_p,0 , RK3568_PMU_PLL_CON(16 ),2 , 7 , 0 , rk3568_pll_rates),static struct rockchip_pll_clock rk3568_pll_clks[] __initdata = {"apll" , mux_pll_p,0 , RK3568_PLL_CON(0 ),0 , 0 , 0 , rk3568_pll_rates),"dpll" , mux_pll_p,0 , RK3568_PLL_CON(8 ),2 , 1 , 0 , NULL),"cpll" , mux_pll_p,0 , RK3568_PLL_CON(24 ),4 , 2 , 0 , rk3568_pll_rates),"gpll" , mux_pll_p,0 , RK3568_PLL_CON(16 ),6 , 3 , 0 , rk3568_pll_rates),"npll" , mux_pll_p,0 , RK3568_PLL_CON(32 ),10 , 5 , 0 , rk3568_pll_rates),"vpll" , mux_pll_p,0 , RK3568_PLL_CON(40 ),12 , 6 , 0 , rk3568_pll_rates),#define MFLAGS CLK_MUX_HIWORD_MASK#define DFLAGS CLK_DIVIDER_HIWORD_MASK#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)static struct rockchip_clk_branch rk3568_i2s0_8ch_tx_fracmux __initdata ="clk_i2s0_8ch_tx" , clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,11 ), 10 , 2 , MFLAGS);static struct rockchip_clk_branch rk3568_i2s0_8ch_rx_fracmux __initdata ="clk_i2s0_8ch_rx" , clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,13 ), 10 , 2 , MFLAGS);static struct rockchip_clk_branch rk3568_i2s1_8ch_tx_fracmux __initdata ="clk_i2s1_8ch_tx" , clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT,15 ), 10 , 2 , MFLAGS);static struct rockchip_clk_branch rk3568_i2s1_8ch_rx_fracmux __initdata ="clk_i2s1_8ch_rx" , clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT,17 ), 10 , 2 , MFLAGS);static struct rockchip_clk_branch rk3568_i2s2_2ch_fracmux __initdata ="clk_i2s2_2ch" , clk_i2s2_2ch_p, CLK_SET_RATE_PARENT,19 ), 10 , 2 , MFLAGS);static struct rockchip_clk_branch rk3568_i2s3_2ch_tx_fracmux __initdata ="clk_i2s3_2ch_tx" , clk_i2s3_2ch_tx_p, CLK_SET_RATE_PARENT,21 ), 10 , 2 , MFLAGS);static struct rockchip_clk_branch rk3568_i2s3_2ch_rx_fracmux __initdata ="clk_i2s3_2ch_rx" , clk_i2s3_2ch_rx_p, CLK_SET_RATE_PARENT,83 ), 10 , 2 , MFLAGS);static struct rockchip_clk_branch rk3568_spdif_8ch_fracmux __initdata ="mclk_spdif_8ch" , mclk_spdif_8ch_p, CLK_SET_RATE_PARENT,23 ), 15 , 1 , MFLAGS);static struct rockchip_clk_branch rk3568_audpwm_fracmux __initdata ="sclk_audpwm" , sclk_audpwm_p, CLK_SET_RATE_PARENT,25 ), 15 , 1 , MFLAGS);static struct rockchip_clk_branch rk3568_uart1_fracmux __initdata =0 , "sclk_uart1_mux" , sclk_uart1_p, CLK_SET_RATE_PARENT,52 ), 12 , 2 , MFLAGS);static struct rockchip_clk_branch rk3568_uart2_fracmux __initdata =0 , "sclk_uart2_mux" , sclk_uart2_p, CLK_SET_RATE_PARENT,54 ), 12 , 2 , MFLAGS);static struct rockchip_clk_branch rk3568_uart3_fracmux __initdata =0 , "sclk_uart3_mux" , sclk_uart3_p, CLK_SET_RATE_PARENT,56 ), 12 , 2 , MFLAGS);static struct rockchip_clk_branch rk3568_uart4_fracmux __initdata =0 , "sclk_uart4_mux" , sclk_uart4_p, CLK_SET_RATE_PARENT,58 ), 12 , 2 , MFLAGS);static struct rockchip_clk_branch rk3568_uart5_fracmux __initdata =0 , "sclk_uart5_mux" , sclk_uart5_p, CLK_SET_RATE_PARENT,60 ), 12 , 2 , MFLAGS);static struct rockchip_clk_branch rk3568_uart6_fracmux __initdata =0 , "sclk_uart6_mux" , sclk_uart6_p, CLK_SET_RATE_PARENT,62 ), 12 , 2 , MFLAGS);static struct rockchip_clk_branch rk3568_uart7_fracmux __initdata =0 , "sclk_uart7_mux" , sclk_uart7_p, CLK_SET_RATE_PARENT,64 ), 12 , 2 , MFLAGS);static struct rockchip_clk_branch rk3568_uart8_fracmux __initdata =0 , "sclk_uart8_mux" , sclk_uart8_p, CLK_SET_RATE_PARENT,66 ), 12 , 2 , MFLAGS);static struct rockchip_clk_branch rk3568_uart9_fracmux __initdata =0 , "sclk_uart9_mux" , sclk_uart9_p, CLK_SET_RATE_PARENT,68 ), 12 , 2 , MFLAGS);static struct rockchip_clk_branch rk3568_uart0_fracmux __initdata =0 , "sclk_uart0_mux" , sclk_uart0_p, CLK_SET_RATE_PARENT,4 ), 10 , 2 , MFLAGS);static struct rockchip_clk_branch rk3568_rtc32k_pmu_fracmux __initdata ="clk_rtc_32k" , clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,0 ), 6 , 2 , MFLAGS);static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {/* * Clock-Architecture Diagram 1 /* SRC_CLK */ 0 , "gpll_400m" , "gpll" , CLK_IGNORE_UNUSED,75 ), 0 , 5 , DFLAGS,35 ), 0 , GFLAGS),0 , "gpll_300m" , "gpll" , CLK_IGNORE_UNUSED,75 ), 8 , 5 , DFLAGS,35 ), 1 , GFLAGS),0 , "gpll_200m" , "gpll" , CLK_IGNORE_UNUSED,76 ), 0 , 5 , DFLAGS,35 ), 2 , GFLAGS),0 , "gpll_150m" , "gpll" , CLK_IGNORE_UNUSED,76 ), 8 , 5 , DFLAGS,35 ), 3 , GFLAGS),0 , "gpll_100m" , "gpll" , CLK_IGNORE_UNUSED,77 ), 0 , 5 , DFLAGS,35 ), 4 , GFLAGS),0 , "gpll_75m" , "gpll" , CLK_IGNORE_UNUSED,77 ), 8 , 5 , DFLAGS,35 ), 5 , GFLAGS),0 , "gpll_20m" , "gpll" , CLK_IGNORE_UNUSED,78 ), 0 , 6 , DFLAGS,35 ), 6 , GFLAGS),"cpll_500m" , "cpll" , CLK_IGNORE_UNUSED,78 ), 8 , 5 , DFLAGS,35 ), 7 , GFLAGS),"cpll_333m" , "cpll" , CLK_IGNORE_UNUSED,79 ), 0 , 5 , DFLAGS,35 ), 8 , GFLAGS),"cpll_250m" , "cpll" , CLK_IGNORE_UNUSED,79 ), 8 , 5 , DFLAGS,35 ), 9 , GFLAGS),"cpll_125m" , "cpll" , CLK_IGNORE_UNUSED,80 ), 0 , 5 , DFLAGS,35 ), 10 , GFLAGS),"cpll_100m" , "cpll" , CLK_IGNORE_UNUSED,82 ), 0 , 5 , DFLAGS,35 ), 11 , GFLAGS),"cpll_62p5" , "cpll" , CLK_IGNORE_UNUSED,80 ), 8 , 5 , DFLAGS,35 ), 12 , GFLAGS),"cpll_50m" , "cpll" , CLK_IGNORE_UNUSED,81 ), 0 , 5 , DFLAGS,35 ), 13 , GFLAGS),"cpll_25m" , "cpll" , CLK_IGNORE_UNUSED,81 ), 8 , 6 , DFLAGS,35 ), 14 , GFLAGS),0 , "clk_osc0_div_750k" , "xin24m" , CLK_IGNORE_UNUSED,82 ), 8 , 6 , DFLAGS,35 ), 15 , GFLAGS),0 , "clk_osc0_div_375k" , "clk_osc0_div_750k" , 0 , 1 , 2 ),0 , "xin_osc0_half" , "xin24m" , 0 , 1 , 2 ),"usb480m" , mux_usb480m_p, CLK_SET_RATE_PARENT,14 , 2 , MFLAGS),"usb480m_phy" , mux_usb480m_phy_p, CLK_SET_RATE_PARENT,15 , 1 , MFLAGS),/* PD_CORE */ 0 , "sclk_core_src" , apll_gpll_npll_p, CLK_IGNORE_UNUSED,2 ), 8 , 2 , MFLAGS, 0 , 4 , DFLAGS | CLK_DIVIDER_READ_ONLY,0 ), 5 , GFLAGS),0 , "sclk_core" , sclk_core_pre_p, CLK_IGNORE_UNUSED,2 ), 15 , 1 , MFLAGS,0 ), 7 , GFLAGS),0 , "atclk_core" , "armclk" , CLK_IGNORE_UNUSED,3 ), 0 , 5 , DFLAGS | CLK_DIVIDER_READ_ONLY,0 ), 8 , GFLAGS),0 , "gicclk_core" , "armclk" , CLK_IGNORE_UNUSED,3 ), 8 , 5 , DFLAGS | CLK_DIVIDER_READ_ONLY,0 ), 9 , GFLAGS),0 , "pclk_core_pre" , "armclk" , CLK_IGNORE_UNUSED,4 ), 0 , 5 , DFLAGS | CLK_DIVIDER_READ_ONLY,0 ), 10 , GFLAGS),0 , "periphclk_core_pre" , "armclk" , CLK_IGNORE_UNUSED,4 ), 8 , 5 , DFLAGS | CLK_DIVIDER_READ_ONLY,0 ), 11 , GFLAGS),0 , "tsclk_core" , "periphclk_core_pre" , CLK_IGNORE_UNUSED,5 ), 0 , 4 , DFLAGS | CLK_DIVIDER_READ_ONLY,0 ), 14 , GFLAGS),0 , "cntclk_core" , "periphclk_core_pre" , CLK_IGNORE_UNUSED,5 ), 4 , 4 , DFLAGS | CLK_DIVIDER_READ_ONLY,0 ), 15 , GFLAGS),0 , "aclk_core" , "sclk_core" , CLK_IGNORE_UNUSED,5 ), 8 , 5 , DFLAGS | CLK_DIVIDER_READ_ONLY,1 ), 0 , GFLAGS),"aclk_core_niu2bus" , gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,5 ), 14 , 2 , MFLAGS,1 ), 2 , GFLAGS),"clk_core_pvtm" , "xin24m" , 0 ,1 ), 10 , GFLAGS),"clk_core_pvtm_core" , "armclk" , 0 ,1 ), 11 , GFLAGS),"clk_core_pvtpll" , "armclk" , CLK_IGNORE_UNUSED,1 ), 12 , GFLAGS),"pclk_core_pvtm" , "pclk_core_pre" , 0 ,1 ), 9 , GFLAGS),/* PD_GPU */ "clk_gpu_src" , mpll_gpll_cpll_npll_p, 0 ,6 ), 6 , 2 , MFLAGS | CLK_MUX_READ_ONLY, 0 , 4 , DFLAGS | CLK_DIVIDER_READ_ONLY,2 ), 0 , GFLAGS),"clk_gpu_pre_mux" , clk_gpu_pre_mux_p, CLK_SET_RATE_PARENT,6 ), 11 , 1 , MFLAGS | CLK_MUX_READ_ONLY),"aclk_gpu_pre" , "clk_gpu_pre_mux" , 0 ,6 ), 8 , 2 , DFLAGS),"pclk_gpu_pre" , "clk_gpu_pre_mux" , 0 ,6 ), 12 , 4 , DFLAGS),"clk_gpu" , "clk_gpu_pre_mux" , 0 ,2 ), 3 , GFLAGS),"pclk_gpu_pvtm" , "pclk_gpu_pre" , 0 ,2 ), 6 , GFLAGS),"clk_gpu_pvtm" , "xin24m" , 0 ,2 ), 7 , GFLAGS),"clk_gpu_pvtm_core" , "clk_gpu_src" , 0 ,2 ), 8 , GFLAGS),"clk_gpu_pvtpll" , "clk_gpu_src" , CLK_IGNORE_UNUSED,2 ), 9 , GFLAGS),/* PD_NPU */ "clk_npu_src" , npll_gpll_p, 0 ,7 ), 6 , 1 , MFLAGS, 0 , 4 , DFLAGS,3 ), 0 , GFLAGS),"clk_npu_pre_ndft" , clk_npu_pre_ndft_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,7 ), 8 , 1 , MFLAGS),"clk_npu" , clk_npu_p, CLK_SET_RATE_PARENT,7 ), 15 , 1 , MFLAGS),"hclk_npu_pre" , "clk_npu" , 0 ,8 ), 0 , 4 , DFLAGS,3 ), 2 , GFLAGS),"pclk_npu_pre" , "clk_npu" , 0 ,8 ), 4 , 4 , DFLAGS,3 ), 3 , GFLAGS),"aclk_npu_pre" , "clk_npu" , 0 ,3 ), 4 , GFLAGS),"aclk_npu" , "aclk_npu_pre" , 0 ,3 ), 7 , GFLAGS),"hclk_npu" , "hclk_npu_pre" , 0 ,3 ), 8 , GFLAGS),"pclk_npu_pvtm" , "pclk_npu_pre" , 0 ,3 ), 9 , GFLAGS),"clk_npu_pvtm" , "xin24m" , 0 ,3 ), 10 , GFLAGS),"clk_npu_pvtm_core" , "clk_npu_pre_ndft" , 0 ,3 ), 11 , GFLAGS),"clk_npu_pvtpll" , "clk_npu_pre_ndft" , CLK_IGNORE_UNUSED,3 ), 12 , GFLAGS),/* PD_DDR */ "clk_ddrphy1x_src" , dpll_gpll_cpll_p, CLK_IGNORE_UNUSED,9 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,4 ), 0 , GFLAGS),"clk_ddr1x" , clk_ddr1x_p, CLK_SET_RATE_PARENT,9 ), 15 , 1 , MFLAGS, grf_type_sys),"clk_msch" , "clk_ddr1x" , CLK_IGNORE_UNUSED,10 ), 0 , 2 , DFLAGS,4 ), 2 , GFLAGS),"clk24_ddrmon" , "xin24m" , CLK_IGNORE_UNUSED,4 ), 15 , GFLAGS),/* PD_GIC_AUDIO */ "aclk_gic_audio" , gpll200_gpll150_gpll100_xin24m_p, CLK_IGNORE_UNUSED,10 ), 8 , 2 , MFLAGS,5 ), 0 , GFLAGS),"hclk_gic_audio" , gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,10 ), 10 , 2 , MFLAGS,5 ), 1 , GFLAGS),"hclk_sdmmc_buffer" , "hclk_gic_audio" , 0 ,5 ), 8 , GFLAGS),"dclk_sdmmc_buffer" , gpll100_gpll75_gpll50_p, 0 ,10 ), 12 , 2 , MFLAGS,5 ), 9 , GFLAGS),"aclk_gic600" , "aclk_gic_audio" , CLK_IGNORE_UNUSED,5 ), 4 , GFLAGS),"aclk_spinlock" , "aclk_gic_audio" , CLK_IGNORE_UNUSED,5 ), 7 , GFLAGS),"hclk_i2s0_8ch" , "hclk_gic_audio" , 0 ,5 ), 10 , GFLAGS),"hclk_i2s1_8ch" , "hclk_gic_audio" , 0 ,5 ), 11 , GFLAGS),"hclk_i2s2_2ch" , "hclk_gic_audio" , 0 ,5 ), 12 , GFLAGS),"hclk_i2s3_2ch" , "hclk_gic_audio" , 0 ,5 ), 13 , GFLAGS),"clk_i2s0_8ch_tx_src" , gpll_cpll_npll_p, 0 ,11 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,6 ), 0 , GFLAGS),"clk_i2s0_8ch_tx_frac" , "clk_i2s0_8ch_tx_src" , CLK_SET_RATE_PARENT,12 ), 0 ,6 ), 1 , GFLAGS,"mclk_i2s0_8ch_tx" , "clk_i2s0_8ch_tx" , 0 ,6 ), 2 , GFLAGS),"i2s0_mclkout_tx" , i2s0_mclkout_tx_p, CLK_SET_RATE_PARENT,11 ), 15 , 1 , MFLAGS,6 ), 3 , GFLAGS),"clk_i2s0_8ch_rx_src" , gpll_cpll_npll_p, 0 ,13 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,6 ), 4 , GFLAGS),"clk_i2s0_8ch_rx_frac" , "clk_i2s0_8ch_rx_src" , CLK_SET_RATE_PARENT,14 ), 0 ,6 ), 5 , GFLAGS,"mclk_i2s0_8ch_rx" , "clk_i2s0_8ch_rx" , 0 ,6 ), 6 , GFLAGS),"i2s0_mclkout_rx" , i2s0_mclkout_rx_p, CLK_SET_RATE_PARENT,13 ), 15 , 1 , MFLAGS,6 ), 7 , GFLAGS),"clk_i2s1_8ch_tx_src" , gpll_cpll_npll_p, 0 ,15 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,6 ), 8 , GFLAGS),"clk_i2s1_8ch_tx_frac" , "clk_i2s1_8ch_tx_src" , CLK_SET_RATE_PARENT,16 ), 0 ,6 ), 9 , GFLAGS,"mclk_i2s1_8ch_tx" , "clk_i2s1_8ch_tx" , 0 ,6 ), 10 , GFLAGS),"i2s1_mclkout_tx" , i2s1_mclkout_tx_p, CLK_SET_RATE_PARENT,15 ), 15 , 1 , MFLAGS,6 ), 11 , GFLAGS),"clk_i2s1_8ch_rx_src" , gpll_cpll_npll_p, 0 ,17 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,6 ), 12 , GFLAGS),"clk_i2s1_8ch_rx_frac" , "clk_i2s1_8ch_rx_src" , CLK_SET_RATE_PARENT,18 ), 0 ,6 ), 13 , GFLAGS,"mclk_i2s1_8ch_rx" , "clk_i2s1_8ch_rx" , 0 ,6 ), 14 , GFLAGS),"i2s1_mclkout_rx" , i2s1_mclkout_rx_p, CLK_SET_RATE_PARENT,17 ), 15 , 1 , MFLAGS,6 ), 15 , GFLAGS),"clk_i2s2_2ch_src" , gpll_cpll_npll_p, 0 ,19 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,7 ), 0 , GFLAGS),"clk_i2s2_2ch_frac" , "clk_i2s2_2ch_src" , CLK_SET_RATE_PARENT,20 ), 0 ,7 ), 1 , GFLAGS,"mclk_i2s2_2ch" , "clk_i2s2_2ch" , 0 ,7 ), 2 , GFLAGS),"i2s2_mclkout" , i2s2_mclkout_p, CLK_SET_RATE_PARENT,19 ), 15 , 1 , MFLAGS,7 ), 3 , GFLAGS),"clk_i2s3_2ch_tx_src" , gpll_cpll_npll_p, 0 ,21 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,7 ), 4 , GFLAGS),"clk_i2s3_2ch_tx_frac" , "clk_i2s3_2ch_tx_src" , CLK_SET_RATE_PARENT,22 ), 0 ,7 ), 5 , GFLAGS,"mclk_i2s3_2ch_tx" , "clk_i2s3_2ch_tx" , 0 ,7 ), 6 , GFLAGS),"i2s3_mclkout_tx" , i2s3_mclkout_tx_p, CLK_SET_RATE_PARENT,21 ), 15 , 1 , MFLAGS,7 ), 7 , GFLAGS),"clk_i2s3_2ch_rx_src" , gpll_cpll_npll_p, 0 ,83 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,7 ), 8 , GFLAGS),"clk_i2s3_2ch_rx_frac" , "clk_i2s3_2ch_rx_src" , CLK_SET_RATE_PARENT,84 ), 0 ,7 ), 9 , GFLAGS,"mclk_i2s3_2ch_rx" , "clk_i2s3_2ch_rx" , 0 ,7 ), 10 , GFLAGS),"i2s3_mclkout_rx" , i2s3_mclkout_rx_p, CLK_SET_RATE_PARENT,83 ), 15 , 1 , MFLAGS,7 ), 11 , GFLAGS),"hclk_pdm" , "hclk_gic_audio" , 0 ,5 ), 14 , GFLAGS),"mclk_pdm" , mclk_pdm_p, 0 ,23 ), 8 , 2 , MFLAGS,5 ), 15 , GFLAGS),"hclk_vad" , "hclk_gic_audio" , 0 ,7 ), 12 , GFLAGS),"hclk_spdif_8ch" , "hclk_gic_audio" , 0 ,7 ), 13 , GFLAGS),"mclk_spdif_8ch_src" , cpll_gpll_p, 0 ,23 ), 14 , 1 , MFLAGS, 0 , 7 , DFLAGS,7 ), 14 , GFLAGS),"mclk_spdif_8ch_frac" , "mclk_spdif_8ch_src" , CLK_SET_RATE_PARENT,24 ), 0 ,7 ), 15 , GFLAGS,"hclk_audpwm" , "hclk_gic_audio" , 0 ,8 ), 0 , GFLAGS),"sclk_audpwm_src" , gpll_cpll_p, 0 ,25 ), 14 , 1 , MFLAGS, 0 , 6 , DFLAGS,8 ), 1 , GFLAGS),"sclk_audpwm_frac" , "sclk_audpwm_src" , CLK_SET_RATE_PARENT,26 ), 0 ,8 ), 2 , GFLAGS,"hclk_acdcdig" , "hclk_gic_audio" , 0 ,8 ), 3 , GFLAGS),"clk_acdcdig_i2c" , clk_i2c_p, 0 ,23 ), 10 , 2 , MFLAGS,8 ), 4 , GFLAGS),"clk_acdcdig_dac" , "mclk_i2s3_2ch_tx" , 0 ,8 ), 5 , GFLAGS),"clk_acdcdig_adc" , "mclk_i2s3_2ch_rx" , 0 ,8 ), 6 , GFLAGS),/* PD_SECURE_FLASH */ "aclk_secure_flash" , gpll200_gpll150_gpll100_xin24m_p, 0 ,27 ), 0 , 2 , MFLAGS,8 ), 7 , GFLAGS),"hclk_secure_flash" , gpll150_gpll100_gpll75_xin24m_p, 0 ,27 ), 2 , 2 , MFLAGS,8 ), 8 , GFLAGS),"aclk_crypto_ns" , "aclk_secure_flash" , 0 ,8 ), 11 , GFLAGS),"hclk_crypto_ns" , "hclk_secure_flash" , 0 ,8 ), 12 , GFLAGS),"clk_crypto_ns_core" , gpll200_gpll150_gpll100_p, 0 ,27 ), 4 , 2 , MFLAGS,8 ), 13 , GFLAGS),"clk_crypto_ns_pka" , gpll300_gpll200_gpll100_p, 0 27 ), 6 , 2 , MFLAGS,8 ), 14 , GFLAGS),"clk_crypto_ns_rng" , "hclk_secure_flash" , 0 ,8 ), 15 , GFLAGS),"hclk_trng_ns" , "hclk_secure_flash" , CLK_IGNORE_UNUSED,9 ), 10 , GFLAGS),"clk_trng_ns" , "hclk_secure_flash" , CLK_IGNORE_UNUSED,9 ), 11 , GFLAGS),"pclk_otpc_ns" , "hclk_secure_flash" , 0 ,26 ), 9 , GFLAGS),"clk_otpc_ns_sbpi" , "xin24m" , 0 ,26 ), 10 , GFLAGS),"clk_otpc_ns_usr" , "xin_osc0_half" , 0 ,26 ), 11 , GFLAGS),"hclk_nandc" , "hclk_secure_flash" , 0 ,9 ), 0 , GFLAGS),"nclk_nandc" , clk_nandc_p, 0 ,28 ), 0 , 2 , MFLAGS,9 ), 1 , GFLAGS),"hclk_sfc" , "hclk_secure_flash" , 0 ,9 ), 2 , GFLAGS),"hclk_sfc_xip" , "hclk_secure_flash" , 0 ,9 ), 3 , GFLAGS),"sclk_sfc" , sclk_sfc_p, 0 ,28 ), 4 , 3 , MFLAGS,9 ), 4 , GFLAGS),"aclk_emmc" , "aclk_secure_flash" , 0 ,9 ), 5 , GFLAGS),"hclk_emmc" , "hclk_secure_flash" , 0 ,9 ), 6 , GFLAGS),"bclk_emmc" , gpll200_gpll150_cpll125_p, 0 ,28 ), 8 , 2 , MFLAGS,9 ), 7 , GFLAGS),"cclk_emmc" , cclk_emmc_p, 0 ,28 ), 12 , 3 , MFLAGS,9 ), 8 , GFLAGS),"tclk_emmc" , "xin24m" , 0 ,9 ), 9 , GFLAGS),"emmc_drv" , "cclk_emmc" , RK3568_EMMC_CON0, 1 ),"emmc_sample" , "cclk_emmc" , RK3568_EMMC_CON1, 1 ),/* PD_PIPE */ "aclk_pipe" , aclk_pipe_p, 0 ,29 ), 0 , 2 , MFLAGS,10 ), 0 , GFLAGS),"pclk_pipe" , "aclk_pipe" , 0 ,29 ), 4 , 4 , DFLAGS,10 ), 1 , GFLAGS),"aclk_pcie20_mst" , "aclk_pipe" , 0 ,12 ), 0 , GFLAGS),"aclk_pcie20_slv" , "aclk_pipe" , 0 ,12 ), 1 , GFLAGS),"aclk_pcie20_dbi" , "aclk_pipe" , 0 ,12 ), 2 , GFLAGS),"pclk_pcie20" , "pclk_pipe" , 0 ,12 ), 3 , GFLAGS),"clk_pcie20_aux_ndft" , "xin24m" , 0 ,12 ), 4 , GFLAGS),"aclk_pcie30x1_mst" , "aclk_pipe" , 0 ,12 ), 8 , GFLAGS),"aclk_pcie30x1_slv" , "aclk_pipe" , 0 ,12 ), 9 , GFLAGS),"aclk_pcie30x1_dbi" , "aclk_pipe" , 0 ,12 ), 10 , GFLAGS),"pclk_pcie30x1" , "pclk_pipe" , 0 ,12 ), 11 , GFLAGS),"clk_pcie30x1_aux_ndft" , "xin24m" , 0 ,12 ), 12 , GFLAGS),"aclk_pcie30x2_mst" , "aclk_pipe" , 0 ,13 ), 0 , GFLAGS),"aclk_pcie30x2_slv" , "aclk_pipe" , 0 ,13 ), 1 , GFLAGS),"aclk_pcie30x2_dbi" , "aclk_pipe" , 0 ,13 ), 2 , GFLAGS),"pclk_pcie30x2" , "pclk_pipe" , 0 ,13 ), 3 , GFLAGS),"clk_pcie30x2_aux_ndft" , "xin24m" , 0 ,13 ), 4 , GFLAGS),"aclk_sata0" , "aclk_pipe" , 0 ,11 ), 0 , GFLAGS),"clk_sata0_pmalive" , "gpll_20m" , 0 ,11 ), 1 , GFLAGS),"clk_sata0_rxoob" , "cpll_50m" , 0 ,11 ), 2 , GFLAGS),"aclk_sata1" , "aclk_pipe" , 0 ,11 ), 4 , GFLAGS),"clk_sata1_pmalive" , "gpll_20m" , 0 ,11 ), 5 , GFLAGS),"clk_sata1_rxoob" , "cpll_50m" , 0 ,11 ), 6 , GFLAGS),"aclk_sata2" , "aclk_pipe" , 0 ,11 ), 8 , GFLAGS),"clk_sata2_pmalive" , "gpll_20m" , 0 ,11 ), 9 , GFLAGS),"clk_sata2_rxoob" , "cpll_50m" , 0 ,11 ), 10 , GFLAGS),"aclk_usb3otg0" , "aclk_pipe" , 0 ,10 ), 8 , GFLAGS),"clk_usb3otg0_ref" , "xin24m" , 0 ,10 ), 9 , GFLAGS),"clk_usb3otg0_suspend" , xin24m_32k_p, 0 ,29 ), 8 , 1 , MFLAGS,10 ), 10 , GFLAGS),"aclk_usb3otg1" , "aclk_pipe" , 0 ,10 ), 12 , GFLAGS),"clk_usb3otg1_ref" , "xin24m" , 0 ,10 ), 13 , GFLAGS),"clk_usb3otg1_suspend" , xin24m_32k_p, 0 ,29 ), 9 , 1 , MFLAGS,10 ), 14 , GFLAGS),"clk_xpcs_eee" , gpll200_cpll125_p, 0 ,29 ), 13 , 1 , MFLAGS,10 ), 4 , GFLAGS),"pclk_xpcs" , "pclk_pipe" , 0 ,13 ), 6 , GFLAGS),/* PD_PHP */ "aclk_php" , gpll300_gpll200_gpll100_xin24m_p, 0 ,30 ), 0 , 2 , MFLAGS,14 ), 8 , GFLAGS),"hclk_php" , gpll150_gpll100_gpll75_xin24m_p, 0 ,30 ), 2 , 2 , MFLAGS,14 ), 9 , GFLAGS),"pclk_php" , "aclk_php" , 0 ,30 ), 4 , 4 , DFLAGS,14 ), 10 , GFLAGS),"hclk_sdmmc0" , "hclk_php" , 0 ,15 ), 0 , GFLAGS),"clk_sdmmc0" , clk_sdmmc_p, 0 ,30 ), 8 , 3 , MFLAGS,15 ), 1 , GFLAGS),"sdmmc0_drv" , "clk_sdmmc0" , RK3568_SDMMC0_CON0, 1 ),"sdmmc0_sample" , "clk_sdmmc0" , RK3568_SDMMC0_CON1, 1 ),"hclk_sdmmc1" , "hclk_php" , 0 ,15 ), 2 , GFLAGS),"clk_sdmmc1" , clk_sdmmc_p, 0 ,30 ), 12 , 3 , MFLAGS,15 ), 3 , GFLAGS),"sdmmc1_drv" , "clk_sdmmc1" , RK3568_SDMMC1_CON0, 1 ),"sdmmc1_sample" , "clk_sdmmc1" , RK3568_SDMMC1_CON1, 1 ),"aclk_gmac0" , "aclk_php" , 0 ,15 ), 5 , GFLAGS),"pclk_gmac0" , "pclk_php" , 0 ,15 ), 6 , GFLAGS),"clk_mac0_2top" , clk_mac_2top_p, 0 ,31 ), 8 , 2 , MFLAGS,15 ), 7 , GFLAGS),"clk_mac0_out" , cpll125_cpll50_cpll25_xin24m_p, 0 ,31 ), 14 , 2 , MFLAGS,15 ), 8 , GFLAGS),"clk_mac0_refout" , "clk_mac0_2top" , 0 ,15 ), 12 , GFLAGS),"clk_gmac0_ptp_ref" , clk_gmac_ptp_p, 0 ,31 ), 12 , 2 , MFLAGS,15 ), 4 , GFLAGS),"clk_gmac0" , mux_gmac0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,31 ), 2 , 1 , MFLAGS),0 , "clk_gmac0_tx_div5" , "clk_gmac0" , 0 , 1 , 5 ),0 , "clk_gmac0_tx_div50" , "clk_gmac0" , 0 , 1 , 50 ),0 , "clk_gmac0_rx_div2" , "clk_gmac0" , 0 , 1 , 2 ),0 , "clk_gmac0_rx_div20" , "clk_gmac0" , 0 , 1 , 20 ),"clk_gmac0_rgmii_speed" , mux_gmac0_rgmii_speed_p, 0 ,31 ), 4 , 2 , MFLAGS),"clk_gmac0_rmii_speed" , mux_gmac0_rmii_speed_p, 0 ,31 ), 3 , 1 , MFLAGS),"clk_gmac0_rx_tx" , mux_gmac0_rx_tx_p, CLK_SET_RATE_PARENT,31 ), 0 , 2 , MFLAGS),/* PD_USB */ "aclk_usb" , gpll300_gpll200_gpll100_xin24m_p, 0 ,32 ), 0 , 2 , MFLAGS,16 ), 0 , GFLAGS),"hclk_usb" , gpll150_gpll100_gpll75_xin24m_p, 0 ,32 ), 2 , 2 , MFLAGS,16 ), 1 , GFLAGS),"pclk_usb" , "aclk_usb" , 0 ,32 ), 4 , 4 , DFLAGS,16 ), 2 , GFLAGS),"hclk_usb2host0" , "hclk_usb" , 0 ,16 ), 12 , GFLAGS),"hclk_usb2host0_arb" , "hclk_usb" , 0 ,16 ), 13 , GFLAGS),"hclk_usb2host1" , "hclk_usb" , 0 ,16 ), 14 , GFLAGS),"hclk_usb2host1_arb" , "hclk_usb" , 0 ,16 ), 15 , GFLAGS),"hclk_sdmmc2" , "hclk_usb" , 0 ,17 ), 0 , GFLAGS),"clk_sdmmc2" , clk_sdmmc_p, 0 ,32 ), 8 , 3 , MFLAGS,17 ), 1 , GFLAGS),"sdmmc2_drv" , "clk_sdmmc2" , RK3568_SDMMC2_CON0, 1 ),"sdmmc2_sample" , "clk_sdmmc2" , RK3568_SDMMC2_CON1, 1 ),"aclk_gmac1" , "aclk_usb" , 0 ,17 ), 3 , GFLAGS),"pclk_gmac1" , "pclk_usb" , 0 ,17 ), 4 , GFLAGS),"clk_mac1_2top" , clk_mac_2top_p, 0 ,33 ), 8 , 2 , MFLAGS,17 ), 5 , GFLAGS),"clk_mac1_out" , cpll125_cpll50_cpll25_xin24m_p, 0 ,33 ), 14 , 2 , MFLAGS,17 ), 6 , GFLAGS),"clk_mac1_refout" , "clk_mac1_2top" , 0 ,17 ), 10 , GFLAGS),"clk_gmac1_ptp_ref" , clk_gmac_ptp_p, 0 ,33 ), 12 , 2 , MFLAGS,17 ), 2 , GFLAGS),"clk_gmac1" , mux_gmac1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,33 ), 2 , 1 , MFLAGS),0 , "clk_gmac1_tx_div5" , "clk_gmac1" , 0 , 1 , 5 ),0 , "clk_gmac1_tx_div50" , "clk_gmac1" , 0 , 1 , 50 ),0 , "clk_gmac1_rx_div2" , "clk_gmac1" , 0 , 1 , 2 ),0 , "clk_gmac1_rx_div20" , "clk_gmac1" , 0 , 1 , 20 ),"clk_gmac1_rgmii_speed" , mux_gmac1_rgmii_speed_p, 0 ,33 ), 4 , 2 , MFLAGS),"clk_gmac1_rmii_speed" , mux_gmac1_rmii_speed_p, 0 ,33 ), 3 , 1 , MFLAGS),"clk_gmac1_rx_tx" , mux_gmac1_rx_tx_p, CLK_SET_RATE_PARENT,33 ), 0 , 2 , MFLAGS),/* PD_PERI */ "aclk_perimid" , gpll300_gpll200_gpll100_xin24m_p, CLK_IGNORE_UNUSED,10 ), 4 , 2 , MFLAGS,14 ), 0 , GFLAGS),"hclk_perimid" , gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,10 ), 6 , 2 , MFLAGS,14 ), 1 , GFLAGS),/* PD_VI */ "aclk_vi" , gpll400_gpll300_gpll200_xin24m_p, 0 ,34 ), 0 , 2 , MFLAGS,18 ), 0 , GFLAGS),"hclk_vi" , "aclk_vi" , 0 ,34 ), 4 , 4 , DFLAGS,18 ), 1 , GFLAGS),"pclk_vi" , "aclk_vi" , 0 ,34 ), 8 , 4 , DFLAGS,18 ), 2 , GFLAGS),"aclk_vicap" , "aclk_vi" , 0 ,18 ), 9 , GFLAGS),"hclk_vicap" , "hclk_vi" , 0 ,18 ), 10 , GFLAGS),"dclk_vicap" , cpll333_gpll300_gpll200_p, 0 ,34 ), 14 , 2 , MFLAGS,18 ), 11 , GFLAGS),"iclk_vicap_g" , "iclk_vicap" , 0 ,18 ), 13 , GFLAGS),"aclk_isp" , "aclk_vi" , 0 ,19 ), 0 , GFLAGS),"hclk_isp" , "hclk_vi" , 0 ,19 ), 1 , GFLAGS),"clk_isp" , cpll_gpll_hpll_p, 0 ,35 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,19 ), 2 , GFLAGS),"pclk_csi2host1" , "pclk_vi" , 0 ,19 ), 4 , GFLAGS),"clk_cif_out" , gpll_usb480m_xin24m_p, 0 ,35 ), 14 , 2 , MFLAGS, 8 , 6 , DFLAGS,19 ), 8 , GFLAGS),"clk_cam0_out" , gpll_usb480m_xin24m_p, 0 ,36 ), 6 , 2 , MFLAGS, 0 , 6 , DFLAGS,19 ), 9 , GFLAGS),"clk_cam1_out" , gpll_usb480m_xin24m_p, 0 ,36 ), 14 , 2 , MFLAGS, 8 , 6 , DFLAGS,19 ), 10 , GFLAGS),/* PD_VO */ "aclk_vo" , gpll300_cpll250_gpll100_xin24m_p, 0 ,37 ), 0 , 2 , MFLAGS,20 ), 0 , GFLAGS),"hclk_vo" , "aclk_vo" , 0 ,37 ), 8 , 4 , DFLAGS,20 ), 1 , GFLAGS),"pclk_vo" , "aclk_vo" , 0 ,37 ), 12 , 4 , DFLAGS,20 ), 2 , GFLAGS),"aclk_vop_pre" , cpll_gpll_hpll_vpll_p, 0 ,38 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,20 ), 6 , GFLAGS),"aclk_vop" , "aclk_vop_pre" , 0 ,20 ), 8 , GFLAGS),"hclk_vop" , "hclk_vo" , 0 ,20 ), 9 , GFLAGS),"dclk_vop0" , hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,39 ), 10 , 2 , MFLAGS, 0 , 8 , DFLAGS,20 ), 10 , GFLAGS),"dclk_vop1" , hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,40 ), 10 , 2 , MFLAGS, 0 , 8 , DFLAGS,20 ), 11 , GFLAGS),"dclk_vop2" , hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,41 ), 10 , 2 , MFLAGS, 0 , 8 , DFLAGS,20 ), 12 , GFLAGS),"clk_vop_pwm" , "xin24m" , 0 ,20 ), 13 , GFLAGS),"aclk_hdcp" , "aclk_vo" , 0 ,21 ), 0 , GFLAGS),"hclk_hdcp" , "hclk_vo" , 0 ,21 ), 1 , GFLAGS),"pclk_hdcp" , "pclk_vo" , 0 ,21 ), 2 , GFLAGS),"pclk_hdmi_host" , "pclk_vo" , 0 ,21 ), 3 , GFLAGS),"clk_hdmi_sfr" , "xin24m" , 0 ,21 ), 4 , GFLAGS),"clk_hdmi_cec" , "clk_rtc_32k" , 0 ,21 ), 5 , GFLAGS),"pclk_dsitx_0" , "pclk_vo" , 0 ,21 ), 6 , GFLAGS),"pclk_dsitx_1" , "pclk_vo" , 0 ,21 ), 7 , GFLAGS),"pclk_edp_ctrl" , "pclk_vo" , 0 ,21 ), 8 , GFLAGS),"clk_edp_200m" , gpll200_gpll150_cpll125_p, 0 ,38 ), 8 , 2 , MFLAGS,21 ), 9 , GFLAGS),/* PD_VPU */ "aclk_vpu_pre" , gpll_cpll_p, 0 ,42 ), 7 , 1 , MFLAGS, 0 , 5 , DFLAGS,22 ), 0 , GFLAGS),"hclk_vpu_pre" , "aclk_vpu_pre" , 0 ,42 ), 8 , 4 , DFLAGS,22 ), 1 , GFLAGS),"aclk_vpu" , "aclk_vpu_pre" , 0 ,22 ), 4 , GFLAGS),"hclk_vpu" , "hclk_vpu_pre" , 0 ,22 ), 5 , GFLAGS),/* PD_RGA */ "aclk_rga_pre" , gpll300_cpll250_gpll100_xin24m_p, 0 ,43 ), 0 , 2 , MFLAGS,23 ), 0 , GFLAGS),"hclk_rga_pre" , "aclk_rga_pre" , 0 ,43 ), 8 , 4 , DFLAGS,23 ), 1 , GFLAGS),"pclk_rga_pre" , "aclk_rga_pre" , 0 ,43 ), 12 , 4 , DFLAGS,22 ), 12 , GFLAGS),"aclk_rga" , "aclk_rga_pre" , 0 ,23 ), 4 , GFLAGS),"hclk_rga" , "hclk_rga_pre" , 0 ,23 ), 5 , GFLAGS),"clk_rga_core" , gpll300_gpll200_gpll100_p, 0 ,43 ), 2 , 2 , MFLAGS,23 ), 6 , GFLAGS),"aclk_iep" , "aclk_rga_pre" , 0 ,23 ), 7 , GFLAGS),"hclk_iep" , "hclk_rga_pre" , 0 ,23 ), 8 , GFLAGS),"clk_iep_core" , gpll300_gpll200_gpll100_p, 0 ,43 ), 4 , 2 , MFLAGS,23 ), 9 , GFLAGS),"hclk_ebc" , "hclk_rga_pre" , 0 , RK3568_CLKGATE_CON(23 ), 10 , GFLAGS),"dclk_ebc" , gpll400_cpll333_gpll200_p, 0 ,43 ), 6 , 2 , MFLAGS,23 ), 11 , GFLAGS),"aclk_jdec" , "aclk_rga_pre" , 0 ,23 ), 12 , GFLAGS),"hclk_jdec" , "hclk_rga_pre" , 0 ,23 ), 13 , GFLAGS),"aclk_jenc" , "aclk_rga_pre" , 0 ,23 ), 14 , GFLAGS),"hclk_jenc" , "hclk_rga_pre" , 0 ,23 ), 15 , GFLAGS),"pclk_eink" , "pclk_rga_pre" , 0 ,22 ), 14 , GFLAGS),"hclk_eink" , "hclk_rga_pre" , 0 ,22 ), 15 , GFLAGS),/* PD_RKVENC */ "aclk_rkvenc_pre" , gpll_cpll_npll_p, 0 ,44 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,24 ), 0 , GFLAGS),"hclk_rkvenc_pre" , "aclk_rkvenc_pre" , 0 ,44 ), 8 , 4 , DFLAGS,24 ), 1 , GFLAGS),"aclk_rkvenc" , "aclk_rkvenc_pre" , 0 ,24 ), 6 , GFLAGS),"hclk_rkvenc" , "hclk_rkvenc_pre" , 0 ,24 ), 7 , GFLAGS),"clk_rkvenc_core" , gpll_cpll_npll_vpll_p, 0 ,45 ), 14 , 2 , MFLAGS, 0 , 5 , DFLAGS,24 ), 8 , GFLAGS),"aclk_rkvdec_pre" , aclk_rkvdec_pre_p, CLK_SET_RATE_NO_REPARENT,47 ), 7 , 1 , MFLAGS, 0 , 5 , DFLAGS,25 ), 0 , GFLAGS),"hclk_rkvdec_pre" , "aclk_rkvdec_pre" , 0 ,47 ), 8 , 4 , DFLAGS,25 ), 1 , GFLAGS),"aclk_rkvdec" , "aclk_rkvdec_pre" , 0 ,25 ), 4 , GFLAGS),"hclk_rkvdec" , "hclk_rkvdec_pre" , 0 ,25 ), 5 , GFLAGS),"clk_rkvdec_ca" , gpll_cpll_npll_vpll_p, 0 ,48 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,25 ), 6 , GFLAGS),"clk_rkvdec_core" , clk_rkvdec_core_p, CLK_SET_RATE_NO_REPARENT,49 ), 14 , 2 , MFLAGS, 8 , 5 , DFLAGS,25 ), 7 , GFLAGS),"clk_rkvdec_hevc_ca" , gpll_cpll_npll_vpll_p, 0 ,49 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,25 ), 8 , GFLAGS),/* PD_BUS */ "aclk_bus" , gpll200_gpll150_gpll100_xin24m_p, 0 ,50 ), 0 , 2 , MFLAGS,26 ), 0 , GFLAGS),"pclk_bus" , gpll100_gpll75_cpll50_xin24m_p, 0 ,50 ), 4 , 2 , MFLAGS,26 ), 1 , GFLAGS),"pclk_tsadc" , "pclk_bus" , 0 ,26 ), 4 , GFLAGS),"clk_tsadc_tsen" , xin24m_gpll100_cpll100_p, 0 ,51 ), 4 , 2 , MFLAGS, 0 , 3 , DFLAGS,26 ), 5 , GFLAGS),"clk_tsadc" , "clk_tsadc_tsen" , 0 ,51 ), 8 , 7 , DFLAGS,26 ), 6 , GFLAGS),"pclk_saradc" , "pclk_bus" , 0 ,26 ), 7 , GFLAGS),"clk_saradc" , "xin24m" , 0 ,26 ), 8 , GFLAGS),"pclk_scr" , "pclk_bus" , CLK_IGNORE_UNUSED,26 ), 12 , GFLAGS),"pclk_wdt_ns" , "pclk_bus" , 0 ,26 ), 13 , GFLAGS),"tclk_wdt_ns" , "xin24m" , 0 ,26 ), 14 , GFLAGS),"aclk_mcu" , "aclk_bus" , CLK_IGNORE_UNUSED,32 ), 13 , GFLAGS),"pclk_intmux" , "pclk_bus" , CLK_IGNORE_UNUSED,32 ), 14 , GFLAGS),"pclk_mailbox" , "pclk_bus" , 0 ,32 ), 15 , GFLAGS),"pclk_uart1" , "pclk_bus" , 0 ,27 ), 12 , GFLAGS),"clk_uart1_src" , gpll_cpll_usb480m_p, 0 ,52 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,27 ), 13 , GFLAGS),"clk_uart1_frac" , "clk_uart1_src" , CLK_SET_RATE_PARENT,53 ), 0 ,27 ), 14 , GFLAGS,"sclk_uart1" , "sclk_uart1_mux" , 0 ,27 ), 15 , GFLAGS),"pclk_uart2" , "pclk_bus" , 0 ,28 ), 0 , GFLAGS),"clk_uart2_src" , gpll_cpll_usb480m_p, 0 ,54 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,28 ), 1 , GFLAGS),"clk_uart2_frac" , "clk_uart2_src" , CLK_SET_RATE_PARENT,55 ), 0 ,28 ), 2 , GFLAGS,"sclk_uart2" , "sclk_uart2_mux" , 0 ,28 ), 3 , GFLAGS),"pclk_uart3" , "pclk_bus" , 0 ,28 ), 4 , GFLAGS),"clk_uart3_src" , gpll_cpll_usb480m_p, 0 ,56 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,28 ), 5 , GFLAGS),"clk_uart3_frac" , "clk_uart3_src" , CLK_SET_RATE_PARENT,57 ), 0 ,28 ), 6 , GFLAGS,"sclk_uart3" , "sclk_uart3_mux" , 0 ,28 ), 7 , GFLAGS),"pclk_uart4" , "pclk_bus" , 0 ,28 ), 8 , GFLAGS),"clk_uart4_src" , gpll_cpll_usb480m_p, 0 ,58 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,28 ), 9 , GFLAGS),"clk_uart4_frac" , "clk_uart4_src" , CLK_SET_RATE_PARENT,59 ), 0 ,28 ), 10 , GFLAGS,"sclk_uart4" , "sclk_uart4_mux" , 0 ,28 ), 11 , GFLAGS),"pclk_uart5" , "pclk_bus" , 0 ,28 ), 12 , GFLAGS),"clk_uart5_src" , gpll_cpll_usb480m_p, 0 ,60 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,28 ), 13 , GFLAGS),"clk_uart5_frac" , "clk_uart5_src" , CLK_SET_RATE_PARENT,61 ), 0 ,28 ), 14 , GFLAGS,"sclk_uart5" , "sclk_uart5_mux" , 0 ,28 ), 15 , GFLAGS),"pclk_uart6" , "pclk_bus" , 0 ,29 ), 0 , GFLAGS),"clk_uart6_src" , gpll_cpll_usb480m_p, 0 ,62 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,29 ), 1 , GFLAGS),"clk_uart6_frac" , "clk_uart6_src" , CLK_SET_RATE_PARENT,63 ), 0 ,29 ), 2 , GFLAGS,"sclk_uart6" , "sclk_uart6_mux" , 0 ,29 ), 3 , GFLAGS),"pclk_uart7" , "pclk_bus" , 0 ,29 ), 4 , GFLAGS),"clk_uart7_src" , gpll_cpll_usb480m_p, 0 ,64 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,29 ), 5 , GFLAGS),"clk_uart7_frac" , "clk_uart7_src" , CLK_SET_RATE_PARENT,65 ), 0 ,29 ), 6 , GFLAGS,"sclk_uart7" , "sclk_uart7_mux" , 0 ,29 ), 7 , GFLAGS),"pclk_uart8" , "pclk_bus" , 0 ,29 ), 8 , GFLAGS),"clk_uart8_src" , gpll_cpll_usb480m_p, 0 ,66 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,29 ), 9 , GFLAGS),"clk_uart8_frac" , "clk_uart8_src" , CLK_SET_RATE_PARENT,67 ), 0 ,29 ), 10 , GFLAGS,"sclk_uart8" , "sclk_uart8_mux" , 0 ,29 ), 11 , GFLAGS),"pclk_uart9" , "pclk_bus" , 0 ,29 ), 12 , GFLAGS),"clk_uart9_src" , gpll_cpll_usb480m_p, 0 ,68 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,29 ), 13 , GFLAGS),"clk_uart9_frac" , "clk_uart9_src" , CLK_SET_RATE_PARENT,69 ), 0 ,29 ), 14 , GFLAGS,"sclk_uart9" , "sclk_uart9_mux" , 0 ,29 ), 15 , GFLAGS),"pclk_can0" , "pclk_bus" , 0 ,27 ), 5 , GFLAGS),"clk_can0" , gpll_cpll_p, 0 ,70 ), 7 , 1 , MFLAGS, 0 , 5 , DFLAGS,27 ), 6 , GFLAGS),"pclk_can1" , "pclk_bus" , 0 ,27 ), 7 , GFLAGS),"clk_can1" , gpll_cpll_p, 0 ,70 ), 15 , 1 , MFLAGS, 8 , 5 , DFLAGS,27 ), 8 , GFLAGS),"pclk_can2" , "pclk_bus" , 0 ,27 ), 9 , GFLAGS),"clk_can2" , gpll_cpll_p, 0 ,71 ), 7 , 1 , MFLAGS, 0 , 5 , DFLAGS,27 ), 10 , GFLAGS),"clk_i2c" , clk_i2c_p, 0 ,71 ), 8 , 2 , MFLAGS,32 ), 10 , GFLAGS),"pclk_i2c1" , "pclk_bus" , 0 ,30 ), 0 , GFLAGS),"clk_i2c1" , "clk_i2c" , 0 ,30 ), 1 , GFLAGS),"pclk_i2c2" , "pclk_bus" , 0 ,30 ), 2 , GFLAGS),"clk_i2c2" , "clk_i2c" , 0 ,30 ), 3 , GFLAGS),"pclk_i2c3" , "pclk_bus" , 0 ,30 ), 4 , GFLAGS),"clk_i2c3" , "clk_i2c" , 0 ,30 ), 5 , GFLAGS),"pclk_i2c4" , "pclk_bus" , 0 ,30 ), 6 , GFLAGS),"clk_i2c4" , "clk_i2c" , 0 ,30 ), 7 , GFLAGS),"pclk_i2c5" , "pclk_bus" , 0 ,30 ), 8 , GFLAGS),"clk_i2c5" , "clk_i2c" , 0 ,30 ), 9 , GFLAGS),"pclk_spi0" , "pclk_bus" , 0 ,30 ), 10 , GFLAGS),"clk_spi0" , gpll200_xin24m_cpll100_p, 0 ,72 ), 0 , 1 , MFLAGS,30 ), 11 , GFLAGS),"pclk_spi1" , "pclk_bus" , 0 ,30 ), 12 , GFLAGS),"clk_spi1" , gpll200_xin24m_cpll100_p, 0 ,72 ), 2 , 1 , MFLAGS,30 ), 13 , GFLAGS),"pclk_spi2" , "pclk_bus" , 0 ,30 ), 14 , GFLAGS),"clk_spi2" , gpll200_xin24m_cpll100_p, 0 ,72 ), 4 , 1 , MFLAGS,30 ), 15 , GFLAGS),"pclk_spi3" , "pclk_bus" , 0 ,31 ), 0 , GFLAGS),"clk_spi3" , gpll200_xin24m_cpll100_p, 0 ,72 ), 6 , 1 , MFLAGS, RK3568_CLKGATE_CON(31 ), 1 , GFLAGS),"pclk_pwm1" , "pclk_bus" , 0 , RK3568_CLKGATE_CON(31 ), 10 , GFLAGS),"clk_pwm1" , gpll100_xin24m_cpll100_p, 0 ,72 ), 8 , 1 , MFLAGS,31 ), 11 , GFLAGS),"clk_pwm1_capture" , "xin24m" , 0 ,31 ), 12 , GFLAGS),"pclk_pwm2" , "pclk_bus" , 0 ,31 ), 13 , GFLAGS),"clk_pwm2" , gpll100_xin24m_cpll100_p, 0 ,72 ), 10 , 1 , MFLAGS,31 ), 14 , GFLAGS),"clk_pwm2_capture" , "xin24m" , 0 ,31 ), 15 , GFLAGS),"pclk_pwm3" , "pclk_bus" , 0 ,32 ), 0 , GFLAGS),"clk_pwm3" , gpll100_xin24m_cpll100_p, 0 ,72 ), 12 , 1 , MFLAGS,32 ), 1 , GFLAGS),"clk_pwm3_capture" , "xin24m" , 0 ,32 ), 2 , GFLAGS),"dbclk_gpio" , xin24m_32k_p, 0 ,72 ), 14 , 1 , MFLAGS,32 ), 11 , GFLAGS),"pclk_gpio1" , "pclk_bus" , 0 ,31 ), 2 , GFLAGS),"dbclk_gpio1" , "dbclk_gpio" , 0 ,31 ), 3 , GFLAGS),"pclk_gpio2" , "pclk_bus" , 0 ,31 ), 4 , GFLAGS),"dbclk_gpio2" , "dbclk_gpio" , 0 ,31 ), 5 , GFLAGS),"pclk_gpio3" , "pclk_bus" , 0 ,31 ), 6 , GFLAGS),"dbclk_gpio3" , "dbclk_gpio" , 0 ,31 ), 7 , GFLAGS),"pclk_gpio4" , "pclk_bus" , 0 ,31 ), 8 , GFLAGS),"dbclk_gpio4" , "dbclk_gpio" , 0 ,31 ), 9 , GFLAGS),"pclk_timer" , "pclk_bus" , 0 ,32 ), 3 , GFLAGS),"clk_timer0" , "xin24m" , 0 ,32 ), 4 , GFLAGS),"clk_timer1" , "xin24m" , 0 ,32 ), 5 , GFLAGS),"clk_timer2" , "xin24m" , 0 ,32 ), 6 , GFLAGS),"clk_timer3" , "xin24m" , 0 ,32 ), 7 , GFLAGS),"clk_timer4" , "xin24m" , 0 ,32 ), 8 , GFLAGS),"clk_timer5" , "xin24m" , 0 ,32 ), 9 , GFLAGS),/* PD_TOP */ "aclk_top_high" , cpll500_gpll400_gpll300_xin24m_p, 0 ,73 ), 0 , 2 , MFLAGS,33 ), 0 , GFLAGS),"aclk_top_low" , gpll400_gpll300_gpll200_xin24m_p, 0 ,73 ), 4 , 2 , MFLAGS,33 ), 1 , GFLAGS),"hclk_top" , gpll150_gpll100_gpll75_xin24m_p, 0 ,73 ), 8 , 2 , MFLAGS,33 ), 2 , GFLAGS),"pclk_top" , gpll100_gpll75_cpll50_xin24m_p, 0 ,73 ), 12 , 2 , MFLAGS,33 ), 3 , GFLAGS),"pclk_pcie30phy" , "pclk_top" , 0 ,33 ), 8 , GFLAGS),"clk_optc_arb" , xin24m_cpll100_p, 0 ,73 ), 15 , 1 , MFLAGS,33 ), 9 , GFLAGS),"pclk_mipicsiphy" , "pclk_top" , 0 ,33 ), 13 , GFLAGS),"pclk_mipidsiphy0" , "pclk_top" , 0 ,33 ), 14 , GFLAGS),"pclk_mipidsiphy1" , "pclk_top" , 0 ,33 ), 15 , GFLAGS),"pclk_pipephy0" , "pclk_top" , 0 ,34 ), 4 , GFLAGS),"pclk_pipephy1" , "pclk_top" , 0 ,34 ), 5 , GFLAGS),"pclk_pipephy2" , "pclk_top" , 0 ,34 ), 6 , GFLAGS),"pclk_cpu_boost" , "pclk_top" , 0 ,34 ), 11 , GFLAGS),"clk_cpu_boost" , "xin24m" , 0 ,34 ), 12 , GFLAGS),"pclk_otpphy" , "pclk_top" , 0 ,34 ), 13 , GFLAGS),"pclk_edpphy_grf" , "pclk_top" , 0 ,34 ), 14 , GFLAGS),static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = {/* PD_PMU */ 0 , "ppll_ph0" , "ppll" , 0 , 1 , 2 ),0 , "ppll_ph180" , "ppll" , 0 , 1 , 2 ),0 , "hpll_ph0" , "hpll" , 0 , 1 , 2 ),"clk_pdpmu" , clk_pdpmu_p, 0 ,2 ), 15 , 1 , MFLAGS),"pclk_pdpmu" , "clk_pdpmu" , 0 ,2 ), 0 , 5 , DFLAGS,0 ), 2 , GFLAGS),"pclk_pmu" , "pclk_pdpmu" , 0 ,0 ), 6 , GFLAGS),"clk_pmu" , "xin24m" , 0 ,0 ), 7 , GFLAGS),"pclk_i2c0" , "pclk_pdpmu" , 0 ,1 ), 0 , GFLAGS),"clk_i2c0" , "clk_pdpmu" , 0 ,3 ), 0 , 7 , DFLAGS,1 ), 1 , GFLAGS),"pclk_uart0" , "pclk_pdpmu" , 0 ,1 ), 2 , GFLAGS),"clk_rtc32k_frac" , "xin24m" , CLK_IGNORE_UNUSED,1 ), 0 ,0 ), 1 , GFLAGS,"xin_osc0_div" , "xin24m" , CLK_IGNORE_UNUSED,0 ), 0 , 5 , DFLAGS,0 ), 0 , GFLAGS),"sclk_uart0_div" , ppll_usb480m_cpll_gpll_p, 0 ,4 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,1 ), 3 , GFLAGS),"sclk_uart0_frac" , "sclk_uart0_div" , CLK_SET_RATE_PARENT,5 ), 0 ,1 ), 4 , GFLAGS,"sclk_uart0" , "sclk_uart0_mux" , 0 ,1 ), 5 , GFLAGS),"pclk_gpio0" , "pclk_pdpmu" , 0 ,1 ), 9 , GFLAGS),"dbclk_gpio0" , xin24m_32k_p, 0 ,6 ), 15 , 1 , MFLAGS,1 ), 10 , GFLAGS),"pclk_pwm0" , "pclk_pdpmu" , 0 ,1 ), 6 , GFLAGS),"clk_pwm0" , clk_pwm0_p, 0 ,6 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,1 ), 7 , GFLAGS),"clk_capture_pwm0_ndft" , "xin24m" , 0 ,1 ), 8 , GFLAGS),"pclk_pmupvtm" , "pclk_pdpmu" , 0 ,1 ), 11 , GFLAGS),"clk_pmupvtm" , "xin24m" , 0 ,1 ), 12 , GFLAGS),"clk_core_pmupvtm" , "xin24m" , 0 ,1 ), 13 , GFLAGS),"clk_ref24m" , "clk_pdpmu" , 0 ,7 ), 0 , 6 , DFLAGS,2 ), 0 , GFLAGS),"xin_osc0_usbphy0_g" , "xin24m" , 0 ,2 ), 1 , GFLAGS),"clk_usbphy0_ref" , clk_usbphy0_ref_p, 0 ,8 ), 0 , 1 , MFLAGS),"xin_osc0_usbphy1_g" , "xin24m" , 0 ,2 ), 2 , GFLAGS),"clk_usbphy1_ref" , clk_usbphy1_ref_p, 0 ,8 ), 1 , 1 , MFLAGS),"xin_osc0_mipidsiphy0_g" , "xin24m" , 0 ,2 ), 3 , GFLAGS),"clk_mipidsiphy0_ref" , clk_mipidsiphy0_ref_p, 0 ,8 ), 2 , 1 , MFLAGS),"xin_osc0_mipidsiphy1_g" , "xin24m" , 0 ,2 ), 4 , GFLAGS),"clk_mipidsiphy1_ref" , clk_mipidsiphy1_ref_p, 0 ,8 ), 3 , 1 , MFLAGS),"clk_wifi_div" , "clk_pdpmu" , 0 ,8 ), 8 , 6 , DFLAGS,2 ), 5 , GFLAGS),"clk_wifi_osc0" , "xin24m" , 0 ,2 ), 6 , GFLAGS),"clk_wifi" , clk_wifi_p, CLK_SET_RATE_PARENT,8 ), 15 , 1 , MFLAGS),"clk_pciephy0_div" , "ppll_ph0" , 0 ,9 ), 0 , 3 , DFLAGS,2 ), 7 , GFLAGS),"clk_pciephy0_osc0" , "xin24m" , 0 ,2 ), 8 , GFLAGS),"clk_pciephy0_ref" , clk_pciephy0_ref_p, CLK_SET_RATE_PARENT,9 ), 3 , 1 , MFLAGS),"clk_pciephy1_div" , "ppll_ph0" , 0 ,9 ), 4 , 3 , DFLAGS,2 ), 9 , GFLAGS),"clk_pciephy1_osc0" , "xin24m" , 0 ,2 ), 10 , GFLAGS),"clk_pciephy1_ref" , clk_pciephy1_ref_p, CLK_SET_RATE_PARENT,9 ), 7 , 1 , MFLAGS),"clk_pciephy2_div" , "ppll_ph0" , 0 ,9 ), 8 , 3 , DFLAGS,2 ), 11 , GFLAGS),"clk_pciephy2_osc0" , "xin24m" , 0 ,2 ), 12 , GFLAGS),"clk_pciephy2_ref" , clk_pciephy2_ref_p, CLK_SET_RATE_PARENT,9 ), 11 , 1 , MFLAGS),"clk_pcie30phy_ref_m" , "ppll_ph0" , 0 ,2 ), 13 , GFLAGS),"clk_pcie30phy_ref_n" , "ppll_ph180" , 0 ,2 ), 14 , GFLAGS),"xin_osc0_edpphy_g" , "xin24m" , 0 ,2 ), 15 , GFLAGS),"clk_hdmi_ref" , clk_hdmi_ref_p, CLK_SET_RATE_PARENT,8 ), 7 , 1 , MFLAGS),static const char *const rk3568_cru_critical_clocks[] __initconst = {"armclk" ,"pclk_core_pre" ,"aclk_bus" ,"pclk_bus" ,"aclk_top_high" ,"aclk_top_low" ,"hclk_top" ,"pclk_top" ,"aclk_perimid" ,"hclk_perimid" ,"aclk_secure_flash" ,"hclk_secure_flash" ,"aclk_core_niu2bus" ,"npll" ,"clk_optc_arb" ,"hclk_php" ,"pclk_php" ,"hclk_usb" ,"pclk_usb" ,"hclk_vi" ,"hclk_vo" ,static const char *const rk3568_pmucru_critical_clocks[] __initconst = {"pclk_pdpmu" ,"pclk_pmu" ,"clk_pmu" ,static void __init rk3568_pmu_clk_init(struct device_node *np)struct rockchip_clk_provider *ctx;void __iomem *reg_base;0 );if (!reg_base) {"%s: could not map cru pmu region\n" , __func__);return ;if (IS_ERR(ctx)) {"%s: rockchip pmu clk init failed\n" , __func__);return ;1 , reg_base + RK3568_PMU_SOFTRST_CON(0 ),"rockchip,rk3568-pmucru" , rk3568_pmu_clk_init);static void __init rk3568_clk_init(struct device_node *np)struct rockchip_clk_provider *ctx;void __iomem *reg_base;0 );if (!reg_base) {"%s: could not map cru region\n" , __func__);return ;if (IS_ERR(ctx)) {"%s: rockchip clk init failed\n" , __func__);return ;"armclk" ,30 , reg_base + RK3568_SOFTRST_CON(0 ),"rockchip,rk3568-cru" , rk3568_clk_init);struct clk_rk3568_inits {void (*inits)(struct device_node *np);static const struct clk_rk3568_inits clk_rk3568_pmucru_init = {static const struct clk_rk3568_inits clk_3568_cru_init = {static const struct of_device_id clk_rk3568_match_table[] = {"rockchip,rk3568-cru" ,"rockchip,rk3568-pmucru" ,static int __init clk_rk3568_probe(struct platform_device *pdev)struct device_node *np = pdev->dev.of_node;const struct clk_rk3568_inits *init_data;struct clk_rk3568_inits *)of_device_get_match_data(&pdev->dev);if (!init_data)return -EINVAL;if (init_data->inits)return 0 ;static struct platform_driver clk_rk3568_driver = {"clk-rk3568" ,true ,
Messung V0.5 in Prozent C=96 H=95 G=95
