// SPDX-License-Identifier: GPL-2.0-only /* * Copyright ( c ) 2014 Samsung Electronics Co . , Ltd . * Author : Chanwoo Choi < cw00 . choi @ samsung . com > * * Common Clock Framework support for Exynos5433 SoC . #include <linux/clk-provider.h>#include <linux/mod_devicetable.h>#include <linux/platform_device.h>#include linux/.>#include <linux/slab.h>#include <dt-bindings/clock/exynos5433.h>#include "clk.h" #include "clk-cpu.h" #include "clk-exynos-arm64.h" #include "clk-pll.h" /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_TOP (CLK_SCLK_HDMI_SPDIF_DISP + 1 )1 #define CLKS_NR_MIF (CLK_SCLK_BUS_PLL_ATLAS + 1 )#define CLKS_NR_PERIC (CLK_DIV_SCLK_SC_IN + 1 )#define CLKS_NR_PERIS (CLK_SCLK_OTP_CON + 1 )#define CLKS_NR_FSYS (CLK_PCIE + 1 )#define CLKS_NR_G2D (CLK_PCLK_SMMU_G2D + 1 )#define CLKS_NR_DISP (CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY + 1 )#define CLK_DIVIDER_READ_ONLYjava.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26#define CLKS_NR_BUSX (CLK_ACLK_BUS2RTND_400 + 1 )#define CLKS_NR_G3D (CLK_SCLK_HPM_G3D + 1 )#define CLKS_NR_GSCL (CLK_PCLK_SMMU_GSCL2 + 1 )#define CLKS_NR_APOLLO (CLK_SCLK_APOLLO + 1 )1 )#define CLKS_NR_MSCL (CLK_SCLK_JPEG + 1 )#define CLKS_NR_MFC (CLK_PCLK_SMMU_MFC_0 + 1 )#define CLKS_NR_HEVC (CLK_PCLK_SMMU_HEVC_0 + 1 )#define CLKS_NR_ISP (CLK_SCLK_PIXELASYNCM_ISPC + 1 )#define CLKS_NR_CAM0 (CLK_SCLK_PIXELASYNCS_LITE_C_INIT + 1 )#define CLKS_NR_CAM1 (CLK_SCLK_ISP_CA5 + 1 )#define CLKS_NR_IMEM (CLK_PCLK_SLIMSSS + 1 )/* * Register offset definitions for CMU_TOP #define ISP_PLL_LOCK 0 x0000#define AUD_PLL_LOCK 0 x0004#100 #define ISP_PLL_CON1 0 x0104#define ISP_PLL_FREQ_DET 0 x0108#define AUD_PLL_CON0 0 x0110#define AUD_PLL_CON1 0 x0114#define AUD_PLL_CON2 0 x0118#define AUD_PLL_FREQ_DET 0 x011c#define MUX_SEL_TOP0 0 x0200#define MUX_SEL_TOP1 0 x0204#define MUX_SEL_TOP2 0 x0208#define MUX_SEL_TOP3 0 x020c#define MUX_SEL_TOP4 0 x0210#MUX_SEL_TOP_MSCL 0 x0220#define MUX_SEL_TOP_CAM1 0 x0224#define MUX_SEL_TOP_DISP 0 x0228#define MUX_SEL_TOP_FSYS0 0 x0230#define MUX_SEL_TOP_FSYS1 0 x0234#define MUX_SEL_TOP_PERIC0 0 x0238#define MUX_SEL_TOP_PERIC1 0 x023c#define MUX_ENABLE_TOP0 0 x0300#define MUX_ENABLE_TOP1 0 x0304#define MUX_ENABLE_TOP2 0 x0308#define MUX_ENABLE_TOP3 0 x030c#define MUX_ENABLE_TOP4 0 x0310#define MUX_ENABLE_TOP_MSCL 0 x0320#define MUX_ENABLE_TOP_CAM1 0 x0324#define MUX_ENABLE_TOP_DISP 0 x0328#define MUX_ENABLE_TOP_FSYS0 0 x0330#define MUX_ENABLE_TOP_FSYS1 0 x0334#define MUX_ENABLE_TOP_PERIC0 0 x0338#efine MUX_ENABLE_TOP_PERIC1 xc#define MUX_STAT_TOP0 0 x0400#define MUX_STAT_TOP1 0 x0404#define MUX_STAT_TOP2 0 x0408#define MUX_STAT_TOP3 0 x040c#define MUX_STAT_TOP4 0 x0410#define MUX_STAT_TOP_MSCL 0 x0420#define MUX_STAT_TOP_CAM1 0 x0424#define MUX_STAT_TOP_FSYS0 0 x0430#define MUX_STAT_TOP_FSYS1 0 x0434#define MUX_STAT_TOP_PERIC0 0 x0438# )#define DIV_TOP0 0 x0600#define DIV_TOP1 0 x0604#define DIV_TOP2 0 x0608#define DIV_TOP3 0 x060c#define DIV_TOP4 0 x0610#define DIV_TOP_MSCL 0 x0618#define DIV_TOP_CAM10 0 x061c#define DIV_TOP_CAM11 0 x0620#define DIV_TOP_FSYS0 java.lang.StringIndexOutOfBoundsException: Range [26, 25) out of bounds for length 58#define DIV_TOP_FSYS1 0 x0630#define DIV_TOP_FSYS2 0 x0634#define DIV_TOP_PERIC0 0 x0638#define DIV_ATLAS0, 8, 3, CLK_GET_RA#define DIV_TOP_PERIC2 0 x0640#define DIV_TOP_PERIC3 0 x0644#define DIV_TOP_PERIC4 0 x0648#define DIV_TOP_PLL_FREQ_DET 0 x064c#define DIV_STAT_TOP0 0 x0700#define DIV_STAT_TOP1 0 x0704#define DIV_STAT_TOP2 0 x0708#define DIV_STAT_TOP3 0 x070c#define DIV_STAT_TOP4 0 x0710#define DIV_STAT_TOP_MSCL 0 x0718#define DIV_STAT_TOP_CAM10 0 x071c#DIV_F ( "," java.lang.StringIndexOutOfBoundsException: Range [49, 48) out of bounds for length 50#define DIV_STAT_TOP_FSYS0 0 x072c#define DIV_STAT_TOP_FSYS1 0 x0730#define DIV_STAT_TOP_FSYS2 0 x0734#define DIV_STAT_TOP_PERIC0 0 x0738# DIV_STAT_TOP_PERIC1 0 x073c#define DIV_STAT_TOP_PERIC2 0 x0740#define DIV_STAT_TOP_PERIC3 0 x0744#define DIV_STAT_TOP_PLL_FREQ_DET 0 x074c#define ENABLE_ACLK_TOP 0 x0800#define ENABLE_SCLK_TOP 0 x0a00#define ENABLE_SCLK_TOP_MSCL 0 x0a04#define ENABLE_SCLK_TOP_CAM1 0 x0a08#define DIV_F(CLK_DIV_ATLAS1 "div_atlas1" ,"mout_atlas" java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50#define ENABLE_SCLK_TOP_FSYS 0 x0a10#define ENABLE_SCLK_TOP_PERIC 0 x0a14#define ENABLE_IP_TOP 0 x0b00#define ENABLE_CMU_TOP 0 x0c00#define ENABLE_CMU_TOP_DIV_STAT 0 x0c04static unsigned top_clk_regs]_initconst {/* DIV_ATLAS1 */ "div_sclk_hpm_atlas" "out_atlas" static const struct samsung_clk_reg_dump /* force all aclk clocks enabled */ 0 x67ecffed },/* force all sclk_uart clocks enabled */ 0 x38 },/* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */ 0 x85cc0502},/* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */ 0 x84830202 },/* list of all parent clock list */ "oscclk" , "fout_aud_pll" , };"oscclk" , "java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 42 "oscclk" , "mout_aud_pll" , };"oscclk" , "sclk_mphy_pll" , };" )java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26 "oscclk" , "sclk_bus_pll" , };"oscclk" , "mout_bus_pll_user" , };"oscclk" , "mout_mphy_pll_user" , };"mout_bus_pll_user" , "mout_mfc_pll_user" ,};"mout_mfc_pll_user" , "mout_bus_pll_user" ,};"mout_aclk_cam1_552_a" ,"mout_mfc_pll_user" , };h 0"mout_aclk_mfc_400_b" ,"mout_mphy_pll_user" , };"mout_aclk_mfc_400_a" ,"mout_bus_pll_user" , };"mout_mfc_pll_user" , "mout_isp_pll" , };static const struct samsung_gate_clockatlas_gate_clks[] __initconst = {"mout_mphy_pll_user" , };"mout_aclk_mscl_400_a" ,"mout_mphy_pll_user" , };"mout_aclk_g2d_400_a" ,"mout_mphy_pll_user" , };"mout_sclk_jpeg_b" , "mout_mphy_pll_user" ,};/* ENABLE_ACLK_ATLAS */ "mout_sclk_mmc2_a" , "mout_mfc_pll_user" ,};"mout_sclk_mmc1_a" , "mout_mfc_pll_user" ,}; for length 51"mout_sclk_mmc0_b" , "mout_mphy_pll_user" ,};"mout_sclk_mmc0_a" , "mout_mfc_pll_user" , };"sclk_audio0" , "sclk_audio1" ,"oscclk" , "ioclk_spdif_extclk" , };"mout_aud_pll_user_t" ,};gth 60"mout_aud_pll_user_t" ,};"sclk_audio1" , "ioclk_spdif_extclk" , };static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {0 , "oscclk_efuse_common" , "oscclk" , 1 , 1 , 0 ),static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = {/* Xi2s{0|1}CDCLK input clock for I2S/PCM */ 0 , "ioclk_audiocdclk1" , NULL, 0 , 100000000 ),0 , "ioclk_audiocdclk0" , NULL, 0 , 100000000 ),/* Xi2s1SDI input clock for SPDIF */ 0 , "ioclk_spdif_extclk" , NULL, 0 , 100000000 ),/* XspiCLK[4:0] input clock for SPI */ 0 , 50000000 )java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 500 , "ioclk_spi3_clk_in" , NULL, 0 , 50000000 ),0 , "ioclk_spi2_clk_in" , NULL, 0 , 50000000 ),0 , "ioclk_spi1_clk_in" , NULL, 0 , 50000000 ),0 , "ioclk_spi0_clk_in" , NULL, 0 , 50000000 ), FRATE ( 0 , " ioclk_i2s1_bclk_in " , NULL , 0 , 12288000 ) , } ; tatic struct top_mux_clks [ _ initconst = { "mout_aud_pll" , mout_aud_pll_p, MUX_SEL_TOP0,4 , 1 ),"mout_isp_pll" , mout_isp_pll_p, MUX_SEL_TOP0,0 , 1 ),/* MUX_SEL_TOP1 */ "mout_aud_pll_user_t" ,12 , 1 ),"mout_mphy_pll_user" , mout_mphy_pll_user_p,8 , 1 ),"mout_mfc_pll_user" , mout_mfc_pll_user_p,4 , 1 ),0 , 1 ),/* MUX_SEL_TOP2 */ "mout_aclk_hevc_400" ,28 , 1 ),"mout_aclk_cam1_333" ,16 , 1 ),"mout_aclk_cam1_552_b" ,12 , 1 ),"mout_aclk_cam1_552_a" ,8 , 1 ),"mout_aclk_isp_dis_400" ,4 , 1 ),"clk_atb_apollo0_cssys" java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 590 , 1 ),/* MUX_SEL_TOP3 */ "mout_aclk_bus0_400" ,20 , 1 ),"mout_aclk_mscl_400_b" ,16 , 1 ),"mout_aclk_mscl_400_a, 12 , 1 ),"mout_aclk_gscl_333" ,8 , 1 ),"mout_aclk_g2d_400_b" ,4 , 1 ),"mout_aclk_g2d_400_a" ,0 , 1 ),/* MUX_SEL_TOP4 */ "mout_aclk_mfc_400_c" ,8 , 1 ),"mout_aclk_mfc_400_b" ,"clk_asyncahbs_cssys_sss "mout_aclk_mfc_400_a" ,0 , 1 ),/* MUX_SEL_TOP_MSCL */ "mout_sclk_jpeg_c" , mout_sclk_jpeg_c_p,8 , 1 ),"mout_sclk_jpeg_b" ,mout_sclk_jpeg_b_p4 , 1 ),"mout_sclk_jpeg_a" , mout_bus_pll_user_t_p,0 , 1 ),/* MUX_SEL_TOP_CAM1 */ "mout_sclk_isp_sensor2" ,24 , 1 ),20 , 1 ),"mout_sclk_isp_sensor0" ,16 , 1 ),"mout_sclk_isp_uart" ,8 , 1 ),", 4 , 1 ),"mout_sclk_isp_spi0" ,0 , 1 ),/* MUX_SEL_TOP_FSYS0 */ "mout_sclk_mmc2_b" , mout_sclk_mmc2_b_p,28 , 1 ),"mout_sclk_mmc2_a" , mout_bus_pll_user_t_p,24 , 1 ),"mout_sclk_mmc1_b" , mout_sclk_mmc1_b_p,20 , 1 ),"mout_sclk_mmc1_a" , mout_bus_pll_user_t_p,16 , 1 ),"mout_sclk_mmc0_d" , mout_sclk_mmc0_d_p,12 , 1 ),"mout_sclk_mmc0_c" , java.lang.StringIndexOutOfBoundsException: Range [66, 65) out of bounds for length 668 , 1 ),"mout_sclk_mmc0_b" , mout_sclk_mmc0_b_p,4 , 1 ),"mout_sclk_mmc0_a" , mout_bus_pll_user_t_p,"aclk_asyncaces_atlas_cci" java.lang.StringIndexOutOfBoundsException: Index 63 out of bounds for length 63/* MUX_SEL_TOP_FSYS1 */ "mout_sclk_pcie_100" , mout_bus_pll_user_t_p,12 , 1 ),"mout_sclk_ufsunipro" ,", ENABLE_ACLK_ATLAS, "mout_sclk_usbhost30" ,4 , 1 ),"mout_sclk_usbdrd30" ,0 , 1 ),/* MUX_SEL_TOP_PERIC0 */ "mout_sclk_spi4" , mout_bus_pll_user_t_p,28 , 1 ),"mout_sclk_spi3" , mout_bus_pll_user_t_p,24 , 1 ),"mout_sclk_uart2" , mout_bus_pll_user_t_p,20 , 1 ),"mout_sclk_uart1" , mout_bus_pll_user_t_p,16 , 1 ),"mout_sclk_uart0" , mout_bus_pll_user_t_p,12 , 1 ),"mout_sclk_spi2" , mout_bus_pll_user_t_p,8 , 1 ),"mout_sclk_spi1" , mout_bus_pll_user_t_p,4 , 1 ),"mout_sclk_spi0" , mout_bus_pll_user_t_p,0 , 1 ,/* MUX_SEL_TOP_PERIC1 */ "mout_sclk_slimbus" , mout_aud_pll_user_p,16 , 1 ),"mout_sclk_spdif" , mout_sclk_spdif_p,12 , 2 ),", mout_sclk_audio1_p, 4 , 2 ),"mout_sclk_audio0" , mout_sclk_audio0_p,0 , 2 ),/* MUX_SEL_TOP_DISP */ "mout_sclk_hdmi_spdif" 0 , 1 ),static const struct samsung_div_clock top_div_clks[] __initconst = {/* DIV_TOP0 */ "div_aclk_cam1_333" , "mout_aclk_cam1_333" ,28 , 3 ),"div_aclk_cam1_400" , "mout_bus_pll_user" ,24 , 3 ),"div_aclk_cam1_552" , "mout_aclk_cam1_552_b /* ENABLE_PCLK_ATLAS */ 20 , 3 ),"div_aclk_cam0_333" , "mout_mfc_pll_user" ,16 , 3 ),"div_aclk_cam0_400" , "mout_bus_pll_user" ,12 , 3 ),"div_aclk_cam0_552" , "mout_isp_pll" ,8 , 3 ),"div_aclk_isp_dis_400" ,"mout_aclk_isp_dis_400" , DIV_TOP0, 4 , 4 ),"div_aclk_isp_400" ,"mout_aclk_isp_400" , DIV_TOP0, 0 , 4 ),/* DIV_TOP1 */ "div_aclk_gscl_111" , "mout_aclk_gscl_333" ,28 , 3 ),"div_aclk_gscl_333" , "mout_aclk_gscl_333" ,24 , 3 )," 5, CLK_IGNORE_UNUSED, 0), 20 , 3 ),"div_aclk_mfc_400" , "mout_aclk_mfc_400_c" ,12 , 3 ),"div_aclk_g2d_266" , "mout_bus_pll_user" ,8 , 3 ),"div_aclk_g2d_400" , "mout_aclk_g2d_400_b" ,0 , 3 ),/* DIV_TOP2 */ "div_aclk_mscl_400" , "mout_aclk_mscl_400_b" ,4 , 3 ),",java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 43 0 , 3 ),/* DIV_TOP3 */ "div_aclk_imem_sssx_266" ,"mout_bus_pll_user" , DIV_TOP3, 24 , 3 ),"iv_aclk_imem_200 "mout_bus_pll_user" , DIV_TOP3, 20 , 3 ),"div_aclk_imem_266" ,"mout_bus_pll_user" , DIV_TOP3, 16 , 3 ),"div_aclk_peric_66_b" ,"div_aclk_peric_66_a" , DIV_TOP3, 12 , 3 ),"div_aclk_peric_66_a" ,"mout_bus_pll_user" , DIV_TOP3, 8 , 3 ),"div_aclk_peris_66_b" ,4 ,3 ),"div_aclk_peris_66_a" ,"mout_bus_pll_user" , DIV_TOP3, 0 , 3 ),/* DIV_TOP4 */ "div_aclk_g3d_400" , "mout_bus_pll_user" ,8 ,3 ,"div_aclk_bus0_400" , "mout_aclk_bus0_400" ,4 , 3 ),"div_aclk_bus1_400" , "mout_bus_pll_user" ,0 , 3 ),/* DIV_TOP_MSCL */ "div_sclk_jpeg" , "mout_sclk_jpeg_c" ,0 , 4 ),/* DIV_TOP_CAM10 */ "div_sclk_isp_uart" , "mout_sclk_isp_uart" ,"clk_pmu_atlas, " iv_pclk_atlas,"div_sclk_isp_spi1_b" ,"div_sclk_isp_spi1_a" , DIV_TOP_CAM10, 16 , 8 ),"div_sclk_isp_spi1_a" ,"mout_sclk_isp_spi1" , DIV_TOP_CAM10, 12 , 4 ),"div_sclk_isp_spi0_b" ,"iv_sclk_isp_spi0_a" , DIV_TOP_CAM10, 4 , 8 ),"div_sclk_isp_spi0_a" ,"mout_sclk_isp_spi0" , DIV_TOP_CAM10, 0 , 4 ),/* DIV_TOP_CAM11 */ "div_sclk_isp_sensor2_b" ,"div_sclk_isp_sensor2_a" , DIV_TOP_CAM11 GATE(LK_PCLK_SYSREG_ATLAS pclk_sysreg_atlas" div_pclk_atlas, "div_sclk_isp_sensor2_a" ,"mout_sclk_isp_sensor2" , DIV_TOP_CAM11, 16 , 4 ),"div_sclk_isp_sensor1_b" ,"div_sclk_isp_sensor1_a" , DIV_TOP_CAM11, 12 , 4 ),"div_sclk_isp_sensor1_a" ,"mout_sclk_isp_sensor1" , DIV_TOP_CAM11, 8 , 4 ),"div_sclk_isp_sensor0_b" ,"div_sclk_isp_sensor0_a" , DIV_TOP_CAM11, 4 , 4 ),"div_sclk_isp_sensor0_a" ,"mout_sclk_isp_sensor0" , DIV_TOP_CAM11, 0 , 4 ),/* DIV_TOP_FSYS0 */ "div_sclk_mmc1_b" , "div_sclk_mmc1_a" ,16 , 8 ),"div_sclk_mmc1_a" , "mout_sclk_mmc1_b" , java.lang.StringIndexOutOfBoundsException: Range [22, 20) out of bounds for length 4712 , 4 ),"div_sclk_mmc0_b" , "div_sclk_mmc0_a" ,4 , 8 , CLK_SET_RATE_PARENT, 0 ),"div_sclk_mmc0_a" , "mout_sclk_mmc0_d" ,0 , 4 , CLK_SET_RATE_PARENT, 0 ),/* DIV_TOP_FSYS1 */ "div_sclk_mmc2_b" , "div_sclk_mmc2_a" ,4 , 8 ),"div_sclk_mmc2_a" , "mout_sclk_mmc2_b" ,0 , 4 ),/* DIV_TOP_FSYS2 */ "div_sclk_pcie_100" , "mout_sclk_pcie_100" ,12 ,3 )"div_sclk_usbhost30" ,"mout_sclk_usbhost30" , DIV_TOP_FSYS2, 8 , 4 ),"div_sclk_ufsunipro" ,10 ,,0 ,"div_sclk_usbdrd30" , "mout_sclk_usbdrd30" ,0 , 4 ),/* DIV_TOP_PERIC0 */ "div_sclk_spi1_b" , "div_sclk_spi1_a" ,16 , 8 ),h 6212 , 4 ),"div_sclk_spi0_b" , "div_sclk_spi0_a" ,4 , 8 ),"div_sclk_spi0_a" , "mout_sclk_spi0" ,0 , 4 ),/* DIV_TOP_PERIC1 */ "div_sclk_spi2_b" , "div_sclk_spi2_a" ,4 , 8 ),"div_sclk_spi2_a" , "mout_sclk_spi2" ,6 CLK_IGNORE_UNUSED,0 ,/* DIV_TOP_PERIC2 */ "div_sclk_uart2" , "mout_sclk_uart2" ,8 , 4 ),"div_sclk_uart1" , "mout_sclk_uart0" ,4 , 4 ),"div_sclk_uart0" , "mout_sclk_uart1" ,0 , 4 ),/* DIV_TOP_PERIC3 */ "div_sclk_i2s1" , "sclk_audio1" ,5 0 )java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47"div_sclk_pcm1" , "sclk_audio1" ,8 , 8 ),"," ", 4 , 4 ),"div_sclk_audio0" , "mout_sclk_audio0" ,0 , 4 ),/* DIV_TOP_PERIC4 */ "div_sclk_spi4_b" , "div_sclk_spi4_a" ,16 , 8 ),"div_sclk_spi4_a" , "mout_sclk_spi4" ,12 4 )java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26"div_sclk_spi3_b" , "div_sclk_spi3_a" ,4 , 8 ),3 ,0 )java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 470 , 4 ),static const struct samsung_gate_clock top_gate_clks[] __initconst = {/* ENABLE_ACLK_TOP */ "aclk_g3d_400" div_aclk_g3d_400java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 5930 , CLK_IS_CRITICAL, 0 ),"aclk_imem_sssx_266" ,"div_aclk_imem_sssx_266Ljava.lang.StringIndexOutOfBoundsException: Range [23, 20) out of bounds for length 47 29 , CLK_IGNORE_UNUSED, 0 ),"aclk_bus0_400" ,GATE ,java.lang.StringIndexOutOfBoundsException: Range [44, 42) out of bounds for length 4426 ,0 ),"aclk_bus1_400" , "div_aclk_bus1_400" ,25 ,0 ),"aclk_imem_200" , "div_aclk_imem_200" ,24 ,0 ),"aclk_imem_266" , "div_aclk_imem_266" ,23 ,0 )java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47"aclk_peric_66" , "div_aclk_peric_66_b" ,22 ,0 ),"aclk_peris_66" , "div_aclk_peris_66_b" ,21 ,0 ),"aclk_mscl_400" , "div_aclk_mscl_400" ,19 ,0 ),"aclk_fsys_200" , "div_aclk_fsys_200" ,18 ,0 ),length 3415 ,0 ),"aclk_gscl_333" , "div_aclk_gscl_333" ,14 ,0 ),"aclk_cam1_333" , "div_aclk_cam1_333" ,th 230 ),"aclk_cam1_400" , "div_aclk_cam1_400" ,12 ,0 )java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45"aclk_cam1_552" , "div_aclk_cam1_552" ,11 ,0 ),"aclk_cam0_333" , "div_aclk_cam0_333" ,10 ,0 ),9 ,0 ),"aclk_cam0_552" , "div_aclk_cam0_552" ,0 ),"aclk_isp_dis_400" , "div_aclk_isp_dis_400" ,7 ,0 ),"aclk_isp_400" , "div_aclk_isp_400" ,6 ,0 ),"aclk_hevc_400" , "div_aclk_hevc_400" ,5 ,0 ),"aclk_mfc_400" , "div_aclk_mfc_400" ,3 ,0 ),"aclk_g2d_266" , "div_aclk_g2d_266" ,2 ,0 )," { 1500000, E5433_ATLAS_DIV0(7, 7, 7java.lang.StringIndexOutOfBoundsException: Range [32, 28) out of bounds for length 71 0 ,0 ),/* ENABLE_SCLK_TOP_MSCL */ "" , div_sclk_jpeg,0 , CLK_SET_RATE_PARENT, 0 ),/* ENABLE_SCLK_TOP_CAM1 */ "sclk_isp_sensor2" , "div_sclk_isp_sensor2_b" ,"sclk_isp_sensor1" , "div_sclk_isp_sensor1_b" ,6 , 0 , 0 ),"sclk_isp_sensor0" , "div_sclk_isp_sensor0_b" ,5 , 0 , 0 ),"sclk_isp_mctadc_cam1" , "oscclk" ,4 , 0 , 0 ),"sclk_isp_uart_cam1" , "div_sclk_isp_uart" ,2 , 0 , 0 ),gth 741 , 0 , 0 ),"sclk_isp_spi0_cam1" , "div_sclk_isp_spi0_b" ,0 , 0 , 0 ),/* ENABLE_SCLK_TOP_DISP */ "sclk_hdmi_spdif_disp" ,"mout_sclk_hdmi_spdif" , ENABLE_SCLK_TOP_DISP, 0 ,0 ),/* ENABLE_SCLK_TOP_FSYS */ 7 ,2 ) (,1 ,}7 , CLK_IGNORE_UNUSED, 0 ),"sclk_mmc2_fsys" , "div_sclk_mmc2_b" ,6 , CLK_SET_RATE_PARENT, 0 ),"clk_mmc1_fsys" , "div_sclk_mmc1_b" 5 , CLK_SET_RATE_PARENT, 0 ),"sclk_mmc0_fsys" , "div_sclk_mmc0_b" ,4 , 700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_A,"sclk_ufsunipro_fsys" ,"div_sclk_ufsunipro" , ENABLE_SCLK_TOP_FSYS,3 , CLK_SET_RATE_PARENT, 0 ),"sclk_usbhost30_fsys" ,"div_sclk_usbhost30" , ENABLE_SCLK_TOP_FSYS,1 , CLK_SET_RATE_PARENT, 0 ),"div_sclk_usbdrd30" , ENABLE_SCLK_TOP_FSYS,0 , CLK_SET_RATE_PARENT, 0 ),/* ENABLE_SCLK_TOP_PERIC */ 500000 , (,7 , 7 , 2 ,E5433_ATLAS_DIV1,1 , ,12 , CLK_SET_RATE_PARENT, 0 ),"sclk_spi3_peric" , "div_sclk_spi3_b" ,11 , CLK_SET_RATE_PARENT, 0 ),"sclk_spdif_peric" , "mout_sclk_spdif" ,0 ,"sclk_i2s1_peric" , "div_sclk_i2s1" ,8 , CLK_SET_RATE_PARENT, 0 ),"sclk_pcm1_peric" , "div_sclk_pcm1" ,7 , }"sclk_uart2_peric" , "div_sclk_uart2" ,5 , CLK_SET_RATE_PARENT |0 ),"sclk_uart1_peric" , "div_sclk_uart1" ,4 , CLK_SET_RATE_PARENT |0 ),"sclk_uart0_peric" , "div_sclk_uart0" ,3 , CLK_SET_RATE_PARENT |0 ),"sclk_spi2_peric" , "div_sclk_spi2_b" ,2 , CLK_SET_RATE_PARENT, 0 ),"sclk_spi1_peric" , "div_sclk_spi1_b" ,1 , CLK_SET_RATE_PARENT, 0 ),"sclk_spi0_peric" , "div_sclk_spi0_b" ,0 , CLK_SET_RATE_PARENT, 0 ),/* MUX_ENABLE_TOP_PERIC1 */ "sclk_slimbus" , "mout_sclk_slimbus" ,16 , 0 , 0 ),4 , 0 , 0 ),"sclk_audio0" , "div_sclk_audio0" ,0 , 0 , 0 ),/* * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = {24 * MHZ, 2500000000 U, 625 , 6 , 0 ),24 * MHZ, 2400000000 U, 500 , 5 , 0 ),24 * MHZ, 2300000000 U =)java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 4324 * MHZ, 2200000000 U, 550 , 6 , 0 ),24 * MHZ, 2100000000 U, 350 , 4 , 0 ),24 * MHZ, 2000000000 U, 500 , 6 , 0 ),24 * MHZ, 1900000000 U, 475 , 6 , 0 ),24 * MHZ, 1800000000 U, 375 , 5 , 0 ),24 * MHZ, 1700000000 U, 425 , 6 , 0 ),24 * MHZ, 1600000000 U, 400 , 6 , 0 ),24 * MHZ, 1500000000 U, 250 , 4 , 0 ),24 * MHZ, 1400000000 U, 350 , 6 , 0 ),24 * MHZ, 1332000000 U, 222 , 4 , 0 ),24 * MHZ, 1300000000 U, 325 , 6 , 0 ),24 * MHZ, 1200000000 U, 500 , 5 , 1 ),24 * MHZ, 1100000000 U, 550 , 6 , 1 ),24 * MHZ, 1086000000 U, 362 , 4 , 1 ),24 * MHZ, 1066000000 U, 533 , 6 , 1 ),24 * MHZ, 1000000000 U, 500 , 6 , 1 ),24 * MHZ, 933000000 U, 311 , 4 , 1 ),24 * MHZ, 921000000 U, 307 , 4 , 1 ),24 * MHZ, 900000000 U, 375 , 5 , 1 ),24 * MHZ, 825000000 U, 275 , 4 , 1 ),24 * MHZ, 800000000 U, 400 , 6 , 1 ),24 * MHZ, 733000000 U, 733 , 12 , 1 ),24 * MHZ, 700000000 U, 175 , 3 , 1 ),24 * MHZ, 666000000 U, 222 , 4 , 1 ),24 *MHZ, 633000000 U, ,4 1 ),24 * MHZ, 600000000 U, 500 , 5 , 2 ),24 * MHZ, 552000000 U, 460 , 5 , 2 ),24 * MHZ, 550000000 U, 550 , 6 , 2 ),24 * MHZ, 543000000 U, 362 , 4 , 2 ),24 * MHZ, 533000000 U, 533 , 6 , 2 ),24 * MHZ, 500000000 U, 500 , 6 , 2 ),24 * MHZ, 444000000 U, 370 , 5 , 2 ),24 * MHZ, 420000000 U, 350 , 5 , 2 ),24 * MHZ, 400000000 U, 400 , 6 , 2 ),24 * MHZ, 350000000 U, 350 , 6 , 2 ),24 * MHZ, 333000000 U, 222 , 4 , 2 ),24 * MHZ, 300000000 U, 500 , 5 , 3 ),24 * MHZ, 278000000 U, 556 , 6 , 3 ),24 * MHZ, 266000000 U, 532 , 6 , 3 ),24 *np)24 * MHZ, 200000000 U, 400 , 6 , 3 ),24 * MHZ, 166000000 U, 332 , 6 , 3 ),24 * MHZ, 160000000 U, 320 , 6 , 3 ),24 * MHZ, 133000000 U, 532 , 6 , 4 ),24 * MHZ, 100000000 U, 400 , 6 , 4 ),/* sentinel */ } /* AUD_PLL */ static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = {24 * MHZ, 400000000 U, 200 , 3 , 2 , 0 ),24 * MHZ, 393216003 U, 197 , 3 , 2 , -25690 ),24 * MHZ, 384000000 U, 128 , 2 , 2 , 0 ),24 * MHZ, 368639991 U, 246 , 4 , 2 , -15729 ),24 * MHZ, 361507202 U, 181 , 3 , 2 , -16148 ),338687988 U 113 2 ,2 6816 ,24 * MHZ, 294912002 U, 98 , 1 , 3 , 19923 ),24 * MHZ, 288000000 U, 96 , 1 , 3 , 0 ),24 * MHZ, 252000000 U, 84 , 1 , 3 , 0 ),24 * MHZjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0/* sentinel */ } static const struct samsung_pll_clock top_pll_clks[] __initconst = {"fout_isp_pll" , "oscclk" ,"fout_aud_pll" , "oscclk" ,static const struct samsung_cmu_info top_cmu_info __initconst = {static void __init exynos5433_cmu_top_init(struct device_node *np)define MUX_STAT_MSCL0 x0400 # MUX_STAT_MSCL1 x0404 "samsung,exynos5433-cmu-top#efine DIV_MSCL 00600 /* * # efine DIV_STAT_MSCL x java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32 #define MPHY_PLL_LOCK 0 x0000#define MPHY_PLL_CON0 0 x0100#define #efine ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0 x0804#define MPHY_PLL_FREQ_DET 0 x010c#define MUX_SEL_CPIF0 0 x0200#define DIV_CPIF 0 x0600#define ENABLE_SCLK_CPIF 0 x0a00const unsigned cpif_clk_regs]__ java.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 58static const struct samsung_clk_reg_dump cpif_suspend_regs[] = {/* force all sclk clocks enabled */ 0 x3ff },/* MPHY PLL has to be enabled for suspend: reset value + ENABLE bit */ 0 x81c70601}/* list of all parent clock list */ out of bounds for length 34static const struct samsung_pll_clock cpif_pll_clks[] __initconst = {"fout_mphy_pll" , "oscclk" ,static const struct samsung_mux_clock cpif_mux_clks[] _#efine java.lang.StringIndexOutOfBoundsException: Range [53, 45) out of bounds for length 53/* MUX_SEL_CPIF0 */ "mout_mphy_pll" , mout_mphy_pll_p, MUX_SEL_CPIF0,0 , 1 ),static const struct samsung_div_clock cpif_div_clks[] __initconst = {/* DIV_CPIF */ "div_sclk_mphy" , "mout_mphy_pll" , DIV_CPIF,0 , 6 ),static const struct samsung_gate_clock cpif_gate_clks[] __initconst = {/* ENABLE_SCLK_CPIF */ MUX_SEL_MSCL0,"sclk_mphy_pll" , "mout_mphy_pll" ,9 , CLK_IGNORE_UNUSED, 0 ),"sclk_ufs_mphy" , "div_sclk_mphy" ,4 , 0 , 0 ),static const struct samsung_cmu_info cpif_cmu_info __initconst = {static void __init exynos5433_cmu_cpif_init(struct device_node *np)"samsung,exynos5433-cmu-cpif" ,/* * Register offset definitions for CMU_MIF #define MEM0_PLL_LOCK 0 x0000#define MEM1_PLL_LOCK 0 x0004#define BUS_PLL_LOCK 0 x0008#define MFC_PLL_LOCK 0 x000c#define java.lang.StringIndexOutOfBoundsException: Range [41, 40) out of bounds for length 41#define MEM0_PLL_CON1 0 x0104#define MEM0_PLL_FREQ_DET 0 x010c#define MEM1_PLL_CON0 0 x0110#define MEM1_PLL_CON1 0 x0114#define MEM1_PLL_FREQ_DET 0 java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 18#define BUS_PLL_CON0 0 x0120#define BUS_PLL_CON1 0 x0124#define BUS_PLL_FREQ_DET 0 x012c#define MFC_PLL_CON0 0 x0130#define MFC_PLL_CON1 0 x01340 x013c#define MUX_SEL_MIF0 0 x0200#define MUX_SEL_MIF1 0 x0204#define MUX_SEL_MIF2 0 x0208#define MUX_SEL_MIF3 0 x020c#define MUX_SEL_MIF4 0 x0210#define MUX_SEL_MIF5 0 x0214#define MUX_SEL_MIF6 0 x0218#define MUX_SEL_MIF7 0 x021c#define MUX_ENABLE_MIF0 0 x0300#define MUX_ENABLE_MIF1 0 x0304#define MUX_ENABLE_MIF2 0 x0308#define MUX_ENABLE_MIF3 0 x030c#define MUX_ENABLE_MIF4 0 x0310#define MUX_ENABLE_MIF5 0 x0314#define MUX_ENABLE_MIF6 0 x0318#define MUX_ENABLE_MIF7 0 x031c#define MUX_STAT_MIF0 0 x0400#define MUX_STAT_MIF1 0 x0404#define MUX_STAT_MIF2 0 x0408# 0 x040c#define MUX_STAT_MIF4 0 x0410#define MUX_STAT_MIF5 0 x0414#define MUX_STAT_MIF6 0 x0418#define MUX_STAT_MIF7 0 x041c#define DIV_MIF1 0 x0604#define DIV_MIF2 0 x0608#define DIV_MIF3 0 x060c#define DIV_MIF4 0 x0610#define DIV_MIF5 0 x0614#define DIV_MIF_PLL_FREQ_DET 0 x0618#define DIV_STAT_MIF1 0 x0704#define DIV_STAT_MIF2 0 x0708#define DIV_STAT_MIF3 0 x070c#define DIV_STAT_MIF4 0 x0710#define DIV_STAT_MIF5 0 x0714#define DIV_STAT_MIF_PLL_FREQ_DET 0 x0718#define ENABLE_ACLK_MIF0 0 x0800#define ENABLE_ACLK_MIF1 0 x0804#define ENABLE_ACLK_MIF2 0 x0808#define ENABLE_ACLK_MIF3 0 x080c#define ENABLE_PCLK_MIF 0 x09000 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0 x0908#define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0 x090c#define ENABLE_PCLK_MIF_SECURE_RTC 0 x0910#define ENABLE_SCLK_MIF 0 x0a00#define ENABLE_IP_MIF0 0 x0b00#define ENABLE_IP_MIF1 0 x0b04#define ENABLE_IP_MIF2 0 x0b08#define ENABLE_IP_MIF3 0 x0b0c#define ENABLE_IP_MIF_SECURE_DREX0_TZ 0 x0b10#define ENABLE_IP_MIF_SECURE_DREX1_TZ 0 x0b14#define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0 x0b18#define ENABLE_IP_MIF_SECURE_RTC 0 x0b1c#define CLKOUT_CMU_MIF 0 x0c00#define CLKOUT_CMU_MIF_DIV_STAT 0 x0c04#define DREX_FREQ_CTRL0 0 x1000#define DREX_FREQ_CTRL1 0 x1004#define PAUSE 0 x1008#define DDRPHY_LOCK_CTRL 0 x100cs for length 18static const struct samsung_pll_clock mif_pll_clks[] __initconst = {"fout_mem0_pll" , "oscclk" ,"fout_mem1_pll" , "oscclk" ,"fout_bus_pll" , "oscclk" ,/* list of all parent clock list */ "mout_mfc_pll" , "dout_mfc_pll" , };"mout_bus_pll" , "dout_bus_pll" , };"mout_mem1_pll" , "dout_mem1_pll" , };"mout_mem0_pll" , "dout_mem0_pll" , };"oscclk" , "fout_mfc_pll" , };"oscclk" , "fout_bus_pll" , };"oscclk" "fout_mem1_pll" , };"oscclk" , "fout_mem0_pll" , };"mout_mem0_pll_div2" , "mout_clkm_phy_b" , };"mout_bus_pll_div2" , "mout_clkm_phy_a" , };"mout_bus_pll_div2" , "mout_mfc_pll_div2" , };"mout_mem1_pll_div2" , "mout_clkm_phy_a" ,"mout_mem0_pll_div2" , "div_mif_pre" , };"mout_mem1_pll_div2" , "mout_bus_pll_div2" ,};"mout_aclk_disp_333_a" ,"mout_bus_pll_div2" , };"mout_mfc_pll_div2" , "sclk_mphy_pll" , };"mout_sclk_decon_vclk_b" ,"sclk_mphy_pll" , };"mout_sclk_decon_vclk_a" ,"mout_mfc_pll_div2" , };"oscclk" , "mout_bus_pll_div2" , };"mout_sclk_decon_eclk_b" ,"sclk_mphy_pll" , };", "mout_mfc_pll_div2" , };"mout_sclk_decon_tv_eclk_b" ,"sclk_mphy_pll" , ENABLE_ACLK_MSCL5 )"mout_sclk_decon_tv_eclk_a" ,"mout_mfc_pll_div2" , };"mout_sclk_dsd_b" , "mout_bus_pll_div2" , };"oscclk" , "mout_mfc_pll_div2" , };0 ,"mout_sclk_dsim0_a" , "mout_mfc_pll_div2" };"mout_sclk_decon_tv_vclk_b" ,"sclk_mphy_pll" , };"mout_sclk_decon_tv_vclk_a" ,"mout_mfc_pll_div2" , };"mout_sclk_dsim1_b" , "sclk_mphy_pll" , };"mout_sclk_dsim1_a" , "mout_mfc_pll_div2" ,};static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = {/* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */ "dout_mfc_pll" , "mout_mfc_pll" , 1 , 1 , 0 ),"dout_bus_pll" , "mout_bus_pll" , 1 , 1 , 0 ),"dout_mem1_pll" , "mout_mem1_pll" , 1 , 1 , 0 ),"dout_mem0_pll" , "mout_mem0_pll" , 1 , 1 , 0 ),static const struct samsung_mux_clock mif_mux_clks[] __initconst = {/* MUX_SEL_MIF0 */ "mout_mfc_pll_div2" , mout_mfc_pll_div2_p,28 , 1 ),"mout_bus_pll_div2" , mout_bus_pll_div2_p,24 , 1 ),"mout_mem1_pll_div2" , mout_mem1_pll_div2_p,20 , 1 ), length 7216 , 1 )," mout_mfc_pll_p, MUX_SEL_MIF0, 12 , 1 ),"mout_bus_pll" , mout_bus_pll_p, MUX_SEL_MIF0,8 , 1 ),"mout_mem1_pll" , mout_mem1_pll_p, MUX_SEL_MIF0,4 , 1 ),"mout_mem0_pll" , mout_mem0_pll_p, MUX_SEL_MIF0,0 , 1 ),/* MUX_SEL_MIF1 */ "mout_clk2x_phy_c" , mout_clk2x_phy_c_p,24 , 1 ),"mout_clk2x_phy_b" , mout_clk2x_phy_b_p,20 , 1 ),"mout_clk2x_phy_a" , mout_clk2x_phy_a_p,16 , 1 ),"mout_clkm_phy_c" , mout_clk2x_phy_c_p,12 , 1 ),"mout_clkm_phy_b" , mout_clkm_phy_b_p,8 , 1 ),"mout_clkm_phy_a" , mout_clk2x_phy_a_p 0 CLK_IGNORE_UNUSED,,4 , 1 ),/* MUX_SEL_MIF2 */ "mout_aclk_mifnm_200" ,8 , 1 ),"mout_aclk_mifnm_400" ,0 , 1 ),/* MUX_SEL_MIF3 */ "mout_aclk_disp_333_b" ,4 , 1 ),"mout_aclk_disp_333_a" ,0 , 1 ),/* MUX_SEL_MIF4 */ "mout_sclk_decon_vclk_c" ,24 , 1 ),"mout_sclk_decon_vclk_b" ,20 , 1 ),"mout_sclk_decon_vclk_a , )java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28 16 , 1 ),"mout_sclk_decon_eclk_c" ,"mout_sclk_decon_eclk_b" ,4 , 1 ),"mout_sclk_decon_eclk_a" ,0 , 1 ),/* MUX_SEL_MIF5 */ h 6424 , 1 ),"mout_sclk_decon_tv_eclk_b" ,20 , 1 ),"mout_sclk_decon_tv_eclk_a" ,16 , 1 ),"mout_sclk_dsd_c" , mout_sclk_dsd_c_p,"mout_sclk_dsd_b" , mout_sclk_dsd_b_p,4 , 1 ),", java.lang.StringIndexOutOfBoundsException: Index 63 out of bounds for length 63 0 , 1 ),/* MUX_SEL_MIF6 */ "mout_sclk_dsim0_c" , mout_sclk_dsim0_c_p,8 , 1 ),4 , 1 ),"mout_sclk_dsim0_a" , mout_sclk_decon_p,0 , 1 ),/* MUX_SEL_MIF7 */ "mout_sclk_decon_tv_vclk_c" ,24 , 1 ),"mout_sclk_decon_tv_vclk_b" ,20 , 1 ),"mout_sclk_decon_tv_vclk_a" ,16 , 1 ),"mout_sclk_dsim1_c" , mout_sclk_dsim1_c_p,0 ),"mout_sclk_dsim1_b" , mout_sclk_dsim1_b_p,4 , 1 ),"mout_sclk_dsim1_a" , mout_sclk_decon_p,0 , 1 ),const [ _initconst={/* DIV_MIF1 */ "div_sclk_hpm_mif" , "div_clk2x_phy" ,16 , 2 ),"div_aclk_drex1" , "div_clk2x_phy" , DIV_MIF1,12 , 2 ),2 , )java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 308 , 2 ),"div_clk2x_phy" , "mout_clk2x_phy_c" , DIV_MIF1,4 , 4 ),/* DIV_MIF2 */ "div_aclk_mif_266" , "mout_bus_pll_div2" ,20 , 3 )," GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0" java.lang.StringIndexOutOfBoundsException: Range [62, 60) out of bounds for length 6216 , 4 ),"div_aclk_mif_133" , "div_mif_pre" ,12 , 4 ),"div_aclk_mifnm_200" ,"mout_aclk_mifnm_200" , DIV_MIF2, 8 , 3 ),"div_aclk_mif_200" , "div_aclk_mif_400" ,4 , 2 ),"div_aclk_mif_400" , "mout_aclk_mifnm_400" ,0 , 3 ),/* DIV_MIF3 */ 42) out of bounds for length 4316 , 4 ),"div_aclk_disp_333" , "mout_aclk_disp_333_b" ,4 , 3 ),"div_aclk_cpif_200" , "mout_aclk_mifnm_200" ,0 , 3 ),/* DIV_MIF4 */ "div_sclk_dsim1" , "java.lang.StringIndexOutOfBoundsException: Range [0, 61) out of bounds for length 46 24 , 4 ),"div_sclk_decon_tv_vclk" ,"mout_sclk_decon_tv_vclk_c" , DIV_MIF4, 20 , 4 ),"div_sclk_dsim0" , "mout_sclk_dsim0_c" ,16 , 4 ),"div_sclk_dsd" , "mout_sclk_dsd_c" ,12 , 4 ),"div_sclk_decon_tv_eclk" ,"mout_sclk_decon_tv_eclk_c" , DIV_MIF4, 8 , 4 ),"div_sclk_decon_vclk" ,"mout_sclk_decon_vclk_c" , DIV_MIF4, 4 , 4 ),"div_sclk_decon_eclk" ,"mout_sclk_decon_eclk_c" , DIV_MIF4, 0 , 4 ),/* DIV_MIF5 */ "div_mif_pre" , "mout_bus_pll_div2" , DIV_MIF5,0 , 3 ),static const java.lang.StringIndexOutOfBoundsException: Range [37, 36) out of bounds for length 37/* ENABLE_ACLK_MIF0 */ "clk2k_phy1" , "java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 28 19 , CLK_IGNORE_UNUSED, 0 ),"clk2x_phy0" , "div_clk2x_phy" , ENABLE_ACLK_MIF0,18 , CLK_IGNORE_UNUSED, 0 ),"clkm_phy1" , "mout_clkm_phy_c" , ENABLE_ACLK_MIF0,17 , CLK_IGNORE_UNUSED, 0 ),"mout_clkm_phy_c" ENABLE_ACLK_MIF0java.lang.StringIndexOutOfBoundsException: Index 70 out of bounds for length 7016 , CLK_IGNORE_UNUSED, 0 ),"rclk_drex1" , "oscclk" , ENABLE_ACLK_MIF0,15 , CLK_IGNORE_UNUSED, 0 ),"rclk_drex0" , "oscclk" , ENABLE_ACLK_MIF0,14 , CLK_IGNORE_UNUSED, 0 ),"aclk_drex1_tz" , "div_aclk_drex1" ,13 , CLK_IGNORE_UNUSED, 0 ),"aclk_drex0_tz" , "div_aclk_drex0" ,12 , CLK_IGNORE_UNUSED, 0 ),"aclk_drex1_perev" , "div_aclk_drex1" ,11 , CLK_IGNORE_UNUSED, 0 ),"aclk_drex0_perev" , "div_aclk_drex0" ,10 , CLK_IGNORE_UNUSED, 0 ),"aclk_drex1_memif" , "div_aclk_drex1" ,0 ),"aclk_drex0_memif" , "div_aclk_drex0" ,8 , CLK_IGNORE_UNUSED, 0 ),"aclk_drex1_sch" , "div_aclk_drex1" ,7 , CLK_IGNORE_UNUSED, 0 ),"aclk_drex0_sch" , "div_aclk_drex0" ,6 , CLK_IGNORE_UNUSED, 0 ),"aclk_drex1_busif" , "div_aclk_drex1" ,5 , CLK_IGNORE_UNUSED, 0 ),"aclk_drex0_busif" , "div_aclk_drex0" ,4 , CLK_IGNORE_UNUSED, 0 ),"aclk_drex1_busif_rd" , "div_aclk_drex1" ,3 , CLK_IGNORE_UNUSED, 0 ),"aclk_drex0_busif_rd" , "div_aclk_drex0" ,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_drex1" , "div_aclk_drex1" ,2 , CLK_IGNORE_UNUSED, 0 ),1 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_ACLK_MIF1 */ "aclk_asyncaxis_mif_imem" ,"div_aclk_mif_200" , ENABLE_ACLK_MIF1, 28 ,0 ),"aclk_asyncaxis_noc_p_cci" ,"div_aclk_mif_200" , ENABLE_ACLK_MIF1,27 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_noc_p_cci" ,"div_aclk_mif_133" , ENABLE_ACLK_MIF1,26 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_cp1" ,"div_aclk_mifnm_200" , ENABLE_ACLK_MIF1,25 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_cp1" ,"div_aclk_drex1" , ENABLE_ACLK_MIF1,24 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_cp0" ,"div_aclk_mifnm_200" , ENABLE_ACLK_MIF1,23 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_cp0" ,"div_aclk_drex0" , ENABLE_ACLK_MIF1,22 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_drex1_3" ,"div_aclk_mif_133" , ENABLE_ACLK_MIF1,21 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_drex1_3" ,#efine 0 x020020 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_drex1_1" ,"div_aclk_mif_133" , ENABLE_ACLK_MIF1,19 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_drex1_1" ,"div_aclk_drex1" , ENABLE_ACLK_MIF1,18 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_drex1_0" ,"div_aclk_mif_133" , ENABLE_ACLK_MIF1,17 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_drex1_0" ,"div_aclk_drex1" , ENABLE_ACLK_MIF1,16 , CLK_IGNORE_UNUSED, 0 ),#define "div_aclk_mif_133" , ENABLE_ACLK_MIF1,15 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_drex0_3" ,"div_aclk_drex0" , ENABLE_ACLK_MIF1,14 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_drex0_1" ,"div_aclk_mif_133" , ENABLE_ACLK_MIF1,13 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_drex0_1" ,"div_aclk_drex0" , ENABLE_ACLK_MIF1,12 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_drex0_0" ,"div_aclk_mif_133" , ENABLE_ACLK_MIF1,11 , CLK_IGNORE_UNUSED, 0 #define ENABLE_IP_MFC1 0 x0b04"aclk_asyncaxim_drex0_0" ,"div_aclk_drex0" , ENABLE_ACLK_MIF1,10 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb2apb_mif2p" , "div_aclk_mif_133" ,9 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb2apb_mif1p" , "div_aclk_mif_133" ,8 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb2apb_mif0p" , "div_aclk_mif_133" ,7 , CLK_IGNORE_UNUSED, 0 ),"aclk_ixiu_cci" , "div_aclk_mif_400" ,6 , CLK_IGNORE_UNUSED, 0 ),"aclk_xiu_mifsfrx MUX_SEL_MFC, 5 , CLK_IGNORE_UNUSED, 0 ),"aclk_mifnp_133" , "div_aclk_mif_133" ,4 , CLK_IGNORE_UNUSED, 0 ),"aclk_mifnm_200" , "div_aclk_mifnm_200" ,3 , CLK_IGNORE_UNUSED, 0 ),"aclk_mifnd_133" , "div_aclk_mifnd_133" ,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_mifnd_400" , "div_aclk_mif_400" ,1 , CLK_IGNORE_UNUSED, 0 ),"aclk_cci" , "div_aclk_mif_400" , ENABLE_ACLK_MIF1,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_ACLK_MIF2 */ "aclk_mifnd_266" , "div_aclk_mif_266" ,20 , CLK_IGNORE_UNUSED, 0 ),"aclk_ppmu_drex1s3" , "div_aclk_drex1" ,17 , CLK_IGNORE_UNUSED, 0 ),"aclk_ppmu_drex1s1" , "div_aclk_drex1" ,16 , CLK_IGNORE_UNUSED, 0 ),"aclk_ppmu_drex1s0" , "div_aclk_drex1" ,15 , CLK_IGNORE_UNUSED, 0 ),"aclk_ppmu_drex0s3" , "div_aclk_drex0" ,14 , CLK_IGNORE_UNUSED, 0 ),"aclk_ppmu_drex0s1" , "div_aclk_drex0" ,13 , CLK_IGNORE_UNUSED, 0 ),"aclk_ppmu_drex0s0" , "div_aclk_drex0" ,12 , CLK_IGNORE_UNUSED, 0 ),"aclk_axids_cci_mifsfrx" ,"div_aclk_mif_200" , ENABLE_ACLK_MIF2, 7 ,0 ),"aclk_axisyncdns_cci" ,"div_aclk_mif_400" , ENABLE_ACLK_MIF2,5 , CLK_IGNORE_UNUSED, 0 ),"aclk_axisyncdn_cci" , "div_aclk_mif_400" ,4 , CLK_IGNORE_UNUSED, 0 ),"aclk_axisyncdn_noc_d" ,"div_aclk_mif_200" , ENABLE_ACLK_MIF2,3 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncapbs_mif_cssys" ,"div_aclk_mifnd_133" , ENABLE_ACLK_MIF2, PNAME) "," aclk_mfc_400" ; /* ENABLE_ACLK_MIF3 */ "aclk_bus2_400" , "div_aclk_bus2_400" ,4 ,0 ),"aclk_disp_333" , "div_aclk_disp_333" ,1 ,0 ),"aclk_cpif_200" , "div_aclk_cpif_200" ,0 ,0 ),/* ENABLE_PCLK_MIF */ "" "iv_aclk_drex1" ,29 , CLK_IGNORE_UNUSED, 0 ),"pclk_ppmu_drex1s1" , "div_aclk_drex1" ,28 , CLK_IGNORE_UNUSED, 0 ),0 , 0 ),27 , CLK_IGNORE_UNUSED, 0 ),"pclk_ppmu_drex0s3" , "div_aclk_drex0" ,26 , CLK_IGNORE_UNUSED, 0 ),"pclk_ppmu_drex0s1" , "div_aclk_drex0" ,25 , CLK_IGNORE_UNUSED, 0 ),"pclk_ppmu_drex0s0" , "div_aclk_drex0" ,24 , CLK_IGNORE_UNUSED, 0 ),"pclk_asyncaxi_noc_p_cci" ,"" , ENABLE_PCLK_MIF, 21 ,,0 ),"pclk_asyncaxi_cp1" , "div_aclk_mif_133" ,19 , 0 , 0 ),"pclk_asyncaxi_cp0" , " DIV(LK_DIV_PCLK_MFC, " div_pclk_mfc", " mout_aclk_mfc_400_user", 18 , 0 , 0 ),"pclk_asyncaxi_drex1_3" ,"div_aclk_mif_133" , ENABLE_PCLK_MIF, 17 , 0 , 0 ),"pclk_asyncaxi_drex1_1 "div_aclk_mif_133" , ENABLE_PCLK_MIF, 16 , 0 , 0 ),0" ,15 ,0), "pclk_asyncaxi_drex0_3" ,"div_aclk_mif_133" , ENABLE_PCLK_MIF, 14 , 0 , 0 ),"pclk_asyncaxi_drex0_1" ,"div_aclk_mif_133" , ENABLE_PCLK_MIF, 13 , 0 , 0 ),"pclk_asyncaxi_drex0_0" ,"div_aclk_mif_133" , ENABLE_PCLK_MIF, 12 , 0 , 0 ),"pclk_mifsrvnd_133" , "div_aclk_mif_133" ,11 , 0 , 0 ),"pclk_pmu_mif" , "div_aclk_mif_133" ,10 , CLK_IGNORE_UNUSED, 0 ),"pclk_sysreg_mif" , "div_aclk_mif_133" ,9 , CLK_IGNORE_UNUSED, 0 ),5 ,0 0 )8 , CLK_IGNORE_UNUSED, 0 ),"pclk_abb" , "div_aclk_mif_133" ,7 , 0 , 0 ),"pclk_pmu_apbif" , "div_aclk_mif_133" ,6 , CLK_IGNORE_UNUSED, 0 ),"pclk_ddr_phy1" , "div_aclk_mif_133" ,5 , 0 , 0 ),"pclk_drex1" , "div_aclk_mif_133" ,3 , CLK_IGNORE_UNUSED, 0 ),"pclk_ddr_phy0" , "div_aclk_mif_133" ,2 , 0 , 0 ),"pclk_drex0" , "div_aclk_mif_133" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */ "pclk_drex0_tz" , "div_aclk_mif_133" ,0 ),"pclk_drex1_tz" , "div_aclk_mif_133" ,0 ,0 ),/* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */ "pclk_monotonic_cnt" , "div_aclk_mif_133" ,0 , 0 , 0 ),/* ENABLE_PCLK_MIF_SECURE_RTC */ "pclk_rtc" , "div_aclk_mif_133" ,0 , 0 , 0 ),/* ENABLE_SCLK_MIF */ "sclk_dsim1_disp" , "div_sclk_dsim1" ,15 , CLK_IGNORE_UNUSED, 0 ),"sclk_decon_tv_vclk_disp" ,"div_sclk_decon_tv_vclk" , ENABLE_SCLK_MIF,14 , CLK_IGNORE_UNUSED, 0 ),"sclk_dsim0_disp" , "div_sclk_dsim0" ,9 , CLK_IGNORE_UNUSED, 0 ),"sclk_dsd_disp" , "div_sclk_dsd" ,0 )java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45"sclk_decon_tv_eclk_disp" ,"div_sclk_decon_tv_eclk" , ENABLE_SCLK_MIF,7 , CLK_IGNORE_UNUSED, 0 ),"sclk_decon_vclk_disp" ,"div_sclk_decon_vclk" , ENABLE_SCLK_MIF,6 , CLK_IGNORE_UNUSED, 0 ),"sclk_decon_eclk_disp" ,"java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 22 5 , CLK_IGNORE_UNUSED, 0 ),"sclk_hpm_mif" , "div_sclk_hpm_mif" ,4 ,0 ),"sclk_mfc_pll" , "mout_mfc_pll_div2" ,3 , CLK_IGNORE_UNUSED, 0 ),"sclk_bus_pll" , "mout_bus_pll_div2" ,2 , CLK_IGNORE_UNUSED, 0 ),"sclk_bus_pll_apollo" , "sclk_bus_pll" ,1 , CLK_IGNORE_UNUSED, 0 ),"sclk_bus_pll_atlas GATE(CLK_PCLK_PMU_MFC, pclk_pmu_mfc" ,"" java.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 550 , CLK_IGNORE_UNUSED, 0 ),static const struct samsung_cmu_info mif_cmu_info __initconst = {gth 27static void __init exynos5433_cmu_mif_init(struct device_node *np)"samsung,exynos5433-cmu-mif" ,/** Register offset definitions for #define DIV_PERIC 0 x0600#define DIV_STAT_PERIC 0 x0700#define ENABLE_ACLK_PERIC 0 x0800#define ENABLE_PCLK_PERIC0 0 x0900#define ENABLE_PCLK_PERIC1 0 x0904#define ENABLE_SCLK_PERIC 0 x0A00#define ENABLE_IP_PERIC0 0 x0B00#define ENABLE_IP_PERIC1 0 x0B04#define ENABLE_IP_PERIC2 0 x0B08static const unsigned long peric_clk_regs[] __initconst = {nds for length 65/* pclk: sci, pmu, sysreg, gpio_{finger, ese, touch, nfc}, uart2-0 */ gate_clks =,0 xe00ff000 },/* sclk: uart2-0 */ 0 x7 },static const struct samsung_div_clock peric_div_clks[] __initconst = {/* DIV_PERIC */ "div_sclk_sci" , "oscclk" , DIV_PERIC, 4 , 4 ),"div_sclk_sc_in" , "oscclk" , DIV_PERIC, 0 , 4 ),static const struct samsung_gate_clock peric_gate_clks[] __initconst = {/* ENABLE_ACLK_PERIC */ "aclk_ahb2apb_peric2p" , "aclk_peric_66" ,3 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb2apb_peric1p" , "aclk_peric_66" ,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb2apb_peric0p" , "aclk_peric_66" ,1 , CLK_IGNORE_UNUSED, 0 ),"aclk_pericnp_66" , "aclk_peric_66" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_PERIC0 */ "pclk_sci" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,31 , CLK_SET_RATE_PARENT, 0 ),"pclk_gpio_finger" , "aclk_peric_66" ,30 , CLK_IGNORE_UNUSED, 0 ),"pclk_gpio_ese" , "aclk_peric_66" ,29 , CLK_IGNORE_UNUSED, 0 ),"," aclk_peric_66ENABLE_PCLK_PERIC0,28 , CLK_SET_RATE_PARENT, 0 ),"pclk_spdif" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,26 , CLK_SET_RATE_PARENT, 0 ),"pclk_pcm1" , "aclk_peric_66" , java.lang.StringIndexOutOfBoundsException: Index 61 out of bounds for length 3125 , CLK_SET_RATE_PARENT, 0 ),"pclk_i2s" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,24 , CLK_SET_RATE_PARENT, 0 ),"pclk_spi2" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,23 , CLK_SET_RATE_PARENT, 0 ),"pclk_spi1" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,22 , CLK_SET_RATE_PARENT, 0 ),"pclk_spi0" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,21 , CLK_SET_RATE_PARENT, 0 ),h 7220 , CLK_SET_RATE_PARENT, 0 ),"pclk_gpio_touch" , "aclk_peric_66" ,19 , CLK_IGNORE_UNUSED, 0 ),"pclk_gpio_nfc" , "aclk_peric_66" ,18 , CLK_IGNORE_UNUSED, 0 ),"pclk_gpio_peric" , "aclk_peric_66" ,17 , CLK_IGNORE_UNUSED, 0 ),"pclk_pmu_peric" , "aclk_peric_66" ,16 , CLK_SET_RATE_PARENT, 0 ),"pclk_sysreg_peric" , "aclk_peric_66" ,15 ,0 ),"pclk_uart2" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,14 , CLK_SET_RATE_PARENT, 0 ),"pclk_uart1" , "aclk_peric_66" , java.lang.StringIndexOutOfBoundsException: Index 61 out of bounds for length 1713 , CLK_SET_RATE_PARENT, 0 ) DIV_HEVC,"pclk_uart0" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,12 , CLK_SET_RATE_PARENT, 0 ),ENABLE_ACLK_HEVC,"pclk_hsi2c3" , "aclk_peric_66" ,"pclk_hsi2c2" , "aclk_peric_66" ,10 , CLK_SET_RATE_PARENT, 0 ),"pclk_hsi2c1" , "aclk_peric_66" ,"pclk_hsi2c0" , "aclk_peric_66" ,8 , CLK_SET_RATE_PARENT, 0 ),"pclk_i2c7" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,7 , CLK_SET_RATE_PARENT, 0 ),"pclk_i2c6" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,6 , CLK_SET_RATE_PARENT, 0 ),"pclk_i2c5" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,5 , CLK_SET_RATE_PARENT, 0 ),"pclk_i2c4" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,4 , CLK_SET_RATE_PARENT, 0 ),"pclk_i2c3" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,3 , CLK_SET_RATE_PARENT, 0 ),"pclk_i2c2" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,2 , CLK_SET_RATE_PARENT, 0 ),"pclk_i2c1" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,1 , CLK_SET_RATE_PARENT, 0 ),"pclk_i2c0" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,0 , CLK_SET_RATE_PARENT, 0 ),/* ENABLE_PCLK_PERIC1 */ "pclk_spi4" , "aclk_peric_66" , ENABLE_PCLK_PERIC1,9 , CLK_SET_RATE_PARENT, 0 ),"pclk_spi3" , "aclk_peric_66" , ENABLE_PCLK_PERIC1,8 , CLK_SET_RATE_PARENT, 0 ),"pclk_hsi2c11" , "aclk_peric_66" ,7 , CLK_SET_RATE_PARENT, 0 ),"pclk_hsi2c10" , "aclk_peric_66" ,6 , CLK_SET_RATE_PARENT, 0 ),"pclk_hsi2c9" , "aclk_peric_66" ,5 , CLK_SET_RATE_PARENT, 0 ),"pclk_hsi2c8" , "aclk_peric_66" ,4 , CLK_SET_RATE_PARENT, 0 ),"pclk_hsi2c7" , "aclk_peric_66" ,3 , CLK_SET_RATE_PARENT, 0 ),"pclk_hsi2c6" , "aclk_peric_66" ,2 , CLK_SET_RATE_PARENT, 0 ),"pclk_hsi2c5" , "aclk_peric_66" ,1 , CLK_SET_RATE_PARENT, 0 ),"pclk_hsi2c4" , "aclk_peric_66" ,0 , CLK_SET_RATE_PARENT, 0 )java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50/* ENABLE_SCLK_PERIC */ "sclk_ioclk_spi4" , "ioclk_spi4_clk_in" ,21 , CLK_SET_RATE_PARENT, 0 ),"sclk_ioclk_spi3" , "ioclk_spi3_clk_in" ,20 , CLK_SET_RATE_PARENT, 0 ),"sclk_spi4" , "sclk_spi4_peric" , ENABLE_SCLK_PERIC,"sclk_spi3" , "sclk_spi3_peric" , ENABLE_SCLK_PERIC,18 , CLK_SET_RATE_PARENT, 0 ),"sclk_sci" , "div_sclk_sci" , ENABLE_SCLK_PERIC,17 , 0 , 0 ),"sclk_sc_in" , "div_sclk_sc_in" , ENABLE_SCLK_PERIC,16 , 0 , 0 ),"sclk_pwm" , "oscclk" , ENABLE_SCLK_PERIC, 15 , 0 , 0 CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0," " "sclk_ioclk_spi2" , "ioclk_spi2_clk_in" ,13 , CLK_SET_RATE_PARENT, 0 ),"sclk_ioclk_spi1" , "ioclk_spi1_clk_in" ,12 , CLK_SET_RATE_PARENT, 0 ),"sclk_ioclk_spi0" , "ioclk_spi0_clk_in" ,11 , CLK_SET_RATE_PARENT, 0 ),"sclk_ioclk_i2s1_bclk" ,",ENABLE_SCLK_PERIC,10java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47 0 ),"sclk_spdif" , "sclk_spdif_peric" ,8 , CLK_SET_RATE_PARENT, 0 ),"sclk_pcm1" , "sclk_pcm1_peric" ,7 , CLK_SET_RATE_PARENT, 0 ),"sclk_i2s1" , "sclk_i2s1_peric" ,6 ,0 ),"sclk_spi2" , "sclk_spi2_peric" , ENABLE_SCLK_PERIC,5 , CLK_SET_RATE_PARENT, 0 ),"sclk_spi1" , "sclk_spi1_peric" , ENABLE_SCLK_PERIC,4 , CLK_SET_RATE_PARENT, 0 ),"sclk_spi0" , "sclk_spi0_peric" , ENABLE_SCLK_PERIC,3 , CLK_SET_RATE_PARENT, 0 ),"java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 0 2 ,0 ),"sclk_uart1" , "sclk_uart1_peric" ,1 ,0 ),"sclk_uart0" , "sclk_uart0_peric" ,0 ,0 ),static const struct samsung_cmu_info peric_cmu_info __initconst = {static void __init exynos5433_cmu_peric_init(struct device_node *np)"samsung,exynos5433-cmu-peric" ,/* * Register offset definitions for CMU_PERIS #define ENABLE_ACLK_PERIS 0 x0800#define ENABLE_PCLK_PERIS 0 0900#define ENABLE_PCLK_PERIS_SECURE_TZPC 0 x0904#define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0 x0908#define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0 x090c0 x0910#define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0 x0914#define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0 x0918#define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0 x091c#define ENABLE_SCLK_PERIS 0 x0a00#define ENABLE_SCLK_PERIS_SECURE_SECKEY 0 x0a04#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0 x0a08#define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0 x0a0c#define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0 x0a10#define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0 x0a14#define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0 x0a18#define ENABLE_IP_PERIS0 0 x0b00#define ENABLE_IP_PERIS1 0 x0b04#define ENABLE_IP_PERIS_SECURE_TZPC 0 x0b08#define ENABLE_IP_PERIS_SECURE_SECKEY 0 x0b0c#define ENABLE_IP_PERIS_SECURE_CHIPID 0 x0b10#define ENABLE_IP_PERIS_SECURE_TOPRTC 0 x0b14#define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0 x0b18#define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0 " java.lang.StringIndexOutOfBoundsException: Index 64 out of bounds for length 64 #define ENABLE_IP_PERIS_SECURE_OTP_CON 0 x0b20static const unsigned long peris_clk_regs[] __initconst = {static const struct samsung_gate_clock peris_gate_clks[] __initconst = {/* ENABLE_ACLK_PERIS */ "aclk_ahb2apb_peris1p" , "aclk_peris_66" ,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb2apb_peris0p" , "aclk_peris_66" ,1 , CLK_IGNORE_UNUSED, 0 ),"aclk_perisnp_66" , "aclk_peris_66" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_PERIS */ "pclk_hpm_apbif" , "aclk_peris_66" ,30 , CLK_IGNORE_UNUSED, 0 ),"pclk_tmu1_apbif" , "aclk_peris_66" ,24 , CLK_IGNORE_UNUSED, 0 ),"pclk_tmu0_apbif" , "aclk_peris_66" ,23 , CLK_IGNORE_UNUSED, 0 ),"pclk_pmu_peris" , "aclk_peris_66" ,22 ,CLK_IGNORE_UNUSED, 0 ),"pclk_sysreg_peris" , "aclk_peris_66" ,21 , CLK_IGNORE_UNUSED, 0 ),"pclk_cmu_top_apbif" , "aclk_peris_66" ,20 , CLK_IGNORE_UNUSED, 0 ),#efine MUX_STAT_ISP 0 x040017 , CLK_IGNORE_UNUSED, 0 ),"" "aclk_peris_66, 16 , CLK_IGNORE_UNUSED, 0 ),"pclk_mct" , "java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 29 15 , CLK_IGNORE_UNUSED, 0 ),"pclk_hdmi_cec" , "aclk_peris_66" ,14 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_PERIS_SECURE_TZPC */ "pclk_tzpc12" , "aclk_peris_66" ,12 , CLK_IGNORE_UNUSED, 0 ),"pclk_tzpc11" , "aclk_peris_66" ,11 , CLK_IGNORE_UNUSED, 0 ),"pclk_tzpc10" , "aclk_peris_66" ,10 , CLK_IGNORE_UNUSED, 0 ),"pclk_tzpc9" , "aclk_peris_66" ,9 , CLK_IGNORE_UNUSED, 0 ),"pclk_tzpc8" , "aclk_peris_66" ,# ENABLE_IP_ISP2 0 0 b08"pclk_tzpc7" , "aclk_peris_66" ,th 59"pclk_tzpc6" , "aclk_peris_66" ,6 , CLK_IGNORE_UNUSED, 0 ),"pclk_tzpc5" , "aclk_peris_66" ,5 , CLK_IGNORE_UNUSED, 0 ),"pclk_tzpc4" , "aclk_peris_66" ,4 , CLK_IGNORE_UNUSED, 0 ),"pclk_tzpc3" , "aclk_peris_66" ,3 , CLK_IGNORE_UNUSED, 0 ),"pclk_tzpc2" , "aclk_peris_66" ,2 , CLK_IGNORE_UNUSED, 0 ),1 , CLK_IGNORE_UNUSED, 0 ),"pclk_tzpc0" , "aclk_peris_66" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */ "pclk_seckey_apbif" , "aclk_peris_66" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */ "pclk_chipid_apbif" , "aclk_peris_66" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_PERIS_SECURE_TOPRTC */ "pclk_toprtc" , "aclk_peris_66" ,0 , 0 , 0 ),/* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */ "pclk_custom_efuse_apbif" ,0 , 0 , 0 ),/* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */ "pclk_antirbk_cnt_apbif" ,0 0 0 )/* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */ "pclk_otp_con_apbif" ,"aclk_peris_66" ,0 , 0 , 0 ),/* ENABLE_SCLK_PERIS */ "sclk_asv_tb" , "oscclk_efuse_common" ,10 , 0 , 0 ),"," scclk_efuse_common,4 , 0 , 0 ),"sclk_tmu0" , "oscclk_efuse_common" ,0 ,/* ENABLE_SCLK_PERIS_SECURE_SECKEY */ "sclk_seckey" , "oscclk_efuse_common" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_SCLK_PERIS_SECURE_CHIPID */ "sclk_chipid" , "oscclk_efuse_common" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_SCLK_PERIS_SECURE_TOPRTC */ "sclk_toprtc" , "oscclk_efuse_common" ,0 , 0 , 0 ),/* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */ "sclk_custom_efuse" , "oscclk_efuse_common" ,0 , 0 , 0 ),/* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */ "sclk_antirbk_cnt" , "oscclk_efuse_common" ,0 , 0 , 0 ),/* ENABLE_SCLK_PERIS_SECURE_OTP_CON */ "sclk_otp_con" , "oscclk_efuse_common" ,static const struct samsung_cmu_info peris_cmu_info __initconst = {static void __init exynos5433_cmu_peris_init(struct device_node *np)"samsung,exynos5433-cmu-peris" ,/* * Register offset definitions for CMU_FSYS #define MUX_SEL_FSYS0 0 x0200#efine 0 x0204#define MUX_SEL_FSYS2 0 x0208#define MUX_SEL_FSYS3 0 x020c#define MUX_SEL_FSYS4 0 x0210#efine MUX_ENABLE_FSYS0 0 x0300#define MUX_ENABLE_FSYS1 0 x0304#define MUX_ENABLE_FSYS2 0 x0308#define MUX_ENABLE_FSYS3 ENABLE_ACLK_ISP0, 2 ,0 0 ,#define MUX_ENABLE_FSYS4 0 x0310#define MUX_STAT_FSYS0 0 x0400#define MUX_STAT_FSYS1 0 x0404#define MUX_STAT_FSYS2 0 x0408#define MUX_STAT_FSYS3 0 x040c#define MUX_STAT_FSYS4 0 x0410#define MUX_IGNORE_FSYS2 0 x0508#define MUX_IGNORE_FSYS3 0 x050c#define ENABLE_ACLK_FSYS0 0 x0800#define ENABLE_ACLK_FSYS1 0 x0804#define ENABLE_PCLK_FSYS 0 x0900#define ENABLE_SCLK_FSYS 0 x0a00#define ENABLE_IP_FSYS0 0 x0b00#define ENABLE_IP_FSYS1 0 x0b04/* list of all parent clock list */ "oscclk" , "sclk_ufs_mphy" , };"oscclk" , "aclk_fsys_200" , };"oscclk" , "sclk_pcie_100_fsys" ,};"oscclk" , "sclk_ufsunipro_fsys" ,};"oscclk" , "sclk_mmc2_fsys" , };"oscclk" , "sclk_mmc0_fsys" , };"oscclk" , "sclk_usbhost30_fsys" ,};"oscclk" , "sclk_usbdrd30_fsys" , };"oscclk" , "phyclk_usbhost30_uhost30_pipe_pclk_phy" , };"oscclk" , "phyclk_usbhost30_uhost30_phyclock_phy" , };"oscclk" , "phyclk_usbhost20_phy_hsic1_phy" , };"oscclk" , "phyclk_usbhost20_phy_clk48mohci_phy" , };"oscclk" , phyclk_usbhost20_phy_phyclock_phy", }; "oscclk" , "phyclk_usbhost20_phy_freeclk_phy" , };or length 55"oscclk" , "phyclk_usbdrd30_udrd30_pipe_pclk_phy" , };"oscclk" , "phyclk_usbdrd30_udrd30_phyclock_phy" , };"oscclk" , "phyclk_ufs_rx1_symbol_phy" , };"oscclk" , "phyclk_ufs_rx0_symbol_phy" , };"oscclk" , "phyclk_ufs_tx1_symbol_phy" , };"oscclk" , "phyclk_ufs_tx0_symbol_phy" , };"oscclk" , "phyclk_lli_mphy_to_ufs_phy" , };"mout_sclk_ufs_mphy_user" ,"mout_phyclk_lli_mphy_to_ufs_user" , };static const unsigned long fsys_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump fsys_suspend_regs[] = {0 },0 },0 },0 },0 },static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = {"phyclk_usbdrd30_udrd30_phyclock_phy" , NULL,0 , 60000000 ),"phyclk_usbdrd30_udrd30_pipe_pclk_phy" , NULL,0 , 125000000 ),/* PHY clocks from USBHOST30_PHY */ "phyclk_usbhost30_uhost30_phyclock_phy" , NULL,0 , 60000000 ),"phyclk_usbhost30_uhost30_pipe_pclk_phy" , NULL,0 , 125000000 ),/* PHY clocks from USBHOST20_PHY */ "phyclk_usbhost20_phy_freeclk_phy" , NULL, 0 , 60000000 ),"phyclk_usbhost20_phy_phyclock_phy" , NULL, 0 , 60000000 ),"phyclk_usbhost20_phy_clk48mohci_phy" , (java.lang.StringIndexOutOfBoundsException: Range [46, 43) out of bounds for length 710 , 48000000 ),"phyclk_usbhost20_phy_hsic1_phy" , NULL, 0 ,60000000 ),/* PHY clocks from UFS_PHY */ "phyclk_ufs_tx0_symbol_phy" ,0 , 300000000 ),"phyclk_ufs_rx0_symbol_phy" ,0 , 300000000 ),"phyclk_ufs_tx1_symbol_phy" ,0 , 300000000 ),"phyclk_ufs_rx1_symbol_phy" ,0 , 300000000 ),/* PHY clocks from LLI_PHY */ "phyclk_lli_mphy_to_ufs_phy" ,0 , 26000000 ),static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {/* MUX_SEL_FSYS0 */ "mout_sclk_ufs_mphy_user" ,4 , 1 )," 0 , 1 ),/* MUX_SEL_FSYS1 */ h 6028 , 1 ),24 , 1 ),"mout_sclk_mmc2_user" ,20 , 1 ),"mout_sclk_mmc1_user" ,16 , 1 ),"mout_sclk_mmc0_user" ,12 , 1 ),ength 464 , 1 ),"mout_sclk_usbdrd30_user" ,0 , 1 ),/* MUX_SEL_FSYS2 */ "mout_phyclk_usbhost30_uhost30_pipe_pclk_user" ,"aclk_smmu_isp" , "mout_aclk_isp_400_user" ,28 , 1 ),"mout_phyclk_usbhost30_uhost30_phyclock_user" ,24 , 1 ),"mout_phyclk_usbhost20_phy_hsic1" ,20 , 1 ),"mout_phyclk_usbhost20_phy_clk48mohci_user" ,16 , 1 ),"clk_bts_dis1" ,"" java.lang.StringIndexOutOfBoundsException: Index 67 out of bounds for length 67"mout_phyclk_usbhost20_phy_phyclock_user" ,12 , 1 ),"mout_phyclk_usbhost20_phy_freeclk_user" ,8 , 1 ),"mout_phyclk_usbdrd30_udrd30_pipe_pclk_user" 1 ,"mout_phyclk_usbdrd30_udrd30_phyclock_user" ,0 , 1 ),/* MUX_SEL_FSYS3 */ "mout_phyclk_ufs_rx1_symbol_user" ,16 , 1 ),"mout_phyclk_ufs_rx0_symbol_user" ,12 , 1 ),"java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37 8 , 1 ),"mout_phyclk_ufs_tx0_symbol_user" ,4 , 1 ),"mout_phyclk_lli_mphy_to_ufs_user" ,0 , 1 ),/* MUX_SEL_FSYS4 */ "mout_sclk_mphy" , mout_sclk_mphy_p,0 , 1 ),static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {/* ENABLE_ACLK_FSYS0 */ length 4613 , CLK_IGNORE_UNUSED, 0 ),"aclk_pdma1" , "mout_aclk_fsys_200_user" ,11 , CLK_IGNORE_UNUSED, 0 ),"aclk_tsi" , "mout_aclk_fsys_200_user" ,10 , CLK_IGNORE_UNUSED, 0 ),"aclk_mmc2" , "mout_aclk_fsys_200_user" ,8 , CLK_IGNORE_UNUSED, 0 ),"aclk_mmc1" , "mout_aclk_fsys_200_user" ,7 , CLK_IGNORE_UNUSED, 0 ),"aclk_mmc0" , "mout_aclk_fsys_200_user" ,6 , CLK_IGNORE_UNUSED, 0 ),"aclk_ufs" , "mout_aclk_fsys_200_user" ,5 , CLK_IGNORE_UNUSED, 0 ),"aclk_usbhost20" , "mout_aclk_fsys_200_user" ,3 , CLK_IGNORE_UNUSED, 0 ),"aclk_usbhost30" , "mout_aclk_fsys_200_user" ,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_usbdrd30" , "mout_aclk_fsys_200_user" ,1 , CLK_IGNORE_UNUSED, 0 ),"aclk_pdma0" , "mout_aclk_fsys_200_user" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_ACLK_FSYS1 */ "aclk_xiu_fsyspx" , "mout_aclk_fsys_200_user" ,27 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb_usblinkh1" ,"mout_aclk_fsys_200_user" , ENABLE_ACLK_FSYS1,26 , CLK_IGNORE_UNUSED, 0 ),"aclk_smmu_pdma1" , "mout_aclk_fsys_200_user" ,25 , CLK_IGNORE_UNUSED, 0 ),"aclk_bts_pcie ,java.lang.StringIndexOutOfBoundsException: Range [44, 41) out of bounds for length 46 24 , CLK_IGNORE_UNUSED, 0 ),"aclk_axius_pdma1" ,"mout_aclk_fsys_200_user" , ENABLE_ACLK_FSYS1,22 , CLK_IGNORE_UNUSED, 0 ),"aclk_smmu_pdma0" , "java.lang.StringIndexOutOfBoundsException: Index 62 out of bounds for length 45 of bounds for length 61"," ", 14 , CLK_IGNORE_UNUSED, 0 ),"aclk_bts_usbhost30" ,"mout_aclk_fsys_200_user" , ENABLE_ACLK_FSYS1,13 , 0 , 0 ),"aclk_bts_usbdrd30" ,"mout_aclk_fsys_200_user" , ENABLE_ACLK_FSYS1,12 , 0 , 0 ),"aclk_axius_pdma0" ,"mout_aclk_fsys_200_user" , ENABLE_ACLK_FSYS1,11 , CLK_IGNORE_UNUSED, 0 ),"aclk_axius_usbhs" ,"mout_aclk_fsys_200_user" , ENABLE_ACLK_FSYS1,10 , CLK_IGNORE_UNUSED, 0 ),"aclk_axius_fsyssx" ,9 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb2apb_fsysp" ,"mout_aclk_fsys_200_user" , ENABLE_ACLK_FSYS1,8 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb2axi_usbhs" ,"mout_aclk_fsys_200_user" , ENABLE_ACLK_FSYS1,7 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb_usblinkh0" ,"mout_aclk_fsys_200_user" , ENABLE_ACLK_FSYS1,6 , CLK_IGNORE_UNUSED, 0 ),"clk_ahb_usbhs" "out_aclk_fsys_200_user" ,5 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb_fsysh" , "mout_aclk_fsys_200_user" ,4 , CLK_IGNORE_UNUSED, 0 ),"aclk_xiu_fsysx" , "mout_aclk_fsys_200_user" ,3 , CLK_IGNORE_UNUSED, 0 ),"aclk_xiu_fsyssx" , "mout_aclk_fsys_200_user" ,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_fsysnp_200" , "mout_aclk_fsys_200_user" ,1 , CLK_IGNORE_UNUSED, 0 ),"aclk_fsysnd_200" , "mout_aclk_fsys_200_user" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_FSYS */ "pclk_pcie_ctrl" , "mout_aclk_fsys_200_user" ,17 , CLK_IGNORE_UNUSED, 0 java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 28"pclk_smmu_pdma1" , "mout_aclk_fsys_200_user" ,16 , CLK_IGNORE_UNUSED, 0 yncm_dis", "pclk_pcie_phy" , "mout_aclk_fsys_200_user" ,14 , CLK_IGNORE_UNUSED, 0 ),"pclk_bts_pcie" , "mout_aclk_fsys_200_user" ,13 , CLK_IGNORE_UNUSED, 0 ),"pclk_smmu_pdma0" , "mout_aclk_fsys_200_user" ,8 , CLK_IGNORE_UNUSED, 0 ),"pclk_bts_ufs" "mout_aclk_fsys_200_user" ,5 , 0 , 0 ),"pclk_bts_usbhost30" ,"mout_aclk_fsys_200_user" , ENABLE_PCLK_FSYS, 4 , 0 , 0 ),"pclk_bts_usbdrd30" ,"mout_aclk_fsys_200_user" , ENABLE_PCLK_FSYS, 3 , 0 , 0 ),"pclk_gpio_fsys" , "mout_aclk_fsys_200_user" ,2 , CLK_IGNORE_UNUSED, 0 ),"pclk_pmu_fsys" , "mout_aclk_fsys_200_user" ,1 , CLK_IGNORE_UNUSED, 0 ),"pclk_sysreg_fsys" ,"mout_aclk_fsys_200_user" , ENABLE_PCLK_FSYS,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_SCLK_FSYS */ "sclk_pcie_100" , "mout_sclk_pcie_100_user" ,21 , 0 , 0 ),"phyclk_usbhost30_uhost30_pipe_pclk" ,"mout_phyclk_usbhost30_uhost30_pipe_pclk_user" ,18 , 0 , 0 ),"phyclk_usbhost30_uhost30_phyclock" ,"mout_phyclk_usbhost30_uhost30_phyclock_user" ,17 , 0 , 0 ),"phyclk_ufs_rx1_symbol" ,"mout_phyclk_ufs_rx1_symbol_user" , ENABLE_SCLK_FSYS,16 , 0 , 0 ),"phyclk_ufs_rx0_symbol" ,"mout_phyclk_ufs_rx0_symbol_user" , ENABLE_SCLK_FSYS,15 , 0 , 0 ),"phyclk_ufs_tx1_symbol" ,"mout_phyclk_ufs_tx1_symbol_user" , ENABLE_SCLK_FSYS,14 , 0 , 0 ),"phyclk_ufs_tx0_symbol" ,"mout_phyclk_ufs_tx0_symbol_user" , ENABLE_SCLK_FSYS,13 , 0 , 0 ),"phyclk_usbhost20_phy_hsic1" ,"mout_phyclk_usbhost20_phy_hsic1" , ENABLE_SCLK_FSYS,12 , 0 , 0 ),"phyclk_usbhost20_phy_clk48mohci" ,"mout_phyclk_usbhost20_phy_clk48mohci_user" ,11 , 0 , 0 ),"phyclk_usbhost20_phy_phyclock" ,"mout_phyclk_usbhost20_phy_phyclock_user" ,10 , 0 , 0 ),"phyclk_usbhost20_phy_freeclk" ,"mout_phyclk_usbhost20_phy_freeclk_user" ,9 , 0 , 0 ),Register for "phyclk_usbdrd30_udrd30_pipe_pclk" ,"mout_phyclk_usbdrd30_udrd30_pipe_pclk_user" ,8 ,0 ,0 )java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30"phyclk_usbdrd30_udrd30_phyclock" ,"mout_phyclk_usbdrd30_udrd30_phyclock_user" ,7 , 0 , 0 ),6 , 0 , 0 ),"sclk_ufsunipro" , "mout_sclk_ufsunipro_user" ,5 , 0 , 0 ),"sclk_mmc2" , "mout_sclk_mmc2_user" ,4 , CLK_SET_RATE_PARENT, 0 ),"sclk_mmc1" , "mout_sclk_mmc1_user" ,3 , CLK_SET_RATE_PARENT, 0 ),"sclk_mmc0" , "mout_sclk_mmc0_user" ,2 , CLK_SET_RATE_PARENT, 0 ),"sclk_usbhost30" , "mout_sclk_usbhost30_user" ,1 , 0 , 0 ),"sclk_usbdrd30" , "mout_sclk_usbdrd30_user" ,/* ENABLE_IP_FSYS0 */ "pcie" , "sclk_pcie_100" , ENABLE_IP_FSYS0, 17 , 0 , 0 ),"pdma1" , "aclk_pdma1" , ENABLE_IP_FSYS0, 15 , 0 , 0 ),"pdma0" , "aclk_pdma0" , ENABLE_IP_FSYS0, 0 , 0 , 0 ),static const struct samsung_cmu_info fsys_cmu_info __initconst = {# 0 java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31"aclk_fsys_200" ,/* * Register offset definitions for CMU_G2D #define MUX_SEL_G2D0 0 x0200#define MUX_SEL_ENABLE_G2D0 0 x0300#define MUX_SEL_STAT_G2D0 0 x0400#define DIV_G2D 0 x0600#define DIV_STAT_G2D 0 x0700#define DIV_ENABLE_ACLK_G2D 0 x0800#define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0 x0804#define DIV_ENABLE_PCLK_G2D 0 x0900#define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0 x0904#define DIV_ENABLE_IP_G2D0 0 x0b00#define DIV_ENABLE_IP_G2D1 0 0b04#define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0 x0b08static const unsigned long g2d_clk_regs[] __initconst = {static const struct java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 180 },/* list of all parent clock list */ "oscclk" , "aclk_g2d_266" , };"oscclk" , "aclk_g2d_400" , };static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {/* MUX_SEL_G2D0 */ "mout_aclk_g2d_266_user" ,4 , 1 ),"mout_aclk_g2d_400_user" ,0 , 1 ),static const struct samsung_div_clock g2d_div_clks[] __initconst = {/* DIV_G2D */ "div_pclk_g2d" , "mout_aclk_g2d_266_user" ,0 , 2 ),static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {/* DIV_ENABLE_ACLK_G2D */ "aclk_smmu_mdma1" , "mout_aclk_g2d_266_user" ,12 , 0 , 0 ),"aclk_bts_mdam1" , "mout_aclk_g2d_266_user" ,11 , 0 , 0 ),"aclk_bts_g2d" , "mout_aclk_g2d_400_user" ,10 , 0 , 0 ),"aclk_alb_g2d" , "mout_aclk_g2d_400_user" ,9 , 0 , 0 ),"aclk_axius_g2dx" , "mout_aclk_g2d_400_user" ,8 , 0 , 0 ),"aclk_asyncaxi_sysx" ,"mout_aclk_g2d_400_user" , DIV_ENABLE_ACLK_G2D,7 , 0 , 0 ),"aclk_ahb2apb_g2d1p" , "div_pclk_g2d" ,"" ;"aclk_ahb2apb_g2d0p" , "div_pclk_g2d" ,5 , CLK_IGNORE_UNUSED, 0 ),"aclk_xiu_g2dx" , "mout_aclk_g2d_400_user" ,4 , CLK_IGNORE_UNUSED, 0 ),"aclk_g2dnp_133" , "div_pclk_g2d" ,3 , CLK_IGNORE_UNUSED, 0 ),"aclk_g2dnd_400" , "mout_aclk_g2d_400_user" ,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_mdma1" , "mout_aclk_g2d_266_user" ,1 , 0 , 0 ),"aclk_g2d" , "mout_aclk_g2d_400_user" ,0 , 0 , 0 ),/* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */ "aclk_smmu_g2d" , "mout_aclk_g2d_400_user" ,0 , 0 , 0 ),/* DIV_ENABLE_PCLK_G2D */ ds for length 547 , 0 , 0 ),"clk_bts_mdam1" "div_pclk_g2d, 6 , 0 , 0 ),"pclk_bts_g2d" "iv_pclk_g2d" ,5 , 0 , 0 ),"pclk_alb_g2d" , "div_pclk_g2d" ,"out_aclk_lite_a_a, "pclk_asyncaxi_sysx" , "div_pclk_g2d" ,3 , 0 , 0 ),"pclk_pmu_g2d" , "div_pclk_g2d" ,2 , CLK_IGNORE_UNUSED, 0 ),"pclk_sysreg_g2d" , "div_pclk_g2d" ,1 , CLK_IGNORE_UNUSED, 0 ),"pclk_g2d" , "div_pclk_g2d" , DIV_ENABLE_PCLK_G2D,0 , 0 , 0 ),/* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */ "pclk_smmu_g2d" , "div_pclk_g2d" ,0 , 0 , 0 )," ; static const struct samsung_cmu_info g2d_cmu_info __initconst = {"aclk_g2d_400" ,/* * Register offset definitions for CMU_DISP #define DISP_PLL_LOCK 0 x0000#define DISP_PLL_CON0 0 x0100#define DISP_PLL_CON1 0 x0104#define DISP_PLL_FREQ_DET 0 x0108#define MUX_SEL_DISP0 0 x0200#define MUX_SEL_DISP1 0 x0204#define MUX_SEL_DISP2 0 x0208#define MUX_SEL_DISP3 0 x020c#define MUX_SEL_DISP4 0 x0210#define MUX_ENABLE_DISP0 0 x0300#define MUX_ENABLE_DISP1 0 x0304#define MUX_ENABLE_DISP2 0 x0308#define MUX_ENABLE_DISP3 " } #define MUX_ENABLE_DISP4 0 x0310#PNAME (java.lang.StringIndexOutOfBoundsException: Range [36, 32) out of bounds for length 65#define MUX_STAT_DISP1 0 x0404#define MUX_STAT_DISP2 0 x0408#define MUX_STAT_DISP3 0 x040c#define MUX_STAT_DISP4 0 x0410#define MUX_IGNORE_DISP2 0 x0508#define DIV_DISP 0 x0600#define DIV_DISP_PLL_FREQ_DET 0 x0604#define DIV_STAT_DISPPNAMEmout_sclk_pixelasync_lite_c_b_p) = { "mout_sclk_pixelasync_lite_c_a" ,#define DIV_STAT_DISP_PLL_FREQ_DET 0 x0704#define ENABLE_ACLK_DISP0 0 x0800#define ENABLE_ACLK_DISP1 0 x0804#define ENABLE_PCLK_DISP 0 x0900#define ENABLE_SCLK_DISP 0 x0a00#PNAME mout_sclk_pixelasync_lite_c_a_p) = { "mout_aclk_cam0_552_user" ,#define ENABLE_IP_DISP1 0 x0b04#define CLKOUT_CMU_DISP 0 x0c00#define CLKOUT_CMU_DISP_DIV_STAT 0 x0c04static const unsigned long disp_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump disp_suspend_regs[] = {/* PLL has to be enabled for suspend */ 0 x85f40502 },/* ignore status of external PHY muxes during suspend to avoid hangs */ 0 x00111111 },0 },0 },0 },0 },0 },/* list of all parent clock list */ "oscclk" , "fout_disp_pll" , };"oscclk" , "sclk_dsim1_disp" , };"oscclk" , "sclk_dsim0_disp" , };"oscclk" , "sclk_dsd_disp" , };"oscclk" ,"sclk_decon_tv_eclk_disp" , };"oscclk" ,"sclk_decon_vclk_disp" , };"oscclk" ,"sclk_decon_eclk_disp" , };"oscclk" ,"sclk_decon_tv_vclk_disp" , };"oscclk" , "aclk_disp_333" , };"phyclk_mipidphy1_bitclkdiv8_phy" , };"oscclk" ,"phyclk_mipidphy1_rxclkesc0_phy" , };"oscclk" ,"java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 0 "oscclk" ,"phyclk_mipidphy0_rxclkesc0_phy" , };"oscclk" ,"phyclk_hdmiphy_tmds_clko_phy" , };"java.lang.StringIndexOutOfBoundsException: Range [72, 71) out of bounds for length 72 "phyclk_hdmiphy_pixel_clko_phy" , };"mout_disp_pll" ,"mout_sclk_dsim0_user" , };"mout_disp_pll" ,"mout_sclk_decon_tv_eclk_user" , };"mout_disp_pll" ,"mout_sclk_decon_vclk_user" , };"mout_disp_pll" ,"mout_sclk_decon_eclk_user" , };"mout_sclk_dsim1_a_disp" ,"mout_sclk_dsim1_user" , };th 24"mout_phyclk_hdmiphy_pixel_clko_user" ,"java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 24 "mout_sclk_decon_tv_vclk_a_disp" ,"mout_sclk_decon_tv_vclk_user" , };static const struct samsung_pll_clock disp_pll_clks[] __initconst = {"fout_disp_pll" , "oscclk" ,static const struct java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 25/* * sclk_rgb_ { vclk | tv_vclk } is half clock of sclk_decon_ { vclk | tv_vclk } . * The divider has fixed value ( 2 ) between sclk_rgb_ { vclk | tv_vclk } * and sclk_decon_ { vclk | tv_vclk } . "sclk_rgb_vclk" , "sclk_decon_vclk" ,1 , 2 , 0 ),"sclk_rgb_tv_vclk" , "sclk_decon_tv_vclk" ,1 , 2 , 0 ),static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {/* PHY clocks from MIPI_DPHY1 */ " java.lang.StringIndexOutOfBoundsException: Range [66, 65) out of bounds for length 66 0 , "phyclk_mipidphy1_rxclkesc0_phyMUX_SEL_CAM03, 0, 1), /* PHY clocks from MIPI_DPHY0 */ "phyclk_mipidphy0_bitclkdiv8_phy" ,0 , 188000000 ),"phyclk_mipidphy0_rxclkesc0_phy" ,0 , 100000000 ),/* PHY clocks from HDMI_PHY */ "java.lang.StringIndexOutOfBoundsException: Range [0, 70) out of bounds for length 53 0 , 300000000 ),"phyclk_hdmiphy_pixel_clko_phy" ,0 , 166000000 ),static const struct samsung_mux_clock disp_mux_clks[] __initconst = {/* MUX_SEL_DISP0 */ "mout_disp_pll ,16 1), 0 , 1 ),/* MUX_SEL_DISP1 */ "mout_sclk_dsim1_user" ,28 , 1 ),"mout_sclk_dsim0_user" ,24 , 1 ),"mout_sclk_dsd_user" , mout_sclk_dsd_user_p,20 , 1 ),"mout_sclk_decon_tv_eclk_user" ,16 , 1 ),"mout_sclk_decon_vclk_user" ,12 , 1 ),"mout_sclk_decon_eclk_user" ,8 , 1 ),"mout_sclk_decon_tv_vclk_user" ,4 , 1 ),"mout_aclk_disp_333_user" ,0 , 1 ),/* MUX_SEL_DISP2 */ "mout_phyclk_mipidphy1_bitclkdiv8_user" ,20 , 1 ),"mout_phyclk_mipidphy1_rxclkesc0_user" ,16 , 1 ),"mout_phyclk_mipidphy0_bitclkdiv8_user" ,12 , 1 ),"mout_phyclk_mipidphy0_rxclkesc0_user" ,8 , 1 ),"mout_phyclk_hdmiphy_tmds_clko_user" ,4 , 1 ),"mout_phyclk_hdmiphy_pixel_clko_user" ,0 , 1 ),/* MUX_SEL_DISP3 */ "mout_sclk_dsim0" , mout_sclk_dsim0_p,12 , 1 ),"mout_sclk_decon_tv_eclk" ,8 , 1 ),"mout_sclk_decon_vclk" ,4 , 1 ),"mout_sclk_decon_eclk" ,0 , 1 ),/* MUX_SEL_DISP4 */ "out_sclk_dsim1_b_disp, 16 , 1 ),"mout_sclk_dsim1_a_disp" ,12 , 1 ),"mout_sclk_decon_tv_vclk_c_disp" ,8 , 1 ),"mout_sclk_decon_tv_vclk_b_disp" ,4 , 1 ),20 3 ,0 , 1 ),static const struct samsung_div_clock disp_div_clks[] __initconst = {/* DIV_DISP */ "java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52 "mout_sclk_dsim1_b_disp" , DIV_DISP, 24 , 3 ),"div_sclk_decon_tv_vclk_disp" ,"mout_sclk_decon_tv_vclk_c_disp" , DIV_DISP, 20 , 3 ),"div_sclk_dsim0_disp" , "mout_sclk_dsim0" ,16 , 3 ),"div_sclk_decon_tv_eclk_disp" ,"mout_sclk_decon_tv_eclk" , DIV_DISP, 12 , 3 ),"div_sclk_decon_vclk_disp" ,"mout_sclk_decon_vclk" , DIV_DISP, 8 , 3 ),"div_sclk_decon_eclk_disp" ,"mout_sclk_decon_eclk" , DIV_DISP, 4 , 3 ),"div_pclk_disp" , "mout_aclk_disp_333_user" ,0 , 2 ),static const struct samsung_gate_clock disp_gate_clks[] __initconst = {/* ENABLE_ACLK_DISP0 */ "aclk_decon_tv" , "mout_aclk_disp_333_user" ,2 , 0 , 0 ),"aclk_decon" , "mout_aclk_disp_333_user" ,0 , 0 , 0 ),/* ENABLE_ACLK_DISP1 */ "aclk_smmu_tv1x" , "mout_aclk_disp_333_user" ,25 , 0 , 0 ),0 , )24 , 0 , 0 ),"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 23 , 0 , 0 ),"aclk_smmu_decon0x" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 22 , 0 , 0 ),", div_aclk_csis1" ,,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 21 , 0 , 0 ),"aclk_bts_decon_tv_m2" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 20 , 0 , GATE(CLK_ACLK_CSIS0 aclk_csis0,"iv_aclk_csis0,ENABLE_ACLK_CAM00 "aclk_bts_decon_tv_m1" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 19 , 0 , 0 ),"aclk-bts_decon_tv_m0" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 18 , 0 , 0 ),"aclk_bts_decon_nm4" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 17 , 0 , 0 ),"aclk_bts_decon_nm3" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 16 , 0 , 0 ),"aclk_bts_decon_nm2" ,"GATE(CLK_ACLK_LITE_D " clk_lite_d,"iv_aclk_lite_d" java.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for length 56"aclk_bts_decon_nm1" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 14 , 0 , 0 ),"aclk_bts_decon_nm0" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 13 , 0 , 0 ),"aclk_ahb2apb_dispsfr2p" ,"div_pclk_disp" , ENABLE_ACLK_DISP1,12 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb2apb_dispsfr1p" ,"div_pclk_disp" , ENABLE_ACLK_DISP1,11 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb2apb_dispsfr0p" ,"div_pclk_disp" , ENABLE_ACLK_DISP1,10 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb_disph" , "div_pclk_disp" ,8 , CLK_IGNORE_UNUSED, 0 ),"aclk_xiu_tv1x" , "mout_aclk_disp_333_user" ,7 , 0 , 0 ),"aclk_xiu_tv0x" , "mout_aclk_disp_333_user" ,6 , 0 , 0 ),"aclk_xiu_decon1x" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0)"aclk_xiu_decon0x" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 4 , 0 , 0 ),"aclk_xiu_disp1x" , "java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 48 3 , CLK_IGNORE_UNUSED, 0 ),"aclk_xiu_dispnp_100" , "div_pclk_disp" ,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_disp1nd_333" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 1 ,0 ),"aclk_disp0nd_333" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_DISP */ "pclk_smmu_tv1x" , "div_pclk_disp" ,23 , 0 , 0 ),"pclk_smmu_tv0x" , "div_pclk_disp" ,22 , 0 , 0 ),"pclk_smmu_decon1x" , "div_pclk_disp" ,21 , 0 , 0 ),"pclk_smmu_decon0x" , "div_pclk_disp" ,20 , 0 , 0 ),"clk_bts_decon_tv_m3," div_pclk_disp19 , 0 , 0 ),"pclk_bts_decon_tv_m2" , "div_pclk_disp" ,18 , 0 , 0 ),"pclk_bts_decon_tv_m1" , "div_pclk_disp" ,17 , 0 , 0 ),"clk_bts_decon_tv_m0" "iv_pclk_disp" ,16 , 0 , 0 ),"pclk_bts_deconm4" , "div_pclk_disp" ,15 , 0 , 0 ),"pclk_bts_deconm3" , "div_pclk_disp" ,14 , 0 , 0 ),"pclk_bts_deconm2" , "div_pclk_disp" ,13 , 0 , 0 ),"pclk_bts_deconm1" , "div_pclk_disp" ,12 , 0 , 0 ),"pclk_bts_deconm0" , "div_pclk_disp" ,0 ,0 ,"pclk_mic1" , "div_pclk_disp" ,10 , 0 , 0 ),"pclk_pmu_disp" , "div_pclk_disp" ,9 , CLK_IGNORE_UNUSED, 0 ),18 ,CLK_IGNORE_UNUSED,0 )java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 298 , CLK_IGNORE_UNUSED, 0 ),"pclk_hdmiphy" , "div_pclk_disp " ,7 , 0 , 0 ),"pclk_hdmi" , "div_pclk_disp" ,"aclk_asyncaxim_3aa1" java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53"pclk_mic0" , "div_pclk_disp" ,5 , 0 , 0 ), 16 ,0 ,"pclk_dsim1" , "div_pclk_disp" ,3 , 0 , 0 ),"pclk_dsim0" , "div_pclk_disp" ,2 , 0 , 0 ),"pclk_decon_tv" , "div_pclk_disp" ,1 , 0 , 0 ),"," div_pclk_disp"java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52 0 , 0 , 0 ) java.lang.StringIndexOutOfBoundsException: Range [27, 25) out of bounds for length 46/* ENABLE_SCLK_DISP */ "phyclk_mipidphy1_bitclkdiv8" ,"mout_phyclk_mipidphy1_bitclkdiv8_user" ,26 , 0 , 0 ),"phyclk_mipidphy1_rxclkesc0" ,"mout_phyclk_mipidphy1_rxclkesc0_user" ,25 , 0 , 0 ),"sclk_rgb_tv_vclk_to_dsim1 GATECLK_ACLK_ASYNCAXIM_LITE_D," aclk_asyncaxim_lite_d", "sclk_rgb_tv_vclk" , ENABLE_SCLK_DISP, 24 , 0 , 0 ),"sclk_rgb_tv_vclk_to_mic1" ,"sclk_rgb_tv_vclk" , ENABLE_SCLK_DISP, 23 , 0 , 0 ),"sclk_dsim1" , "div_sclk_dsim1_disp" ,22 , 0 , GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d" ,"sclk_decon_tv_vclk" ,"div_sclk_decon_tv_vclk_disp" ,21 , 0 , 0 ),"phyclk_mipidphy0_bitclkdiv8" ,"mout_phyclk_mipidphy0_bitclkdiv8_user" ,15 , 0 , 0 ),"phyclk_mipidphy0_rxclkesc0" ,"mout_phyclk_mipidphy0_rxclkesc0_user" ,14 , 0 , 0 ),"phyclk_hdmiphy_tmds_clko" ,"mout_phyclk_hdmiphy_tmds_clko_user" ,13 , 0 , 0 ),"phyclk_hdmi_pixel" ,"sclk_rgb_tv_vclk" , ENABLE_SCLK_DISP, 12 , 0 , 0 ),"sclk_rgb_vclk_to_smies" ,"sclk_rgb_vclk" , ENABLE_SCLK_DISP, 11 , 0 , 0 ),"sclk_rgb_vclk_to_dsim0" ,"sclk_rgb_vclk" , ENABLE_SCLK_DISP, 9 , 0 , 0 ),"sclk_rgb_vclk_to_mic0" ,"sclk_rgb_vclk" , ENABLE_SCLK_DISP, 8 , 0 , 0 ),"sclk_dsd" , "mout_sclk_dsd_user" ,7 , 0 , 0 ),"sclk_hdmi_spdif" , "sclk_hdmi_spdif_disp" ,6 , 0 , 0 ),"sclk_dsim0" , "div_sclk_dsim0_disp" ,5 , 0 , 0 ),"sclk_decon_tv_eclk" ,"div_sclk_decon_tv_eclk_disp" ,4 , 0 , 0 ),"clk_decon_vclk" ,"div_sclk_decon_vclk_disp" , ENABLE_SCLK_DISP, 3 , 0 , 0 ),"sclk_decon_eclk" ,"div_sclk_decon_eclk_disp" , ENABLE_SCLK_DISP, 2 , 0 , 0 ),static const struct samsung_cmu_info disp_cmu_info __initconst = {" java.lang.StringIndexOutOfBoundsException: Range [66, 64) out of bounds for length 66 "aclk_disp_333" ,/* java.lang.StringIndexOutOfBoundsException: Range [21, 20) out of bounds for length 47 #define MUX_SEL_AUD0 0 x0200#define MUX_SEL_AUD1 0 x0204#define MUX_ENABLE_AUD0 0 x0300#define MUX_ENABLE_AUD1 0 x0304#define MUX_STAT_AUD0 0 x0400#define DIV_AUD0 0 x0600#define DIV_AUD1 0 x0604#define DIV_STAT_AUD0 0 x0700#define DIV_STAT_AUD1 0 x0704#define ENABLE_ACLK_AUD 0 x0800#define 0 x0900#define ENABLE_SCLK_AUD0 0 x0a00#define ENABLE_SCLK_AUD1 0 x0a04#define ENABLE_IP_AUD0 0 x0b00#define ENABLE_IP_AUD1 0 x0b04static const unsigned long aud_clk_regs[] __initconst = {0 ,"java.lang.StringIndexOutOfBoundsException: Range [45, 43) out of bounds for length 70 2 ,,static const struct samsung_clk_reg_dump aud_suspend_regs[] = {0 },0 },/* list of all parent clock list */ "oscclk" , "fout_aud_pll" , };"mout_aud_pll_user" , "ioclk_audiocdclk0" ,};static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {0 "" ,NULL ,33000000 ),0 , "ioclk_slimbus_clk" , NULL, 0 , 25000000 ),0 , "ioclk_i2s_bclk" , NULL, 0 , 50000000 ),static const struct samsung_mux_clock aud_mux_clks[] __initconst = {/* MUX_SEL_AUD0 */ "mout_aud_pll_user" ,0 , 1 ),/* MUX_SEL_AUD1 */ "mout_sclk_aud_pcm" , mout_sclk_aud_pcm_p,8 , 1 ),"mout_sclk_aud_i2s" , mout_sclk_aud_pcm_p,0 , 1 ),static const struct samsung_div_clock aud_div_clks[] __initconst = {/* DIV_AUD0 */ "div_atclk_aud" , "div_aud_ca5" , DIV_AUD0,12 , 4 ),"div_pclk_dbg_aud" , "div_aud_ca5" , DIV_AUD0,8 , 4 ),"div_aclk_aud" , "div_aud_ca5" , DIV_AUD0,4 , 4 ),"div_aud_ca5" , "mout_aud_pll_user" , DIV_AUD0,0 , 4 ),/* DIV_AUD1 */ "div_sclk_aud_slimbus" ,"mout_aud_pll_user" , DIV_AUD1, 16 , 5 ),"div_sclk_aud_uart" , "mout_aud_pll_user" ,12 , 4 ),"div_sclk_aud_pcm" , "mout_sclk_aud_pcm" ,4 , 8 ),"div_sclk_aud_i2s" , "mout_sclk_aud_i2s" ,0 , 4 ),static const struct samsung_gate_clock aud_gate_clks[] __initconst = {/* ENABLE_ACLK_AUD */ "aclk_intr_ctrl" , " 12 CLK_IGNORE_UNUSED,0)java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29 12 , 0 , 0 ),"aclk_smmu_lpassx" , "div_aclk_aud " iv_pclk_cam0_50, ENABLE_PCLK_CAM0,7 , 0 , 0 ),0 , 4 , 0 ),"aclk_audnp_133" , "div_aclk_aud" ,0 , 3 , 0 ),"aclk_audnd_133" , "div_aclk_aud" ,0 , 2 , 0 ),"aclk_sramc" , "div_aclk_aud" , ENABLE_ACLK_AUD,0 , 1 , 0 ),"aclk_dmac" , "div_aclk_aud" , ENABLE_ACLK_AUD,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_AUD */ "pclk_wdt1" , "div_aclk_aud" , ENABLE_PCLK_AUD,13 , 0 , 0 ),"pclk_wdt0" , "div_aclk_aud" , ENABLE_PCLK_AUD,12 , 0 , 0 ),"pclk_sfr1" , "div_aclk_aud" , ENABLE_PCLK_AUD,11 , 0 , 0 ),"pclk_smmu_lpassx" , "div_aclk_aud" ,10 , 0 , 0 ),"pclk_gpio_aud" , "div_aclk_aud" ,9 , CLK_IGNORE_UNUSED, 0 ),"pclk_pmu_aud" , "div_aclk_aud" ,8 , CLK_IGNORE_UNUSED, 0 ),"pclk_sysreg_aud" , "div_aclk_aud" ,7 , CLK_IGNORE_UNUSED, 0 ),"pclk_aud_slimbus" , "div_aclk_aud" ,6 , 0 , 0 ),"clk_aud_uart" ,"div_aclk_aud" ,5 , 0 , 0 ),3 , CLK_IGNORE_UNUSED, 0 ),4 , 0 , 0 ),"pclk_aud_i2s" , "div_aclk_aud" ,3 , 0 , 0 ),"pclk_timer" , "div_aclk_aud" , ENABLE_PCLK_AUD,2 , 0 , 0 ),"pclk_sfr0_ctrl" , "div_aclk_aud" ,0 , 0 , 0 ),/* ENABLE_SCLK_AUD0 */ "atclk_aud" , "div_atclk_aud" , ENABLE_SCLK_AUD0,2 , CLK_IGNORE_UNUSED, 0 ),"pclk_dbg_aud" , "div_pclk_dbg_aud" ,1 , 0 , 0 ),"sclk_aud_ca5" , "div_aud_ca5" , ENABLE_SCLK_AUD0,0 , 0 , 0 ),/* ENABLE_SCLK_AUD1 */ "sclk_jtag_tck" , "ioclk_jtag_tclk" ,6 , 0 , 0 ),"sclk_slimbus_clkin" , "ioclk_slimbus_clk" ,5 , 0 , 0 ),"sclk_aud_slimbus" , "div_sclk_aud_slimbus" ,4 , 0 , 0 ),3 , CLK_IGNORE_UNUSED, 0 ),"sclk_aud_pcm" , "div_sclk_aud_pcm" ,2 , 0 , 0 ),"sclk_i2s_bclk" , "ioclk_i2s_bclk" ,", ,0 ) "sclk_aud_i2s" , "div_sclk_aud_i2s" ,0 , CLK_IGNORE_UNUSED, 0 ),static const struct GATE(LK_SCLK_PIXELASYNCS_3AA0sclk_pixelasycs_3aa0,"fout_aud_pll" ,Register offset definitions for CMU_BUS{0 |1 |2 }#define DIV_BUS#define DIV_STAT_BUS 0 x0700#define ENABLE_ACLK_BUS 0 x0800#define ENABLE_PCLK_BUS 0 x0900#define ENABLE_IP_BUS0 0 x0b00#define ENABLE_IP_BUS1 0 x0b04#define MUX_SEL_BUS2 0 x0200 /* Only for CMU_BUS2 */ #define MUX_ENABLE_BUS2 0 x0300 /* Only for CMU_BUS2 */ #define MUX_STAT_BUS2 0 x0400 /* Only for CMU_BUS2 */ /* list of all parent clock list */ "oscclk" , "aclk_bus2_400" , };static const unsigned long bus01_clk_regs[] __initconst = {static const unsigned long bus2_clk_regs[] __initconst = {static const struct samsung_div_clock bus0_div_clks[] __initconst = {/* DIV_BUS0 */ "div_pclk_bus0_133" , "aclk_bus0_400" ,0 , 3 ),/* CMU_BUS0 clocks */ static const struct samsung_gate_clock bus0_gate_clks[] __initconst = {/* ENABLE_ACLK_BUS0 */ "aclk_ahb2apb_bus0p" , "div_pclk_bus0_133" ,4 , CLK_IGNORE_UNUSED, 0 ),"aclk_bus0np_133" , "div_pclk_bus0_133" ,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_bus0nd_400" , "aclk_bus0_400" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_BUS0 */ "pclk_bus0srvnd_133" , "div_pclk_bus0_133" ,2 , 0 , 0 ),"pclk_pmu_bus0" , "div_pclk_bus0_133" ,1 , CLK_IGNORE_UNUSED, 0 ),"pclk_sysreg_bus0" , "div_pclk_bus0_133" ,0 , CLK_IGNORE_UNUSED, 0 ),/* CMU_BUS1 clocks */ static const struct samsung_div_clock bus1_div_clks[] __initconst = {/* DIV_BUS1 */ "div_pclk_bus1_133" , "aclk_bus1_400" ,0 , 3 ),static const struct samsung_gate_clock bus1_gate_clks[] __initconst = {/* ENABLE_ACLK_BUS1 */ "aclk_ahb2apb_bus1p" , "div_pclk_bus1_133" ,4 , CLK_IGNORE_UNUSED, 0 ),"aclk_bus1np_133" , "div_pclk_bus1_133" ,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_bus1nd_400" , "aclk_bus1_400" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_BUS1 */ "pclk_bus1srvnd_133" , "div_pclk_bus1_133" ,2 , 0 , 0 ),"pclk_pmu_bus1" , "div_pclk_bus1_133" ,1 , CLK_IGNORE_UNUSED, 0 ),"pclk_sysreg_bus1" , "div_pclk_bus1_133" ,0 , CLK_IGNORE_UNUSED, 0 ),/* CMU_BUS2 clocks */ static const struct samsung_mux_clock bus2_mux_clks[] __initconst = {/* MUX_SEL_BUS2 */ "mout_aclk_bus2_400_user" ,0 , 1 ),static const struct samsung_div_clock bus2_div_clks[] __initconst = {/* DIV_BUS2 */ 18"mout_aclk_bus2_400_user" , DIV_BUS, 0 , 3 ),static const struct samsung_gate_clock bus2_gate_clks[] __initconst = {/* ENABLE_ACLK_BUS2 */ "aclk_ahb2apb_bus2p" , "div_pclk_bus2_133" ,3 , CLK_IGNORE_UNUSED, 0 ),"aclk_bus2np_133" , "div_pclk_bus2_133" ,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_bus2bend_400" ,"mout_aclk_bus2_400_user" , ENABLE_ACLK_BUS,1 , CLK_IGNORE_UNUSED, 0 ),th 22"mout_aclk_bus2_400_user" , ENABLE_ACLK_BUS,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_BUS2 */ "pclk_bus2srvnd_133" , "div_pclk_bus2_133" ,2 , 0 , 0 ),"pclk_pmu_bus2" , "div_pclk_bus2_133" ,1 , CLK_IGNORE_UNUSED, 0 ),"pclk_sysreg_bus2" , "div_pclk_bus2_133" ,0 , CLK_IGNORE_UNUSED, 0 ),#define CMU_BUS_INFO_CLKS(id) \## id## _div_clks, \## id## _div_clks), \## id## _gate_clks, \## id## _gate_clks), \static _ java.lang.StringIndexOutOfBoundsException: Index 66 out of bounds for length 660 ),static const struct samsung_cmu_info bus1_cmu_info __initconst = {1 ),static const struct samsung_cmu_info bus2_cmu_info __initconst = {2 ),#define exynos5433_cmu_bus_init(id) \static void __init exynos5433_cmu_bus## id## _init(struct device_node *np)\## id## _cmu_info); \## id, \"samsung,exynos5433-cmu-bus" #id , \## id## _init)0 );1 );2 );/* * Register offset definitions for CMU_G3D #define G3D_PLL_LOCK 0 x0000#define G3D_PLL_CON0 0 x0100#define G3D_PLL_CON1 0 x0104#define G3D_PLL_FREQ_DET 0 x010c#define MUX_SEL_G3D 0 MUX(CLK_MOUT_PHYCLK_RXBYTEC,#define MUX_ENABLE_G3D 0 x0300#define MUX_STAT_G3D 0 x0400#define DIV_G3D 0 x0600#define DIV_G3D_PLL_FREQ_DET 0 x0604#define DIV_STAT_G3D 0 x0700#define DIV_STAT_G3D_PLL_FREQ_DET 0 x0704#define ENABLE_ACLK_G3D 0 x0800#define ENABLE_PCLK_G3D 0 x0900#define ENABLE_SCLK_G3D 0 x0a00#define ENABLE_IP_G3D0 0 x0b00#define ENABLE_IP_G3D1 0 x0b04#define CLKOUT_CMU_G3D 0 x0c00#define CLKOUT_CMU_G3D_DIV_STAT 0 x0c04#define CLK_STOPCTRL 0 x1000static const unsigned long g3d_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump g3d_suspend_regs[] = {0 },/* list of all parent clock list */ "mout_g3d_pll" , "aclk_g3d_400" , };" ; static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {"fout_g3d_pll" , "oscclk" ,/* MUX_SEL_G3D */ "mout_aclk_g3d_400" , mout_aclk_g3d_400_p,8 , 1 , CLK_SET_RATE_PARENT, 0 ),"mout_g3d_pll" , mout_g3d_pll_p,0 , 1 , CLK_SET_RATE_PARENT, 0 ),static const struct samsung_div_clock g3d_div_clks[] __initconst = {/* DIV_G3D */ "div_sclk_hpm_g3d" , "mout_g3d_pll" , DIV_G3D,8 , 2 ),"div_pclk_g3d" , "div_aclk_g3d" , DIV_G3D,4 , 3 ),"div_aclk_g3d" ,java.lang.StringIndexOutOfBoundsException: Range [43, 42) out of bounds for length 440 , 3 , CLK_SET_RATE_PARENT, 0 ),static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {/* ENABLE_ACLK_G3D */ "aclk_bts_g3d1" , "div_aclk_g3d" ,7 , 0 , 0 ),"aclk_bts_g3d0" , "div_aclk_g3d" ,6 , 0 , 0 ),"aclk_asyncapbs_g3d" , "div_pclk_g3d" ,5 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncapbm_g3ddjava.lang.StringIndexOutOfBoundsException: Range [66, 65) out of bounds for length 67 4 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb2apb_g3dp" , "div_pclk_g3d" ,3 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncapbs_lite_c" java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 572 ,CLK_IGNORE_UNUSED 0 ),"aclk_g3dnd_600" , "div_aclk_g3d" ,1 , CLK_IGNORE_UNUSED, 0 ),"aclk_g3d" , "div_aclk_g3d" ,0 , CLK_SET_RATE_PARENT, 0 ),/* ENABLE_PCLK_G3D */ "pclk_bts_g3d1" , "div_pclk_g3d" ,3 , 0 , 0 ),"pclk_bts_g3d0" , "div_pclk_g3d" ,2 , 0 , 0 ),3 d", 1 , CLK_IGNORE_UNUSED, 0 ),"pclk_sysreg_g3d" , "div_pclk_g3d" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_SCLK_G3D */ "sclk_hpm_g3d" , "div_sclk_hpm_g3d" ,0 , 0 , 0 ),static const struct samsung_cmu_info g3d_cmu_info __initconst = {"aclk_g3d_400" ,/** offset definitions for CMU_GSCL #define MUX_SEL_GSCL 0 x0200#define MUX_ENABLE_GSCL 0 x0300#define MUX_STAT_GSCL 0 x0400#define ENABLE_ACLK_GSCL 0 x0800#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0 x0804#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0 x0808#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0 x080c#define ENABLE_PCLK_GSCL 0 x0900#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0 x0904#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0 x0908#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0 x090c#define ENABLE_IP_GSCL0 0 x0b00#define ENABLE_IP_GSCL1 0 x0b04#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0 x0b08#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0 x0b0c#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0 x0b10static const unsigned long gscl_clk_regs[] __initconst = {10 , CLK_IGNORE_UNUSED 0 )java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48"java.lang.StringIndexOutOfBoundsException: Range [69, 68) out of bounds for length 70 static const struct samsung_clk_reg_dump gscl_suspend_regs[] = {0 },0 xfff },0 xff },/* list of all parent clock list */ " aclk_gscl_111" ,}java.lang.StringIndexOutOfBoundsException: Index 61 out of bounds for length 61"oscclk" , "aclk_gscl_333" , };static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {/* MUX_SEL_GSCL */ "mout_aclk_gscl_111_user" ,4 , 1 ),"mout_aclk_gscl_333_user" ,0 , 1 ),static const struct samsung_gate_clock gscl_gate_clks[] __initconst 10 ,CLK_IGNORE_UNUSED, 0 ),/* ENABLE_ACLK_GSCL */ "aclk_bts_gscl2" , "mout_aclk_gscl_333_user" ,"aclk_bts_gscl1" , "mout_aclk_gscl_333_user" ,10 , 0 , 0 ),"aclk_bts_gscl0" , "mout_aclk_gscl_333_user" ,9 , 0 , 0 ),"aclk_ahb2apb_gsclp" ,"mout_aclk_gscl_111_user" , ENABLE_ACLK_GSCL,0 ,"aclk_xiu_gsclx" , "mout_aclk_gscl_333_user" ,7 , 0 , 0 ),"aclk_gsclnp_111" , "mout_aclk_gscl_111_user" ,6 , CLK_IGNORE_UNUSED, 0 ),"aclk_gsclrtnd_333" ,"out_aclk_gscl_333_user" ,ENABLE_ACLK_GSCL 5 ,0 ),"aclk_gsclbend_333" ,"mout_aclk_gscl_333_user" , ENABLE_ACLK_GSCL, 4 ,0 ),"aclk_gsd" , "mout_aclk_gscl_333_user" ,3 , 0 , 0 ),"aclk_gscl2" , "mout_aclk_gscl_333_user" ,2 , 0 , 0 ),"aclk_gscl1" , "mout_aclk_gscl_333_user" ,1 , 0 , 0 ),"aclk_gscl0" , "mout_aclk_gscl_333_user" ,0 , 0 , 0 ),/* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */ 2 ,0 )0 , 0 , 0 ),/* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */ "aclk_smmu_gscl1" , ENABLE_ACLK_CAM12,1 ,CLK_IGNORE_UNUSED 0 0 , 0 , 0 ),/* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */ "aclk_smmu_gscl2" , "mout_aclk_gscl_333_user" ,0 , 0 , 0 ),/* ENABLE_PCLK_GSCL */ "pclk_bts_gscl2" , "mout_aclk_gscl_111_user" ,7 , 0 , 0 ),"pclk_bts_gscl1" , "mout_aclk_gscl_111_user" ,6 , 0 , 0 )," m" java.lang.StringIndexOutOfBoundsException: Index 70 out of bounds for length 705 , 0 , 0 ), out of bounds for length 680 ,"pclk_sysreg_gscl" ,"mout_aclk_gscl_111_user" , ENABLE_PCLK_GSCL,3 , CLK_IGNORE_UNUSED, 0 ),"pclk_gscl2" , "mout_aclk_gscl_111_user" ,2 , 0 , 0 ),"pclk_gscl1" , "mout_aclk_gscl_111_user" ,1 , 0 , 0 ),"pclk_gscl0" , "mout_aclk_gscl_111_user" ,0 , 0 , 0 ),/* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */ "pclk_smmu_gscl0" , "mout_aclk_gscl_111_user" ,0 , 0 , 0 ),/* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */ 0 , 0 , 0 ),/* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */ "pclk_smmu_gscl2" , "mout_aclk_gscl_111_user" ,0 , 0 , 0 ),static const struct samsung_cmu_info gscl_cmu_info __initconst = {e [44, 42) out of bounds for length 47"aclk_gscl_111" ,/* * Register offset definitions for CMU_APOLLO #define APOLLO_PLL_LOCK 0 x0000#define APOLLO_PLL_CON0 0 x0100#define APOLLO_PLL_CON1 0 x0104#define APOLLO_PLL_FREQ_DET 0 x010c#define MUX_SEL_APOLLO0 0 x0200#define MUX_SEL_APOLLO1 0 x0204#define MUX_SEL_APOLLO2 0 x0208#define MUX_ENABLE_APOLLO0 0 x0300#define MUX_ENABLE_APOLLO1 0 x0304#define MUX_ENABLE_APOLLO2 0 x0308#define MUX_STAT_APOLLO0 0 x0400#define MUX_STAT_APOLLO1 0 x0404#define MUX_STAT_APOLLO2 0 x0408#define DIV_APOLLO0 0 x0600#define DIV_APOLLO1 0 x0604#define DIV_APOLLO_PLL_FREQ_DET 0 x06080 x0700#define DIV_STAT_APOLLO1 0 x0704#define DIV_STAT_APOLLO_PLL_FREQ_DET 0 x07080 x0800#define ENABLE_PCLK_APOLLO 0 x0900#define ENABLE_SCLK_APOLLO 0 x0a00#define ENABLE_IP_APOLLO0 0 x0b00#define ENABLE_IP_APOLLO1 0 x0b04#define CLKOUT_CMU_APOLLO 0 x0c00#define CLKOUT_CMU_APOLLO_DIV_STAT 0 x0c04#define ARMCLK_STOPCTRL 0 x1000#define APOLLO_PWR_CTRL 0 x1020#define APOLLO_PWR_CTRL2 0 x1024#define ENABLE_PCLK_CAM1 4 , CLK_IGNORE_UNUSED, 0 ,#define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0 x1084#define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0 x1088static const unsigned long apollo_clk_regs[] __initconst = {ex 69 out of bounds for length 69"hyclk_rxbyteclkhs0_s2b, /* list of all parent clock list */ "oscclk" , "fout_apollo_pll" , };"oscclk" , "sclk_bus_pll_apollo" , };"mout_apollo_pll" ,"mout_bus_pll_apollo_user" , };static const struct samsung_pll_clock apollo_pll_clks[] __initconst = {"fout_apollo_pll" , "oscclk" ,static const struct samsung_mux_clock apollo_mux_clks[] __initconst = {/* MUX_SEL_APOLLO0 */ "mout_apollo_pll" , mout_apollo_pll_p,0 , 1 , CLK_SET_RATE_PARENT |0 ),/* MUX_SEL_APOLLO1 */ "mout_bus_pll_apollo_user" ,0 , 1 ),"mout_apollo" , mout_apollo_p, MUX_SEL_APOLLO2,0 , 1 , CLK_SET_RATE_PARENT, 0 ),static const struct samsung_div_clock apollo_div_clks[] __initconst = {/* DIV_APOLLO0 */ 24 , 3 , CLK_GET_RATE_NOCACHE,20 , 3 , CLK_GET_RATE_NOCACHE,"div_atclk_apollo" , "div_apollo2" ,16 , 3 , CLK_GET_RATE_NOCACHE,"div_pclk_apollo" , "div_apollo2" ,12 , 3 , CLK_GET_RATE_NOCACHE,"div_aclk_apollo" , "div_apollo2" ,8 , 3 , CLK_GET_RATE_NOCACHE,"div_apollo2" , "div_apollo1" ,4 , 3 , CLK_SET_RATE_PARENT, 0 ),"div_apollo1" , "mout_apollo" ,0 , 3 , CLK_SET_RATE_PARENT, 0 ),/* DIV_APOLLO1 */ " 4 , 3 , CLK_GET_RATE_NOCACHE,"div_apollo_pll 0 , 3 , CLK_GET_RATE_NOCACHE,static const struct samsung_gate_clock apollo_gate_clks[] __initconst = {/* ENABLE_ACLK_APOLLO */ "aclk_asatbslv_apollo_3_cssys" ,"div_atclk_apollo" , ENABLE_ACLK_APOLLO,6 , CLK_IGNORE_UNUSED, 0 ),"aclk_asatbslv_apollo_2_cssys" ,"div_atclk_apollo" , ENABLE_ACLK_APOLLO,5 , CLK_IGNORE_UNUSED, 0 ),"aclk_asatbslv_apollo_1_cssys" ,"div_atclk_apollo" , ENABLE_ACLK_APOLLO,4 , CLK_IGNORE_UNUSED, 0 ),"aclk_asatbslv_apollo_0_cssys" ,3 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaces_apollo_cci" ,"div_aclk_apollo" , ENABLE_ACLK_APOLLO,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb2apb_apollop" ,"div_pclk_apollo" , ENABLE_ACLK_APOLLO,1 , CLK_IGNORE_UNUSED, 0 ),"aclk_apollonp_200" ,"div_pclk_apollo" , ENABLE_ACLK_APOLLO,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_APOLLO */ "div_pclk_dbg_apollo" , ENABLE_PCLK_APOLLO,2 , CLK_IGNORE_UNUSED, 0 ),1 , CLK_IGNORE_UNUSED, 0 ),"pclk_sysreg_apollo" ,"div_pclk_apollo" , ENABLE_PCLK_APOLLO,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_SCLK_APOLLO */ "cntclk_apollo" , "div_cntclk_apollo" .clk_name = "aclk_imem_200" ,3 , CLK_IGNORE_UNUSED, 0 ),"sclk_hpm_apollo" , "div_sclk_hpm_apollo" ,1 , CLK_IGNORE_UNUSED, 0 ),#define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \24 ) | ((pclk_dbg) << 20 ) | ((atclk) << 16 ) | \12 ) | ((aclk) << 8 ))#define E5433_APOLLO_DIV1(hpm, copy) \4 ) | ((copy) << 0 ))static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[ java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 21300000 , E5433_APOLLO_DIV0(3 , 7 , 7 , 7 , 2 ), E5433_APOLLO_DIV1(7 , 1 ), },1200000 , E5433_APOLLO_DIV0(3 , 7 , 7 , 7 , 2 ), E5433_APOLLO_DIV1(7 , 1 ), },1100000 , E5433_APOLLO_DIV0(3 , 7 , 7 , 7 , 2 ), E5433_APOLLO_DIV1(7 , 1 ), },1000000 , E5433_APOLLO_DIV0(3 , 7 , 7 , 7 , 2 ), E5433_APOLLO_DIV1(7 , 1 ), },900000 , E5433_APOLLO_DIV0(3 , 7 , 7 , 7 , 2 ), E5433_APOLLO_DIV1(7 , 1 ), },800000 , E5433_APOLLO_DIV0(3 , 7 , 7 , 7 , 2 ), E5433_APOLLO_DIV1(7 , 1 ), },700000 , E5433_APOLLO_DIV0(3 , 7 , 7 , 7 , 2 ), E5433_APOLLO_DIV1(7 , 1 ), },600000 , E5433_APOLLO_DIV0(3 , 7 , 7 , 7 , 1 ), 500000 , E5433_APOLLO_DIV0(3 , 7 , 7 , 7 , 1 ), E5433_APOLLO_DIV1(7 , 1 ), },400000 , E5433_APOLLO_DIV0(3 , 7 , 7 , 7 , 1 ), E5433_APOLLO_DIV1(7 , 1 ), },0 },static const struct samsung_cpu_clock apollo_cpu_clks[] __initconst = {0 , .data = &3 d_cmu_info,static const struct static void __init exynos5433_cmu_apollo_init(struct device_node *np)"samsung,exynos5433-cmu-apollo" ,/* * Register offset definitions for CMU_ATLAS #define ATLAS_PLL_LOCK 0 x0000#define ATLAS_PLL_CON0 0 x0100#define ATLAS_PLL_CON1 0 x0104#define ATLAS_PLL_FREQ_DET 0 x010c#define MUX_SEL_ATLAS0 0 x0200#define MUX_SEL_ATLAS1 0 x0204#define MUX_SEL_ATLAS2 0 x0208#define MUX_ENABLE_ATLAS0 0 x0300#define MUX_ENABLE_ATLAS10 x0304#define MUX_ENABLE_ATLAS2 0 x0308#define MUX_STAT_ATLAS0 0 x0400#define MUX_STAT_ATLAS1 0 x0404#define MUX_STAT_ATLAS2 0 x0408#define DIV_ATLAS0 0 x0600#define DIV_ATLAS1 0 x0604#define DIV_ATLAS_PLL_FREQ_DET 0 x0608#define DIV_STAT_ATLAS0 0 x0700#define DIV_STAT_ATLAS1 0 x0704#define DIV_STAT_ATLAS_PLL_FREQ_DET 0 x0708#define ENABLE_ACLK_ATLAS 0 x0800#define ENABLE_PCLK_ATLAS 0 x0900#define ENABLE_SCLK_ATLAS 0 x0a00#define ENABLE_IP_ATLAS0 0 x0b00#define ENABLE_IP_ATLAS1 0 x0b04#define CLKOUT_CMU_ATLAS 0 x0c00#define CLKOUT_CMU_ATLAS_DIV_STAT 0 x0c04#define ARMCLK_STOPCTRL 0 x1000# .ame exynos5433", #define ATLAS_PWR_CTRL2 0 x1024#define ATLAS_INTR_SPREAD_ENABLE 0 x1080#define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0 x1084#define java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 31static const unsigned long atlas_clk_regs[] __initconst = {/* list of all parent clock list */ "oscclk" , "fout_atlas_pll" , };"oscclk" , "sclk_bus_pll_atlas" , };"mout_atlas_pll" ,"mout_bus_pll_atlas_user" , };static const struct samsung_pll_clock atlas_pll_clks[] __initconst = {"fout_atlas_pll" , "oscclk" ,static const struct samsung_mux_clock atlas_mux_clks[] __initconst = {/* MUX_SEL_ATLAS0 */ "mout_atlas_pll" , mout_atlas_pll_p,0 , 1 , CLK_SET_RATE_PARENT |0 ),/* MUX_SEL_ATLAS1 */ "mout_bus_pll_atlas_user" ,0 , 1 ),/* MUX_SEL_ATLAS2 */ "mout_atlas" , mout_atlas_p, MUX_SEL_ATLAS2,0 , 1 , CLK_SET_RATE_PARENT, 0 ),static const struct samsung_div_clock atlas_div_clks[] __initconst = {/* DIV_ATLAS0 */ "div_cntclk_atlas" , "div_atlas2" ,24 , 3 , CLK_GET_RATE_NOCACHE,"div_pclk_dbg_atlas" , "div_atclk_atlas" ,20 , 3 , CLK_GET_RATE_NOCACHE,"div_atclk_atlas" , "div_atlas2" ,16 , 3 , CLK_GET_RATE_NOCACHE,"div_pclk_atlas" , "div_atlas2" ,12 , 3 , CLK_GET_RATE_NOCACHE,"div_aclk_atlas" , "div_atlas2" ,8 , 3 , CLK_GET_RATE_NOCACHE,"div_atlas2" , "div_atlas1" ,4 , 3 , CLK_SET_RATE_PARENT, 0 ),"div_atlas1" , "mout_atlas" ,0 , 3 , CLK_SET_RATE_PARENT, 0 ),/* DIV_ATLAS1 */ "div_sclk_hpm_atlas" , "mout_atlas" ,4 , 3 , CLK_GET_RATE_NOCACHE,"div_atlas_pll" , "mout_atlas" ,0 , 3 , CLK_GET_RATE_NOCACHE,static const struct samsung_gate_clock atlas_gate_clks[] __initconst = {/* ENABLE_ACLK_ATLAS */ "aclk_atb_aud_cssys" ,"div_atclk_atlas" , ENABLE_ACLK_ATLAS,9 , CLK_IGNORE_UNUSED, 0 ),"aclk_atb_apollo3_cssys" ,"div_atclk_atlas" , ENABLE_ACLK_ATLAS,8 , CLK_IGNORE_UNUSED, 0 ),"aclk_atb_apollo2_cssys" ,"div_atclk_atlas" , ENABLE_ACLK_ATLAS,7 , CLK_IGNORE_UNUSED, 0 ),"aclk_atb_apollo1_cssys" ,"div_atclk_atlas" , ENABLE_ACLK_ATLAS,6 , CLK_IGNORE_UNUSED, 0 ),"aclk_atb_apollo0_cssys" ,"div_atclk_atlas" , ENABLE_ACLK_ATLAS,5 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncahbs_cssys_sss" ,"div_atclk_atlas" , ENABLE_ACLK_ATLAS,4 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_cssys_ccix" ,"div_pclk_dbg_atlas" , ENABLE_ACLK_ATLAS,3 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaces_atlas_cci" ,"div_aclk_atlas" , ENABLE_ACLK_ATLAS,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb2apb_atlasp" , "div_pclk_atlas" ,1 , CLK_IGNORE_UNUSED, 0 ),"aclk_atlasnp_200" , "div_pclk_atlas" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_ATLAS */ "pclk_asyncapb_aud_cssys" ,"div_pclk_dbg_atlas" , ENABLE_PCLK_ATLAS,5 , CLK_IGNORE_UNUSED, 0 ),"pclk_asyncapb_isp_cssys" ,"div_pclk_dbg_atlas" , ENABLE_PCLK_ATLAS,4 , CLK_IGNORE_UNUSED, 0 ),"pclk_asyncapb_apollo_cssys" ,"div_pclk_dbg_atlas" , ENABLE_PCLK_ATLAS,3 , CLK_IGNORE_UNUSED, 0 ),"pclk_pmu_atlas" , "div_pclk_atlas" ,2 , CLK_IGNORE_UNUSED, 0 ),"pclk_sysreg_atlas" , "div_pclk_atlas" ,1 , CLK_IGNORE_UNUSED, 0 ),"pclk_secjtag" , "div_pclk_dbg_atlas" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_SCLK_ATLAS */ "cntclk_atlas" , "div_cntclk_atlas" ,10 , CLK_IGNORE_UNUSED, 0 ),"sclk_hpm_atlas" , "div_sclk_hpm_atlas" ,7 , CLK_IGNORE_UNUSED, 0 ),"traceclk" , "div_atclk_atlas" ,6 , CLK_IGNORE_UNUSED, 0 ),"ctmclk" , "div_atclk_atlas" ,5 , CLK_IGNORE_UNUSED, 0 ),"hclk_cssys" , "div_atclk_atlas" ,4 , CLK_IGNORE_UNUSED, 0 ),"pclk_dbg_cssys" , "div_pclk_dbg_atlas" ,3 , CLK_IGNORE_UNUSED, 0 ),"pclk_dbg" , "div_pclk_dbg_atlas" ,2 , CLK_IGNORE_UNUSED, 0 ),"atclk" , "div_atclk_atlas" ,1 , CLK_IGNORE_UNUSED, 0 ),#define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \24 ) | ((pclk_dbg) << 20 ) | ((atclk) << 16 ) | \12 ) | ((aclk) << 8 ))#define E5433_ATLAS_DIV1(hpm, copy) \static th 264 ,E5433_ATLAS_DIV1(7 ) ,1700000 , E5433_ATLAS_DIV0(7 , 7 , 7 , 7 , 4 ), E5433_ATLAS_DIV1(7 , 1 ), },7 ,,7 )java.lang.StringIndexOutOfBoundsException: Range [62, 61) out of bounds for length 711500000 ngth 50ngth 60gth 411000000 , E5433_ATLAS_DIV0 java.lang.StringIndexOutOfBoundsException: Range [22, 21) out of bounds for length 31gth 71800000 ,E5433_ATLAS_DIV0(7 , 7 , 7 , 7 , 2 ), E5433_ATLAS_DIV1(7 , 1 ), },700000 , E5433_ATLAS_DIV0(7 , 7 , 7 , 7 , (, "in_pll" xusbxti1 ,,0 )600000 , E5433_ATLAS_DIV0(7 , 7 , 7 *thenjava.lang.StringIndexOutOfBoundsException: Range [34, 33) out of bounds for length 68500000 ,7 ,7 ,,2 ) java.lang.StringIndexOutOfBoundsException: Range [62, 61) out of bounds for length 710 },static java.lang.StringIndexOutOfBoundsException: Range [26, 25) out of bounds for length 64th 80th 38 length 67gth 43nds for length 67ngth 28nds for length 43nds for length 42gth 60gth 68th 47/** offset #define MUX_SEL_MSCL0 0 DIV(CLK_DIV_I2S, "div_i2s", "dijava.lang.StringIndexOutOfBoundsException: Range [53, 52) out of bounds for length 60#define MUX_SEL_MSCL1 0 x0204#define MUX_ENABLE_MSCL0 0 x0300#define MUX_ENABLE_MSCL1 0 x0304#define MUX_STAT_MSCL0 0 x0400#define MUX_STAT_MSCL1 0 x0404#define DIV_MSCL 0 x0600#define DIV_STAT_MSCL 0 x0700#define ENABLE_ACLK_MSCL #define java.lang.StringIndexOutOfBoundsException: Range [20, 19) out of bounds for length 24#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0 x0808#define (CLK_ASYNC_CAMX" java.lang.StringIndexOutOfBoundsException: Range [51, 49) out of bounds for length 72 # "java.lang.StringIndexOutOfBoundsException: Range [28, 27) out of bounds for length 64 #define GATE(CLK_PROVISIONKEY1, "provisionkey1", #define java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 24#define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0 x090c#define ENABLE_SCLK_MSCL 0 x0a00#define ENABLE_IP_MSCL0 0 x0b00#define ENABLE_IP_MSCL1 0 x0b04#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0 x0b08 53#define GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0 ),unsigned java.lang.StringIndexOutOfBoundsException: Range [43, 40) out of bounds for length 58ounds for length 44s for length 49f bounds for length 47th 41of bounds for length 58"java.lang.StringIndexOutOfBoundsException: Range [32, 31) out of bounds for length 65 static java.lang.StringIndexOutOfBoundsException: Range [20, 19) out of bounds for length 72th 220 )/* list of all parent clock list */ 17, 16) out of bounds for length 67gth 66"mout_sclk_jpeg_user" ,"mout_aclk_mscl_400_user" , };th 69ngth 64"mout_sclk_jpeg_user" ,24 *,,400 )"mout_aclk_mscl_400_user" ,850000000 , 425 , 6 , 1 ),/* MUX_SEL_MSCL1 */ *,520000000 ,,2 ,"mout_sclk_jpeg" , mout_sclk_jpeg_p,0 , 1 ) struct java.lang.StringIndexOutOfBoundsException: Range [43, 42) out of bounds for length 82static const struct samsung_div_clock mscl_div_clks[] __initconst = {/* DIV_MSCL */ "div_pclk_mscl" , "mout_aclk_mscl_400_user" ,0 , 3 ),struct java.lang.StringIndexOutOfBoundsException: Range [39, 38) out of bounds for length 71/* ENABLE_ACLK_MSCL */ "aclk_bts_jpeg" , "mout_aclk_mscl_400_user" ,9 , 0 , 0 ),"aclk_bts_m2mscaler1" ,"mout_aclk_mscl_400_user" , ENABLE_ACLK_MSCL, 8 , 0 , 0 ) java.lang.StringIndexOutOfBoundsException: Range [15, 14) out of bounds for length 54 71"mout_aclk_mscl_400_user" , ENABLE_ACLK_MSCL, 7 , 0 , 0 java.lang.StringIndexOutOfBoundsException: Range [13, 12) out of bounds for length 47h 2"const struct exynos_cpuclk_cfg_data_java.lang.StringIndexOutOfBoundsException: Range [75, 71) out of bounds for length 75 5 , CLK_IGNORE_UNUSED, 0 ),"aclk_msclnp_100" , "div_pclk_mscl" ,4 , { 200000, E3250_CPU_DIV0(1, 3, 3, 1),,"aclk_msclnd_400" , "mout_aclk_mscl_400_user" ,3 , CLK_IGNORE_UNUSED, 0 )," java.lang.StringIndexOutOfBoundsException: Range [60, 58) out of bounds for length 60 th 30"aclk_m2mscaler1" , "mout_aclk_mscl_400_user" ,1 , 0 , 0 ),gth 720 , 0 , 0 ),/* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */ "java.lang.StringIndexOutOfBoundsException: Range [29, 27) out of bounds for length 29 : Range [13, 12) out of bounds for length 290 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */ "samsung,exynos3250-cmu" , exynos3250_cmu_init);"mout_aclk_mscl_400_user" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */ "# 0 , CLK_IGNORE_UNUSEDjava.lang.StringIndexOutOfBoundsException: Range [11, 10) out of bounds for length 11/* ENABLE_PCLK_MSCL */ "pclk_bts_jpeg" , "div_pclk_mscl" ,th 11th 30"pclk_bts_m2mscaler0" , "div_pclk_mscl" ,5 , 0 , 0 ),"pclk_pmu_mscl" , "div_pclk_mscl" ,4 , CLK_IGNORE_UNUSED, 0 ),"pclk_sysreg_mscl" , "div_pclk_mscl" ,3 , CLK_IGNORE_UNUSED, 0 )," 2 , 0 , 0 ),t of bounds for length 621 , 0 , 0 ),"pclk_m2mscaler0" , "div_pclk_mscl" ,0 , 0 , 0 ),/* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */ th 720 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */ gth 720 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */ 0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_SCLK_MSCL */ "sclk_jpeg" , "mout_sclk_jpeg" , ENABLE_SCLK_MSCL, 0 ,0 ),static const * java.lang.StringIndexOutOfBoundsException: Range [17, 16) out of bounds for length 42Range [11, 10) out of bounds for length 18"aclk_mscl_400" ,/* * Register offset definitions for CMU_MFC th 46#define C,q" java.lang.StringIndexOutOfBoundsException: Range [48, 46) out of bounds for length 48 #define MUX_STAT_MFC 0 x0400#define java.lang.StringIndexOutOfBoundsException: Range [16, 14) out of bounds for length 42#define DIV_STAT_MFC 0 java.lang.StringIndexOutOfBoundsException: Range [15, 14) out of bounds for length 41th 41#define GATE_IP_ISP0, 5, CLK_IGNORE_UNUSED, 0#define ENABLE_PCLK_MFC 0 x0900#define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0 x0904#define java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 0ngth 51#define ENABLE_IP_MFC_SECURE_SMMU_MFC 0 x0b08static const unsigned long mfc_clk_regsjava.lang.StringIndexOutOfBoundsException: Range [16, 14) out of bounds for length 42th 42or length 41static const struct samsung_clk_reg_dump mfc_suspend_regs[] = {r length 12th 31static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {/* MUX_SEL_MFC */ "mout_aclk_mfc_400_user" ,0 , 0 ),static const struct samsung_div_clock mfc_div_clks[] __initconst = {/* DIV_MFC */ "div_pclk_mfc" , "mout_aclk_mfc_400_user" ,0 , 2 ),static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {/* ENABLE_ACLK_MFC */ "aclk_bts_mfc_1" , "mout_aclk_mfc_400_user" ,6 , 0 , 0 ),"aclk_bts_mfc_0" , "mout_aclk_mfc_400_user" ,5 , 0 , 0 ),"aclk_ahb2apb_mfcp" , "div_pclk_mfc" ,4 , CLK_IGNORE_UNUSED, 0 ),"aclk_xiu_mfcx" , "mout_aclk_mfc_400_user" ,3 , CLK_IGNORE_UNUSED, 0 ),"aclk_mfcnp_100" , "div_pclk_mfc" ,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_mfcnd_400" , "mout_aclk_mfc_400_user" ,1 , CLK_IGNORE_UNUSED, 0 ),"aclk_mfc" , "mout_aclk_mfc_400_user" ,0 , 0 , 0 ),/* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */ "aclk_smmu_mfc_1" , "mout_aclk_mfc_400_user" ,1 , CLK_IGNORE_UNUSED, 0 ),"aclk_smmu_mfc_0" , "mout_aclk_mfc_400_user" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_MFC */ "pclk_bts_mfc_1" , "div_pclk_mfc" ,4 , 0 , 0 ),"pclk_bts_mfc_0" , "div_pclk_mfc" ,3 , 0 , 0 ),"pclk_pmu_mfc" , "div_pclk_mfc" ,2 , CLK_IGNORE_UNUSED, 0 ),"pclk_sysreg_mfc" , "div_pclk_mfc" ,1 , CLK_IGNORE_UNUSED, 0 ),"pclk_mfc" , "div_pclk_mfc" ,4 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */ "pclk_smmu_mfc_1" , "div_pclk_mfc" ,1 , CLK_IGNORE_UNUSED, 0 ),"pclk_smmu_mfc_0" , "div_pclk_mfc" ,0 , CLK_IGNORE_UNUSED, 0 ),static const struct samsung_cmu_info mfc_cmu_info __initconst = {"aclk_mfc_400" ,/* * Register offset definitions for CMU_HEVC #define MUX_SEL_HEVC 0 x0200#define MUX_ENABLE_HEVC 0 x0300#define MUX_STAT_HEVC 0 x0400#define DIV_HEVC 0 x0600#define DIV_STAT_HEVC 0 x0700#define ENABLE_ACLK_HEVC 0 x0800#define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0 x0804#define ENABLE_PCLK_HEVC 0 x0900#define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0 x0904#define ENABLE_IP_HEVC0 0 x0b00#define ENABLE_IP_HEVC1 0 x0b04#define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0 x0b08static const unsigned long hevc_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump hevc_suspend_regs[] = {0 },"oscclk" , "aclk_hevc_400" , };static const struct samsung_mux_clock hevc_mux_clks[] __initconst = {/* MUX_SEL_HEVC */ "mout_aclk_hevc_400_user" ,0 , 0 ),static const struct samsung_div_clock hevc_div_clks[] __initconst = {/* DIV_HEVC */ "div_pclk_hevc" , "mout_aclk_hevc_400_user" ,0 , 2 ),static const struct samsung_gate_clock hevc_gate_clks[] __initconst = {/* ENABLE_ACLK_HEVC */ "aclk_bts_hevc_1" , "mout_aclk_hevc_400_user" ,6 , 0 , 0 ),"aclk_bts_hevc_0" , "mout_aclk_hevc_400_user" ,5 , 0 , 0 ),"aclk_ahb2apb_hevcp" , "div_pclk_hevc" ,4 , CLK_IGNORE_UNUSED, 0 ),"aclk_xiu_hevcx" , "mout_aclk_hevc_400_user" ,3 , CLK_IGNORE_UNUSED, 0 ),"aclk_hevcnp_100" , "div_pclk_hevc" ,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_hevcnd_400" , "mout_aclk_hevc_400_user" ,1 , CLK_IGNORE_UNUSED, 0 ),"aclk_hevc" , "mout_aclk_hevc_400_user" ,0 , 0 , 0 ),/* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */ "aclk_smmu_hevc_1" ,"mout_aclk_hevc_400_user" ,1 , CLK_IGNORE_UNUSED, 0 ),"aclk_smmu_hevc_0" ,"mout_aclk_hevc_400_user" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_HEVC */ "pclk_bts_hevc_1" , "div_pclk_hevc" ,4 , 0 , 0 ),"pclk_bts_hevc_0" , "div_pclk_hevc" ,3 , 0 , 0 ),"pclk_pmu_hevc" , "div_pclk_hevc" ,2 , CLK_IGNORE_UNUSED, 0 ),"pclk_sysreg_hevc" , "div_pclk_hevc" ,1 , CLK_IGNORE_UNUSED, 0 ),"pclk_hevc" , "div_pclk_hevc" ,4 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */ "pclk_smmu_hevc_1" , "div_pclk_hevc" ,1 , CLK_IGNORE_UNUSED, 0 ),"pclk_smmu_hevc_0" , "div_pclk_hevc" ,0 , CLK_IGNORE_UNUSED, 0 ),static const struct samsung_cmu_info hevc_cmu_info __initconst = {"aclk_hevc_400" ,/* * Register offset definitions for CMU_ISP #define MUX_SEL_ISP 0 x0200#define MUX_ENABLE_ISP 0 x0300#define MUX_STAT_ISP 0 x0400#define DIV_ISP 0 x0600#define DIV_STAT_ISP 0 x0700#define ENABLE_ACLK_ISP0 0 x0800#define ENABLE_ACLK_ISP1 0 x0804#define ENABLE_ACLK_ISP2 0 x0808#define ENABLE_PCLK_ISP 0 x0900#define ENABLE_SCLK_ISP 0 x0a00#define ENABLE_IP_ISP0 0 x0b00#define ENABLE_IP_ISP1 0 x0b04#define ENABLE_IP_ISP2 0 x0b08#define ENABLE_IP_ISP3 0 x0b0cstatic const unsigned long isp_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump isp_suspend_regs[] = {0 },"oscclk" , "aclk_isp_dis_400" , };"oscclk" , "aclk_isp_400" , };static const struct samsung_mux_clock isp_mux_clks[] __initconst = {/* MUX_SEL_ISP */ "mout_aclk_isp_dis_400_user" ,4 , 0 ),"mout_aclk_isp_400_user" ,0 , 0 ),static const struct samsung_div_clock isp_div_clks[] __initconst = {/* DIV_ISP */ "div_pclk_isp_dis" ,"mout_aclk_isp_dis_400_user" , DIV_ISP, 12 , 3 ),"div_pclk_isp" , "mout_aclk_isp_400_user" ,8 , 3 ),"div_aclk_isp_d_200" ,"mout_aclk_isp_400_user" , DIV_ISP, 4 , 3 ),"div_aclk_isp_c_200" ,"mout_aclk_isp_400_user" , DIV_ISP, 0 , 3 ),static const struct samsung_gate_clock isp_gate_clks[] __initconst = {/* ENABLE_ACLK_ISP0 */ "aclk_isp_d_glue" , "mout_aclk_isp_400_user" ,6 , CLK_IGNORE_UNUSED, 0 ),"aclk_scalerp" , "mout_aclk_isp_400_user" ,5 , 0 , 0 ),"aclk_3dnr" , "mout_aclk_isp_400_user" ,4 , 0 , 0 ),"aclk_dis" , "mout_aclk_isp_dis_400_user" ,3 , 0 , 0 ),"aclk_scalerc" , "mout_aclk_isp_400_user" ,2 , 0 , 0 ),"aclk_drc" , "mout_aclk_isp_400_user" ,1 , 0 , 0 ),"aclk_isp" , "mout_aclk_isp_400_user" ,0 , 0 , 0 ),/* ENABLE_ACLK_ISP1 */ "aclk_axius_scalerp" ,"mout_aclk_isp_400_user" , ENABLE_ACLK_ISP1,17 , CLK_IGNORE_UNUSED, 0 ),"aclk_axius_scalerc" ,"mout_aclk_isp_400_user" , ENABLE_ACLK_ISP1,16 , CLK_IGNORE_UNUSED, 0 ),"aclk_axius_drc" ,"mout_aclk_isp_400_user" , ENABLE_ACLK_ISP1,15 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncahbm_isp2p" ,"div_pclk_isp" , ENABLE_ACLK_ISP1,14 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncahbm_isp1p" ,"div_pclk_isp" , ENABLE_ACLK_ISP1,13 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_dis1" ,"mout_aclk_isp_dis_400_user" , ENABLE_ACLK_ISP1,12 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_dis0" ,"mout_aclk_isp_dis_400_user" , ENABLE_ACLK_ISP1,11 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_dis1" ,"mout_aclk_isp_400_user" , ENABLE_ACLK_ISP1,10 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_dis0" ,"mout_aclk_isp_400_user" , ENABLE_ACLK_ISP1,9 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_isp2p" ,"div_aclk_isp_d_200" , ENABLE_ACLK_ISP1,8 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_isp1p" ,"div_aclk_isp_c_200" , ENABLE_ACLK_ISP1,7 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb2apb_isp2p" , "div_pclk_isp" ,6 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb2apb_isp1p" , "div_pclk_isp" ,5 , CLK_IGNORE_UNUSED, 0 ),"aclk_axi2apb_isp2p" ,"div_aclk_isp_d_200" , ENABLE_ACLK_ISP1,4 , CLK_IGNORE_UNUSED, 0 ),"aclk_axi2apb_isp1p" ,"div_aclk_isp_c_200" , ENABLE_ACLK_ISP1,3 , CLK_IGNORE_UNUSED, 0 ),"aclk_xiu_ispex1" , "mout_aclk_isp_400_user" ,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_xiu_ispex0" , "mout_aclk_isp_400_user" ,1 , CLK_IGNORE_UNUSED, 0 ),"aclk_ispnd_400" , "mout_aclk_isp_400_user" ,1 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_ACLK_ISP2 */ "aclk_smmu_scalerp" ,"mout_aclk_isp_400_user" , ENABLE_ACLK_ISP2,13 , CLK_IGNORE_UNUSED, 0 ),"aclk_smmu_3dnr" , "mout_aclk_isp_400_user" ,12 , CLK_IGNORE_UNUSED, 0 ),"aclk_smmu_dis1" , "mout_aclk_isp_400_user" ,11 , CLK_IGNORE_UNUSED, 0 ),"aclk_smmu_dis0" , "mout_aclk_isp_400_user" ,10 , CLK_IGNORE_UNUSED, 0 ),"aclk_smmu_scalerc" ,"mout_aclk_isp_400_user" , ENABLE_ACLK_ISP2,9 , CLK_IGNORE_UNUSED, 0 ),"aclk_smmu_drc" , "mout_aclk_isp_400_user" ,8 , CLK_IGNORE_UNUSED, 0 ),"aclk_smmu_isp" , "mout_aclk_isp_400_user" ,7 , CLK_IGNORE_UNUSED, 0 ),"aclk_bts_scalerp" ,"mout_aclk_isp_400_user" , ENABLE_ACLK_ISP2,6 , CLK_IGNORE_UNUSED, 0 ),"aclk_bts_3dnr" , "mout_aclk_isp_400_user" ,5 , CLK_IGNORE_UNUSED, 0 ),"aclk_bts_dis1" , "mout_aclk_isp_400_user" ,4 , CLK_IGNORE_UNUSED, 0 ),"aclk_bts_dis0" , "mout_aclk_isp_400_user" ,3 , CLK_IGNORE_UNUSED, 0 ),"aclk_bts_scalerc" ,"mout_aclk_isp_400_user" , ENABLE_ACLK_ISP2,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_bts_drc" , "mout_aclk_isp_400_user" ,1 , CLK_IGNORE_UNUSED, 0 ),"aclk_bts_isp" , "mout_aclk_isp_400_user" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_ISP */ "pclk_smmu_scalerp" , "div_aclk_isp_d_200" ,25 , CLK_IGNORE_UNUSED, 0 ),"pclk_smmu_3dnr" , "div_aclk_isp_d_200" ,24 , CLK_IGNORE_UNUSED, 0 ),"pclk_smmu_dis1" , "div_aclk_isp_d_200" ,23 , CLK_IGNORE_UNUSED, 0 ),"pclk_smmu_dis0" , "div_aclk_isp_d_200" ,22 , CLK_IGNORE_UNUSED, 0 ),"pclk_smmu_scalerc" , "div_aclk_isp_c_200" ,21 , CLK_IGNORE_UNUSED, 0 ),"pclk_smmu_drc" , "div_aclk_isp_c_200" ,20 , CLK_IGNORE_UNUSED, 0 ),"pclk_smmu_isp" , "div_aclk_isp_c_200" ,19 , CLK_IGNORE_UNUSED, 0 ),"pclk_bts_scalerp" , "div_pclk_isp" ,18 , CLK_IGNORE_UNUSED, 0 ),"pclk_bts_3dnr" , "div_pclk_isp" ,17 , CLK_IGNORE_UNUSED, 0 ),"pclk_bts_dis1" , "div_pclk_isp" ,16 , CLK_IGNORE_UNUSED, 0 ),"pclk_bts_dis0" , "div_pclk_isp" ,15 , CLK_IGNORE_UNUSED, 0 ),"pclk_bts_scalerc" , "div_pclk_isp" ,14 , CLK_IGNORE_UNUSED, 0 ),"pclk_bts_drc" , "div_pclk_isp" ,13 , CLK_IGNORE_UNUSED, 0 ),"pclk_bts_isp" , "div_pclk_isp" ,12 , CLK_IGNORE_UNUSED, 0 ),"pclk_asyncaxi_dis1" , "div_pclk_isp" ,11 , CLK_IGNORE_UNUSED, 0 ),"pclk_asyncaxi_dis0" , "div_pclk_isp" ,10 , CLK_IGNORE_UNUSED, 0 ),"pclk_pmu_isp" , "div_pclk_isp" ,9 , CLK_IGNORE_UNUSED, 0 ),"pclk_sysreg_isp" , "div_pclk_isp" ,8 , CLK_IGNORE_UNUSED, 0 ),"pclk_cmu_isp_local" ,"div_aclk_isp_c_200" , ENABLE_PCLK_ISP,7 , CLK_IGNORE_UNUSED, 0 ),"pclk_scalerp" , "div_aclk_isp_d_200" ,6 , CLK_IGNORE_UNUSED, 0 ),"pclk_3dnr" , "div_aclk_isp_d_200" ,5 , CLK_IGNORE_UNUSED, 0 ),"pclk_dis_core" , "div_pclk_isp_dis" ,4 , CLK_IGNORE_UNUSED, 0 ),"pclk_dis" , "div_aclk_isp_d_200" ,3 , CLK_IGNORE_UNUSED, 0 ),"pclk_scalerc" , "div_aclk_isp_c_200" ,2 , CLK_IGNORE_UNUSED, 0 ),"pclk_drc" , "div_aclk_isp_c_200" ,1 , CLK_IGNORE_UNUSED, 0 ),"pclk_isp" , "div_aclk_isp_c_200" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_SCLK_ISP */ "sclk_pixelasyncs_dis" ,"mout_aclk_isp_dis_400_user" , ENABLE_SCLK_ISP,5 , CLK_IGNORE_UNUSED, 0 ),"sclk_pixelasyncm_dis" ,"mout_aclk_isp_dis_400_user" , ENABLE_SCLK_ISP,4 , CLK_IGNORE_UNUSED, 0 ),"sclk_pixelasyncs_scalerp" ,"mout_aclk_isp_400_user" , ENABLE_SCLK_ISP,3 , CLK_IGNORE_UNUSED, 0 ),"sclk_pixelasyncm_ispd" ,"mout_aclk_isp_400_user" , ENABLE_SCLK_ISP,2 , CLK_IGNORE_UNUSED, 0 ),"sclk_pixelasyncs_ispc" ,"mout_aclk_isp_400_user" , ENABLE_SCLK_ISP,1 , CLK_IGNORE_UNUSED, 0 ),"sclk_pixelasyncm_ispc" ,"mout_aclk_isp_400_user" , ENABLE_SCLK_ISP,0 , CLK_IGNORE_UNUSED, 0 ),static const struct samsung_cmu_info isp_cmu_info __initconst = {"aclk_isp_400" ,/* * Register offset definitions for CMU_CAM0 #define MUX_SEL_CAM00 0 x0200#define MUX_SEL_CAM01 0 x0204#define MUX_SEL_CAM02 0 x0208#define MUX_SEL_CAM03 0 x020c#define MUX_SEL_CAM04 0 x0210#define MUX_ENABLE_CAM00 0 x0300#define MUX_ENABLE_CAM01 0 x0304#define MUX_ENABLE_CAM02 0 x0308#define MUX_ENABLE_CAM03 0 x030c#define MUX_ENABLE_CAM04 0 x0310#define MUX_STAT_CAM00 0 x0400#define MUX_STAT_CAM01 0 x0404#define MUX_STAT_CAM02 0 x0408#define MUX_STAT_CAM03 0 x040c#define MUX_STAT_CAM04 0 x0410#define MUX_IGNORE_CAM01 0 x0504#define DIV_CAM00 0 x0600#define DIV_CAM01 0 x0604#define DIV_CAM02 0 x0608#define DIV_CAM03 0 x060c#define DIV_STAT_CAM00 0 x0700#define DIV_STAT_CAM01 0 x0704#define DIV_STAT_CAM02 0 x0708#define DIV_STAT_CAM03 0 x070c#define ENABLE_ACLK_CAM00 0 X0800#define ENABLE_ACLK_CAM01 0 X0804#define ENABLE_ACLK_CAM02 0 X0808#define ENABLE_PCLK_CAM0 0 X0900#define ENABLE_SCLK_CAM0 0 X0a00#define ENABLE_IP_CAM00 0 X0b00#define ENABLE_IP_CAM01 0 X0b04#define ENABLE_IP_CAM02 0 X0b08#define ENABLE_IP_CAM03 0 X0b0Cstatic const unsigned long cam0_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump cam0_suspend_regs[] = {0 },0 },0 },0 },0 },"oscclk" , "aclk_cam0_333" , };"oscclk" , "aclk_cam0_400" , };"oscclk" , "aclk_cam0_552" , };"oscclk" ,"phyclk_rxbyteclkhs0_s4_phy" , };"oscclk" ,"phyclk_rxbyteclkhs0_s2a_phy" , };"mout_aclk_lite_d_a" ,"mout_aclk_cam0_333_user" , };"mout_aclk_cam0_552_user" ,"mout_aclk_cam0_400_user" , };"mout_aclk_lite_b_a" ,"mout_aclk_cam0_333_user" , };"mout_aclk_cam0_552_user" ,"mout_aclk_cam0_400_user" , };"mout_aclk_lite_a_a" ,"mout_aclk_cam0_333_user" , };"mout_aclk_cam0_552_user" ,"mout_aclk_cam0_400_user" , };"mout_aclk_cam0_400_user" ,"mout_aclk_cam0_333_user" , };"mout_aclk_csis1_a" ,"mout_aclk_cam0_333_user" };"mout_aclk_cam0_552_user" ,"mout_aclk_cam0_400_user" , };"mout_aclk_csis0_a" ,"mout_aclk_cam0_333_user" , };"mout_aclk_cam0_552_user" ,"mout_aclk-cam0_400_user" , };"mout_aclk_3aa1_a" ,"mout_aclk_cam0_333_user" , };"mout_aclk_cam0_552_user" ,"mout_aclk_cam0_400_user" , };"mout_aclk_3aa0_a" ,"mout_aclk_cam0_333_user" , };"mout_aclk_cam0_552_user" ,"mout_aclk_cam0_400_user" , };"mout_sclk_lite_freecnt_b" ,"div_pclk_lite_d" , };"mout_sclk_lite_freecnt_a" ,"div_pclk_pixelasync_lite_c" , };"div_pclk_lite_a" ,"div_pclk_lite_b" , };"mout_sclk_pixelasync_lite_c_a" ,"mout_aclk_cam0_333_user" , };"mout_aclk_cam0_552_user" ,"mout_aclk_cam0_400_user" , };"mout_sclk_pixelasync_lite_c_init_a" ,"mout_aclk_cam0_400_user" , };"mout_aclk_cam0_552_user" ,"mout_aclk_cam0_400_user" , };static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = {"phyclk_rxbyteclkhs0_s4_phy" ,0 , 100000000 ),"phyclk_rxbyteclkhs0_s2a_phy" ,0 , 100000000 ),static const struct samsung_mux_clock cam0_mux_clks[] __initconst = {/* MUX_SEL_CAM00 */ "mout_aclk_cam0_333_user" ,8 , 1 ),"mout_aclk_cam0_400_user" ,4 , 1 ),"mout_aclk_cam0_552_user" ,0 , 1 ),/* MUX_SEL_CAM01 */ "mout_phyclk_rxbyteclkhs0_s4_user" ,4 , 1 ),"mout_phyclk_rxbyteclkhs0_s2a_user" ,0 , 1 ),/* MUX_SEL_CAM02 */ "mout_aclk_lite_d_b" , mout_aclk_lite_d_b_p,24 , 1 ),"mout_aclk_lite_d_a" , mout_aclk_lite_d_a_p,20 , 1 ),"mout_aclk_lite_b_b" , mout_aclk_lite_b_b_p,16 , 1 ),"mout_aclk_lite_b_a" , mout_aclk_lite_b_a_p,12 , 1 ),"mout_aclk_lite_a_b" , mout_aclk_lite_a_b_p,8 , 1 ),"mout_aclk_lite_a_a" , mout_aclk_lite_a_a_p,4 , 1 ),"mout_aclk_cam0_400" , mout_aclk_cam0_400_p,0 , 1 ),/* MUX_SEL_CAM03 */ "mout_aclk_csis1_b" , mout_aclk_csis1_b_p,28 , 1 ),"mout_aclk_csis1_a" , mout_aclk_csis1_a_p,24 , 1 ),"mout_aclk_csis0_b" , mout_aclk_csis0_b_p,20 , 1 ),"mout_aclk_csis0_a" , mout_aclk_csis0_a_p,16 , 1 ),"mout_aclk_3aa1_b" , mout_aclk_3aa1_b_p,12 , 1 ),"mout_aclk_3aa1_a" , mout_aclk_3aa1_a_p,8 , 1 ),"mout_aclk_3aa0_b" , mout_aclk_3aa0_b_p,4 , 1 ),"mout_aclk_3aa0_a" , mout_aclk_3aa0_a_p,0 , 1 ),/* MUX_SEL_CAM04 */ "mout_sclk_lite_freecnt_c" ,24 , 1 ),"mout_sclk_lite_freecnt_b" ,20 , 1 ),"mout_sclk_lite_freecnt_a" ,16 , 1 ),"mout_sclk_pixelasync_lite_c_b" ,12 , 1 ),"mout_sclk_pixelasync_lite_c_a" ,8 , 1 ),"mout_sclk_pixelasync_lite_c_init_b" ,4 , 1 ),"mout_sclk_pixelasync_lite_c_init_a" ,0 , 1 ),static const struct samsung_div_clock cam0_div_clks[] __initconst = {/* DIV_CAM00 */ "div_pclk_cam0_50" , "div_aclk_cam0_200" ,8 , 2 ),"div_aclk_cam0_200" , "mout_aclk_cam0_400" ,4 , 3 ),"div_aclk_cam0_bus_400" ,"mout_aclk_cam0_400" , DIV_CAM00, 0 , 3 ),/* DIV_CAM01 */ "div_pclk_lite_d" , "div_aclk_lite_d" ,20 , 2 ),"div_aclk_lite_d" , "mout_aclk_lite_d_b" ,16 , 3 ),"div_pclk_lite_b" , "div_aclk_lite_b" ,12 , 2 ),"div_aclk_lite_b" , "mout_aclk_lite_b_b" ,8 , 3 ),"div_pclk_lite_a" , "div_aclk_lite_a" ,4 , 2 ),"div_aclk_lite_a" , "mout_aclk_lite_a_b" ,0 , 3 ),/* DIV_CAM02 */ "div_aclk_csis1" , "mout_aclk_csis1_b" ,20 , 3 ),"div_aclk_csis0" , "mout_aclk_csis0_b" ,16 , 3 ),"div_pclk_3aa1" , "div_aclk_3aa1" ,12 , 2 ),"div_aclk_3aa1" , "mout_aclk_3aa1_b" ,8 , 3 ),"div_pclk_3aa0" , "div_aclk_3aa0" ,4 , 2 ),"div_aclk_3aa0" , "mout_aclk_3aa0_b" ,0 , 3 ),/* DIV_CAM03 */ "div_sclk_pixelasync_lite_c" ,"mout_sclk_pixelasync_lite_c_b" , DIV_CAM03, 8 , 3 ),"div_pclk_pixelasync_lite_c" ,"div_sclk_pixelasync_lite_c_init" , DIV_CAM03, 4 , 2 ),"div_sclk_pixelasync_lite_c_init" ,"mout_sclk_pixelasync_lite_c_init_b" , DIV_CAM03, 0 , 3 ),static const struct samsung_gate_clock cam0_gate_clks[] __initconst = {/* ENABLE_ACLK_CAM00 */ "aclk_csis1" , "div_aclk_csis1" , ENABLE_ACLK_CAM00,6 , 0 , 0 ),"aclk_csis0" , "div_aclk_csis0" , ENABLE_ACLK_CAM00,5 , 0 , 0 ),"aclk_3aa1" , "div_aclk_3aa1" , ENABLE_ACLK_CAM00,4 , 0 , 0 ),"aclk_3aa0" , "div_aclk_3aa0" , ENABLE_ACLK_CAM00,3 , 0 , 0 ),"aclk_lite_d" , "div_aclk_lite_d" ,2 , 0 , 0 ),"aclk_lite_b" , "div_aclk_lite_b" ,1 , 0 , 0 ),"aclk_lite_a" , "div_aclk_lite_a" ,0 , 0 , 0 ),/* ENABLE_ACLK_CAM01 */ "aclk_ahbsyncdn" , "div_aclk_cam0_200" ,31 , CLK_IGNORE_UNUSED, 0 ),"aclk_axius_lite_d" , "div_aclk_cam0_bus_400" ,30 , CLK_IGNORE_UNUSED, 0 ),"aclk_axius_lite_b" , "div_aclk_cam0_bus_400" ,29 , CLK_IGNORE_UNUSED, 0 ),"aclk_axius_lite_a" , "div_aclk_cam0_bus_400" ,28 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncapbm_3aa1" , "div_pclk_3aa1" ,27 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncapbs_3aa1" , "div_aclk_3aa1" ,26 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncapbm_3aa0" , "div_pclk_3aa0" ,25 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncapbs_3aa0" , "div_aclk_3aa0" ,24 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncapbm_lite_d" ,"div_pclk_lite_d" , ENABLE_ACLK_CAM01,23 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncapbs_lite_d" ,"div_aclk_cam0_200" , ENABLE_ACLK_CAM01,22 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncapbm_lite_b" ,"div_pclk_lite_b" , ENABLE_ACLK_CAM01,21 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncapbs_lite_b" ,"div_aclk_cam0_200" , ENABLE_ACLK_CAM01,20 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncapbm_lite_a" ,"div_pclk_lite_a" , ENABLE_ACLK_CAM01,19 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncapbs_lite_a" ,"div_aclk_cam0_200" , ENABLE_ACLK_CAM01,18 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_isp0p" ,"div_aclk_cam0_200" , ENABLE_ACLK_CAM01,17 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_3aa1" ,"div_aclk_cam0_bus_400" , ENABLE_ACLK_CAM01,16 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_3aa1" ,"div_aclk_3aa1" , ENABLE_ACLK_CAM01,15 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_3aa0" ,"div_aclk_cam0_bus_400" , ENABLE_ACLK_CAM01,14 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_3aa0" ,"div_aclk_3aa0" , ENABLE_ACLK_CAM01,13 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_lite_d" ,"div_aclk_cam0_bus_400" , ENABLE_ACLK_CAM01,12 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_lite_d" ,"div_aclk_lite_d" , ENABLE_ACLK_CAM01,11 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_lite_b" ,"div_aclk_cam0_bus_400" , ENABLE_ACLK_CAM01,10 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_lite_b" ,"div_aclk_lite_b" , ENABLE_ACLK_CAM01,9 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_lite_a" ,"div_aclk_cam0_bus_400" , ENABLE_ACLK_CAM01,8 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_lite_a" ,"div_aclk_lite_a" , ENABLE_ACLK_CAM01,7 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb2apb_ispsfrp" ,"div_pclk_cam0_50" , ENABLE_ACLK_CAM01,6 , CLK_IGNORE_UNUSED, 0 ),"aclk_axi2apb_isp0p" , "div_aclk_cam0_200" ,5 , CLK_IGNORE_UNUSED, 0 ),"aclk_axi2ahb_isp0p" , "div_aclk_cam0_200" ,4 , CLK_IGNORE_UNUSED, 0 ),"aclk_xiu_is0x" , "div_aclk_cam0_200" ,3 , CLK_IGNORE_UNUSED, 0 ),"aclk_xiu_isp0ex" , "div_aclk_cam0_bus_400" ,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_cam0np_276" , "div_aclk_cam0_200" ,1 , CLK_IGNORE_UNUSED, 0 ),"aclk_cam0nd_400" , "div_aclk_cam0_bus_400" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_ACLK_CAM02 */ "aclk_smmu_3aa1" , "div_aclk_cam0_bus_400" ,9 , CLK_IGNORE_UNUSED, 0 ),"aclk_smmu_3aa0" , "div_aclk_cam0_bus_400" ,8 , CLK_IGNORE_UNUSED, 0 ),"aclk_smmu_lite_d" , "div_aclk_cam0_bus_400" ,7 , CLK_IGNORE_UNUSED, 0 ),"aclk_smmu_lite_b" , "div_aclk_cam0_bus_400" ,6 , CLK_IGNORE_UNUSED, 0 ),"aclk_smmu_lite_a" , "div_aclk_cam0_bus_400" ,5 , CLK_IGNORE_UNUSED, 0 ),"aclk_bts_3aa1" , "div_aclk_cam0_bus_400" ,4 , CLK_IGNORE_UNUSED, 0 ),"aclk_bts_3aa0" , "div_aclk_cam0_bus_400" ,3 , CLK_IGNORE_UNUSED, 0 ),"aclk_bts_lite_d" , "div_aclk_cam0_bus_400" ,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_bts_lite_b" , "div_aclk_cam0_bus_400" ,1 , CLK_IGNORE_UNUSED, 0 ),"aclk_bts_lite_a" , "div_aclk_cam0_bus_400" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_CAM0 */ "pclk_smmu_3aa1" , "div_aclk_cam0_200" ,25 , CLK_IGNORE_UNUSED, 0 ),"pclk_smmu_3aa0" , "div_aclk_cam0_200" ,24 , CLK_IGNORE_UNUSED, 0 ),"pclk_smmu_lite_d" , "div_aclk_cam0_200" ,23 , CLK_IGNORE_UNUSED, 0 ),"pclk_smmu_lite_b" , "div_aclk_cam0_200" ,22 , CLK_IGNORE_UNUSED, 0 ),"pclk_smmu_lite_a" , "div_aclk_cam0_200" ,21 , CLK_IGNORE_UNUSED, 0 ),"pclk_bts_3aa1" , "div_pclk_cam0_50" ,20 , CLK_IGNORE_UNUSED, 0 ),"pclk_bts_3aa0" , "div_pclk_cam0_50" ,19 , CLK_IGNORE_UNUSED, 0 ),"pclk_bts_lite_d" , "div_pclk_cam0_50" ,18 , CLK_IGNORE_UNUSED, 0 ),"pclk_bts_lite_b" , "div_pclk_cam0_50" ,17 , CLK_IGNORE_UNUSED, 0 ),"pclk_bts_lite_a" , "div_pclk_cam0_50" ,16 , CLK_IGNORE_UNUSED, 0 ),"pclk_asyncaxi_cam1" , "div_pclk_cam0_50" ,15 , CLK_IGNORE_UNUSED, 0 ),"pclk_asyncaxi_3aa1" , "div_pclk_cam0_50" ,14 , CLK_IGNORE_UNUSED, 0 ),"pclk_asyncaxi_3aa0" , "div_pclk_cam0_50" ,13 , CLK_IGNORE_UNUSED, 0 ),"pclk_asyncaxi_lite_d" ,"div_pclk_cam0_50" , ENABLE_PCLK_CAM0,12 , CLK_IGNORE_UNUSED, 0 ),"pclk_asyncaxi_lite_b" ,"div_pclk_cam0_50" , ENABLE_PCLK_CAM0,11 , CLK_IGNORE_UNUSED, 0 ),"pclk_asyncaxi_lite_a" ,"div_pclk_cam0_50" , ENABLE_PCLK_CAM0,10 , CLK_IGNORE_UNUSED, 0 ),"pclk_pmu_cam0" , "div_pclk_cam0_50" ,9 , CLK_IGNORE_UNUSED, 0 ),"pclk_sysreg_cam0" , "div_pclk_cam0_50" ,8 , CLK_IGNORE_UNUSED, 0 ),"pclk_cmu_cam0_local" ,"div_aclk_cam0_200" , ENABLE_PCLK_CAM0,7 , CLK_IGNORE_UNUSED, 0 ),"pclk_csis1" , "div_aclk_cam0_200" ,6 , CLK_IGNORE_UNUSED, 0 ),"pclk_csis0" , "div_aclk_cam0_200" ,5 , CLK_IGNORE_UNUSED, 0 ),"pclk_3aa1" , "div_pclk_3aa1" ,4 , CLK_IGNORE_UNUSED, 0 ),"pclk_3aa0" , "div_pclk_3aa0" ,3 , CLK_IGNORE_UNUSED, 0 ),"pclk_lite_d" , "div_pclk_lite_d" ,2 , CLK_IGNORE_UNUSED, 0 ),"pclk_lite_b" , "div_pclk_lite_b" ,1 , CLK_IGNORE_UNUSED, 0 ),"pclk_lite_a" , "div_pclk_lite_a" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_SCLK_CAM0 */ "phyclk_rxbyteclkhs0_s4" ,"mout_phyclk_rxbyteclkhs0_s4_user" ,8 , 0 , 0 ),"phyclk_rxbyteclkhs0_s2a" ,"mout_phyclk_rxbyteclkhs0_s2a_user" ,7 , 0 , 0 ),"sclk_lite_freecnt" ,"mout_sclk_lite_freecnt_c" , ENABLE_SCLK_CAM0, 6 , 0 , 0 ),"sclk_pixelasycm_3aa1" ,"div_aclk_3aa1" , ENABLE_SCLK_CAM0, 5 , 0 , 0 ),"sclk_pixelasycm_3aa0" ,"div_aclk_3aa0" , ENABLE_SCLK_CAM0, 4 , 0 , 0 ),"sclk_pixelasycs_3aa0" ,"div_aclk_3aa0" , ENABLE_SCLK_CAM0, 3 , 0 , 0 ),"sclk_pixelasyncm_lite_c" ,"div_sclk_pixelasync_lite_c" ,2 , 0 , 0 ),"sclk_pixelasyncm_lite_c_init" ,"div_sclk_pixelasync_lite_c_init" ,1 , 0 , 0 ),"sclk_pixelasyncs_lite_c_init" ,"div_sclk_pixelasync_lite_c" ,0 , 0 , 0 ),static const struct samsung_cmu_info cam0_cmu_info __initconst = {"aclk_cam0_400" ,/* * Register offset definitions for CMU_CAM1 #define MUX_SEL_CAM10 0 x0200#define MUX_SEL_CAM11 0 x0204#define MUX_SEL_CAM12 0 x0208#define MUX_ENABLE_CAM10 0 x0300#define MUX_ENABLE_CAM11 0 x0304#define MUX_ENABLE_CAM12 0 x0308#define MUX_STAT_CAM10 0 x0400#define MUX_STAT_CAM11 0 x0404#define MUX_STAT_CAM12 0 x0408#define MUX_IGNORE_CAM11 0 x0504#define DIV_CAM10 0 x0600#define DIV_CAM11 0 x0604#define DIV_STAT_CAM10 0 x0700#define DIV_STAT_CAM11 0 x0704#define ENABLE_ACLK_CAM10 0 X0800#define ENABLE_ACLK_CAM11 0 X0804#define ENABLE_ACLK_CAM12 0 X0808#define ENABLE_PCLK_CAM1 0 X0900#define ENABLE_SCLK_CAM1 0 X0a00#define ENABLE_IP_CAM10 0 X0b00#define ENABLE_IP_CAM11 0 X0b04#define ENABLE_IP_CAM12 0 X0b08static const unsigned long cam1_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump cam1_suspend_regs[] = {0 },0 },0 },"oscclk" , "sclk_isp_uart_cam1" , };"oscclk" , "sclk_isp_spi1_cam1" , };"oscclk" , "sclk_isp_spi0_cam1" , };"oscclk" , "aclk_cam1_333" , };"oscclk" , "aclk_cam1_400" , };"oscclk" , "aclk_cam1_552" , };"oscclk" ,"phyclk_rxbyteclkhs0_s2b_phy" , };"mout_aclk_csis2_a" ,"mout_aclk_cam1_333_user" , };"mout_aclk_cam1_552_user" ,"mout_aclk_cam1_400_user" , };"mout_aclk_fd_a" ,"mout_aclk_cam1_333_user" , };"mout_aclk_cam1_552_user" ,"mout_aclk_cam1_400_user" , };"mout_aclk_lite_c_a" ,"mout_aclk_cam1_333_user" , };"mout_aclk_cam1_552_user" ,"mout_aclk_cam1_400_user" , };static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = {"phyclk_rxbyteclkhs0_s2b_phy" , NULL,0 , 100000000 ),static const struct samsung_mux_clock cam1_mux_clks[] __initconst = {/* MUX_SEL_CAM10 */ "mout_sclk_isp_uart_user" ,20 , 1 ),"mout_sclk_isp_spi1_user" ,16 , 1 ),"mout_sclk_isp_spi0_user" ,12 , 1 ),"mout_aclk_cam1_333_user" ,8 , 1 ),"mout_aclk_cam1_400_user" ,4 , 1 ),"mout_aclk_cam1_552_user" ,0 , 1 ),/* MUX_SEL_CAM11 */ "mout_phyclk_rxbyteclkhs0_s2b_user" ,0 , 1 ),/* MUX_SEL_CAM12 */ "mout_aclk_csis2_b" , mout_aclk_csis2_b_p,20 , 1 ),"mout_aclk_csis2_a" , mout_aclk_csis2_a_p,16 , 1 ),"mout_aclk_fd_b" , mout_aclk_fd_b_p,12 , 1 ),"mout_aclk_fd_a" , mout_aclk_fd_a_p,8 , 1 ),"mout_aclk_lite_c_b" , mout_aclk_lite_c_b_p,4 , 1 ),"mout_aclk_lite_c_a" , mout_aclk_lite_c_a_p,0 , 1 ),static const struct samsung_div_clock cam1_div_clks[] __initconst = {/* DIV_CAM10 */ "div_sclk_isp_mpwm" ,"div_pclk_cam1_83" , DIV_CAM10, 16 , 2 ),"div_pclk_cam1_83" ,"mout_aclk_cam1_333_user" , DIV_CAM10, 12 , 2 ),"div_pclk_cam1_166" ,"mout_aclk_cam1_333_user" , DIV_CAM10, 8 , 2 ),"div_pclk_dbg_cam1" ,"mout_aclk_cam1_552_user" , DIV_CAM10, 4 , 3 ),"div_atclk_cam1" , "mout_aclk_cam1_552_user" ,0 , 3 ),/* DIV_CAM11 */ "div_aclk_csis2" , "mout_aclk_csis2_b" ,16 , 3 ),"div_pclk_fd" , "div_aclk_fd" , DIV_CAM11, 12 , 2 ),"div_aclk_fd" , "mout_aclk_fd_b" , DIV_CAM11, 8 , 3 ),"div_pclk_lite_c" , "div_aclk_lite_c" ,4 , 2 ),"div_aclk_lite_c" , "mout_aclk_lite_c_b" ,0 , 3 ),static const struct samsung_gate_clock cam1_gate_clks[] __initconst = {/* ENABLE_ACLK_CAM10 */ "aclk_isp_gic" , "mout_aclk_cam1_333_user" ,4 , 0 , 0 ),"aclk_fd" , "div_aclk_fd" ,3 , 0 , 0 ),"aclk_lite_c" , "div_aclk_lite_c" ,1 , 0 , 0 ),"aclk_csis2" , "div_aclk_csis2" ,0 , 0 , 0 ),/* ENABLE_ACLK_CAM11 */ "aclk_asyncapbm_fd" , "div_pclk_fd" ,29 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncapbs_fd" , "div_pclk_cam1_166" ,28 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncapbm_lite_c" ,"div_pclk_lite_c" , ENABLE_ACLK_CAM11,27 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncapbs_lite_c" ,"div_pclk_cam1_166" , ENABLE_ACLK_CAM11,26 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncahbs_sfrisp2h2" ,"div_pclk_cam1_83" , ENABLE_ACLK_CAM11,25 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncahbs_sfrisp2h1" ,"div_pclk_cam1_83" , ENABLE_ACLK_CAM11,24 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_ca5" ,"mout_aclk_cam1_333_user" , ENABLE_ACLK_CAM11,23 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_ca5" ,"mout_aclk_cam1_552_user" , ENABLE_ACLK_CAM11,22 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_ispx2" ,"mout_aclk_cam1_333_user" , ENABLE_ACLK_CAM11,21 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_ispx1" ,"mout_aclk_cam1_333_user" , ENABLE_ACLK_CAM11,20 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_ispx0" ,"mout_aclk_cam1_333_user" , ENABLE_ACLK_CAM11,19 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_ispex" ,"mout_aclk_cam1_400_user" , ENABLE_ACLK_CAM11,18 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_isp3p" ,"mout_aclk_cam1_400_user" , ENABLE_ACLK_CAM11,17 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_isp3p" ,"mout_aclk_cam1_333_user" , ENABLE_ACLK_CAM11,16 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_fd" ,"mout_aclk_cam1_400_user" , ENABLE_ACLK_CAM11,15 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_fd" , "div_aclk_fd" ,14 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxim_lite_c" ,"mout_aclk_cam1_400_user" , ENABLE_ACLK_CAM11,13 , CLK_IGNORE_UNUSED, 0 ),"aclk_asyncaxis_lite_c" ,"div_aclk_lite_c" , ENABLE_ACLK_CAM11,12 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb2apb_isp5p" , "div_pclk_cam1_83" ,11 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb2apb_isp3p" , "div_pclk_cam1_83" ,10 , CLK_IGNORE_UNUSED, 0 ),"aclk_axi2apb_isp3p" ,"mout_aclk_cam1_333_user" , ENABLE_ACLK_CAM11,9 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahb_sfrisp2h" , "div_pclk_cam1_83" ,8 , CLK_IGNORE_UNUSED, 0 ),"aclk_axi_isp_hx_r" , "div_pclk_cam1_166" ,7 , CLK_IGNORE_UNUSED, 0 ),"aclk_axi_isp_cx_r" , "div_pclk_cam1_166" ,6 , CLK_IGNORE_UNUSED, 0 ),"aclk_axi_isp_hx" , "mout_aclk_cam1_333_user" ,5 , CLK_IGNORE_UNUSED, 0 ),"aclk_axi_isp_cx" , "mout_aclk_cam1_333_user" ,4 , CLK_IGNORE_UNUSED, 0 ),"aclk_xiu_ispx" , "mout_aclk_cam1_333_user" ,3 , CLK_IGNORE_UNUSED, 0 ),"aclk_xiu_ispex" , "mout_aclk_cam1_400_user" ,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_cam1np_333" , "mout_aclk_cam1_333_user" ,1 , CLK_IGNORE_UNUSED, 0 ),"aclk_cam1nd_400" , "mout_aclk_cam1_400_user" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_ACLK_CAM12 */ "aclk_smmu_ispcpu" ,"mout_aclk_cam1_400_user" , ENABLE_ACLK_CAM12,10 , CLK_IGNORE_UNUSED, 0 ),"aclk_smmu_fd" , "mout_aclk_cam1_400_user" ,9 , CLK_IGNORE_UNUSED, 0 ),"aclk_smmu_lite_c" ,"mout_aclk_cam1_400_user" , ENABLE_ACLK_CAM12,8 , CLK_IGNORE_UNUSED, 0 ),"aclk_bts_isp3p" , "mout_aclk_cam1_400_user" ,7 , CLK_IGNORE_UNUSED, 0 ),"aclk_bts_fd" , "mout_aclk_cam1_400_user" ,6 , CLK_IGNORE_UNUSED, 0 ),"aclk_bts_lite_c" , "mout_aclk_cam1_400_user" ,5 , CLK_IGNORE_UNUSED, 0 ),"aclk_ahbdn_sfrisp2h" ,"mout_aclk_cam1_333_user" , ENABLE_ACLK_CAM12,4 , CLK_IGNORE_UNUSED, 0 ),"aclk_aclk-shbdn_isp5p" ,"mout_aclk_cam1_333_user" , ENABLE_ACLK_CAM12,3 , CLK_IGNORE_UNUSED, 0 ),"aclk_axius_isp3p" ,"mout_aclk_cam1_400_user" , ENABLE_ACLK_CAM12,2 , CLK_IGNORE_UNUSED, 0 ),"aclk_axius_fd" , "mout_aclk_cam1_400_user" ,1 , CLK_IGNORE_UNUSED, 0 ),"aclk_axius_lite_c" ,"mout_aclk_cam1_400_user" , ENABLE_ACLK_CAM12,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_CAM1 */ "pclk_smmu_ispcpu" , "div_pclk_cam1_166" ,27 , CLK_IGNORE_UNUSED, 0 ),"pclk_smmu_fd" , "div_pclk_cam1_166" ,26 , CLK_IGNORE_UNUSED, 0 ),"pclk_smmu_lite_c" , "div_pclk_cam1_166" ,25 , CLK_IGNORE_UNUSED, 0 ),"pclk_bts_isp3p" , "div_pclk_cam1_83" ,24 , CLK_IGNORE_UNUSED, 0 ),"pclk_bts_fd" , "div_pclk_cam1_83" ,23 , CLK_IGNORE_UNUSED, 0 ),"pclk_bts_lite_c" , "div_pclk_cam1_83" ,22 , CLK_IGNORE_UNUSED, 0 ),"pclk_asyncaxim_ca5" , "div_pclk_cam1_166" ,21 , CLK_IGNORE_UNUSED, 0 ),"pclk_asyncaxim_ispex" ,"div_pclk_cam1_83" , ENABLE_PCLK_CAM1,20 , CLK_IGNORE_UNUSED, 0 ),"pclk_asyncaxim_isp3p" ,"div_pclk_cam1_83" , ENABLE_PCLK_CAM1,19 , CLK_IGNORE_UNUSED, 0 ),"pclk_asyncaxim_fd" , "div_pclk_cam1_83" ,18 , CLK_IGNORE_UNUSED, 0 ),"pclk_asyncaxim_lite_c" ,"div_pclk_cam1_83" , ENABLE_PCLK_CAM1,17 , CLK_IGNORE_UNUSED, 0 ),"pclk_pmu_cam1" , "div_pclk_cam1_83" ,16 , CLK_IGNORE_UNUSED, 0 ),"pclk_sysreg_cam1" , "div_pclk_cam1_83" ,15 , CLK_IGNORE_UNUSED, 0 ),"pclk_cmu_cam1_local" ,"div_pclk_cam1_166" , ENABLE_PCLK_CAM1,14 , CLK_IGNORE_UNUSED, 0 ),"pclk_isp_mctadc" , "div_pclk_cam1_83" ,13 , CLK_IGNORE_UNUSED, 0 ),"pclk_isp_wdt" , "div_pclk_cam1_83" ,12 , CLK_IGNORE_UNUSED, 0 ),"pclk_isp_pwm" , "div_pclk_cam1_83" ,11 , CLK_IGNORE_UNUSED, 0 ),"pclk_isp_uart" , "div_pclk_cam1_83" ,10 , CLK_IGNORE_UNUSED, 0 ),"pclk_isp_mcuctl" , "div_pclk_cam1_83" ,9 , CLK_IGNORE_UNUSED, 0 ),"pclk_isp_spi1" , "div_pclk_cam1_83" ,8 , CLK_IGNORE_UNUSED, 0 ),"pclk_isp_spi0" , "div_pclk_cam1_83" ,7 , CLK_IGNORE_UNUSED, 0 ),"pclk_isp_i2c2" , "div_pclk_cam1_83" ,6 , CLK_IGNORE_UNUSED, 0 ),"pclk_isp_i2c1" , "div_pclk_cam1_83" ,5 , CLK_IGNORE_UNUSED, 0 ),"pclk_isp_i2c0" , "div_pclk_cam1_83" ,4 , CLK_IGNORE_UNUSED, 0 ),"pclk_isp_mpwm" , "div_pclk_cam1_83" ,3 , CLK_IGNORE_UNUSED, 0 ),"pclk_fd" , "div_pclk_fd" ,3 , CLK_IGNORE_UNUSED, 0 ),"pclk_lite_c" , "div_pclk_lite_c" ,1 , CLK_IGNORE_UNUSED, 0 ),"pclk_csis2" , "div_pclk_cam1_166" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_SCLK_CAM1 */ "sclk_isp_i2c2" , "oscclk" , ENABLE_SCLK_CAM1,15 , 0 , 0 ),"sclk_isp_i2c1" , "oscclk" , ENABLE_SCLK_CAM1,14 , 0 , 0 ),"sclk_isp_i2c0" , "oscclk" , ENABLE_SCLK_CAM1,13 , 0 , 0 ),"sclk_isp_pwm" , "oscclk" , ENABLE_SCLK_CAM1,12 , 0 , 0 ),"phyclk_rxbyteclkhs0_s2b" ,"mout_phyclk_rxbyteclkhs0_s2b_user" ,11 , 0 , 0 ),"sclk_lite_c_freecnt" , "div_pclk_lite_c" ,10 , 0 , 0 ),"sclk_pixelasyncm_fd" , "div_aclk_fd" ,9 , 0 , 0 ),"sclk_isp_mctadc" , "sclk_isp_mctadc_cam1" ,7 , 0 , 0 ),"sclk_isp_uart" , "mout_sclk_isp_uart_user" ,6 , 0 , 0 ),"sclk_isp_spi1" , "mout_sclk_isp_spi1_user" ,5 , 0 , 0 ),"sclk_isp_spi0" , "mout_sclk_isp_spi0_user" ,4 , 0 , 0 ),"sclk_isp_mpwm" , "div_sclk_isp_mpwm" ,3 , 0 , 0 ),"sclk_dbg_isp" , "div_pclk_dbg_cam1" ,2 , 0 , 0 ),"atclk_isp" , "div_atclk_cam1" ,1 , 0 , 0 ),"sclk_isp_ca5" , "mout_aclk_cam1_552_user" ,0 , 0 , 0 ),static const struct samsung_cmu_info cam1_cmu_info __initconst = {"aclk_cam1_400" ,/* * Register offset definitions for CMU_IMEM #define ENABLE_ACLK_IMEM_SLIMSSS 0 x080c#define ENABLE_PCLK_IMEM_SLIMSSS 0 x0908static const unsigned long imem_clk_regs[] __initconst = {static const struct samsung_gate_clock imem_gate_clks[] __initconst = {/* ENABLE_ACLK_IMEM_SLIMSSS */ "aclk_slimsss" , "aclk_imem_sssx_266" ,0 , CLK_IGNORE_UNUSED, 0 ),/* ENABLE_PCLK_IMEM_SLIMSSS */ "pclk_slimsss" , "aclk_imem_200" ,0 , CLK_IGNORE_UNUSED, 0 ),static const struct samsung_cmu_info imem_cmu_info __initconst = {"aclk_imem_200" ,static int __init exynos5433_cmu_probe(struct platform_device *pdev)return exynos_arm64_register_cmu_pm(pdev, false );static const struct of_device_id exynos5433_cmu_of_match[] = {"samsung,exynos5433-cmu-aud" ,"samsung,exynos5433-cmu-cam0" ,"samsung,exynos5433-cmu-cam1" ,"samsung,exynos5433-cmu-disp" ,"samsung,exynos5433-cmu-g2d" ,"samsung,exynos5433-cmu-g3d" ,"samsung,exynos5433-cmu-fsys" ,"samsung,exynos5433-cmu-gscl" ,"samsung,exynos5433-cmu-mfc" ,"samsung,exynos5433-cmu-hevc" ,"samsung,exynos5433-cmu-isp" ,"samsung,exynos5433-cmu-mscl" ,"samsung,exynos5433-cmu-imem" ,static const struct dev_pm_ops exynos5433_cmu_pm_ops = {static struct platform_driver exynos5433_cmu_driver __refdata = {"exynos5433-cmu" ,true ,static int __init exynos5433_cmu_init(void )return platform_driver_register(&exynos5433_cmu_driver);
Messung V0.5 in Prozent C=97 H=100 G=98
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