// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2014 Samsung Electronics Co., Ltd. * Author: Chanwoo Choi <cw00.choi@samsung.com> * * Common Clock Framework support for Exynos5433 SoC. #include <linux/clk-provider.h>#include <linux/mod_devicetable.h>#include <linux/platform_device.h>#include <linux/pm_runtime.h>#include <linux/slab.h>#include <dt-bindings/clock/exynos5433.h>#include "clk.h" #include "clk-cpu.h" #include "clk-exynos-arm64.h" #include "clk-pll.h" /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_TOP (CLK_SCLK_HDMI_SPDIF_DISP + 1)#define CLKS_NR_CPIF (CLK_SCLK_UFS_MPHY + 1)#define CLKS_NR_MIF (CLK_SCLK_BUS_PLL_ATLAS + 1)#define CLKS_NR_PERIC (CLK_DIV_SCLK_SC_IN + 1)#define CLKS_NR_PERIS (CLK_SCLK_OTP_CON + 1)#define CLKS_NR_FSYS (CLK_PCIE + 1)#define CLKS_NR_G2D (CLK_PCLK_SMMU_G2D + 1)#define CLKS_NR_DISP (CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY + 1)#define CLKS_NR_AUD (CLK_SCLK_AUD_I2S + 1)#define CLKS_NR_BUSX (CLK_ACLK_BUS2RTND_400 + 1)#define CLKS_NR_G3D (CLK_SCLK_HPM_G3D + 1)#define CLKS_NR_GSCL (CLK_PCLK_SMMU_GSCL2 + 1)#define CLKS_NR_APOLLO (CLK_SCLK_APOLLO + 1)#define CLKS_NR_ATLAS (CLK_SCLK_ATLAS + 1)#define CLKS_NR_MSCL (CLK_SCLK_JPEG + 1)#define CLKS_NR_MFC (CLK_PCLK_SMMU_MFC_0 + 1)#define CLKS_NR_HEVC (CLK_PCLK_SMMU_HEVC_0 + 1)#define CLKS_NR_ISP (CLK_SCLK_PIXELASYNCM_ISPC + 1)#define CLKS_NR_CAM0 (CLK_SCLK_PIXELASYNCS_LITE_C_INIT + 1)#define CLKS_NR_CAM1 (CLK_SCLK_ISP_CA5 + 1)#define CLKS_NR_IMEM (CLK_PCLK_SLIMSSS + 1)/* * Register offset definitions for CMU_TOP #define ISP_PLL_LOCK 0x0000#define AUD_PLL_LOCK 0x0004#define ISP_PLL_CON0 0x0100#define ISP_PLL_CON1 0x0104#define ISP_PLL_FREQ_DET 0x0108#define AUD_PLL_CON0 0x0110#define AUD_PLL_CON1 0x0114#define AUD_PLL_CON2 0x0118#define AUD_PLL_FREQ_DET 0x011c#define MUX_SEL_TOP0 0x0200#define MUX_SEL_TOP1 0x0204#define MUX_SEL_TOP2 0x0208#define MUX_SEL_TOP3 0x020c#define MUX_SEL_TOP4 0x0210#define MUX_SEL_TOP_MSCL 0x0220#define MUX_SEL_TOP_CAM1 0x0224#define MUX_SEL_TOP_DISP 0x0228#define MUX_SEL_TOP_FSYS0 0x0230#define MUX_SEL_TOP_FSYS1 0x0234#define MUX_SEL_TOP_PERIC0 0x0238#define MUX_SEL_TOP_PERIC1 0x023c#define MUX_ENABLE_TOP0 0x0300#define MUX_ENABLE_TOP1 0x0304#define MUX_ENABLE_TOP2 0x0308#define MUX_ENABLE_TOP3 0x030c#define MUX_ENABLE_TOP4 0x0310#define MUX_ENABLE_TOP_MSCL 0x0320#define MUX_ENABLE_TOP_CAM1 0x0324#define MUX_ENABLE_TOP_DISP 0x0328#define MUX_ENABLE_TOP_FSYS0 0x0330#define MUX_ENABLE_TOP_FSYS1 0x0334#define MUX_ENABLE_TOP_PERIC0 0x0338#define MUX_ENABLE_TOP_PERIC1 0x033c#define MUX_STAT_TOP0 0x0400#define MUX_STAT_TOP1 0x0404#define MUX_STAT_TOP2 0x0408#define MUX_STAT_TOP3 0x040c#define MUX_STAT_TOP4 0x0410#define MUX_STAT_TOP_MSCL 0x0420#define MUX_STAT_TOP_CAM1 0x0424#define MUX_STAT_TOP_FSYS0 0x0430#define MUX_STAT_TOP_FSYS1 0x0434#define MUX_STAT_TOP_PERIC0 0x0438#define MUX_STAT_TOP_PERIC1 0x043c#define DIV_TOP0 0x0600#define DIV_TOP1 0x0604#define DIV_TOP2 0x0608#define DIV_TOP3 0x060c#define DIV_TOP4 0x0610#define DIV_TOP_MSCL 0x0618#define DIV_TOP_CAM10 0x061c#define DIV_TOP_CAM11 0x0620#define DIV_TOP_FSYS0 0x062c#define DIV_TOP_FSYS1 0x0630#define DIV_TOP_FSYS2 0x0634#define DIV_TOP_PERIC0 0x0638#define DIV_TOP_PERIC1 0x063c#define DIV_TOP_PERIC2 0x0640#define DIV_TOP_PERIC3 0x0644#define DIV_TOP_PERIC4 0x0648#define DIV_TOP_PLL_FREQ_DET 0x064c#define DIV_STAT_TOP0 0x0700#define DIV_STAT_TOP1 0x0704#define DIV_STAT_TOP2 0x0708#define DIV_STAT_TOP3 0x070c#define DIV_STAT_TOP4 0x0710#define DIV_STAT_TOP_MSCL 0x0718#define DIV_STAT_TOP_CAM10 0x071c#define DIV_STAT_TOP_CAM11 0x0720#define DIV_STAT_TOP_FSYS0 0x072c#define DIV_STAT_TOP_FSYS1 0x0730#define DIV_STAT_TOP_FSYS2 0x0734#define DIV_STAT_TOP_PERIC0 0x0738#define DIV_STAT_TOP_PERIC1 0x073c#define DIV_STAT_TOP_PERIC2 0x0740#define DIV_STAT_TOP_PERIC3 0x0744#define DIV_STAT_TOP_PLL_FREQ_DET 0x074c#define ENABLE_ACLK_TOP 0x0800#define ENABLE_SCLK_TOP 0x0a00#define ENABLE_SCLK_TOP_MSCL 0x0a04#define ENABLE_SCLK_TOP_CAM1 0x0a08#define ENABLE_SCLK_TOP_DISP 0x0a0c#define ENABLE_SCLK_TOP_FSYS 0x0a10#define ENABLE_SCLK_TOP_PERIC 0x0a14#define ENABLE_IP_TOP 0x0b00#define ENABLE_CMU_TOP 0x0c00#define ENABLE_CMU_TOP_DIV_STAT 0x0c04static const unsigned long top_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump top_suspend_regs[] = {/* force all aclk clocks enabled */ /* force all sclk_uart clocks enabled */ /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */ /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */ /* list of all parent clock list */ "oscclk" , "fout_aud_pll" , };"oscclk" , "fout_isp_pll" , };"oscclk" , "mout_aud_pll" , };"oscclk" , "sclk_mphy_pll" , };"oscclk" , "sclk_mfc_pll" , };"oscclk" , "sclk_bus_pll" , };"oscclk" , "mout_bus_pll_user" , };"oscclk" , "mout_mphy_pll_user" , };"mout_bus_pll_user" , "mout_mfc_pll_user" ,};"mout_mfc_pll_user" , "mout_bus_pll_user" ,};"mout_aclk_cam1_552_a" ,"mout_mfc_pll_user" , };"mout_isp_pll" , "mout_bus_pll_user" , };"mout_aclk_mfc_400_b" ,"mout_mphy_pll_user" , };"mout_aclk_mfc_400_a" ,"mout_bus_pll_user" , };"mout_mfc_pll_user" , "mout_isp_pll" , };"mout_bus_pll_user" ,"mout_mphy_pll_user" , };"mout_aclk_mscl_400_a" ,"mout_mphy_pll_user" , };"mout_aclk_g2d_400_a" ,"mout_mphy_pll_user" , };"mout_sclk_jpeg_b" , "mout_mphy_pll_user" ,};"mout_sclk_jpeg_a" , "mout_mfc_pll_user" , };"mout_sclk_mmc2_a" , "mout_mfc_pll_user" ,};"mout_sclk_mmc1_a" , "mout_mfc_pll_user" ,};"mout_sclk_mmc0_c" , "mout_isp_pll" , };"mout_sclk_mmc0_b" , "mout_mphy_pll_user" ,};"mout_sclk_mmc0_a" , "mout_mfc_pll_user" , };"sclk_audio0" , "sclk_audio1" ,"oscclk" , "ioclk_spdif_extclk" , };"ioclk_audiocdclk1" , "oscclk" ,"mout_aud_pll_user_t" ,};"ioclk_audiocdclk0" , "oscclk" ,"mout_aud_pll_user_t" ,};"sclk_audio1" , "ioclk_spdif_extclk" , };static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {"oscclk_efuse_common" , "oscclk" , 1, 1, 0),static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = {/* Xi2s{0|1}CDCLK input clock for I2S/PCM */ "ioclk_audiocdclk1" , NULL, 0, 100000000),"ioclk_audiocdclk0" , NULL, 0, 100000000),/* Xi2s1SDI input clock for SPDIF */ "ioclk_spdif_extclk" , NULL, 0, 100000000),/* XspiCLK[4:0] input clock for SPI */ "ioclk_spi4_clk_in" , NULL, 0, 50000000),"ioclk_spi3_clk_in" , NULL, 0, 50000000),"ioclk_spi2_clk_in" , NULL, 0, 50000000),"ioclk_spi1_clk_in" , NULL, 0, 50000000),"ioclk_spi0_clk_in" , NULL, 0, 50000000),/* Xi2s1SCLK input clock for I2S1_BCLK */ "ioclk_i2s1_bclk_in" , NULL, 0, 12288000),static const struct samsung_mux_clock top_mux_clks[] __initconst = {/* MUX_SEL_TOP0 */ "mout_aud_pll" , mout_aud_pll_p, MUX_SEL_TOP0,"mout_isp_pll" , mout_isp_pll_p, MUX_SEL_TOP0,/* MUX_SEL_TOP1 */ "mout_aud_pll_user_t" ,"mout_mphy_pll_user" , mout_mphy_pll_user_p,"mout_mfc_pll_user" , mout_mfc_pll_user_p,"mout_bus_pll_user" , mout_bus_pll_user_p,/* MUX_SEL_TOP2 */ "mout_aclk_hevc_400" ,"mout_aclk_cam1_333" ,"mout_aclk_cam1_552_b" ,"mout_aclk_cam1_552_a" ,"mout_aclk_isp_dis_400" ,"mout_aclk_isp_400" ,/* MUX_SEL_TOP3 */ "mout_aclk_bus0_400" ,"mout_aclk_mscl_400_b" ,"mout_aclk_mscl_400_a" ,"mout_aclk_gscl_333" ,"mout_aclk_g2d_400_b" ,"mout_aclk_g2d_400_a" ,/* MUX_SEL_TOP4 */ "mout_aclk_mfc_400_c" ,"mout_aclk_mfc_400_b" ,"mout_aclk_mfc_400_a" ,/* MUX_SEL_TOP_MSCL */ "mout_sclk_jpeg_c" , mout_sclk_jpeg_c_p,"mout_sclk_jpeg_b" , mout_sclk_jpeg_b_p,"mout_sclk_jpeg_a" , mout_bus_pll_user_t_p,/* MUX_SEL_TOP_CAM1 */ "mout_sclk_isp_sensor2" ,"mout_sclk_isp_sensor1" ,"mout_sclk_isp_sensor0" ,"mout_sclk_isp_uart" ,"mout_sclk_isp_spi1" ,"mout_sclk_isp_spi0" ,/* MUX_SEL_TOP_FSYS0 */ "mout_sclk_mmc2_b" , mout_sclk_mmc2_b_p,"mout_sclk_mmc2_a" , mout_bus_pll_user_t_p,"mout_sclk_mmc1_b" , mout_sclk_mmc1_b_p,"mout_sclk_mmc1_a" , mout_bus_pll_user_t_p,"mout_sclk_mmc0_d" , mout_sclk_mmc0_d_p,"mout_sclk_mmc0_c" , mout_sclk_mmc0_c_p,"mout_sclk_mmc0_b" , mout_sclk_mmc0_b_p,"mout_sclk_mmc0_a" , mout_bus_pll_user_t_p,/* MUX_SEL_TOP_FSYS1 */ "mout_sclk_pcie_100" , mout_bus_pll_user_t_p,"mout_sclk_ufsunipro" ,"mout_sclk_usbhost30" ,"mout_sclk_usbdrd30" ,/* MUX_SEL_TOP_PERIC0 */ "mout_sclk_spi4" , mout_bus_pll_user_t_p,"mout_sclk_spi3" , mout_bus_pll_user_t_p,"mout_sclk_uart2" , mout_bus_pll_user_t_p,"mout_sclk_uart1" , mout_bus_pll_user_t_p,"mout_sclk_uart0" , mout_bus_pll_user_t_p,"mout_sclk_spi2" , mout_bus_pll_user_t_p,"mout_sclk_spi1" , mout_bus_pll_user_t_p,"mout_sclk_spi0" , mout_bus_pll_user_t_p,/* MUX_SEL_TOP_PERIC1 */ "mout_sclk_slimbus" , mout_aud_pll_user_p,"mout_sclk_spdif" , mout_sclk_spdif_p,"mout_sclk_audio1" , mout_sclk_audio1_p,"mout_sclk_audio0" , mout_sclk_audio0_p,/* MUX_SEL_TOP_DISP */ "mout_sclk_hdmi_spdif" ,static const struct samsung_div_clock top_div_clks[] __initconst = {/* DIV_TOP0 */ "div_aclk_cam1_333" , "mout_aclk_cam1_333" ,"div_aclk_cam1_400" , "mout_bus_pll_user" ,"div_aclk_cam1_552" , "mout_aclk_cam1_552_b" ,"div_aclk_cam0_333" , "mout_mfc_pll_user" ,"div_aclk_cam0_400" , "mout_bus_pll_user" ,"div_aclk_cam0_552" , "mout_isp_pll" ,"div_aclk_isp_dis_400" ,"mout_aclk_isp_dis_400" , DIV_TOP0, 4, 4),"div_aclk_isp_400" ,"mout_aclk_isp_400" , DIV_TOP0, 0, 4),/* DIV_TOP1 */ "div_aclk_gscl_111" , "mout_aclk_gscl_333" ,"div_aclk_gscl_333" , "mout_aclk_gscl_333" ,"div_aclk_hevc_400" , "mout_aclk_hevc_400" ,"div_aclk_mfc_400" , "mout_aclk_mfc_400_c" ,"div_aclk_g2d_266" , "mout_bus_pll_user" ,"div_aclk_g2d_400" , "mout_aclk_g2d_400_b" ,/* DIV_TOP2 */ "div_aclk_mscl_400" , "mout_aclk_mscl_400_b" ,"div_aclk_fsys_200" , "mout_bus_pll_user" ,/* DIV_TOP3 */ "div_aclk_imem_sssx_266" ,"mout_bus_pll_user" , DIV_TOP3, 24, 3),"div_aclk_imem_200" ,"mout_bus_pll_user" , DIV_TOP3, 20, 3),"div_aclk_imem_266" ,"mout_bus_pll_user" , DIV_TOP3, 16, 3),"div_aclk_peric_66_b" ,"div_aclk_peric_66_a" , DIV_TOP3, 12, 3),"div_aclk_peric_66_a" ,"mout_bus_pll_user" , DIV_TOP3, 8, 3),"div_aclk_peris_66_b" ,"div_aclk_peris_66_a" , DIV_TOP3, 4, 3),"div_aclk_peris_66_a" ,"mout_bus_pll_user" , DIV_TOP3, 0, 3),/* DIV_TOP4 */ "div_aclk_g3d_400" , "mout_bus_pll_user" ,"div_aclk_bus0_400" , "mout_aclk_bus0_400" ,"div_aclk_bus1_400" , "mout_bus_pll_user" ,/* DIV_TOP_MSCL */ "div_sclk_jpeg" , "mout_sclk_jpeg_c" ,/* DIV_TOP_CAM10 */ "div_sclk_isp_uart" , "mout_sclk_isp_uart" ,"div_sclk_isp_spi1_b" ,"div_sclk_isp_spi1_a" , DIV_TOP_CAM10, 16, 8),"div_sclk_isp_spi1_a" ,"mout_sclk_isp_spi1" , DIV_TOP_CAM10, 12, 4),"div_sclk_isp_spi0_b" ,"div_sclk_isp_spi0_a" , DIV_TOP_CAM10, 4, 8),"div_sclk_isp_spi0_a" ,"mout_sclk_isp_spi0" , DIV_TOP_CAM10, 0, 4),/* DIV_TOP_CAM11 */ "div_sclk_isp_sensor2_b" ,"div_sclk_isp_sensor2_a" , DIV_TOP_CAM11, 20, 4),"div_sclk_isp_sensor2_a" ,"mout_sclk_isp_sensor2" , DIV_TOP_CAM11, 16, 4),"div_sclk_isp_sensor1_b" ,"div_sclk_isp_sensor1_a" , DIV_TOP_CAM11, 12, 4),"div_sclk_isp_sensor1_a" ,"mout_sclk_isp_sensor1" , DIV_TOP_CAM11, 8, 4),"div_sclk_isp_sensor0_b" ,"div_sclk_isp_sensor0_a" , DIV_TOP_CAM11, 4, 4),"div_sclk_isp_sensor0_a" ,"mout_sclk_isp_sensor0" , DIV_TOP_CAM11, 0, 4),/* DIV_TOP_FSYS0 */ "div_sclk_mmc1_b" , "div_sclk_mmc1_a" ,"div_sclk_mmc1_a" , "mout_sclk_mmc1_b" ,"div_sclk_mmc0_b" , "div_sclk_mmc0_a" ,"div_sclk_mmc0_a" , "mout_sclk_mmc0_d" ,/* DIV_TOP_FSYS1 */ "div_sclk_mmc2_b" , "div_sclk_mmc2_a" ,"div_sclk_mmc2_a" , "mout_sclk_mmc2_b" ,/* DIV_TOP_FSYS2 */ "div_sclk_pcie_100" , "mout_sclk_pcie_100" ,"div_sclk_usbhost30" ,"mout_sclk_usbhost30" , DIV_TOP_FSYS2, 8, 4),"div_sclk_ufsunipro" ,"mout_sclk_ufsunipro" , DIV_TOP_FSYS2, 4, 4),"div_sclk_usbdrd30" , "mout_sclk_usbdrd30" ,/* DIV_TOP_PERIC0 */ "div_sclk_spi1_b" , "div_sclk_spi1_a" ,"div_sclk_spi1_a" , "mout_sclk_spi1" ,"div_sclk_spi0_b" , "div_sclk_spi0_a" ,"div_sclk_spi0_a" , "mout_sclk_spi0" ,/* DIV_TOP_PERIC1 */ "div_sclk_spi2_b" , "div_sclk_spi2_a" ,"div_sclk_spi2_a" , "mout_sclk_spi2" ,/* DIV_TOP_PERIC2 */ "div_sclk_uart2" , "mout_sclk_uart2" ,"div_sclk_uart1" , "mout_sclk_uart0" ,"div_sclk_uart0" , "mout_sclk_uart1" ,/* DIV_TOP_PERIC3 */ "div_sclk_i2s1" , "sclk_audio1" ,"div_sclk_pcm1" , "sclk_audio1" ,"div_sclk_audio1" , "mout_sclk_audio1" ,"div_sclk_audio0" , "mout_sclk_audio0" ,/* DIV_TOP_PERIC4 */ "div_sclk_spi4_b" , "div_sclk_spi4_a" ,"div_sclk_spi4_a" , "mout_sclk_spi4" ,"div_sclk_spi3_b" , "div_sclk_spi3_a" ,"div_sclk_spi3_a" , "mout_sclk_spi3" ,static const struct samsung_gate_clock top_gate_clks[] __initconst = {/* ENABLE_ACLK_TOP */ "aclk_g3d_400" , "div_aclk_g3d_400" ,"aclk_imem_sssx_266" ,"div_aclk_imem_sssx_266" , ENABLE_ACLK_TOP,"aclk_bus0_400" , "div_aclk_bus0_400" ,"aclk_bus1_400" , "div_aclk_bus1_400" ,"aclk_imem_200" , "div_aclk_imem_200" ,"aclk_imem_266" , "div_aclk_imem_266" ,"aclk_peric_66" , "div_aclk_peric_66_b" ,"aclk_peris_66" , "div_aclk_peris_66_b" ,"aclk_mscl_400" , "div_aclk_mscl_400" ,"aclk_fsys_200" , "div_aclk_fsys_200" ,"aclk_gscl_111" , "div_aclk_gscl_111" ,"aclk_gscl_333" , "div_aclk_gscl_333" ,"aclk_cam1_333" , "div_aclk_cam1_333" ,"aclk_cam1_400" , "div_aclk_cam1_400" ,"aclk_cam1_552" , "div_aclk_cam1_552" ,"aclk_cam0_333" , "div_aclk_cam0_333" ,"aclk_cam0_400" , "div_aclk_cam0_400" ,"aclk_cam0_552" , "div_aclk_cam0_552" ,"aclk_isp_dis_400" , "div_aclk_isp_dis_400" ,"aclk_isp_400" , "div_aclk_isp_400" ,"aclk_hevc_400" , "div_aclk_hevc_400" ,"aclk_mfc_400" , "div_aclk_mfc_400" ,"aclk_g2d_266" , "div_aclk_g2d_266" ,"aclk_g2d_400" , "div_aclk_g2d_400" ,/* ENABLE_SCLK_TOP_MSCL */ "sclk_jpeg_mscl" , "div_sclk_jpeg" ,/* ENABLE_SCLK_TOP_CAM1 */ "sclk_isp_sensor2" , "div_sclk_isp_sensor2_b" ,"sclk_isp_sensor1" , "div_sclk_isp_sensor1_b" ,"sclk_isp_sensor0" , "div_sclk_isp_sensor0_b" ,"sclk_isp_mctadc_cam1" , "oscclk" ,"sclk_isp_uart_cam1" , "div_sclk_isp_uart" ,"sclk_isp_spi1_cam1" , "div_sclk_isp_spi1_b" ,"sclk_isp_spi0_cam1" , "div_sclk_isp_spi0_b" ,/* ENABLE_SCLK_TOP_DISP */ "sclk_hdmi_spdif_disp" ,"mout_sclk_hdmi_spdif" , ENABLE_SCLK_TOP_DISP, 0,/* ENABLE_SCLK_TOP_FSYS */ "sclk_pcie_100_fsys" , "div_sclk_pcie_100" ,"sclk_mmc2_fsys" , "div_sclk_mmc2_b" ,"sclk_mmc1_fsys" , "div_sclk_mmc1_b" ,"sclk_mmc0_fsys" , "div_sclk_mmc0_b" ,"sclk_ufsunipro_fsys" ,"div_sclk_ufsunipro" , ENABLE_SCLK_TOP_FSYS,"sclk_usbhost30_fsys" ,"div_sclk_usbhost30" , ENABLE_SCLK_TOP_FSYS,"sclk_usbdrd30_fsys" ,"div_sclk_usbdrd30" , ENABLE_SCLK_TOP_FSYS,/* ENABLE_SCLK_TOP_PERIC */ "sclk_spi4_peric" , "div_sclk_spi4_b" ,"sclk_spi3_peric" , "div_sclk_spi3_b" ,"sclk_spdif_peric" , "mout_sclk_spdif" ,"sclk_i2s1_peric" , "div_sclk_i2s1" ,"sclk_pcm1_peric" , "div_sclk_pcm1" ,"sclk_uart2_peric" , "div_sclk_uart2" ,"sclk_uart1_peric" , "div_sclk_uart1" ,"sclk_uart0_peric" , "div_sclk_uart0" ,"sclk_spi2_peric" , "div_sclk_spi2_b" ,"sclk_spi1_peric" , "div_sclk_spi1_b" ,"sclk_spi0_peric" , "div_sclk_spi0_b" ,/* MUX_ENABLE_TOP_PERIC1 */ "sclk_slimbus" , "mout_sclk_slimbus" ,"sclk_audio1" , "div_sclk_audio1" ,"sclk_audio0" , "div_sclk_audio0" ,/* * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = {/* sentinel */ } /* AUD_PLL */ static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = {/* sentinel */ } static const struct samsung_pll_clock top_pll_clks[] __initconst = {"fout_isp_pll" , "oscclk" ,"fout_aud_pll" , "oscclk" ,static const struct samsung_cmu_info top_cmu_info __initconst = {static void __init exynos5433_cmu_top_init(struct device_node *np)"samsung,exynos5433-cmu-top" ,/* * Register offset definitions for CMU_CPIF #define MPHY_PLL_LOCK 0x0000#define MPHY_PLL_CON0 0x0100#define MPHY_PLL_CON1 0x0104#define MPHY_PLL_FREQ_DET 0x010c#define MUX_SEL_CPIF0 0x0200#define DIV_CPIF 0x0600#define ENABLE_SCLK_CPIF 0x0a00static const unsigned long cpif_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump cpif_suspend_regs[] = {/* force all sclk clocks enabled */ /* MPHY PLL has to be enabled for suspend: reset value + ENABLE bit */ /* list of all parent clock list */ "oscclk" , "fout_mphy_pll" , };static const struct samsung_pll_clock cpif_pll_clks[] __initconst = {"fout_mphy_pll" , "oscclk" ,static const struct samsung_mux_clock cpif_mux_clks[] __initconst = {/* MUX_SEL_CPIF0 */ "mout_mphy_pll" , mout_mphy_pll_p, MUX_SEL_CPIF0,static const struct samsung_div_clock cpif_div_clks[] __initconst = {/* DIV_CPIF */ "div_sclk_mphy" , "mout_mphy_pll" , DIV_CPIF,static const struct samsung_gate_clock cpif_gate_clks[] __initconst = {/* ENABLE_SCLK_CPIF */ "sclk_mphy_pll" , "mout_mphy_pll" ,"sclk_ufs_mphy" , "div_sclk_mphy" ,static const struct samsung_cmu_info cpif_cmu_info __initconst = {static void __init exynos5433_cmu_cpif_init(struct device_node *np)"samsung,exynos5433-cmu-cpif" ,/* * Register offset definitions for CMU_MIF #define MEM0_PLL_LOCK 0x0000#define MEM1_PLL_LOCK 0x0004#define BUS_PLL_LOCK 0x0008#define MFC_PLL_LOCK 0x000c#define MEM0_PLL_CON0 0x0100#define MEM0_PLL_CON1 0x0104#define MEM0_PLL_FREQ_DET 0x010c#define MEM1_PLL_CON0 0x0110#define MEM1_PLL_CON1 0x0114#define MEM1_PLL_FREQ_DET 0x011c#define BUS_PLL_CON0 0x0120#define BUS_PLL_CON1 0x0124#define BUS_PLL_FREQ_DET 0x012c#define MFC_PLL_CON0 0x0130#define MFC_PLL_CON1 0x0134#define MFC_PLL_FREQ_DET 0x013c#define MUX_SEL_MIF0 0x0200#define MUX_SEL_MIF1 0x0204#define MUX_SEL_MIF2 0x0208#define MUX_SEL_MIF3 0x020c#define MUX_SEL_MIF4 0x0210#define MUX_SEL_MIF5 0x0214#define MUX_SEL_MIF6 0x0218#define MUX_SEL_MIF7 0x021c#define MUX_ENABLE_MIF0 0x0300#define MUX_ENABLE_MIF1 0x0304#define MUX_ENABLE_MIF2 0x0308#define MUX_ENABLE_MIF3 0x030c#define MUX_ENABLE_MIF4 0x0310#define MUX_ENABLE_MIF5 0x0314#define MUX_ENABLE_MIF6 0x0318#define MUX_ENABLE_MIF7 0x031c#define MUX_STAT_MIF0 0x0400#define MUX_STAT_MIF1 0x0404#define MUX_STAT_MIF2 0x0408#define MUX_STAT_MIF3 0x040c#define MUX_STAT_MIF4 0x0410#define MUX_STAT_MIF5 0x0414#define MUX_STAT_MIF6 0x0418#define MUX_STAT_MIF7 0x041c#define DIV_MIF1 0x0604#define DIV_MIF2 0x0608#define DIV_MIF3 0x060c#define DIV_MIF4 0x0610#define DIV_MIF5 0x0614#define DIV_MIF_PLL_FREQ_DET 0x0618#define DIV_STAT_MIF1 0x0704#define DIV_STAT_MIF2 0x0708#define DIV_STAT_MIF3 0x070c#define DIV_STAT_MIF4 0x0710#define DIV_STAT_MIF5 0x0714#define DIV_STAT_MIF_PLL_FREQ_DET 0x0718#define ENABLE_ACLK_MIF0 0x0800#define ENABLE_ACLK_MIF1 0x0804#define ENABLE_ACLK_MIF2 0x0808#define ENABLE_ACLK_MIF3 0x080c#define ENABLE_PCLK_MIF 0x0900#define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904#define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908#define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c#define ENABLE_PCLK_MIF_SECURE_RTC 0x0910#define ENABLE_SCLK_MIF 0x0a00#define ENABLE_IP_MIF0 0x0b00#define ENABLE_IP_MIF1 0x0b04#define ENABLE_IP_MIF2 0x0b08#define ENABLE_IP_MIF3 0x0b0c#define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10#define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14#define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18#define ENABLE_IP_MIF_SECURE_RTC 0x0b1c#define CLKOUT_CMU_MIF 0x0c00#define CLKOUT_CMU_MIF_DIV_STAT 0x0c04#define DREX_FREQ_CTRL0 0x1000#define DREX_FREQ_CTRL1 0x1004#define PAUSE 0x1008#define DDRPHY_LOCK_CTRL 0x100cstatic const unsigned long mif_clk_regs[] __initconst = {static const struct samsung_pll_clock mif_pll_clks[] __initconst = {"fout_mem0_pll" , "oscclk" ,"fout_mem1_pll" , "oscclk" ,"fout_bus_pll" , "oscclk" ,"fout_mfc_pll" , "oscclk" ,/* list of all parent clock list */ "mout_mfc_pll" , "dout_mfc_pll" , };"mout_bus_pll" , "dout_bus_pll" , };"mout_mem1_pll" , "dout_mem1_pll" , };"mout_mem0_pll" , "dout_mem0_pll" , };"oscclk" , "fout_mfc_pll" , };"oscclk" , "fout_bus_pll" , };"oscclk" , "fout_mem1_pll" , };"oscclk" , "fout_mem0_pll" , };"mout_mem0_pll_div2" , "mout_clkm_phy_b" , };"mout_bus_pll_div2" , "mout_clkm_phy_a" , };"mout_bus_pll_div2" , "mout_mfc_pll_div2" , };"mout_mem1_pll_div2" , "mout_clkm_phy_a" , };"mout_mem0_pll_div2" , "div_mif_pre" , };"mout_mem1_pll_div2" , "mout_bus_pll_div2" ,};"mout_aclk_disp_333_a" ,"mout_bus_pll_div2" , };"mout_mfc_pll_div2" , "sclk_mphy_pll" , };"mout_sclk_decon_vclk_b" ,"sclk_mphy_pll" , };"mout_sclk_decon_vclk_a" ,"mout_mfc_pll_div2" , };"oscclk" , "mout_bus_pll_div2" , };"mout_sclk_decon_eclk_b" ,"sclk_mphy_pll" , };"mout_sclk_decon_eclk_a" ,"mout_mfc_pll_div2" , };"mout_sclk_decon_tv_eclk_b" ,"sclk_mphy_pll" , };"mout_sclk_decon_tv_eclk_a" ,"mout_mfc_pll_div2" , };"mout_sclk_dsd_b" , "mout_bus_pll_div2" , };"mout_sclk_dsd_a" , "sclk_mphy_pll" , };"oscclk" , "mout_mfc_pll_div2" , };"mout_sclk_dsim0_b" , "sclk_mphy_pll" , };"mout_sclk_dsim0_a" , "mout_mfc_pll_div2" };"mout_sclk_decon_tv_vclk_b" ,"sclk_mphy_pll" , };"mout_sclk_decon_tv_vclk_a" ,"mout_mfc_pll_div2" , };"mout_sclk_dsim1_b" , "sclk_mphy_pll" , };"mout_sclk_dsim1_a" , "mout_mfc_pll_div2" ,};static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = {/* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */ "dout_mfc_pll" , "mout_mfc_pll" , 1, 1, 0),"dout_bus_pll" , "mout_bus_pll" , 1, 1, 0),"dout_mem1_pll" , "mout_mem1_pll" , 1, 1, 0),"dout_mem0_pll" , "mout_mem0_pll" , 1, 1, 0),static const struct samsung_mux_clock mif_mux_clks[] __initconst = {/* MUX_SEL_MIF0 */ "mout_mfc_pll_div2" , mout_mfc_pll_div2_p,"mout_bus_pll_div2" , mout_bus_pll_div2_p,"mout_mem1_pll_div2" , mout_mem1_pll_div2_p,"mout_mem0_pll_div2" , mout_mem0_pll_div2_p,"mout_mfc_pll" , mout_mfc_pll_p, MUX_SEL_MIF0,"mout_bus_pll" , mout_bus_pll_p, MUX_SEL_MIF0,"mout_mem1_pll" , mout_mem1_pll_p, MUX_SEL_MIF0,"mout_mem0_pll" , mout_mem0_pll_p, MUX_SEL_MIF0,/* MUX_SEL_MIF1 */ "mout_clk2x_phy_c" , mout_clk2x_phy_c_p,"mout_clk2x_phy_b" , mout_clk2x_phy_b_p,"mout_clk2x_phy_a" , mout_clk2x_phy_a_p,"mout_clkm_phy_c" , mout_clk2x_phy_c_p,"mout_clkm_phy_b" , mout_clkm_phy_b_p,"mout_clkm_phy_a" , mout_clk2x_phy_a_p,/* MUX_SEL_MIF2 */ "mout_aclk_mifnm_200" ,"mout_aclk_mifnm_400" ,/* MUX_SEL_MIF3 */ "mout_aclk_disp_333_b" ,"mout_aclk_disp_333_a" ,/* MUX_SEL_MIF4 */ "mout_sclk_decon_vclk_c" ,"mout_sclk_decon_vclk_b" ,"mout_sclk_decon_vclk_a" ,"mout_sclk_decon_eclk_c" ,"mout_sclk_decon_eclk_b" ,"mout_sclk_decon_eclk_a" ,/* MUX_SEL_MIF5 */ "mout_sclk_decon_tv_eclk_c" ,"mout_sclk_decon_tv_eclk_b" ,"mout_sclk_decon_tv_eclk_a" ,"mout_sclk_dsd_c" , mout_sclk_dsd_c_p,"mout_sclk_dsd_b" , mout_sclk_dsd_b_p,"mout_sclk_dsd_a" , mout_sclk_dsd_a_p,/* MUX_SEL_MIF6 */ "mout_sclk_dsim0_c" , mout_sclk_dsim0_c_p,"mout_sclk_dsim0_b" , mout_sclk_dsim0_b_p,"mout_sclk_dsim0_a" , mout_sclk_decon_p,/* MUX_SEL_MIF7 */ "mout_sclk_decon_tv_vclk_c" ,"mout_sclk_decon_tv_vclk_b" ,"mout_sclk_decon_tv_vclk_a" ,"mout_sclk_dsim1_c" , mout_sclk_dsim1_c_p,"mout_sclk_dsim1_b" , mout_sclk_dsim1_b_p,"mout_sclk_dsim1_a" , mout_sclk_decon_p,static const struct samsung_div_clock mif_div_clks[] __initconst = {/* DIV_MIF1 */ "div_sclk_hpm_mif" , "div_clk2x_phy" ,"div_aclk_drex1" , "div_clk2x_phy" , DIV_MIF1,"div_aclk_drex0" , "div_clk2x_phy" , DIV_MIF1,"div_clk2x_phy" , "mout_clk2x_phy_c" , DIV_MIF1,/* DIV_MIF2 */ "div_aclk_mif_266" , "mout_bus_pll_div2" ,"div_aclk_mifnd_133" , "div_mif_pre" ,"div_aclk_mif_133" , "div_mif_pre" ,"div_aclk_mifnm_200" ,"mout_aclk_mifnm_200" , DIV_MIF2, 8, 3),"div_aclk_mif_200" , "div_aclk_mif_400" ,"div_aclk_mif_400" , "mout_aclk_mifnm_400" ,/* DIV_MIF3 */ "div_aclk_bus2_400" , "div_mif_pre" ,"div_aclk_disp_333" , "mout_aclk_disp_333_b" ,"div_aclk_cpif_200" , "mout_aclk_mifnm_200" ,/* DIV_MIF4 */ "div_sclk_dsim1" , "mout_sclk_dsim1_c" ,"div_sclk_decon_tv_vclk" ,"mout_sclk_decon_tv_vclk_c" , DIV_MIF4, 20, 4),"div_sclk_dsim0" , "mout_sclk_dsim0_c" ,"div_sclk_dsd" , "mout_sclk_dsd_c" ,"div_sclk_decon_tv_eclk" ,"mout_sclk_decon_tv_eclk_c" , DIV_MIF4, 8, 4),"div_sclk_decon_vclk" ,"mout_sclk_decon_vclk_c" , DIV_MIF4, 4, 4),"div_sclk_decon_eclk" ,"mout_sclk_decon_eclk_c" , DIV_MIF4, 0, 4),/* DIV_MIF5 */ "div_mif_pre" , "mout_bus_pll_div2" , DIV_MIF5,static const struct samsung_gate_clock mif_gate_clks[] __initconst = {/* ENABLE_ACLK_MIF0 */ "clk2k_phy1" , "div_clk2x_phy" , ENABLE_ACLK_MIF0,"clk2x_phy0" , "div_clk2x_phy" , ENABLE_ACLK_MIF0,"clkm_phy1" , "mout_clkm_phy_c" , ENABLE_ACLK_MIF0,"clkm_phy0" , "mout_clkm_phy_c" , ENABLE_ACLK_MIF0,"rclk_drex1" , "oscclk" , ENABLE_ACLK_MIF0,"rclk_drex0" , "oscclk" , ENABLE_ACLK_MIF0,"aclk_drex1_tz" , "div_aclk_drex1" ,"aclk_drex0_tz" , "div_aclk_drex0" ,"aclk_drex1_perev" , "div_aclk_drex1" ,"aclk_drex0_perev" , "div_aclk_drex0" ,"aclk_drex1_memif" , "div_aclk_drex1" ,"aclk_drex0_memif" , "div_aclk_drex0" ,"aclk_drex1_sch" , "div_aclk_drex1" ,"aclk_drex0_sch" , "div_aclk_drex0" ,"aclk_drex1_busif" , "div_aclk_drex1" ,"aclk_drex0_busif" , "div_aclk_drex0" ,"aclk_drex1_busif_rd" , "div_aclk_drex1" ,"aclk_drex0_busif_rd" , "div_aclk_drex0" ,"aclk_drex1" , "div_aclk_drex1" ,"aclk_drex0" , "div_aclk_drex0" ,/* ENABLE_ACLK_MIF1 */ "aclk_asyncaxis_mif_imem" ,"div_aclk_mif_200" , ENABLE_ACLK_MIF1, 28,"aclk_asyncaxis_noc_p_cci" ,"div_aclk_mif_200" , ENABLE_ACLK_MIF1,"aclk_asyncaxim_noc_p_cci" ,"div_aclk_mif_133" , ENABLE_ACLK_MIF1,"aclk_asyncaxis_cp1" ,"div_aclk_mifnm_200" , ENABLE_ACLK_MIF1,"aclk_asyncaxim_cp1" ,"div_aclk_drex1" , ENABLE_ACLK_MIF1,"aclk_asyncaxis_cp0" ,"div_aclk_mifnm_200" , ENABLE_ACLK_MIF1,"aclk_asyncaxim_cp0" ,"div_aclk_drex0" , ENABLE_ACLK_MIF1,"aclk_asyncaxis_drex1_3" ,"div_aclk_mif_133" , ENABLE_ACLK_MIF1,"aclk_asyncaxim_drex1_3" ,"div_aclk_drex1" , ENABLE_ACLK_MIF1,"aclk_asyncaxis_drex1_1" ,"div_aclk_mif_133" , ENABLE_ACLK_MIF1,"aclk_asyncaxim_drex1_1" ,"div_aclk_drex1" , ENABLE_ACLK_MIF1,"aclk_asyncaxis_drex1_0" ,"div_aclk_mif_133" , ENABLE_ACLK_MIF1,"aclk_asyncaxim_drex1_0" ,"div_aclk_drex1" , ENABLE_ACLK_MIF1,"aclk_asyncaxis_drex0_3" ,"div_aclk_mif_133" , ENABLE_ACLK_MIF1,"aclk_asyncaxim_drex0_3" ,"div_aclk_drex0" , ENABLE_ACLK_MIF1,"aclk_asyncaxis_drex0_1" ,"div_aclk_mif_133" , ENABLE_ACLK_MIF1,"aclk_asyncaxim_drex0_1" ,"div_aclk_drex0" , ENABLE_ACLK_MIF1,"aclk_asyncaxis_drex0_0" ,"div_aclk_mif_133" , ENABLE_ACLK_MIF1,"aclk_asyncaxim_drex0_0" ,"div_aclk_drex0" , ENABLE_ACLK_MIF1,"aclk_ahb2apb_mif2p" , "div_aclk_mif_133" ,"aclk_ahb2apb_mif1p" , "div_aclk_mif_133" ,"aclk_ahb2apb_mif0p" , "div_aclk_mif_133" ,"aclk_ixiu_cci" , "div_aclk_mif_400" ,"aclk_xiu_mifsfrx" , "div_aclk_mif_200" ,"aclk_mifnp_133" , "div_aclk_mif_133" ,"aclk_mifnm_200" , "div_aclk_mifnm_200" ,"aclk_mifnd_133" , "div_aclk_mifnd_133" ,"aclk_mifnd_400" , "div_aclk_mif_400" ,"aclk_cci" , "div_aclk_mif_400" , ENABLE_ACLK_MIF1,/* ENABLE_ACLK_MIF2 */ "aclk_mifnd_266" , "div_aclk_mif_266" ,"aclk_ppmu_drex1s3" , "div_aclk_drex1" ,"aclk_ppmu_drex1s1" , "div_aclk_drex1" ,"aclk_ppmu_drex1s0" , "div_aclk_drex1" ,"aclk_ppmu_drex0s3" , "div_aclk_drex0" ,"aclk_ppmu_drex0s1" , "div_aclk_drex0" ,"aclk_ppmu_drex0s0" , "div_aclk_drex0" ,"aclk_axids_cci_mifsfrx" ,"div_aclk_mif_200" , ENABLE_ACLK_MIF2, 7,"aclk_axisyncdns_cci" ,"div_aclk_mif_400" , ENABLE_ACLK_MIF2,"aclk_axisyncdn_cci" , "div_aclk_mif_400" ,"aclk_axisyncdn_noc_d" ,"div_aclk_mif_200" , ENABLE_ACLK_MIF2,"aclk_asyncapbs_mif_cssys" ,"div_aclk_mifnd_133" , ENABLE_ACLK_MIF2, 0, 0, 0),/* ENABLE_ACLK_MIF3 */ "aclk_bus2_400" , "div_aclk_bus2_400" ,"aclk_disp_333" , "div_aclk_disp_333" ,"aclk_cpif_200" , "div_aclk_cpif_200" ,/* ENABLE_PCLK_MIF */ "pclk_ppmu_drex1s3" , "div_aclk_drex1" ,"pclk_ppmu_drex1s1" , "div_aclk_drex1" ,"pclk_ppmu_drex1s0" , "div_aclk_drex1" ,"pclk_ppmu_drex0s3" , "div_aclk_drex0" ,"pclk_ppmu_drex0s1" , "div_aclk_drex0" ,"pclk_ppmu_drex0s0" , "div_aclk_drex0" ,"pclk_asyncaxi_noc_p_cci" ,"div_aclk_mif_133" , ENABLE_PCLK_MIF, 21,"pclk_asyncaxi_cp1" , "div_aclk_mif_133" ,"pclk_asyncaxi_cp0" , "div_aclk_mif_133" ,"pclk_asyncaxi_drex1_3" ,"div_aclk_mif_133" , ENABLE_PCLK_MIF, 17, 0, 0),"pclk_asyncaxi_drex1_1" ,"div_aclk_mif_133" , ENABLE_PCLK_MIF, 16, 0, 0),"pclk_asyncaxi_drex1_0" ,"div_aclk_mif_133" , ENABLE_PCLK_MIF, 15, 0, 0),"pclk_asyncaxi_drex0_3" ,"div_aclk_mif_133" , ENABLE_PCLK_MIF, 14, 0, 0),"pclk_asyncaxi_drex0_1" ,"div_aclk_mif_133" , ENABLE_PCLK_MIF, 13, 0, 0),"pclk_asyncaxi_drex0_0" ,"div_aclk_mif_133" , ENABLE_PCLK_MIF, 12, 0, 0),"pclk_mifsrvnd_133" , "div_aclk_mif_133" ,"pclk_pmu_mif" , "div_aclk_mif_133" ,"pclk_sysreg_mif" , "div_aclk_mif_133" ,"pclk_gpio_alive" , "div_aclk_mif_133" ,"pclk_abb" , "div_aclk_mif_133" ,"pclk_pmu_apbif" , "div_aclk_mif_133" ,"pclk_ddr_phy1" , "div_aclk_mif_133" ,"pclk_drex1" , "div_aclk_mif_133" ,"pclk_ddr_phy0" , "div_aclk_mif_133" ,"pclk_drex0" , "div_aclk_mif_133" ,/* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */ "pclk_drex0_tz" , "div_aclk_mif_133" ,/* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */ "pclk_drex1_tz" , "div_aclk_mif_133" ,/* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */ "pclk_monotonic_cnt" , "div_aclk_mif_133" ,/* ENABLE_PCLK_MIF_SECURE_RTC */ "pclk_rtc" , "div_aclk_mif_133" ,/* ENABLE_SCLK_MIF */ "sclk_dsim1_disp" , "div_sclk_dsim1" ,"sclk_decon_tv_vclk_disp" ,"div_sclk_decon_tv_vclk" , ENABLE_SCLK_MIF,"sclk_dsim0_disp" , "div_sclk_dsim0" ,"sclk_dsd_disp" , "div_sclk_dsd" ,"sclk_decon_tv_eclk_disp" ,"div_sclk_decon_tv_eclk" , ENABLE_SCLK_MIF,"sclk_decon_vclk_disp" ,"div_sclk_decon_vclk" , ENABLE_SCLK_MIF,"sclk_decon_eclk_disp" ,"div_sclk_decon_eclk" , ENABLE_SCLK_MIF,"sclk_hpm_mif" , "div_sclk_hpm_mif" ,"sclk_mfc_pll" , "mout_mfc_pll_div2" ,"sclk_bus_pll" , "mout_bus_pll_div2" ,"sclk_bus_pll_apollo" , "sclk_bus_pll" ,"sclk_bus_pll_atlas" , "sclk_bus_pll" ,static const struct samsung_cmu_info mif_cmu_info __initconst = {static void __init exynos5433_cmu_mif_init(struct device_node *np)"samsung,exynos5433-cmu-mif" ,/* * Register offset definitions for CMU_PERIC #define DIV_PERIC 0x0600#define DIV_STAT_PERIC 0x0700#define ENABLE_ACLK_PERIC 0x0800#define ENABLE_PCLK_PERIC0 0x0900#define ENABLE_PCLK_PERIC1 0x0904#define ENABLE_SCLK_PERIC 0x0A00#define ENABLE_IP_PERIC0 0x0B00#define ENABLE_IP_PERIC1 0x0B04#define ENABLE_IP_PERIC2 0x0B08static const unsigned long peric_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump peric_suspend_regs[] = {/* pclk: sci, pmu, sysreg, gpio_{finger, ese, touch, nfc}, uart2-0 */ /* sclk: uart2-0 */ static const struct samsung_div_clock peric_div_clks[] __initconst = {/* DIV_PERIC */ "div_sclk_sci" , "oscclk" , DIV_PERIC, 4, 4),"div_sclk_sc_in" , "oscclk" , DIV_PERIC, 0, 4),static const struct samsung_gate_clock peric_gate_clks[] __initconst = {/* ENABLE_ACLK_PERIC */ "aclk_ahb2apb_peric2p" , "aclk_peric_66" ,"aclk_ahb2apb_peric1p" , "aclk_peric_66" ,"aclk_ahb2apb_peric0p" , "aclk_peric_66" ,"aclk_pericnp_66" , "aclk_peric_66" ,/* ENABLE_PCLK_PERIC0 */ "pclk_sci" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_gpio_finger" , "aclk_peric_66" ,"pclk_gpio_ese" , "aclk_peric_66" ,"pclk_pwm" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_spdif" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_pcm1" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_i2s" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_spi2" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_spi1" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_spi0" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_adcif" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_gpio_touch" , "aclk_peric_66" ,"pclk_gpio_nfc" , "aclk_peric_66" ,"pclk_gpio_peric" , "aclk_peric_66" ,"pclk_pmu_peric" , "aclk_peric_66" ,"pclk_sysreg_peric" , "aclk_peric_66" ,"pclk_uart2" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_uart1" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_uart0" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_hsi2c3" , "aclk_peric_66" ,"pclk_hsi2c2" , "aclk_peric_66" ,"pclk_hsi2c1" , "aclk_peric_66" ,"pclk_hsi2c0" , "aclk_peric_66" ,"pclk_i2c7" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_i2c6" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_i2c5" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_i2c4" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_i2c3" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_i2c2" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_i2c1" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,"pclk_i2c0" , "aclk_peric_66" , ENABLE_PCLK_PERIC0,/* ENABLE_PCLK_PERIC1 */ "pclk_spi4" , "aclk_peric_66" , ENABLE_PCLK_PERIC1,"pclk_spi3" , "aclk_peric_66" , ENABLE_PCLK_PERIC1,"pclk_hsi2c11" , "aclk_peric_66" ,"pclk_hsi2c10" , "aclk_peric_66" ,"pclk_hsi2c9" , "aclk_peric_66" ,"pclk_hsi2c8" , "aclk_peric_66" ,"pclk_hsi2c7" , "aclk_peric_66" ,"pclk_hsi2c6" , "aclk_peric_66" ,"pclk_hsi2c5" , "aclk_peric_66" ,"pclk_hsi2c4" , "aclk_peric_66" ,/* ENABLE_SCLK_PERIC */ "sclk_ioclk_spi4" , "ioclk_spi4_clk_in" ,"sclk_ioclk_spi3" , "ioclk_spi3_clk_in" ,"sclk_spi4" , "sclk_spi4_peric" , ENABLE_SCLK_PERIC,"sclk_spi3" , "sclk_spi3_peric" , ENABLE_SCLK_PERIC,"sclk_sci" , "div_sclk_sci" , ENABLE_SCLK_PERIC,"sclk_sc_in" , "div_sclk_sc_in" , ENABLE_SCLK_PERIC,"sclk_pwm" , "oscclk" , ENABLE_SCLK_PERIC, 15, 0, 0),"sclk_ioclk_spi2" , "ioclk_spi2_clk_in" ,"sclk_ioclk_spi1" , "ioclk_spi1_clk_in" ,"sclk_ioclk_spi0" , "ioclk_spi0_clk_in" ,"sclk_ioclk_i2s1_bclk" ,"ioclk_i2s1_bclk_in" , ENABLE_SCLK_PERIC, 10,"sclk_spdif" , "sclk_spdif_peric" ,"sclk_pcm1" , "sclk_pcm1_peric" ,"sclk_i2s1" , "sclk_i2s1_peric" ,"sclk_spi2" , "sclk_spi2_peric" , ENABLE_SCLK_PERIC,"sclk_spi1" , "sclk_spi1_peric" , ENABLE_SCLK_PERIC,"sclk_spi0" , "sclk_spi0_peric" , ENABLE_SCLK_PERIC,"sclk_uart2" , "sclk_uart2_peric" ,"sclk_uart1" , "sclk_uart1_peric" ,"sclk_uart0" , "sclk_uart0_peric" ,static const struct samsung_cmu_info peric_cmu_info __initconst = {static void __init exynos5433_cmu_peric_init(struct device_node *np)"samsung,exynos5433-cmu-peric" ,/* * Register offset definitions for CMU_PERIS #define ENABLE_ACLK_PERIS 0x0800#define ENABLE_PCLK_PERIS 0x0900#define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904#define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908#define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c#define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910#define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914#define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918#define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c#define ENABLE_SCLK_PERIS 0x0a00#define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08#define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c#define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10#define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14#define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18#define ENABLE_IP_PERIS0 0x0b00#define ENABLE_IP_PERIS1 0x0b04#define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08#define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c#define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10#define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14#define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18#define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c#define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20static const unsigned long peris_clk_regs[] __initconst = {static const struct samsung_gate_clock peris_gate_clks[] __initconst = {/* ENABLE_ACLK_PERIS */ "aclk_ahb2apb_peris1p" , "aclk_peris_66" ,"aclk_ahb2apb_peris0p" , "aclk_peris_66" ,"aclk_perisnp_66" , "aclk_peris_66" ,/* ENABLE_PCLK_PERIS */ "pclk_hpm_apbif" , "aclk_peris_66" ,"pclk_tmu1_apbif" , "aclk_peris_66" ,"pclk_tmu0_apbif" , "aclk_peris_66" ,"pclk_pmu_peris" , "aclk_peris_66" ,"pclk_sysreg_peris" , "aclk_peris_66" ,"pclk_cmu_top_apbif" , "aclk_peris_66" ,"pclk_wdt_apollo" , "aclk_peris_66" ,"pclk_wdt_atlas" , "aclk_peris_66" ,"pclk_mct" , "aclk_peris_66" ,"pclk_hdmi_cec" , "aclk_peris_66" ,/* ENABLE_PCLK_PERIS_SECURE_TZPC */ "pclk_tzpc12" , "aclk_peris_66" ,"pclk_tzpc11" , "aclk_peris_66" ,"pclk_tzpc10" , "aclk_peris_66" ,"pclk_tzpc9" , "aclk_peris_66" ,"pclk_tzpc8" , "aclk_peris_66" ,"pclk_tzpc7" , "aclk_peris_66" ,"pclk_tzpc6" , "aclk_peris_66" ,"pclk_tzpc5" , "aclk_peris_66" ,"pclk_tzpc4" , "aclk_peris_66" ,"pclk_tzpc3" , "aclk_peris_66" ,"pclk_tzpc2" , "aclk_peris_66" ,"pclk_tzpc1" , "aclk_peris_66" ,"pclk_tzpc0" , "aclk_peris_66" ,/* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */ "pclk_seckey_apbif" , "aclk_peris_66" ,/* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */ "pclk_chipid_apbif" , "aclk_peris_66" ,/* ENABLE_PCLK_PERIS_SECURE_TOPRTC */ "pclk_toprtc" , "aclk_peris_66" ,/* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */ "pclk_custom_efuse_apbif" ,"aclk_peris_66" ,/* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */ "pclk_antirbk_cnt_apbif" ,"aclk_peris_66" ,/* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */ "pclk_otp_con_apbif" ,"aclk_peris_66" ,/* ENABLE_SCLK_PERIS */ "sclk_asv_tb" , "oscclk_efuse_common" ,"sclk_tmu1" , "oscclk_efuse_common" ,"sclk_tmu0" , "oscclk_efuse_common" ,/* ENABLE_SCLK_PERIS_SECURE_SECKEY */ "sclk_seckey" , "oscclk_efuse_common" ,/* ENABLE_SCLK_PERIS_SECURE_CHIPID */ "sclk_chipid" , "oscclk_efuse_common" ,/* ENABLE_SCLK_PERIS_SECURE_TOPRTC */ "sclk_toprtc" , "oscclk_efuse_common" ,/* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */ "sclk_custom_efuse" , "oscclk_efuse_common" ,/* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */ "sclk_antirbk_cnt" , "oscclk_efuse_common" ,/* ENABLE_SCLK_PERIS_SECURE_OTP_CON */ "sclk_otp_con" , "oscclk_efuse_common" ,static const struct samsung_cmu_info peris_cmu_info __initconst = {static void __init exynos5433_cmu_peris_init(struct device_node *np)"samsung,exynos5433-cmu-peris" ,/* * Register offset definitions for CMU_FSYS #define MUX_SEL_FSYS0 0x0200#define MUX_SEL_FSYS1 0x0204#define MUX_SEL_FSYS2 0x0208#define MUX_SEL_FSYS3 0x020c#define MUX_SEL_FSYS4 0x0210#define MUX_ENABLE_FSYS0 0x0300#define MUX_ENABLE_FSYS1 0x0304#define MUX_ENABLE_FSYS2 0x0308#define MUX_ENABLE_FSYS3 0x030c#define MUX_ENABLE_FSYS4 0x0310#define MUX_STAT_FSYS0 0x0400#define MUX_STAT_FSYS1 0x0404#define MUX_STAT_FSYS2 0x0408#define MUX_STAT_FSYS3 0x040c#define MUX_STAT_FSYS4 0x0410#define MUX_IGNORE_FSYS2 0x0508#define MUX_IGNORE_FSYS3 0x050c#define ENABLE_ACLK_FSYS0 0x0800#define ENABLE_ACLK_FSYS1 0x0804#define ENABLE_PCLK_FSYS 0x0900#define ENABLE_SCLK_FSYS 0x0a00#define ENABLE_IP_FSYS0 0x0b00#define ENABLE_IP_FSYS1 0x0b04/* list of all parent clock list */ "oscclk" , "sclk_ufs_mphy" , };"oscclk" , "aclk_fsys_200" , };"oscclk" , "sclk_pcie_100_fsys" ,};"oscclk" , "sclk_ufsunipro_fsys" ,};"oscclk" , "sclk_mmc2_fsys" , };"oscclk" , "sclk_mmc1_fsys" , };"oscclk" , "sclk_mmc0_fsys" , };"oscclk" , "sclk_usbhost30_fsys" ,};"oscclk" , "sclk_usbdrd30_fsys" , };"oscclk" , "phyclk_usbhost30_uhost30_pipe_pclk_phy" , };"oscclk" , "phyclk_usbhost30_uhost30_phyclock_phy" , };"oscclk" , "phyclk_usbhost20_phy_hsic1_phy" , };"oscclk" , "phyclk_usbhost20_phy_clk48mohci_phy" , };"oscclk" , "phyclk_usbhost20_phy_phyclock_phy" , };"oscclk" , "phyclk_usbhost20_phy_freeclk_phy" , };"oscclk" , "phyclk_usbdrd30_udrd30_pipe_pclk_phy" , };"oscclk" , "phyclk_usbdrd30_udrd30_phyclock_phy" , };"oscclk" , "phyclk_ufs_rx1_symbol_phy" , };"oscclk" , "phyclk_ufs_rx0_symbol_phy" , };"oscclk" , "phyclk_ufs_tx1_symbol_phy" , };"oscclk" , "phyclk_ufs_tx0_symbol_phy" , };"oscclk" , "phyclk_lli_mphy_to_ufs_phy" , };"mout_sclk_ufs_mphy_user" ,"mout_phyclk_lli_mphy_to_ufs_user" , };static const unsigned long fsys_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump fsys_suspend_regs[] = {static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = {/* PHY clocks from USBDRD30_PHY */ "phyclk_usbdrd30_udrd30_phyclock_phy" , NULL,"phyclk_usbdrd30_udrd30_pipe_pclk_phy" , NULL,/* PHY clocks from USBHOST30_PHY */ "phyclk_usbhost30_uhost30_phyclock_phy" , NULL,"phyclk_usbhost30_uhost30_pipe_pclk_phy" , NULL,/* PHY clocks from USBHOST20_PHY */ "phyclk_usbhost20_phy_freeclk_phy" , NULL, 0, 60000000),"phyclk_usbhost20_phy_phyclock_phy" , NULL, 0, 60000000),"phyclk_usbhost20_phy_clk48mohci_phy" , NULL,"phyclk_usbhost20_phy_hsic1_phy" , NULL, 0,/* PHY clocks from UFS_PHY */ "phyclk_ufs_tx0_symbol_phy" ,"phyclk_ufs_rx0_symbol_phy" ,"phyclk_ufs_tx1_symbol_phy" ,"phyclk_ufs_rx1_symbol_phy" ,/* PHY clocks from LLI_PHY */ "phyclk_lli_mphy_to_ufs_phy" ,static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {/* MUX_SEL_FSYS0 */ "mout_sclk_ufs_mphy_user" ,"mout_aclk_fsys_200_user" ,/* MUX_SEL_FSYS1 */ "mout_sclk_pcie_100_user" ,"mout_sclk_ufsunipro_user" ,"mout_sclk_mmc2_user" ,"mout_sclk_mmc1_user" ,"mout_sclk_mmc0_user" ,"mout_sclk_usbhost30_user" ,"mout_sclk_usbdrd30_user" ,/* MUX_SEL_FSYS2 */ "mout_phyclk_usbhost30_uhost30_pipe_pclk_user" ,"mout_phyclk_usbhost30_uhost30_phyclock_user" ,"mout_phyclk_usbhost20_phy_hsic1" ,"mout_phyclk_usbhost20_phy_clk48mohci_user" ,"mout_phyclk_usbhost20_phy_phyclock_user" ,"mout_phyclk_usbhost20_phy_freeclk_user" ,"mout_phyclk_usbdrd30_udrd30_pipe_pclk_user" ,"mout_phyclk_usbdrd30_udrd30_phyclock_user" ,/* MUX_SEL_FSYS3 */ "mout_phyclk_ufs_rx1_symbol_user" ,"mout_phyclk_ufs_rx0_symbol_user" ,"mout_phyclk_ufs_tx1_symbol_user" ,"mout_phyclk_ufs_tx0_symbol_user" ,"mout_phyclk_lli_mphy_to_ufs_user" ,/* MUX_SEL_FSYS4 */ "mout_sclk_mphy" , mout_sclk_mphy_p,static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {/* ENABLE_ACLK_FSYS0 */ "aclk_pcie" , "mout_aclk_fsys_200_user" ,"aclk_pdma1" , "mout_aclk_fsys_200_user" ,"aclk_tsi" , "mout_aclk_fsys_200_user" ,"aclk_mmc2" , "mout_aclk_fsys_200_user" ,"aclk_mmc1" , "mout_aclk_fsys_200_user" ,"aclk_mmc0" , "mout_aclk_fsys_200_user" ,"aclk_ufs" , "mout_aclk_fsys_200_user" ,"aclk_usbhost20" , "mout_aclk_fsys_200_user" ,"aclk_usbhost30" , "mout_aclk_fsys_200_user" ,"aclk_usbdrd30" , "mout_aclk_fsys_200_user" ,"aclk_pdma0" , "mout_aclk_fsys_200_user" ,/* ENABLE_ACLK_FSYS1 */ "aclk_xiu_fsyspx" , "mout_aclk_fsys_200_user" ,"aclk_ahb_usblinkh1" ,"mout_aclk_fsys_200_user" , ENABLE_ACLK_FSYS1,"aclk_smmu_pdma1" , "mout_aclk_fsys_200_user" ,"aclk_bts_pcie" , "mout_aclk_fsys_200_user" ,"aclk_axius_pdma1" ,"mout_aclk_fsys_200_user" , ENABLE_ACLK_FSYS1,"aclk_smmu_pdma0" , "mout_aclk_fsys_200_user" ,"aclk_bts_ufs" , "mout_aclk_fsys_200_user" ,"aclk_bts_usbhost30" ,"mout_aclk_fsys_200_user" , ENABLE_ACLK_FSYS1,"aclk_bts_usbdrd30" ,"mout_aclk_fsys_200_user" , ENABLE_ACLK_FSYS1,"aclk_axius_pdma0" ,"mout_aclk_fsys_200_user" , ENABLE_ACLK_FSYS1,"aclk_axius_usbhs" ,"mout_aclk_fsys_200_user" , ENABLE_ACLK_FSYS1,"aclk_axius_fsyssx" ,"mout_aclk_fsys_200_user" , ENABLE_ACLK_FSYS1,"aclk_ahb2apb_fsysp" ,"mout_aclk_fsys_200_user" , ENABLE_ACLK_FSYS1,"aclk_ahb2axi_usbhs" ,"mout_aclk_fsys_200_user" , ENABLE_ACLK_FSYS1,"aclk_ahb_usblinkh0" ,"mout_aclk_fsys_200_user" , ENABLE_ACLK_FSYS1,"aclk_ahb_usbhs" , "mout_aclk_fsys_200_user" ,"aclk_ahb_fsysh" , "mout_aclk_fsys_200_user" ,"aclk_xiu_fsysx" , "mout_aclk_fsys_200_user" ,"aclk_xiu_fsyssx" , "mout_aclk_fsys_200_user" ,"aclk_fsysnp_200" , "mout_aclk_fsys_200_user" ,"aclk_fsysnd_200" , "mout_aclk_fsys_200_user" ,/* ENABLE_PCLK_FSYS */ "pclk_pcie_ctrl" , "mout_aclk_fsys_200_user" ,"pclk_smmu_pdma1" , "mout_aclk_fsys_200_user" ,"pclk_pcie_phy" , "mout_aclk_fsys_200_user" ,"pclk_bts_pcie" , "mout_aclk_fsys_200_user" ,"pclk_smmu_pdma0" , "mout_aclk_fsys_200_user" ,"pclk_bts_ufs" , "mout_aclk_fsys_200_user" ,"pclk_bts_usbhost30" ,"mout_aclk_fsys_200_user" , ENABLE_PCLK_FSYS, 4, 0, 0),"pclk_bts_usbdrd30" ,"mout_aclk_fsys_200_user" , ENABLE_PCLK_FSYS, 3, 0, 0),"pclk_gpio_fsys" , "mout_aclk_fsys_200_user" ,"pclk_pmu_fsys" , "mout_aclk_fsys_200_user" ,"pclk_sysreg_fsys" ,"mout_aclk_fsys_200_user" , ENABLE_PCLK_FSYS,/* ENABLE_SCLK_FSYS */ "sclk_pcie_100" , "mout_sclk_pcie_100_user" ,"phyclk_usbhost30_uhost30_pipe_pclk" ,"mout_phyclk_usbhost30_uhost30_pipe_pclk_user" ,"phyclk_usbhost30_uhost30_phyclock" ,"mout_phyclk_usbhost30_uhost30_phyclock_user" ,"phyclk_ufs_rx1_symbol" ,"mout_phyclk_ufs_rx1_symbol_user" , ENABLE_SCLK_FSYS,"phyclk_ufs_rx0_symbol" ,"mout_phyclk_ufs_rx0_symbol_user" , ENABLE_SCLK_FSYS,"phyclk_ufs_tx1_symbol" ,"mout_phyclk_ufs_tx1_symbol_user" , ENABLE_SCLK_FSYS,"phyclk_ufs_tx0_symbol" ,"mout_phyclk_ufs_tx0_symbol_user" , ENABLE_SCLK_FSYS,"phyclk_usbhost20_phy_hsic1" ,"mout_phyclk_usbhost20_phy_hsic1" , ENABLE_SCLK_FSYS,"phyclk_usbhost20_phy_clk48mohci" ,"mout_phyclk_usbhost20_phy_clk48mohci_user" ,"phyclk_usbhost20_phy_phyclock" ,"mout_phyclk_usbhost20_phy_phyclock_user" ,"phyclk_usbhost20_phy_freeclk" ,"mout_phyclk_usbhost20_phy_freeclk_user" ,"phyclk_usbdrd30_udrd30_pipe_pclk" ,"mout_phyclk_usbdrd30_udrd30_pipe_pclk_user" ,"phyclk_usbdrd30_udrd30_phyclock" ,"mout_phyclk_usbdrd30_udrd30_phyclock_user" ,"sclk_mphy" , "mout_sclk_mphy" ,"sclk_ufsunipro" , "mout_sclk_ufsunipro_user" ,"sclk_mmc2" , "mout_sclk_mmc2_user" ,"sclk_mmc1" , "mout_sclk_mmc1_user" ,"sclk_mmc0" , "mout_sclk_mmc0_user" ,"sclk_usbhost30" , "mout_sclk_usbhost30_user" ,"sclk_usbdrd30" , "mout_sclk_usbdrd30_user" ,/* ENABLE_IP_FSYS0 */ "pcie" , "sclk_pcie_100" , ENABLE_IP_FSYS0, 17, 0, 0),"pdma1" , "aclk_pdma1" , ENABLE_IP_FSYS0, 15, 0, 0),"pdma0" , "aclk_pdma0" , ENABLE_IP_FSYS0, 0, 0, 0),static const struct samsung_cmu_info fsys_cmu_info __initconst = {"aclk_fsys_200" ,/* * Register offset definitions for CMU_G2D #define MUX_SEL_G2D0 0x0200#define MUX_SEL_ENABLE_G2D0 0x0300#define MUX_SEL_STAT_G2D0 0x0400#define DIV_G2D 0x0600#define DIV_STAT_G2D 0x0700#define DIV_ENABLE_ACLK_G2D 0x0800#define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804#define DIV_ENABLE_PCLK_G2D 0x0900#define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904#define DIV_ENABLE_IP_G2D0 0x0b00#define DIV_ENABLE_IP_G2D1 0x0b04#define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08static const unsigned long g2d_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump g2d_suspend_regs[] = {/* list of all parent clock list */ "oscclk" , "aclk_g2d_266" , };"oscclk" , "aclk_g2d_400" , };static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {/* MUX_SEL_G2D0 */ "mout_aclk_g2d_266_user" ,"mout_aclk_g2d_400_user" ,static const struct samsung_div_clock g2d_div_clks[] __initconst = {/* DIV_G2D */ "div_pclk_g2d" , "mout_aclk_g2d_266_user" ,static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {/* DIV_ENABLE_ACLK_G2D */ "aclk_smmu_mdma1" , "mout_aclk_g2d_266_user" ,"aclk_bts_mdam1" , "mout_aclk_g2d_266_user" ,"aclk_bts_g2d" , "mout_aclk_g2d_400_user" ,"aclk_alb_g2d" , "mout_aclk_g2d_400_user" ,"aclk_axius_g2dx" , "mout_aclk_g2d_400_user" ,"aclk_asyncaxi_sysx" ,"mout_aclk_g2d_400_user" , DIV_ENABLE_ACLK_G2D,"aclk_ahb2apb_g2d1p" , "div_pclk_g2d" ,"aclk_ahb2apb_g2d0p" , "div_pclk_g2d" ,"aclk_xiu_g2dx" , "mout_aclk_g2d_400_user" ,"aclk_g2dnp_133" , "div_pclk_g2d" ,"aclk_g2dnd_400" , "mout_aclk_g2d_400_user" ,"aclk_mdma1" , "mout_aclk_g2d_266_user" ,"aclk_g2d" , "mout_aclk_g2d_400_user" ,/* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */ "aclk_smmu_g2d" , "mout_aclk_g2d_400_user" ,/* DIV_ENABLE_PCLK_G2D */ "pclk_smmu_mdma1" , "div_pclk_g2d" ,"pclk_bts_mdam1" , "div_pclk_g2d" ,"pclk_bts_g2d" , "div_pclk_g2d" ,"pclk_alb_g2d" , "div_pclk_g2d" ,"pclk_asyncaxi_sysx" , "div_pclk_g2d" ,"pclk_pmu_g2d" , "div_pclk_g2d" ,"pclk_sysreg_g2d" , "div_pclk_g2d" ,"pclk_g2d" , "div_pclk_g2d" , DIV_ENABLE_PCLK_G2D,/* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */ "pclk_smmu_g2d" , "div_pclk_g2d" ,static const struct samsung_cmu_info g2d_cmu_info __initconst = {"aclk_g2d_400" ,/* * Register offset definitions for CMU_DISP #define DISP_PLL_LOCK 0x0000#define DISP_PLL_CON0 0x0100#define DISP_PLL_CON1 0x0104#define DISP_PLL_FREQ_DET 0x0108#define MUX_SEL_DISP0 0x0200#define MUX_SEL_DISP1 0x0204#define MUX_SEL_DISP2 0x0208#define MUX_SEL_DISP3 0x020c#define MUX_SEL_DISP4 0x0210#define MUX_ENABLE_DISP0 0x0300#define MUX_ENABLE_DISP1 0x0304#define MUX_ENABLE_DISP2 0x0308#define MUX_ENABLE_DISP3 0x030c#define MUX_ENABLE_DISP4 0x0310#define MUX_STAT_DISP0 0x0400#define MUX_STAT_DISP1 0x0404#define MUX_STAT_DISP2 0x0408#define MUX_STAT_DISP3 0x040c#define MUX_STAT_DISP4 0x0410#define MUX_IGNORE_DISP2 0x0508#define DIV_DISP 0x0600#define DIV_DISP_PLL_FREQ_DET 0x0604#define DIV_STAT_DISP 0x0700#define DIV_STAT_DISP_PLL_FREQ_DET 0x0704#define ENABLE_ACLK_DISP0 0x0800#define ENABLE_ACLK_DISP1 0x0804#define ENABLE_PCLK_DISP 0x0900#define ENABLE_SCLK_DISP 0x0a00#define ENABLE_IP_DISP0 0x0b00#define ENABLE_IP_DISP1 0x0b04#define CLKOUT_CMU_DISP 0x0c00#define CLKOUT_CMU_DISP_DIV_STAT 0x0c04static const unsigned long disp_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump disp_suspend_regs[] = {/* PLL has to be enabled for suspend */ /* ignore status of external PHY muxes during suspend to avoid hangs */ /* list of all parent clock list */ "oscclk" , "fout_disp_pll" , };"oscclk" , "sclk_dsim1_disp" , };"oscclk" , "sclk_dsim0_disp" , };"oscclk" , "sclk_dsd_disp" , };"oscclk" ,"sclk_decon_tv_eclk_disp" , };"oscclk" ,"sclk_decon_vclk_disp" , };"oscclk" ,"sclk_decon_eclk_disp" , };"oscclk" ,"sclk_decon_tv_vclk_disp" , };"oscclk" , "aclk_disp_333" , };"oscclk" ,"phyclk_mipidphy1_bitclkdiv8_phy" , };"oscclk" ,"phyclk_mipidphy1_rxclkesc0_phy" , };"oscclk" ,"phyclk_mipidphy0_bitclkdiv8_phy" , };"oscclk" ,"phyclk_mipidphy0_rxclkesc0_phy" , };"oscclk" ,"phyclk_hdmiphy_tmds_clko_phy" , };"oscclk" ,"phyclk_hdmiphy_pixel_clko_phy" , };"mout_disp_pll" ,"mout_sclk_dsim0_user" , };"mout_disp_pll" ,"mout_sclk_decon_tv_eclk_user" , };"mout_disp_pll" ,"mout_sclk_decon_vclk_user" , };"mout_disp_pll" ,"mout_sclk_decon_eclk_user" , };"mout_sclk_dsim1_a_disp" ,"mout_sclk_dsim1_user" , };"mout_phyclk_hdmiphy_pixel_clko_user" ,"mout_sclk_decon_tv_vclk_b_disp" , };"mout_sclk_decon_tv_vclk_a_disp" ,"mout_sclk_decon_tv_vclk_user" , };static const struct samsung_pll_clock disp_pll_clks[] __initconst = {"fout_disp_pll" , "oscclk" ,static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = {/* * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}. * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk} * and sclk_decon_{vclk|tv_vclk}. "sclk_rgb_vclk" , "sclk_decon_vclk" ,"sclk_rgb_tv_vclk" , "sclk_decon_tv_vclk" ,static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {/* PHY clocks from MIPI_DPHY1 */ "phyclk_mipidphy1_bitclkdiv8_phy" , NULL, 0, 188000000),"phyclk_mipidphy1_rxclkesc0_phy" , NULL, 0, 100000000),/* PHY clocks from MIPI_DPHY0 */ "phyclk_mipidphy0_bitclkdiv8_phy" ,"phyclk_mipidphy0_rxclkesc0_phy" ,/* PHY clocks from HDMI_PHY */ "phyclk_hdmiphy_tmds_clko_phy" ,"phyclk_hdmiphy_pixel_clko_phy" ,static const struct samsung_mux_clock disp_mux_clks[] __initconst = {/* MUX_SEL_DISP0 */ "mout_disp_pll" , mout_disp_pll_p, MUX_SEL_DISP0,/* MUX_SEL_DISP1 */ "mout_sclk_dsim1_user" ,"mout_sclk_dsim0_user" ,"mout_sclk_dsd_user" , mout_sclk_dsd_user_p,"mout_sclk_decon_tv_eclk_user" ,"mout_sclk_decon_vclk_user" ,"mout_sclk_decon_eclk_user" ,"mout_sclk_decon_tv_vclk_user" ,"mout_aclk_disp_333_user" ,/* MUX_SEL_DISP2 */ "mout_phyclk_mipidphy1_bitclkdiv8_user" ,"mout_phyclk_mipidphy1_rxclkesc0_user" ,"mout_phyclk_mipidphy0_bitclkdiv8_user" ,"mout_phyclk_mipidphy0_rxclkesc0_user" ,"mout_phyclk_hdmiphy_tmds_clko_user" ,"mout_phyclk_hdmiphy_pixel_clko_user" ,/* MUX_SEL_DISP3 */ "mout_sclk_dsim0" , mout_sclk_dsim0_p,"mout_sclk_decon_tv_eclk" ,"mout_sclk_decon_vclk" ,"mout_sclk_decon_eclk" ,/* MUX_SEL_DISP4 */ "mout_sclk_dsim1_b_disp" ,"mout_sclk_dsim1_a_disp" ,"mout_sclk_decon_tv_vclk_c_disp" ,"mout_sclk_decon_tv_vclk_b_disp" ,"mout_sclk_decon_tv_vclk_a_disp" ,static const struct samsung_div_clock disp_div_clks[] __initconst = {/* DIV_DISP */ "div_sclk_dsim1_disp" ,"mout_sclk_dsim1_b_disp" , DIV_DISP, 24, 3),"div_sclk_decon_tv_vclk_disp" ,"mout_sclk_decon_tv_vclk_c_disp" , DIV_DISP, 20, 3),"div_sclk_dsim0_disp" , "mout_sclk_dsim0" ,"div_sclk_decon_tv_eclk_disp" ,"mout_sclk_decon_tv_eclk" , DIV_DISP, 12, 3),"div_sclk_decon_vclk_disp" ,"mout_sclk_decon_vclk" , DIV_DISP, 8, 3),"div_sclk_decon_eclk_disp" ,"mout_sclk_decon_eclk" , DIV_DISP, 4, 3),"div_pclk_disp" , "mout_aclk_disp_333_user" ,static const struct samsung_gate_clock disp_gate_clks[] __initconst = {/* ENABLE_ACLK_DISP0 */ "aclk_decon_tv" , "mout_aclk_disp_333_user" ,"aclk_decon" , "mout_aclk_disp_333_user" ,/* ENABLE_ACLK_DISP1 */ "aclk_smmu_tv1x" , "mout_aclk_disp_333_user" ,"aclk_smmu_tv0x" , "mout_aclk_disp_333_user" ,"aclk_smmu_decon1x" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 23, 0, 0),"aclk_smmu_decon0x" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 22, 0, 0),"aclk_bts_decon_tv_m3" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 21, 0, 0),"aclk_bts_decon_tv_m2" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 20, 0, 0),"aclk_bts_decon_tv_m1" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 19, 0, 0),"aclk-bts_decon_tv_m0" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 18, 0, 0),"aclk_bts_decon_nm4" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 17, 0, 0),"aclk_bts_decon_nm3" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 16, 0, 0),"aclk_bts_decon_nm2" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 15, 0, 0),"aclk_bts_decon_nm1" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 14, 0, 0),"aclk_bts_decon_nm0" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 13, 0, 0),"aclk_ahb2apb_dispsfr2p" ,"div_pclk_disp" , ENABLE_ACLK_DISP1,"aclk_ahb2apb_dispsfr1p" ,"div_pclk_disp" , ENABLE_ACLK_DISP1,"aclk_ahb2apb_dispsfr0p" ,"div_pclk_disp" , ENABLE_ACLK_DISP1,"aclk_ahb_disph" , "div_pclk_disp" ,"aclk_xiu_tv1x" , "mout_aclk_disp_333_user" ,"aclk_xiu_tv0x" , "mout_aclk_disp_333_user" ,"aclk_xiu_decon1x" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 5, 0, 0),"aclk_xiu_decon0x" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 4, 0, 0),"aclk_xiu_disp1x" , "mout_aclk_disp_333_user" ,"aclk_xiu_dispnp_100" , "div_pclk_disp" ,"aclk_disp1nd_333" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1, 1,"aclk_disp0nd_333" ,"mout_aclk_disp_333_user" , ENABLE_ACLK_DISP1,/* ENABLE_PCLK_DISP */ "pclk_smmu_tv1x" , "div_pclk_disp" ,"pclk_smmu_tv0x" , "div_pclk_disp" ,"pclk_smmu_decon1x" , "div_pclk_disp" ,"pclk_smmu_decon0x" , "div_pclk_disp" ,"pclk_bts_decon_tv_m3" , "div_pclk_disp" ,"pclk_bts_decon_tv_m2" , "div_pclk_disp" ,"pclk_bts_decon_tv_m1" , "div_pclk_disp" ,"pclk_bts_decon_tv_m0" , "div_pclk_disp" ,"pclk_bts_deconm4" , "div_pclk_disp" ,"pclk_bts_deconm3" , "div_pclk_disp" ,"pclk_bts_deconm2" , "div_pclk_disp" ,"pclk_bts_deconm1" , "div_pclk_disp" ,"pclk_bts_deconm0" , "div_pclk_disp" ,"pclk_mic1" , "div_pclk_disp" ,"pclk_pmu_disp" , "div_pclk_disp" ,"pclk_sysreg_disp" , "div_pclk_disp" ,"pclk_hdmiphy" , "div_pclk_disp" ,"pclk_hdmi" , "div_pclk_disp" ,"pclk_mic0" , "div_pclk_disp" ,"pclk_dsim1" , "div_pclk_disp" ,"pclk_dsim0" , "div_pclk_disp" ,"pclk_decon_tv" , "div_pclk_disp" ,"pclk_decon" , "div_pclk_disp" ,/* ENABLE_SCLK_DISP */ "phyclk_mipidphy1_bitclkdiv8" ,"mout_phyclk_mipidphy1_bitclkdiv8_user" ,"phyclk_mipidphy1_rxclkesc0" ,"mout_phyclk_mipidphy1_rxclkesc0_user" ,"sclk_rgb_tv_vclk_to_dsim1" ,"sclk_rgb_tv_vclk" , ENABLE_SCLK_DISP, 24, 0, 0),"sclk_rgb_tv_vclk_to_mic1" ,"sclk_rgb_tv_vclk" , ENABLE_SCLK_DISP, 23, 0, 0),"sclk_dsim1" , "div_sclk_dsim1_disp" ,"sclk_decon_tv_vclk" ,"div_sclk_decon_tv_vclk_disp" ,"phyclk_mipidphy0_bitclkdiv8" ,"mout_phyclk_mipidphy0_bitclkdiv8_user" ,"phyclk_mipidphy0_rxclkesc0" ,"mout_phyclk_mipidphy0_rxclkesc0_user" ,"phyclk_hdmiphy_tmds_clko" ,"mout_phyclk_hdmiphy_tmds_clko_user" ,"phyclk_hdmi_pixel" ,"sclk_rgb_tv_vclk" , ENABLE_SCLK_DISP, 12, 0, 0),"sclk_rgb_vclk_to_smies" ,"sclk_rgb_vclk" , ENABLE_SCLK_DISP, 11, 0, 0),"sclk_rgb_vclk_to_dsim0" ,"sclk_rgb_vclk" , ENABLE_SCLK_DISP, 9, 0, 0),"sclk_rgb_vclk_to_mic0" ,"sclk_rgb_vclk" , ENABLE_SCLK_DISP, 8, 0, 0),"sclk_dsd" , "mout_sclk_dsd_user" ,"sclk_hdmi_spdif" , "sclk_hdmi_spdif_disp" ,"sclk_dsim0" , "div_sclk_dsim0_disp" ,"sclk_decon_tv_eclk" ,"div_sclk_decon_tv_eclk_disp" ,"sclk_decon_vclk" ,"div_sclk_decon_vclk_disp" , ENABLE_SCLK_DISP, 3, 0, 0),"sclk_decon_eclk" ,"div_sclk_decon_eclk_disp" , ENABLE_SCLK_DISP, 2, 0, 0),static const struct samsung_cmu_info disp_cmu_info __initconst = {"aclk_disp_333" ,/* * Register offset definitions for CMU_AUD #define MUX_SEL_AUD0 0x0200#define MUX_SEL_AUD1 0x0204#define MUX_ENABLE_AUD0 0x0300#define MUX_ENABLE_AUD1 0x0304#define MUX_STAT_AUD0 0x0400#define DIV_AUD0 0x0600#define DIV_AUD1 0x0604#define DIV_STAT_AUD0 0x0700#define DIV_STAT_AUD1 0x0704#define ENABLE_ACLK_AUD 0x0800#define ENABLE_PCLK_AUD 0x0900#define ENABLE_SCLK_AUD0 0x0a00#define ENABLE_SCLK_AUD1 0x0a04#define ENABLE_IP_AUD0 0x0b00#define ENABLE_IP_AUD1 0x0b04static const unsigned long aud_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump aud_suspend_regs[] = {/* list of all parent clock list */ "oscclk" , "fout_aud_pll" , };"mout_aud_pll_user" , "ioclk_audiocdclk0" ,};static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {"ioclk_jtag_tclk" , NULL, 0, 33000000),"ioclk_slimbus_clk" , NULL, 0, 25000000),"ioclk_i2s_bclk" , NULL, 0, 50000000),static const struct samsung_mux_clock aud_mux_clks[] __initconst = {/* MUX_SEL_AUD0 */ "mout_aud_pll_user" ,/* MUX_SEL_AUD1 */ "mout_sclk_aud_pcm" , mout_sclk_aud_pcm_p,"mout_sclk_aud_i2s" , mout_sclk_aud_pcm_p,static const struct samsung_div_clock aud_div_clks[] __initconst = {/* DIV_AUD0 */ "div_atclk_aud" , "div_aud_ca5" , DIV_AUD0,"div_pclk_dbg_aud" , "div_aud_ca5" , DIV_AUD0,"div_aclk_aud" , "div_aud_ca5" , DIV_AUD0,"div_aud_ca5" , "mout_aud_pll_user" , DIV_AUD0,/* DIV_AUD1 */ "div_sclk_aud_slimbus" ,"mout_aud_pll_user" , DIV_AUD1, 16, 5),"div_sclk_aud_uart" , "mout_aud_pll_user" ,"div_sclk_aud_pcm" , "mout_sclk_aud_pcm" ,"div_sclk_aud_i2s" , "mout_sclk_aud_i2s" ,static const struct samsung_gate_clock aud_gate_clks[] __initconst = {/* ENABLE_ACLK_AUD */ "aclk_intr_ctrl" , "div_aclk_aud" ,"aclk_smmu_lpassx" , "div_aclk_aud" ,"aclk_xiu_lpassx" , "div_aclk_aud" ,"aclk_audnp_133" , "div_aclk_aud" ,"aclk_audnd_133" , "div_aclk_aud" ,"aclk_sramc" , "div_aclk_aud" , ENABLE_ACLK_AUD,"aclk_dmac" , "div_aclk_aud" , ENABLE_ACLK_AUD,/* ENABLE_PCLK_AUD */ "pclk_wdt1" , "div_aclk_aud" , ENABLE_PCLK_AUD,"pclk_wdt0" , "div_aclk_aud" , ENABLE_PCLK_AUD,"pclk_sfr1" , "div_aclk_aud" , ENABLE_PCLK_AUD,"pclk_smmu_lpassx" , "div_aclk_aud" ,"pclk_gpio_aud" , "div_aclk_aud" ,"pclk_pmu_aud" , "div_aclk_aud" ,"pclk_sysreg_aud" , "div_aclk_aud" ,"pclk_aud_slimbus" , "div_aclk_aud" ,"pclk_aud_uart" , "div_aclk_aud" ,"pclk_aud_pcm" , "div_aclk_aud" ,"pclk_aud_i2s" , "div_aclk_aud" ,"pclk_timer" , "div_aclk_aud" , ENABLE_PCLK_AUD,"pclk_sfr0_ctrl" , "div_aclk_aud" ,/* ENABLE_SCLK_AUD0 */ "atclk_aud" , "div_atclk_aud" , ENABLE_SCLK_AUD0,"pclk_dbg_aud" , "div_pclk_dbg_aud" ,"sclk_aud_ca5" , "div_aud_ca5" , ENABLE_SCLK_AUD0,/* ENABLE_SCLK_AUD1 */ "sclk_jtag_tck" , "ioclk_jtag_tclk" ,"sclk_slimbus_clkin" , "ioclk_slimbus_clk" ,"sclk_aud_slimbus" , "div_sclk_aud_slimbus" ,"sclk_aud_uart" , "div_sclk_aud_uart" ,"sclk_aud_pcm" , "div_sclk_aud_pcm" ,"sclk_i2s_bclk" , "ioclk_i2s_bclk" ,"sclk_aud_i2s" , "div_sclk_aud_i2s" ,static const struct samsung_cmu_info aud_cmu_info __initconst = {"fout_aud_pll" ,/* * Register offset definitions for CMU_BUS{0|1|2} #define DIV_BUS 0x0600#define DIV_STAT_BUS 0x0700#define ENABLE_ACLK_BUS 0x0800#define ENABLE_PCLK_BUS 0x0900#define ENABLE_IP_BUS0 0x0b00#define ENABLE_IP_BUS1 0x0b04#define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */ #define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */ #define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */ /* list of all parent clock list */ "oscclk" , "aclk_bus2_400" , };#define CMU_BUS_COMMON_CLK_REGS \static const unsigned long bus01_clk_regs[] __initconst = {static const unsigned long bus2_clk_regs[] __initconst = {static const struct samsung_div_clock bus0_div_clks[] __initconst = {/* DIV_BUS0 */ "div_pclk_bus0_133" , "aclk_bus0_400" ,/* CMU_BUS0 clocks */ static const struct samsung_gate_clock bus0_gate_clks[] __initconst = {/* ENABLE_ACLK_BUS0 */ "aclk_ahb2apb_bus0p" , "div_pclk_bus0_133" ,"aclk_bus0np_133" , "div_pclk_bus0_133" ,"aclk_bus0nd_400" , "aclk_bus0_400" ,/* ENABLE_PCLK_BUS0 */ "pclk_bus0srvnd_133" , "div_pclk_bus0_133" ,"pclk_pmu_bus0" , "div_pclk_bus0_133" ,"pclk_sysreg_bus0" , "div_pclk_bus0_133" ,/* CMU_BUS1 clocks */ static const struct samsung_div_clock bus1_div_clks[] __initconst = {/* DIV_BUS1 */ "div_pclk_bus1_133" , "aclk_bus1_400" ,static const struct samsung_gate_clock bus1_gate_clks[] __initconst = {/* ENABLE_ACLK_BUS1 */ "aclk_ahb2apb_bus1p" , "div_pclk_bus1_133" ,"aclk_bus1np_133" , "div_pclk_bus1_133" ,"aclk_bus1nd_400" , "aclk_bus1_400" ,/* ENABLE_PCLK_BUS1 */ "pclk_bus1srvnd_133" , "div_pclk_bus1_133" ,"pclk_pmu_bus1" , "div_pclk_bus1_133" ,"pclk_sysreg_bus1" , "div_pclk_bus1_133" ,/* CMU_BUS2 clocks */ static const struct samsung_mux_clock bus2_mux_clks[] __initconst = {/* MUX_SEL_BUS2 */ "mout_aclk_bus2_400_user" ,static const struct samsung_div_clock bus2_div_clks[] __initconst = {/* DIV_BUS2 */ "div_pclk_bus2_133" ,"mout_aclk_bus2_400_user" , DIV_BUS, 0, 3),static const struct samsung_gate_clock bus2_gate_clks[] __initconst = {/* ENABLE_ACLK_BUS2 */ "aclk_ahb2apb_bus2p" , "div_pclk_bus2_133" ,"aclk_bus2np_133" , "div_pclk_bus2_133" ,"aclk_bus2bend_400" ,"mout_aclk_bus2_400_user" , ENABLE_ACLK_BUS,"aclk_bus2rtnd_400" ,"mout_aclk_bus2_400_user" , ENABLE_ACLK_BUS,/* ENABLE_PCLK_BUS2 */ "pclk_bus2srvnd_133" , "div_pclk_bus2_133" ,"pclk_pmu_bus2" , "div_pclk_bus2_133" ,"pclk_sysreg_bus2" , "div_pclk_bus2_133" ,#define CMU_BUS_INFO_CLKS(id) \## id## _div_clks, \## id## _div_clks), \## id## _gate_clks, \## id## _gate_clks), \static const struct samsung_cmu_info bus0_cmu_info __initconst = {static const struct samsung_cmu_info bus1_cmu_info __initconst = {static const struct samsung_cmu_info bus2_cmu_info __initconst = {#define exynos5433_cmu_bus_init(id) \static void __init exynos5433_cmu_bus## id## _init(struct device_node *np)\## id## _cmu_info); \## id, \"samsung,exynos5433-cmu-bus" #id , \## id## _init)/* * Register offset definitions for CMU_G3D #define G3D_PLL_LOCK 0x0000#define G3D_PLL_CON0 0x0100#define G3D_PLL_CON1 0x0104#define G3D_PLL_FREQ_DET 0x010c#define MUX_SEL_G3D 0x0200#define MUX_ENABLE_G3D 0x0300#define MUX_STAT_G3D 0x0400#define DIV_G3D 0x0600#define DIV_G3D_PLL_FREQ_DET 0x0604#define DIV_STAT_G3D 0x0700#define DIV_STAT_G3D_PLL_FREQ_DET 0x0704#define ENABLE_ACLK_G3D 0x0800#define ENABLE_PCLK_G3D 0x0900#define ENABLE_SCLK_G3D 0x0a00#define ENABLE_IP_G3D0 0x0b00#define ENABLE_IP_G3D1 0x0b04#define CLKOUT_CMU_G3D 0x0c00#define CLKOUT_CMU_G3D_DIV_STAT 0x0c04#define CLK_STOPCTRL 0x1000static const unsigned long g3d_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump g3d_suspend_regs[] = {/* list of all parent clock list */ "mout_g3d_pll" , "aclk_g3d_400" , };"oscclk" , "fout_g3d_pll" , };static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {"fout_g3d_pll" , "oscclk" ,static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {/* MUX_SEL_G3D */ "mout_aclk_g3d_400" , mout_aclk_g3d_400_p,"mout_g3d_pll" , mout_g3d_pll_p,static const struct samsung_div_clock g3d_div_clks[] __initconst = {/* DIV_G3D */ "div_sclk_hpm_g3d" , "mout_g3d_pll" , DIV_G3D,"div_pclk_g3d" , "div_aclk_g3d" , DIV_G3D,"div_aclk_g3d" , "mout_aclk_g3d_400" , DIV_G3D,static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {/* ENABLE_ACLK_G3D */ "aclk_bts_g3d1" , "div_aclk_g3d" ,"aclk_bts_g3d0" , "div_aclk_g3d" ,"aclk_asyncapbs_g3d" , "div_pclk_g3d" ,"aclk_asyncapbm_g3d" , "div_aclk_g3d" ,"aclk_ahb2apb_g3dp" , "div_pclk_g3d" ,"aclk_g3dnp_150" , "div_pclk_g3d" ,"aclk_g3dnd_600" , "div_aclk_g3d" ,"aclk_g3d" , "div_aclk_g3d" ,/* ENABLE_PCLK_G3D */ "pclk_bts_g3d1" , "div_pclk_g3d" ,"pclk_bts_g3d0" , "div_pclk_g3d" ,"pclk_pmu_g3d" , "div_pclk_g3d" ,"pclk_sysreg_g3d" , "div_pclk_g3d" ,/* ENABLE_SCLK_G3D */ "sclk_hpm_g3d" , "div_sclk_hpm_g3d" ,static const struct samsung_cmu_info g3d_cmu_info __initconst = {"aclk_g3d_400" ,/* * Register offset definitions for CMU_GSCL #define MUX_SEL_GSCL 0x0200#define MUX_ENABLE_GSCL 0x0300#define MUX_STAT_GSCL 0x0400#define ENABLE_ACLK_GSCL 0x0800#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c#define ENABLE_PCLK_GSCL 0x0900#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c#define ENABLE_IP_GSCL0 0x0b00#define ENABLE_IP_GSCL1 0x0b04#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10static const unsigned long gscl_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump gscl_suspend_regs[] = {/* list of all parent clock list */ "oscclk" , "aclk_gscl_111" , };"oscclk" , "aclk_gscl_333" , };static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {/* MUX_SEL_GSCL */ "mout_aclk_gscl_111_user" ,"mout_aclk_gscl_333_user" ,static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {/* ENABLE_ACLK_GSCL */ "aclk_bts_gscl2" , "mout_aclk_gscl_333_user" ,"aclk_bts_gscl1" , "mout_aclk_gscl_333_user" ,"aclk_bts_gscl0" , "mout_aclk_gscl_333_user" ,"aclk_ahb2apb_gsclp" ,"mout_aclk_gscl_111_user" , ENABLE_ACLK_GSCL,"aclk_xiu_gsclx" , "mout_aclk_gscl_333_user" ,"aclk_gsclnp_111" , "mout_aclk_gscl_111_user" ,"aclk_gsclrtnd_333" ,"mout_aclk_gscl_333_user" , ENABLE_ACLK_GSCL, 5,"aclk_gsclbend_333" ,"mout_aclk_gscl_333_user" , ENABLE_ACLK_GSCL, 4,"aclk_gsd" , "mout_aclk_gscl_333_user" ,"aclk_gscl2" , "mout_aclk_gscl_333_user" ,"aclk_gscl1" , "mout_aclk_gscl_333_user" ,"aclk_gscl0" , "mout_aclk_gscl_333_user" ,/* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */ "aclk_smmu_gscl0" , "mout_aclk_gscl_333_user" ,/* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */ "aclk_smmu_gscl1" , "mout_aclk_gscl_333_user" ,/* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */ "aclk_smmu_gscl2" , "mout_aclk_gscl_333_user" ,/* ENABLE_PCLK_GSCL */ "pclk_bts_gscl2" , "mout_aclk_gscl_111_user" ,"pclk_bts_gscl1" , "mout_aclk_gscl_111_user" ,"pclk_bts_gscl0" , "mout_aclk_gscl_111_user" ,"pclk_pmu_gscl" , "mout_aclk_gscl_111_user" ,"pclk_sysreg_gscl" ,"mout_aclk_gscl_111_user" , ENABLE_PCLK_GSCL,"pclk_gscl2" , "mout_aclk_gscl_111_user" ,"pclk_gscl1" , "mout_aclk_gscl_111_user" ,"pclk_gscl0" , "mout_aclk_gscl_111_user" ,/* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */ "pclk_smmu_gscl0" , "mout_aclk_gscl_111_user" ,/* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */ "pclk_smmu_gscl1" , "mout_aclk_gscl_111_user" ,/* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */ "pclk_smmu_gscl2" , "mout_aclk_gscl_111_user" ,static const struct samsung_cmu_info gscl_cmu_info __initconst = {"aclk_gscl_111" ,/* * Register offset definitions for CMU_APOLLO #define APOLLO_PLL_LOCK 0x0000#define APOLLO_PLL_CON0 0x0100#define APOLLO_PLL_CON1 0x0104#define APOLLO_PLL_FREQ_DET 0x010c#define MUX_SEL_APOLLO0 0x0200#define MUX_SEL_APOLLO1 0x0204#define MUX_SEL_APOLLO2 0x0208#define MUX_ENABLE_APOLLO0 0x0300#define MUX_ENABLE_APOLLO1 0x0304#define MUX_ENABLE_APOLLO2 0x0308#define MUX_STAT_APOLLO0 0x0400#define MUX_STAT_APOLLO1 0x0404#define MUX_STAT_APOLLO2 0x0408#define DIV_APOLLO0 0x0600#define DIV_APOLLO1 0x0604#define DIV_APOLLO_PLL_FREQ_DET 0x0608#define DIV_STAT_APOLLO0 0x0700#define DIV_STAT_APOLLO1 0x0704#define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708#define ENABLE_ACLK_APOLLO 0x0800#define ENABLE_PCLK_APOLLO 0x0900#define ENABLE_SCLK_APOLLO 0x0a00#define ENABLE_IP_APOLLO0 0x0b00#define ENABLE_IP_APOLLO1 0x0b04#define CLKOUT_CMU_APOLLO 0x0c00#define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04#define ARMCLK_STOPCTRL 0x1000#define APOLLO_PWR_CTRL 0x1020#define APOLLO_PWR_CTRL2 0x1024#define APOLLO_INTR_SPREAD_ENABLE 0x1080#define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084#define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088static const unsigned long apollo_clk_regs[] __initconst = {/* list of all parent clock list */ "oscclk" , "fout_apollo_pll" , };"oscclk" , "sclk_bus_pll_apollo" , };"mout_apollo_pll" ,"mout_bus_pll_apollo_user" , };static const struct samsung_pll_clock apollo_pll_clks[] __initconst = {"fout_apollo_pll" , "oscclk" ,static const struct samsung_mux_clock apollo_mux_clks[] __initconst = {/* MUX_SEL_APOLLO0 */ "mout_apollo_pll" , mout_apollo_pll_p,/* MUX_SEL_APOLLO1 */ "mout_bus_pll_apollo_user" ,/* MUX_SEL_APOLLO2 */ "mout_apollo" , mout_apollo_p, MUX_SEL_APOLLO2,static const struct samsung_div_clock apollo_div_clks[] __initconst = {/* DIV_APOLLO0 */ "div_cntclk_apollo" , "div_apollo2" ,"div_pclk_dbg_apollo" , "div_apollo2" ,"div_atclk_apollo" , "div_apollo2" ,"div_pclk_apollo" , "div_apollo2" ,"div_aclk_apollo" , "div_apollo2" ,"div_apollo2" , "div_apollo1" ,"div_apollo1" , "mout_apollo" ,/* DIV_APOLLO1 */ "div_sclk_hpm_apollo" , "mout_apollo" ,"div_apollo_pll" , "mout_apollo" ,static const struct samsung_gate_clock apollo_gate_clks[] __initconst = {/* ENABLE_ACLK_APOLLO */ "aclk_asatbslv_apollo_3_cssys" ,"div_atclk_apollo" , ENABLE_ACLK_APOLLO,"aclk_asatbslv_apollo_2_cssys" ,"div_atclk_apollo" , ENABLE_ACLK_APOLLO,"aclk_asatbslv_apollo_1_cssys" ,"div_atclk_apollo" , ENABLE_ACLK_APOLLO,"aclk_asatbslv_apollo_0_cssys" ,"div_atclk_apollo" , ENABLE_ACLK_APOLLO,"aclk_asyncaces_apollo_cci" ,"div_aclk_apollo" , ENABLE_ACLK_APOLLO,"aclk_ahb2apb_apollop" ,"div_pclk_apollo" , ENABLE_ACLK_APOLLO,"aclk_apollonp_200" ,"div_pclk_apollo" , ENABLE_ACLK_APOLLO,/* ENABLE_PCLK_APOLLO */ "pclk_asapbmst_cssys_apollo" ,"div_pclk_dbg_apollo" , ENABLE_PCLK_APOLLO,"pclk_pmu_apollo" , "div_pclk_apollo" ,"pclk_sysreg_apollo" ,"div_pclk_apollo" , ENABLE_PCLK_APOLLO,/* ENABLE_SCLK_APOLLO */ "cntclk_apollo" , "div_cntclk_apollo" ,"sclk_hpm_apollo" , "div_sclk_hpm_apollo" ,#define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \#define E5433_APOLLO_DIV1(hpm, copy) \static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = {static const struct samsung_cpu_clock apollo_cpu_clks[] __initconst = {"apolloclk" , CLK_MOUT_APOLLO_PLL,static const struct samsung_cmu_info apollo_cmu_info __initconst = {static void __init exynos5433_cmu_apollo_init(struct device_node *np)"samsung,exynos5433-cmu-apollo" ,/* * Register offset definitions for CMU_ATLAS #define ATLAS_PLL_LOCK 0x0000#define ATLAS_PLL_CON0 0x0100#define ATLAS_PLL_CON1 0x0104#define ATLAS_PLL_FREQ_DET 0x010c#define MUX_SEL_ATLAS0 0x0200#define MUX_SEL_ATLAS1 0x0204#define MUX_SEL_ATLAS2 0x0208#define MUX_ENABLE_ATLAS0 0x0300#define MUX_ENABLE_ATLAS1 0x0304#define MUX_ENABLE_ATLAS2 0x0308#define MUX_STAT_ATLAS0 0x0400#define MUX_STAT_ATLAS1 0x0404#define MUX_STAT_ATLAS2 0x0408#define DIV_ATLAS0 0x0600#define DIV_ATLAS1 0x0604#define DIV_ATLAS_PLL_FREQ_DET 0x0608#define DIV_STAT_ATLAS0 0x0700#define DIV_STAT_ATLAS1 0x0704#define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708#define ENABLE_ACLK_ATLAS 0x0800#define ENABLE_PCLK_ATLAS 0x0900#define ENABLE_SCLK_ATLAS 0x0a00#define ENABLE_IP_ATLAS0 0x0b00#define ENABLE_IP_ATLAS1 0x0b04#define CLKOUT_CMU_ATLAS 0x0c00#define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04#define ARMCLK_STOPCTRL 0x1000#define ATLAS_PWR_CTRL 0x1020#define ATLAS_PWR_CTRL2 0x1024#define ATLAS_INTR_SPREAD_ENABLE 0x1080#define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084#define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088static const unsigned long atlas_clk_regs[] __initconst = {/* list of all parent clock list */ "oscclk" , "fout_atlas_pll" , };"oscclk" , "sclk_bus_pll_atlas" , };"mout_atlas_pll" ,"mout_bus_pll_atlas_user" , };static const struct samsung_pll_clock atlas_pll_clks[] __initconst = {"fout_atlas_pll" , "oscclk" ,static const struct samsung_mux_clock atlas_mux_clks[] __initconst = {/* MUX_SEL_ATLAS0 */ "mout_atlas_pll" , mout_atlas_pll_p,/* MUX_SEL_ATLAS1 */ "mout_bus_pll_atlas_user" ,/* MUX_SEL_ATLAS2 */ "mout_atlas" , mout_atlas_p, MUX_SEL_ATLAS2,static const struct samsung_div_clock atlas_div_clks[] __initconst = {/* DIV_ATLAS0 */ "div_cntclk_atlas" , "div_atlas2" ,"div_pclk_dbg_atlas" , "div_atclk_atlas" ,"div_atclk_atlas" , "div_atlas2" ,"div_pclk_atlas" , "div_atlas2" ,"div_aclk_atlas" , "div_atlas2" ,"div_atlas2" , "div_atlas1" ,"div_atlas1" , "mout_atlas" ,/* DIV_ATLAS1 */ "div_sclk_hpm_atlas" , "mout_atlas" ,"div_atlas_pll" , "mout_atlas" ,static const struct samsung_gate_clock atlas_gate_clks[] __initconst = {/* ENABLE_ACLK_ATLAS */ "aclk_atb_aud_cssys" ,"div_atclk_atlas" , ENABLE_ACLK_ATLAS,"aclk_atb_apollo3_cssys" ,"div_atclk_atlas" , ENABLE_ACLK_ATLAS,"aclk_atb_apollo2_cssys" ,"div_atclk_atlas" , ENABLE_ACLK_ATLAS,"aclk_atb_apollo1_cssys" ,"div_atclk_atlas" , ENABLE_ACLK_ATLAS,"aclk_atb_apollo0_cssys" ,"div_atclk_atlas" , ENABLE_ACLK_ATLAS,"aclk_asyncahbs_cssys_sss" ,"div_atclk_atlas" , ENABLE_ACLK_ATLAS,"aclk_asyncaxis_cssys_ccix" ,"div_pclk_dbg_atlas" , ENABLE_ACLK_ATLAS,"aclk_asyncaces_atlas_cci" ,"div_aclk_atlas" , ENABLE_ACLK_ATLAS,"aclk_ahb2apb_atlasp" , "div_pclk_atlas" ,"aclk_atlasnp_200" , "div_pclk_atlas" ,/* ENABLE_PCLK_ATLAS */ "pclk_asyncapb_aud_cssys" ,"div_pclk_dbg_atlas" , ENABLE_PCLK_ATLAS,"pclk_asyncapb_isp_cssys" ,"div_pclk_dbg_atlas" , ENABLE_PCLK_ATLAS,"pclk_asyncapb_apollo_cssys" ,"div_pclk_dbg_atlas" , ENABLE_PCLK_ATLAS,"pclk_pmu_atlas" , "div_pclk_atlas" ,"pclk_sysreg_atlas" , "div_pclk_atlas" ,"pclk_secjtag" , "div_pclk_dbg_atlas" ,/* ENABLE_SCLK_ATLAS */ "cntclk_atlas" , "div_cntclk_atlas" ,"sclk_hpm_atlas" , "div_sclk_hpm_atlas" ,"traceclk" , "div_atclk_atlas" ,"ctmclk" , "div_atclk_atlas" ,"hclk_cssys" , "div_atclk_atlas" ,"pclk_dbg_cssys" , "div_pclk_dbg_atlas" ,"pclk_dbg" , "div_pclk_dbg_atlas" ,"atclk" , "div_atclk_atlas" ,#define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \#define E5433_ATLAS_DIV1(hpm, copy) \static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = {static const struct samsung_cpu_clock atlas_cpu_clks[] __initconst = {"atlasclk" , CLK_MOUT_ATLAS_PLL,static const struct samsung_cmu_info atlas_cmu_info __initconst = {static void __init exynos5433_cmu_atlas_init(struct device_node *np)"samsung,exynos5433-cmu-atlas" ,/* * Register offset definitions for CMU_MSCL #define MUX_SEL_MSCL0 0x0200#define MUX_SEL_MSCL1 0x0204#define MUX_ENABLE_MSCL0 0x0300#define MUX_ENABLE_MSCL1 0x0304#define MUX_STAT_MSCL0 0x0400#define MUX_STAT_MSCL1 0x0404#define DIV_MSCL 0x0600#define DIV_STAT_MSCL 0x0700#define ENABLE_ACLK_MSCL 0x0800#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808#define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c#define ENABLE_PCLK_MSCL 0x0900#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908#define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c#define ENABLE_SCLK_MSCL 0x0a00#define ENABLE_IP_MSCL0 0x0b00#define ENABLE_IP_MSCL1 0x0b04#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c#define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10static const unsigned long mscl_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump mscl_suspend_regs[] = {/* list of all parent clock list */ "oscclk" , "sclk_jpeg_mscl" , };"oscclk" , "aclk_mscl_400" , };"mout_sclk_jpeg_user" ,"mout_aclk_mscl_400_user" , };static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {/* MUX_SEL_MSCL0 */ "mout_sclk_jpeg_user" ,"mout_aclk_mscl_400_user" ,/* MUX_SEL_MSCL1 */ "mout_sclk_jpeg" , mout_sclk_jpeg_p,static const struct samsung_div_clock mscl_div_clks[] __initconst = {/* DIV_MSCL */ "div_pclk_mscl" , "mout_aclk_mscl_400_user" ,static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {/* ENABLE_ACLK_MSCL */ "aclk_bts_jpeg" , "mout_aclk_mscl_400_user" ,"aclk_bts_m2mscaler1" ,"mout_aclk_mscl_400_user" , ENABLE_ACLK_MSCL, 8, 0, 0),"aclk_bts_m2mscaler0" ,"mout_aclk_mscl_400_user" , ENABLE_ACLK_MSCL, 7, 0, 0),"aclk_abh2apb_mscl0p" , "div_pclk_mscl" ,"aclk_xiu_msclx" , "mout_aclk_mscl_400_user" ,"aclk_msclnp_100" , "div_pclk_mscl" ,"aclk_msclnd_400" , "mout_aclk_mscl_400_user" ,"aclk_jpeg" , "mout_aclk_mscl_400_user" ,"aclk_m2mscaler1" , "mout_aclk_mscl_400_user" ,"aclk_m2mscaler0" , "mout_aclk_mscl_400_user" ,/* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */ "aclk_smmu_m2mscaler0" ,"mout_aclk_mscl_400_user" ,/* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */ "aclk_smmu_m2mscaler1" ,"mout_aclk_mscl_400_user" ,/* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */ "aclk_smmu_jpeg" , "mout_aclk_mscl_400_user" ,/* ENABLE_PCLK_MSCL */ "pclk_bts_jpeg" , "div_pclk_mscl" ,"pclk_bts_m2mscaler1" , "div_pclk_mscl" ,"pclk_bts_m2mscaler0" , "div_pclk_mscl" ,"pclk_pmu_mscl" , "div_pclk_mscl" ,"pclk_sysreg_mscl" , "div_pclk_mscl" ,"pclk_jpeg" , "div_pclk_mscl" ,"pclk_m2mscaler1" , "div_pclk_mscl" ,"pclk_m2mscaler0" , "div_pclk_mscl" ,/* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */ "pclk_smmu_m2mscaler0" , "div_pclk_mscl" ,/* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */ "pclk_smmu_m2mscaler1" , "div_pclk_mscl" ,/* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */ "pclk_smmu_jpeg" , "div_pclk_mscl" ,/* ENABLE_SCLK_MSCL */ "sclk_jpeg" , "mout_sclk_jpeg" , ENABLE_SCLK_MSCL, 0,static const struct samsung_cmu_info mscl_cmu_info __initconst = {"aclk_mscl_400" ,/* * Register offset definitions for CMU_MFC #define MUX_SEL_MFC 0x0200#define MUX_ENABLE_MFC 0x0300#define MUX_STAT_MFC 0x0400#define DIV_MFC 0x0600#define DIV_STAT_MFC 0x0700#define ENABLE_ACLK_MFC 0x0800#define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804#define ENABLE_PCLK_MFC 0x0900#define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904#define ENABLE_IP_MFC0 0x0b00#define ENABLE_IP_MFC1 0x0b04#define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08static const unsigned long mfc_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump mfc_suspend_regs[] = {"oscclk" , "aclk_mfc_400" , };static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {/* MUX_SEL_MFC */ "mout_aclk_mfc_400_user" ,static const struct samsung_div_clock mfc_div_clks[] __initconst = {/* DIV_MFC */ "div_pclk_mfc" , "mout_aclk_mfc_400_user" ,static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {/* ENABLE_ACLK_MFC */ "aclk_bts_mfc_1" , "mout_aclk_mfc_400_user" ,"aclk_bts_mfc_0" , "mout_aclk_mfc_400_user" ,"aclk_ahb2apb_mfcp" , "div_pclk_mfc" ,"aclk_xiu_mfcx" , "mout_aclk_mfc_400_user" ,"aclk_mfcnp_100" , "div_pclk_mfc" ,"aclk_mfcnd_400" , "mout_aclk_mfc_400_user" ,"aclk_mfc" , "mout_aclk_mfc_400_user" ,/* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */ "aclk_smmu_mfc_1" , "mout_aclk_mfc_400_user" ,"aclk_smmu_mfc_0" , "mout_aclk_mfc_400_user" ,/* ENABLE_PCLK_MFC */ "pclk_bts_mfc_1" , "div_pclk_mfc" ,"pclk_bts_mfc_0" , "div_pclk_mfc" ,"pclk_pmu_mfc" , "div_pclk_mfc" ,"pclk_sysreg_mfc" , "div_pclk_mfc" ,"pclk_mfc" , "div_pclk_mfc" ,/* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */ "pclk_smmu_mfc_1" , "div_pclk_mfc" ,"pclk_smmu_mfc_0" , "div_pclk_mfc" ,static const struct samsung_cmu_info mfc_cmu_info __initconst = {"aclk_mfc_400" ,/* * Register offset definitions for CMU_HEVC #define MUX_SEL_HEVC 0x0200#define MUX_ENABLE_HEVC 0x0300#define MUX_STAT_HEVC 0x0400#define DIV_HEVC 0x0600#define DIV_STAT_HEVC 0x0700#define ENABLE_ACLK_HEVC 0x0800#define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804#define ENABLE_PCLK_HEVC 0x0900#define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904#define ENABLE_IP_HEVC0 0x0b00#define ENABLE_IP_HEVC1 0x0b04#define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08static const unsigned long hevc_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump hevc_suspend_regs[] = {"oscclk" , "aclk_hevc_400" , };static const struct samsung_mux_clock hevc_mux_clks[] __initconst = {/* MUX_SEL_HEVC */ "mout_aclk_hevc_400_user" ,static const struct samsung_div_clock hevc_div_clks[] __initconst = {/* DIV_HEVC */ "div_pclk_hevc" , "mout_aclk_hevc_400_user" ,static const struct samsung_gate_clock hevc_gate_clks[] __initconst = {/* ENABLE_ACLK_HEVC */ "aclk_bts_hevc_1" , "mout_aclk_hevc_400_user" ,"aclk_bts_hevc_0" , "mout_aclk_hevc_400_user" ,"aclk_ahb2apb_hevcp" , "div_pclk_hevc" ,"aclk_xiu_hevcx" , "mout_aclk_hevc_400_user" ,"aclk_hevcnp_100" , "div_pclk_hevc" ,"aclk_hevcnd_400" , "mout_aclk_hevc_400_user" ,"aclk_hevc" , "mout_aclk_hevc_400_user" ,/* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */ "aclk_smmu_hevc_1" ,"mout_aclk_hevc_400_user" ,"aclk_smmu_hevc_0" ,"mout_aclk_hevc_400_user" ,/* ENABLE_PCLK_HEVC */ "pclk_bts_hevc_1" , "div_pclk_hevc" ,"pclk_bts_hevc_0" , "div_pclk_hevc" ,"pclk_pmu_hevc" , "div_pclk_hevc" ,"pclk_sysreg_hevc" , "div_pclk_hevc" ,"pclk_hevc" , "div_pclk_hevc" ,/* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */ "pclk_smmu_hevc_1" , "div_pclk_hevc" ,"pclk_smmu_hevc_0" , "div_pclk_hevc" ,static const struct samsung_cmu_info hevc_cmu_info __initconst = {"aclk_hevc_400" ,/* * Register offset definitions for CMU_ISP #define MUX_SEL_ISP 0x0200#define MUX_ENABLE_ISP 0x0300#define MUX_STAT_ISP 0x0400#define DIV_ISP 0x0600#define DIV_STAT_ISP 0x0700#define ENABLE_ACLK_ISP0 0x0800#define ENABLE_ACLK_ISP1 0x0804#define ENABLE_ACLK_ISP2 0x0808#define ENABLE_PCLK_ISP 0x0900#define ENABLE_SCLK_ISP 0x0a00#define ENABLE_IP_ISP0 0x0b00#define ENABLE_IP_ISP1 0x0b04#define ENABLE_IP_ISP2 0x0b08#define ENABLE_IP_ISP3 0x0b0cstatic const unsigned long isp_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump isp_suspend_regs[] = {"oscclk" , "aclk_isp_dis_400" , };"oscclk" , "aclk_isp_400" , };static const struct samsung_mux_clock isp_mux_clks[] __initconst = {/* MUX_SEL_ISP */ "mout_aclk_isp_dis_400_user" ,"mout_aclk_isp_400_user" ,static const struct samsung_div_clock isp_div_clks[] __initconst = {/* DIV_ISP */ "div_pclk_isp_dis" ,"mout_aclk_isp_dis_400_user" , DIV_ISP, 12, 3),"div_pclk_isp" , "mout_aclk_isp_400_user" ,"div_aclk_isp_d_200" ,"mout_aclk_isp_400_user" , DIV_ISP, 4, 3),"div_aclk_isp_c_200" ,"mout_aclk_isp_400_user" , DIV_ISP, 0, 3),static const struct samsung_gate_clock isp_gate_clks[] __initconst = {/* ENABLE_ACLK_ISP0 */ "aclk_isp_d_glue" , "mout_aclk_isp_400_user" ,"aclk_scalerp" , "mout_aclk_isp_400_user" ,"aclk_3dnr" , "mout_aclk_isp_400_user" ,"aclk_dis" , "mout_aclk_isp_dis_400_user" ,"aclk_scalerc" , "mout_aclk_isp_400_user" ,"aclk_drc" , "mout_aclk_isp_400_user" ,"aclk_isp" , "mout_aclk_isp_400_user" ,/* ENABLE_ACLK_ISP1 */ "aclk_axius_scalerp" ,"mout_aclk_isp_400_user" , ENABLE_ACLK_ISP1,"aclk_axius_scalerc" ,"mout_aclk_isp_400_user" , ENABLE_ACLK_ISP1,"aclk_axius_drc" ,"mout_aclk_isp_400_user" , ENABLE_ACLK_ISP1,"aclk_asyncahbm_isp2p" ,"div_pclk_isp" , ENABLE_ACLK_ISP1,"aclk_asyncahbm_isp1p" ,"div_pclk_isp" , ENABLE_ACLK_ISP1,"aclk_asyncaxis_dis1" ,"mout_aclk_isp_dis_400_user" , ENABLE_ACLK_ISP1,"aclk_asyncaxis_dis0" ,"mout_aclk_isp_dis_400_user" , ENABLE_ACLK_ISP1,"aclk_asyncaxim_dis1" ,"mout_aclk_isp_400_user" , ENABLE_ACLK_ISP1,"aclk_asyncaxim_dis0" ,"mout_aclk_isp_400_user" , ENABLE_ACLK_ISP1,"aclk_asyncaxim_isp2p" ,"div_aclk_isp_d_200" , ENABLE_ACLK_ISP1,"aclk_asyncaxim_isp1p" ,"div_aclk_isp_c_200" , ENABLE_ACLK_ISP1,"aclk_ahb2apb_isp2p" , "div_pclk_isp" ,"aclk_ahb2apb_isp1p" , "div_pclk_isp" ,"aclk_axi2apb_isp2p" ,"div_aclk_isp_d_200" , ENABLE_ACLK_ISP1,"aclk_axi2apb_isp1p" ,"div_aclk_isp_c_200" , ENABLE_ACLK_ISP1,"aclk_xiu_ispex1" , "mout_aclk_isp_400_user" ,"aclk_xiu_ispex0" , "mout_aclk_isp_400_user" ,"aclk_ispnd_400" , "mout_aclk_isp_400_user" ,/* ENABLE_ACLK_ISP2 */ "aclk_smmu_scalerp" ,"mout_aclk_isp_400_user" , ENABLE_ACLK_ISP2,"aclk_smmu_3dnr" , "mout_aclk_isp_400_user" ,"aclk_smmu_dis1" , "mout_aclk_isp_400_user" ,"aclk_smmu_dis0" , "mout_aclk_isp_400_user" ,"aclk_smmu_scalerc" ,"mout_aclk_isp_400_user" , ENABLE_ACLK_ISP2,"aclk_smmu_drc" , "mout_aclk_isp_400_user" ,"aclk_smmu_isp" , "mout_aclk_isp_400_user" ,"aclk_bts_scalerp" ,"mout_aclk_isp_400_user" , ENABLE_ACLK_ISP2,"aclk_bts_3dnr" , "mout_aclk_isp_400_user" ,"aclk_bts_dis1" , "mout_aclk_isp_400_user" ,"aclk_bts_dis0" , "mout_aclk_isp_400_user" ,"aclk_bts_scalerc" ,"mout_aclk_isp_400_user" , ENABLE_ACLK_ISP2,"aclk_bts_drc" , "mout_aclk_isp_400_user" ,"aclk_bts_isp" , "mout_aclk_isp_400_user" ,/* ENABLE_PCLK_ISP */ "pclk_smmu_scalerp" , "div_aclk_isp_d_200" ,"pclk_smmu_3dnr" , "div_aclk_isp_d_200" ,"pclk_smmu_dis1" , "div_aclk_isp_d_200" ,"pclk_smmu_dis0" , "div_aclk_isp_d_200" ,"pclk_smmu_scalerc" , "div_aclk_isp_c_200" ,"pclk_smmu_drc" , "div_aclk_isp_c_200" ,"pclk_smmu_isp" , "div_aclk_isp_c_200" ,"pclk_bts_scalerp" , "div_pclk_isp" ,"pclk_bts_3dnr" , "div_pclk_isp" ,"pclk_bts_dis1" , "div_pclk_isp" ,"pclk_bts_dis0" , "div_pclk_isp" ,"pclk_bts_scalerc" , "div_pclk_isp" ,"pclk_bts_drc" , "div_pclk_isp" ,"pclk_bts_isp" , "div_pclk_isp" ,"pclk_asyncaxi_dis1" , "div_pclk_isp" ,"pclk_asyncaxi_dis0" , "div_pclk_isp" ,"pclk_pmu_isp" , "div_pclk_isp" ,"pclk_sysreg_isp" , "div_pclk_isp" ,"pclk_cmu_isp_local" ,"div_aclk_isp_c_200" , ENABLE_PCLK_ISP,"pclk_scalerp" , "div_aclk_isp_d_200" ,"pclk_3dnr" , "div_aclk_isp_d_200" ,"pclk_dis_core" , "div_pclk_isp_dis" ,"pclk_dis" , "div_aclk_isp_d_200" ,"pclk_scalerc" , "div_aclk_isp_c_200" ,"pclk_drc" , "div_aclk_isp_c_200" ,"pclk_isp" , "div_aclk_isp_c_200" ,/* ENABLE_SCLK_ISP */ "sclk_pixelasyncs_dis" ,"mout_aclk_isp_dis_400_user" , ENABLE_SCLK_ISP,"sclk_pixelasyncm_dis" ,"mout_aclk_isp_dis_400_user" , ENABLE_SCLK_ISP,"sclk_pixelasyncs_scalerp" ,"mout_aclk_isp_400_user" , ENABLE_SCLK_ISP,"sclk_pixelasyncm_ispd" ,"mout_aclk_isp_400_user" , ENABLE_SCLK_ISP,"sclk_pixelasyncs_ispc" ,"mout_aclk_isp_400_user" , ENABLE_SCLK_ISP,"sclk_pixelasyncm_ispc" ,"mout_aclk_isp_400_user" , ENABLE_SCLK_ISP,static const struct samsung_cmu_info isp_cmu_info __initconst = {"aclk_isp_400" ,/* * Register offset definitions for CMU_CAM0 #define MUX_SEL_CAM00 0x0200#define MUX_SEL_CAM01 0x0204#define MUX_SEL_CAM02 0x0208#define MUX_SEL_CAM03 0x020c#define MUX_SEL_CAM04 0x0210#define MUX_ENABLE_CAM00 0x0300#define MUX_ENABLE_CAM01 0x0304#define MUX_ENABLE_CAM02 0x0308#define MUX_ENABLE_CAM03 0x030c#define MUX_ENABLE_CAM04 0x0310#define MUX_STAT_CAM00 0x0400#define MUX_STAT_CAM01 0x0404#define MUX_STAT_CAM02 0x0408#define MUX_STAT_CAM03 0x040c#define MUX_STAT_CAM04 0x0410#define MUX_IGNORE_CAM01 0x0504#define DIV_CAM00 0x0600#define DIV_CAM01 0x0604#define DIV_CAM02 0x0608#define DIV_CAM03 0x060c#define DIV_STAT_CAM00 0x0700#define DIV_STAT_CAM01 0x0704#define DIV_STAT_CAM02 0x0708#define DIV_STAT_CAM03 0x070c#define ENABLE_ACLK_CAM00 0X0800#define ENABLE_ACLK_CAM01 0X0804#define ENABLE_ACLK_CAM02 0X0808#define ENABLE_PCLK_CAM0 0X0900#define ENABLE_SCLK_CAM0 0X0a00#define ENABLE_IP_CAM00 0X0b00#define ENABLE_IP_CAM01 0X0b04#define ENABLE_IP_CAM02 0X0b08#define ENABLE_IP_CAM03 0X0b0Cstatic const unsigned long cam0_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump cam0_suspend_regs[] = {"oscclk" , "aclk_cam0_333" , };"oscclk" , "aclk_cam0_400" , };"oscclk" , "aclk_cam0_552" , };"oscclk" ,"phyclk_rxbyteclkhs0_s4_phy" , };"oscclk" ,"phyclk_rxbyteclkhs0_s2a_phy" , };"mout_aclk_lite_d_a" ,"mout_aclk_cam0_333_user" , };"mout_aclk_cam0_552_user" ,"mout_aclk_cam0_400_user" , };"mout_aclk_lite_b_a" ,"mout_aclk_cam0_333_user" , };"mout_aclk_cam0_552_user" ,"mout_aclk_cam0_400_user" , };"mout_aclk_lite_a_a" ,"mout_aclk_cam0_333_user" , };"mout_aclk_cam0_552_user" ,"mout_aclk_cam0_400_user" , };"mout_aclk_cam0_400_user" ,"mout_aclk_cam0_333_user" , };"mout_aclk_csis1_a" ,"mout_aclk_cam0_333_user" };"mout_aclk_cam0_552_user" ,"mout_aclk_cam0_400_user" , };"mout_aclk_csis0_a" ,"mout_aclk_cam0_333_user" , };"mout_aclk_cam0_552_user" ,"mout_aclk-cam0_400_user" , };"mout_aclk_3aa1_a" ,"mout_aclk_cam0_333_user" , };"mout_aclk_cam0_552_user" ,"mout_aclk_cam0_400_user" , };"mout_aclk_3aa0_a" ,"mout_aclk_cam0_333_user" , };"mout_aclk_cam0_552_user" ,"mout_aclk_cam0_400_user" , };"mout_sclk_lite_freecnt_b" ,"div_pclk_lite_d" , };"mout_sclk_lite_freecnt_a" ,"div_pclk_pixelasync_lite_c" , };"div_pclk_lite_a" ,"div_pclk_lite_b" , };"mout_sclk_pixelasync_lite_c_a" ,"mout_aclk_cam0_333_user" , };"mout_aclk_cam0_552_user" ,"mout_aclk_cam0_400_user" , };"mout_sclk_pixelasync_lite_c_init_a" ,"mout_aclk_cam0_400_user" , };"mout_aclk_cam0_552_user" ,"mout_aclk_cam0_400_user" , };static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = {"phyclk_rxbyteclkhs0_s4_phy" ,"phyclk_rxbyteclkhs0_s2a_phy" ,static const struct samsung_mux_clock cam0_mux_clks[] __initconst = {/* MUX_SEL_CAM00 */ "mout_aclk_cam0_333_user" ,"mout_aclk_cam0_400_user" ,"mout_aclk_cam0_552_user" ,/* MUX_SEL_CAM01 */ "mout_phyclk_rxbyteclkhs0_s4_user" ,"mout_phyclk_rxbyteclkhs0_s2a_user" ,/* MUX_SEL_CAM02 */ "mout_aclk_lite_d_b" , mout_aclk_lite_d_b_p,"mout_aclk_lite_d_a" , mout_aclk_lite_d_a_p,"mout_aclk_lite_b_b" , mout_aclk_lite_b_b_p,"mout_aclk_lite_b_a" , mout_aclk_lite_b_a_p,"mout_aclk_lite_a_b" , mout_aclk_lite_a_b_p,"mout_aclk_lite_a_a" , mout_aclk_lite_a_a_p,"mout_aclk_cam0_400" , mout_aclk_cam0_400_p,/* MUX_SEL_CAM03 */ "mout_aclk_csis1_b" , mout_aclk_csis1_b_p,"mout_aclk_csis1_a" , mout_aclk_csis1_a_p,"mout_aclk_csis0_b" , mout_aclk_csis0_b_p,"mout_aclk_csis0_a" , mout_aclk_csis0_a_p,"mout_aclk_3aa1_b" , mout_aclk_3aa1_b_p,"mout_aclk_3aa1_a" , mout_aclk_3aa1_a_p,"mout_aclk_3aa0_b" , mout_aclk_3aa0_b_p,"mout_aclk_3aa0_a" , mout_aclk_3aa0_a_p,/* MUX_SEL_CAM04 */ "mout_sclk_lite_freecnt_c" ,"mout_sclk_lite_freecnt_b" ,"mout_sclk_lite_freecnt_a" ,"mout_sclk_pixelasync_lite_c_b" ,"mout_sclk_pixelasync_lite_c_a" ,"mout_sclk_pixelasync_lite_c_init_b" ,"mout_sclk_pixelasync_lite_c_init_a" ,static const struct samsung_div_clock cam0_div_clks[] __initconst = {/* DIV_CAM00 */ "div_pclk_cam0_50" , "div_aclk_cam0_200" ,"div_aclk_cam0_200" , "mout_aclk_cam0_400" ,"div_aclk_cam0_bus_400" ,"mout_aclk_cam0_400" , DIV_CAM00, 0, 3),/* DIV_CAM01 */ "div_pclk_lite_d" , "div_aclk_lite_d" ,"div_aclk_lite_d" , "mout_aclk_lite_d_b" ,"div_pclk_lite_b" , "div_aclk_lite_b" ,"div_aclk_lite_b" , "mout_aclk_lite_b_b" ,"div_pclk_lite_a" , "div_aclk_lite_a" ,"div_aclk_lite_a" , "mout_aclk_lite_a_b" ,/* DIV_CAM02 */ "div_aclk_csis1" , "mout_aclk_csis1_b" ,"div_aclk_csis0" , "mout_aclk_csis0_b" ,"div_pclk_3aa1" , "div_aclk_3aa1" ,"div_aclk_3aa1" , "mout_aclk_3aa1_b" ,"div_pclk_3aa0" , "div_aclk_3aa0" ,"div_aclk_3aa0" , "mout_aclk_3aa0_b" ,/* DIV_CAM03 */ "div_sclk_pixelasync_lite_c" ,"mout_sclk_pixelasync_lite_c_b" , DIV_CAM03, 8, 3),"div_pclk_pixelasync_lite_c" ,"div_sclk_pixelasync_lite_c_init" , DIV_CAM03, 4, 2),"div_sclk_pixelasync_lite_c_init" ,"mout_sclk_pixelasync_lite_c_init_b" , DIV_CAM03, 0, 3),static const struct samsung_gate_clock cam0_gate_clks[] __initconst = {/* ENABLE_ACLK_CAM00 */ "aclk_csis1" , "div_aclk_csis1" , ENABLE_ACLK_CAM00,"aclk_csis0" , "div_aclk_csis0" , ENABLE_ACLK_CAM00,"aclk_3aa1" , "div_aclk_3aa1" , ENABLE_ACLK_CAM00,"aclk_3aa0" , "div_aclk_3aa0" , ENABLE_ACLK_CAM00,"aclk_lite_d" , "div_aclk_lite_d" ,"aclk_lite_b" , "div_aclk_lite_b" ,"aclk_lite_a" , "div_aclk_lite_a" ,/* ENABLE_ACLK_CAM01 */ "aclk_ahbsyncdn" , "div_aclk_cam0_200" ,"aclk_axius_lite_d" , "div_aclk_cam0_bus_400" ,"aclk_axius_lite_b" , "div_aclk_cam0_bus_400" ,"aclk_axius_lite_a" , "div_aclk_cam0_bus_400" ,"aclk_asyncapbm_3aa1" , "div_pclk_3aa1" ,"aclk_asyncapbs_3aa1" , "div_aclk_3aa1" ,"aclk_asyncapbm_3aa0" , "div_pclk_3aa0" ,"aclk_asyncapbs_3aa0" , "div_aclk_3aa0" ,"aclk_asyncapbm_lite_d" ,"div_pclk_lite_d" , ENABLE_ACLK_CAM01,"aclk_asyncapbs_lite_d" ,"div_aclk_cam0_200" , ENABLE_ACLK_CAM01,"aclk_asyncapbm_lite_b" ,"div_pclk_lite_b" , ENABLE_ACLK_CAM01,"aclk_asyncapbs_lite_b" ,"div_aclk_cam0_200" , ENABLE_ACLK_CAM01,"aclk_asyncapbm_lite_a" ,"div_pclk_lite_a" , ENABLE_ACLK_CAM01,"aclk_asyncapbs_lite_a" ,"div_aclk_cam0_200" , ENABLE_ACLK_CAM01,"aclk_asyncaxim_isp0p" ,"div_aclk_cam0_200" , ENABLE_ACLK_CAM01,"aclk_asyncaxim_3aa1" ,"div_aclk_cam0_bus_400" , ENABLE_ACLK_CAM01,"aclk_asyncaxis_3aa1" ,"div_aclk_3aa1" , ENABLE_ACLK_CAM01,"aclk_asyncaxim_3aa0" ,"div_aclk_cam0_bus_400" , ENABLE_ACLK_CAM01,"aclk_asyncaxis_3aa0" ,"div_aclk_3aa0" , ENABLE_ACLK_CAM01,"aclk_asyncaxim_lite_d" ,"div_aclk_cam0_bus_400" , ENABLE_ACLK_CAM01,"aclk_asyncaxis_lite_d" ,"div_aclk_lite_d" , ENABLE_ACLK_CAM01,"aclk_asyncaxim_lite_b" ,"div_aclk_cam0_bus_400" , ENABLE_ACLK_CAM01,"aclk_asyncaxis_lite_b" ,"div_aclk_lite_b" , ENABLE_ACLK_CAM01,"aclk_asyncaxim_lite_a" ,"div_aclk_cam0_bus_400" , ENABLE_ACLK_CAM01,"aclk_asyncaxis_lite_a" ,"div_aclk_lite_a" , ENABLE_ACLK_CAM01,"aclk_ahb2apb_ispsfrp" ,"div_pclk_cam0_50" , ENABLE_ACLK_CAM01,"aclk_axi2apb_isp0p" , "div_aclk_cam0_200" ,"aclk_axi2ahb_isp0p" , "div_aclk_cam0_200" ,"aclk_xiu_is0x" , "div_aclk_cam0_200" ,"aclk_xiu_isp0ex" , "div_aclk_cam0_bus_400" ,"aclk_cam0np_276" , "div_aclk_cam0_200" ,"aclk_cam0nd_400" , "div_aclk_cam0_bus_400" ,/* ENABLE_ACLK_CAM02 */ "aclk_smmu_3aa1" , "div_aclk_cam0_bus_400" ,"aclk_smmu_3aa0" , "div_aclk_cam0_bus_400" ,"aclk_smmu_lite_d" , "div_aclk_cam0_bus_400" ,"aclk_smmu_lite_b" , "div_aclk_cam0_bus_400" ,"aclk_smmu_lite_a" , "div_aclk_cam0_bus_400" ,"aclk_bts_3aa1" , "div_aclk_cam0_bus_400" ,"aclk_bts_3aa0" , "div_aclk_cam0_bus_400" ,"aclk_bts_lite_d" , "div_aclk_cam0_bus_400" ,"aclk_bts_lite_b" , "div_aclk_cam0_bus_400" ,"aclk_bts_lite_a" , "div_aclk_cam0_bus_400" ,/* ENABLE_PCLK_CAM0 */ "pclk_smmu_3aa1" , "div_aclk_cam0_200" ,"pclk_smmu_3aa0" , "div_aclk_cam0_200" ,"pclk_smmu_lite_d" , "div_aclk_cam0_200" ,"pclk_smmu_lite_b" , "div_aclk_cam0_200" ,"pclk_smmu_lite_a" , "div_aclk_cam0_200" ,"pclk_bts_3aa1" , "div_pclk_cam0_50" ,"pclk_bts_3aa0" , "div_pclk_cam0_50" ,"pclk_bts_lite_d" , "div_pclk_cam0_50" ,"pclk_bts_lite_b" , "div_pclk_cam0_50" ,"pclk_bts_lite_a" , "div_pclk_cam0_50" ,"pclk_asyncaxi_cam1" , "div_pclk_cam0_50" ,"pclk_asyncaxi_3aa1" , "div_pclk_cam0_50" ,"pclk_asyncaxi_3aa0" , "div_pclk_cam0_50" ,"pclk_asyncaxi_lite_d" ,"div_pclk_cam0_50" , ENABLE_PCLK_CAM0,"pclk_asyncaxi_lite_b" ,"div_pclk_cam0_50" , ENABLE_PCLK_CAM0,"pclk_asyncaxi_lite_a" ,"div_pclk_cam0_50" , ENABLE_PCLK_CAM0,"pclk_pmu_cam0" , "div_pclk_cam0_50" ,"pclk_sysreg_cam0" , "div_pclk_cam0_50" ,"pclk_cmu_cam0_local" ,"div_aclk_cam0_200" , ENABLE_PCLK_CAM0,"pclk_csis1" , "div_aclk_cam0_200" ,"pclk_csis0" , "div_aclk_cam0_200" ,"pclk_3aa1" , "div_pclk_3aa1" ,"pclk_3aa0" , "div_pclk_3aa0" ,"pclk_lite_d" , "div_pclk_lite_d" ,"pclk_lite_b" , "div_pclk_lite_b" ,"pclk_lite_a" , "div_pclk_lite_a" ,/* ENABLE_SCLK_CAM0 */ "phyclk_rxbyteclkhs0_s4" ,"mout_phyclk_rxbyteclkhs0_s4_user" ,"phyclk_rxbyteclkhs0_s2a" ,"mout_phyclk_rxbyteclkhs0_s2a_user" ,"sclk_lite_freecnt" ,"mout_sclk_lite_freecnt_c" , ENABLE_SCLK_CAM0, 6, 0, 0),"sclk_pixelasycm_3aa1" ,"div_aclk_3aa1" , ENABLE_SCLK_CAM0, 5, 0, 0),"sclk_pixelasycm_3aa0" ,"div_aclk_3aa0" , ENABLE_SCLK_CAM0, 4, 0, 0),"sclk_pixelasycs_3aa0" ,"div_aclk_3aa0" , ENABLE_SCLK_CAM0, 3, 0, 0),"sclk_pixelasyncm_lite_c" ,"div_sclk_pixelasync_lite_c" ,"sclk_pixelasyncm_lite_c_init" ,"div_sclk_pixelasync_lite_c_init" ,"sclk_pixelasyncs_lite_c_init" ,"div_sclk_pixelasync_lite_c" ,static const struct samsung_cmu_info cam0_cmu_info __initconst = {"aclk_cam0_400" ,/* * Register offset definitions for CMU_CAM1 #define MUX_SEL_CAM10 0x0200#define MUX_SEL_CAM11 0x0204#define MUX_SEL_CAM12 0x0208#define MUX_ENABLE_CAM10 0x0300#define MUX_ENABLE_CAM11 0x0304#define MUX_ENABLE_CAM12 0x0308#define MUX_STAT_CAM10 0x0400#define MUX_STAT_CAM11 0x0404#define MUX_STAT_CAM12 0x0408#define MUX_IGNORE_CAM11 0x0504#define DIV_CAM10 0x0600#define DIV_CAM11 0x0604#define DIV_STAT_CAM10 0x0700#define DIV_STAT_CAM11 0x0704#define ENABLE_ACLK_CAM10 0X0800#define ENABLE_ACLK_CAM11 0X0804#define ENABLE_ACLK_CAM12 0X0808#define ENABLE_PCLK_CAM1 0X0900#define ENABLE_SCLK_CAM1 0X0a00#define ENABLE_IP_CAM10 0X0b00#define ENABLE_IP_CAM11 0X0b04#define ENABLE_IP_CAM12 0X0b08static const unsigned long cam1_clk_regs[] __initconst = {static const struct samsung_clk_reg_dump cam1_suspend_regs[] = {"oscclk" , "sclk_isp_uart_cam1" , };"oscclk" , "sclk_isp_spi1_cam1" , };"oscclk" , "sclk_isp_spi0_cam1" , };"oscclk" , "aclk_cam1_333" , };"oscclk" , "aclk_cam1_400" , };"oscclk" , "aclk_cam1_552" , };"oscclk" ,"phyclk_rxbyteclkhs0_s2b_phy" , };"mout_aclk_csis2_a" ,"mout_aclk_cam1_333_user" , };"mout_aclk_cam1_552_user" ,"mout_aclk_cam1_400_user" , };"mout_aclk_fd_a" ,"mout_aclk_cam1_333_user" , };"mout_aclk_cam1_552_user" ,"mout_aclk_cam1_400_user" , };"mout_aclk_lite_c_a" ,"mout_aclk_cam1_333_user" , };"mout_aclk_cam1_552_user" ,"mout_aclk_cam1_400_user" , };static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = {"phyclk_rxbyteclkhs0_s2b_phy" , NULL,static const struct samsung_mux_clock cam1_mux_clks[] __initconst = {/* MUX_SEL_CAM10 */ "mout_sclk_isp_uart_user" ,"mout_sclk_isp_spi1_user" ,"mout_sclk_isp_spi0_user" ,"mout_aclk_cam1_333_user" ,"mout_aclk_cam1_400_user" ,"mout_aclk_cam1_552_user" ,/* MUX_SEL_CAM11 */ "mout_phyclk_rxbyteclkhs0_s2b_user" ,/* MUX_SEL_CAM12 */ "mout_aclk_csis2_b" , mout_aclk_csis2_b_p,"mout_aclk_csis2_a" , mout_aclk_csis2_a_p,"mout_aclk_fd_b" , mout_aclk_fd_b_p,"mout_aclk_fd_a" , mout_aclk_fd_a_p,"mout_aclk_lite_c_b" , mout_aclk_lite_c_b_p,"mout_aclk_lite_c_a" , mout_aclk_lite_c_a_p,static const struct samsung_div_clock cam1_div_clks[] __initconst = {/* DIV_CAM10 */ "div_sclk_isp_mpwm" ,"div_pclk_cam1_83" , DIV_CAM10, 16, 2),"div_pclk_cam1_83" ,"mout_aclk_cam1_333_user" , DIV_CAM10, 12, 2),"div_pclk_cam1_166" ,"mout_aclk_cam1_333_user" , DIV_CAM10, 8, 2),"div_pclk_dbg_cam1" ,"mout_aclk_cam1_552_user" , DIV_CAM10, 4, 3),"div_atclk_cam1" , "mout_aclk_cam1_552_user" ,/* DIV_CAM11 */ "div_aclk_csis2" , "mout_aclk_csis2_b" ,"div_pclk_fd" , "div_aclk_fd" , DIV_CAM11, 12, 2),"div_aclk_fd" , "mout_aclk_fd_b" , DIV_CAM11, 8, 3),"div_pclk_lite_c" , "div_aclk_lite_c" ,"div_aclk_lite_c" , "mout_aclk_lite_c_b" ,static const struct samsung_gate_clock cam1_gate_clks[] __initconst = {/* ENABLE_ACLK_CAM10 */ "aclk_isp_gic" , "mout_aclk_cam1_333_user" ,"aclk_fd" , "div_aclk_fd" ,"aclk_lite_c" , "div_aclk_lite_c" ,"aclk_csis2" , "div_aclk_csis2" ,/* ENABLE_ACLK_CAM11 */ "aclk_asyncapbm_fd" , "div_pclk_fd" ,"aclk_asyncapbs_fd" , "div_pclk_cam1_166" ,"aclk_asyncapbm_lite_c" ,"div_pclk_lite_c" , ENABLE_ACLK_CAM11,"aclk_asyncapbs_lite_c" ,"div_pclk_cam1_166" , ENABLE_ACLK_CAM11,"aclk_asyncahbs_sfrisp2h2" ,"div_pclk_cam1_83" , ENABLE_ACLK_CAM11,"aclk_asyncahbs_sfrisp2h1" ,"div_pclk_cam1_83" , ENABLE_ACLK_CAM11,"aclk_asyncaxim_ca5" ,"mout_aclk_cam1_333_user" , ENABLE_ACLK_CAM11,"aclk_asyncaxis_ca5" ,"mout_aclk_cam1_552_user" , ENABLE_ACLK_CAM11,"aclk_asyncaxis_ispx2" ,"mout_aclk_cam1_333_user" , ENABLE_ACLK_CAM11,"aclk_asyncaxis_ispx1" ,"mout_aclk_cam1_333_user" , ENABLE_ACLK_CAM11,"aclk_asyncaxis_ispx0" ,"mout_aclk_cam1_333_user" , ENABLE_ACLK_CAM11,"aclk_asyncaxim_ispex" ,"mout_aclk_cam1_400_user" , ENABLE_ACLK_CAM11,"aclk_asyncaxim_isp3p" ,"mout_aclk_cam1_400_user" , ENABLE_ACLK_CAM11,"aclk_asyncaxis_isp3p" ,"mout_aclk_cam1_333_user" , ENABLE_ACLK_CAM11,"aclk_asyncaxim_fd" ,"mout_aclk_cam1_400_user" , ENABLE_ACLK_CAM11,"aclk_asyncaxis_fd" , "div_aclk_fd" ,"aclk_asyncaxim_lite_c" ,"mout_aclk_cam1_400_user" , ENABLE_ACLK_CAM11,"aclk_asyncaxis_lite_c" ,"div_aclk_lite_c" , ENABLE_ACLK_CAM11,"aclk_ahb2apb_isp5p" , "div_pclk_cam1_83" ,"aclk_ahb2apb_isp3p" , "div_pclk_cam1_83" ,"aclk_axi2apb_isp3p" ,"mout_aclk_cam1_333_user" , ENABLE_ACLK_CAM11,"aclk_ahb_sfrisp2h" , "div_pclk_cam1_83" ,"aclk_axi_isp_hx_r" , "div_pclk_cam1_166" ,"aclk_axi_isp_cx_r" , "div_pclk_cam1_166" ,"aclk_axi_isp_hx" , "mout_aclk_cam1_333_user" ,"aclk_axi_isp_cx" , "mout_aclk_cam1_333_user" ,"aclk_xiu_ispx" , "mout_aclk_cam1_333_user" ,"aclk_xiu_ispex" , "mout_aclk_cam1_400_user" ,"aclk_cam1np_333" , "mout_aclk_cam1_333_user" ,"aclk_cam1nd_400" , "mout_aclk_cam1_400_user" ,/* ENABLE_ACLK_CAM12 */ "aclk_smmu_ispcpu" ,"mout_aclk_cam1_400_user" , ENABLE_ACLK_CAM12,"aclk_smmu_fd" , "mout_aclk_cam1_400_user" ,"aclk_smmu_lite_c" ,"mout_aclk_cam1_400_user" , ENABLE_ACLK_CAM12,"aclk_bts_isp3p" , "mout_aclk_cam1_400_user" ,"aclk_bts_fd" , "mout_aclk_cam1_400_user" ,"aclk_bts_lite_c" , "mout_aclk_cam1_400_user" ,"aclk_ahbdn_sfrisp2h" ,"mout_aclk_cam1_333_user" , ENABLE_ACLK_CAM12,"aclk_aclk-shbdn_isp5p" ,"mout_aclk_cam1_333_user" , ENABLE_ACLK_CAM12,"aclk_axius_isp3p" ,"mout_aclk_cam1_400_user" , ENABLE_ACLK_CAM12,"aclk_axius_fd" , "mout_aclk_cam1_400_user" ,"aclk_axius_lite_c" ,"mout_aclk_cam1_400_user" , ENABLE_ACLK_CAM12,/* ENABLE_PCLK_CAM1 */ "pclk_smmu_ispcpu" , "div_pclk_cam1_166" ,"pclk_smmu_fd" , "div_pclk_cam1_166" ,"pclk_smmu_lite_c" , "div_pclk_cam1_166" ,"pclk_bts_isp3p" , "div_pclk_cam1_83" ,"pclk_bts_fd" , "div_pclk_cam1_83" ,"pclk_bts_lite_c" , "div_pclk_cam1_83" ,"pclk_asyncaxim_ca5" , "div_pclk_cam1_166" ,"pclk_asyncaxim_ispex" ,"div_pclk_cam1_83" , ENABLE_PCLK_CAM1,"pclk_asyncaxim_isp3p" ,"div_pclk_cam1_83" , ENABLE_PCLK_CAM1,"pclk_asyncaxim_fd" , "div_pclk_cam1_83" ,"pclk_asyncaxim_lite_c" ,"div_pclk_cam1_83" , ENABLE_PCLK_CAM1,"pclk_pmu_cam1" , "div_pclk_cam1_83" ,"pclk_sysreg_cam1" , "div_pclk_cam1_83" ,"pclk_cmu_cam1_local" ,"div_pclk_cam1_166" , ENABLE_PCLK_CAM1,"pclk_isp_mctadc" , "div_pclk_cam1_83" ,"pclk_isp_wdt" , "div_pclk_cam1_83" ,"pclk_isp_pwm" , "div_pclk_cam1_83" ,"pclk_isp_uart" , "div_pclk_cam1_83" ,"pclk_isp_mcuctl" , "div_pclk_cam1_83" ,"pclk_isp_spi1" , "div_pclk_cam1_83" ,"pclk_isp_spi0" , "div_pclk_cam1_83" ,"pclk_isp_i2c2" , "div_pclk_cam1_83" ,"pclk_isp_i2c1" , "div_pclk_cam1_83" ,"pclk_isp_i2c0" , "div_pclk_cam1_83" ,"pclk_isp_mpwm" , "div_pclk_cam1_83" ,"pclk_fd" , "div_pclk_fd" ,"pclk_lite_c" , "div_pclk_lite_c" ,"pclk_csis2" , "div_pclk_cam1_166" ,/* ENABLE_SCLK_CAM1 */ "sclk_isp_i2c2" , "oscclk" , ENABLE_SCLK_CAM1,"sclk_isp_i2c1" , "oscclk" , ENABLE_SCLK_CAM1,"sclk_isp_i2c0" , "oscclk" , ENABLE_SCLK_CAM1,"sclk_isp_pwm" , "oscclk" , ENABLE_SCLK_CAM1,"phyclk_rxbyteclkhs0_s2b" ,"mout_phyclk_rxbyteclkhs0_s2b_user" ,"sclk_lite_c_freecnt" , "div_pclk_lite_c" ,"sclk_pixelasyncm_fd" , "div_aclk_fd" ,"sclk_isp_mctadc" , "sclk_isp_mctadc_cam1" ,"sclk_isp_uart" , "mout_sclk_isp_uart_user" ,"sclk_isp_spi1" , "mout_sclk_isp_spi1_user" ,"sclk_isp_spi0" , "mout_sclk_isp_spi0_user" ,"sclk_isp_mpwm" , "div_sclk_isp_mpwm" ,"sclk_dbg_isp" , "div_pclk_dbg_cam1" ,"atclk_isp" , "div_atclk_cam1" ,"sclk_isp_ca5" , "mout_aclk_cam1_552_user" ,static const struct samsung_cmu_info cam1_cmu_info __initconst = {"aclk_cam1_400" ,/* * Register offset definitions for CMU_IMEM #define ENABLE_ACLK_IMEM_SLIMSSS 0x080c#define ENABLE_PCLK_IMEM_SLIMSSS 0x0908static const unsigned long imem_clk_regs[] __initconst = {static const struct samsung_gate_clock imem_gate_clks[] __initconst = {/* ENABLE_ACLK_IMEM_SLIMSSS */ "aclk_slimsss" , "aclk_imem_sssx_266" ,/* ENABLE_PCLK_IMEM_SLIMSSS */ "pclk_slimsss" , "aclk_imem_200" ,static const struct samsung_cmu_info imem_cmu_info __initconst = {"aclk_imem_200" ,static int __init exynos5433_cmu_probe(struct platform_device *pdev)return exynos_arm64_register_cmu_pm(pdev, false );static const struct of_device_id exynos5433_cmu_of_match[] = {"samsung,exynos5433-cmu-aud" ,"samsung,exynos5433-cmu-cam0" ,"samsung,exynos5433-cmu-cam1" ,"samsung,exynos5433-cmu-disp" ,"samsung,exynos5433-cmu-g2d" ,"samsung,exynos5433-cmu-g3d" ,"samsung,exynos5433-cmu-fsys" ,"samsung,exynos5433-cmu-gscl" ,"samsung,exynos5433-cmu-mfc" ,"samsung,exynos5433-cmu-hevc" ,"samsung,exynos5433-cmu-isp" ,"samsung,exynos5433-cmu-mscl" ,"samsung,exynos5433-cmu-imem" ,static const struct dev_pm_ops exynos5433_cmu_pm_ops = {static struct platform_driver exynos5433_cmu_driver __refdata = {"exynos5433-cmu" ,true ,static int __init exynos5433_cmu_init(void )return platform_driver_register(&exynos5433_cmu_driver);
Messung V0.5 in Prozent C=94 H=97 G=95
¤ Dauer der Verarbeitung: 0.107 Sekunden
(vorverarbeitet am 2026-04-26)
¤ *© Formatika GbR, Deutschland
