// SPDX-License-Identifier: GPL-2.0-only /* * Copyright ( c ) 2022 Samsung Electronics Co . , Ltd . * Author : Chanho Park < chanho61 . park @ samsung . com > * * Common Clock Framework support for ExynosAuto V9 SoC . #include <linux/clk-provider.h>#include <linux/mod_devicetable.h>#include <linux/of.h>#include <linux/platform_device.h>#include <dt-bindings/clock/samsung,exynosautov9.h>#include "clk.h" #include "clk-exynos-arm64.h" /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_TOP (GOUT_CLKCMU_PERIS_BUS + 1 )#define CLKS_NR_BUSMC (CLK_GOUT_BUSMC_SPDMA_PCLK + 1 )#define CLKS_NR_CORE (CLK_GOUT_CORE_CMU_CORE_PCLK + 1 )#define CLKS_NR_DPUM (CLK_GOUT_DPUM_SYSMMU_D3_CLK + 1 )#define CLKS_NR_FSYS0 (CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK + 1 )#define CLKS_NR_FSYS1 (CLK_GOUT_FSYS1_USB30_1_ACLK + 1 )#define CLKS_NR_FSYS2 (CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO + 1 )#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_PCLK_11 + 1 )#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_PCLK_11 + 1 )#define CLKS_NR_PERIS (CLK_GOUT_WDT_CLUSTER1 + 1 )/* ---- CMU_TOP ------------------------------------------------------------ */ /* Register Offset definitions for CMU_TOP (0x1b240000) */ #define PLL_LOCKTIME_PLL_SHARED0 0 x0000#define PLL_LOCKTIME_PLL_SHARED1 0 x0004#define PLL_LOCKTIME_PLL_SHARED2 0 x0008#define PLL_LOCKTIME_PLL_SHARED3 0 x000c#define PLL_LOCKTIME_PLL_SHARED4 0 x0010#define PLL_CON0_PLL_SHARED0 0 x0100#define PLL_CON3_PLL_SHARED0 0 x010c#define PLL_CON0_PLL_SHARED1 0 x0140#define PLL_CON3_PLL_SHARED1 0 x014c#define PLL_CON0_PLL_SHARED2 0 x0180#define PLL_CON3_PLL_SHARED2 0 x018c#define PLL_CON0_PLL_SHARED3 0 x01c0#define PLL_CON3_PLL_SHARED3 0 x01cc#define PLL_CON0_PLL_SHARED4 0 x0200#define PLL_CON3_PLL_SHARED4 0 x020c/* MUX */ #define CLK_CON_MUX_MUX_CLKCMU_ACC_BUS 0 x1000#define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0 x1004#define CLK_CON_MUX_MUX_CLKCMU_AUD_BUS 0 x1008#define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0 x100c#define CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS 0 x1010#define CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS 0 x1018#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0 x101c#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0 x1020#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER 0 x1024#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0 x102c#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER 0 x1030#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0 x1034#define CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS 0 x1040#define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC 0 x1044#define CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS 0 x1048#define CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS 0 x104c#define CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS 0 x1050#define CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS 0 x1054#define CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE 0 x1058#define CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS 0 x105c#define CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD 0 x1060#define CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD 0 x1064#define CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS 0 x1068#define CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET 0 x106c#define CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD 0 x1070#define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0 x1074#define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0 x1078#define CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH 0 x107c#define CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH 0 x1080#define CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH 0 x1084#define CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS 0 x108c#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0 x1090#define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD 0 x1094#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0 x109c#define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0 x1098#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0 x109c#define CLK_CON_MUX_MUX_CLKCMU_NPU_BUS 0 x10a0#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0 x10a4#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0 x10a8#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0 x10ac#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0 x10b0#define CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS 0 x10b4#define CLK_CON_MUX_MUX_CMU_CMUREF 0 x10c0/* DIV */ #define CLK_CON_DIV_CLKCMU_ACC_BUS 0 x1800#define CLK_CON_DIV_CLKCMU_APM_BUS 0 x1804#define CLK_CON_DIV_CLKCMU_AUD_BUS 0 x1808#define CLK_CON_DIV_CLKCMU_AUD_CPU 0 x180c#define CLK_CON_DIV_CLKCMU_BUSC_BUS 0 x1810#define CLK_CON_DIV_CLKCMU_BUSMC_BUS 0 x1818#define CLK_CON_DIV_CLKCMU_CORE_BUS 0 x181c#define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER 0 x1820#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0 x1828#define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER 0 x182c#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0 x1830#define CLK_CON_DIV_CLKCMU_DPTX_BUS 0 x183c#define CLK_CON_DIV_CLKCMU_DPTX_DPGTC 0 x1840#define CLK_CON_DIV_CLKCMU_DPUM_BUS 0 x1844#define CLK_CON_DIV_CLKCMU_DPUS0_BUS 0 x1848#define CLK_CON_DIV_CLKCMU_DPUS1_BUS 0 x184c#define CLK_CON_DIV_CLKCMU_FSYS0_BUS 0 x1850#define CLK_CON_DIV_CLKCMU_FSYS0_PCIE 0 x1854#define CLK_CON_DIV_CLKCMU_FSYS1_BUS 0 x1858#define CLK_CON_DIV_CLKCMU_FSYS1_USBDRD 0 x185c#define CLK_CON_DIV_CLKCMU_FSYS2_BUS 0 x1860#define CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET 0 x1864#define CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD 0 x1868#define CLK_CON_DIV_CLKCMU_G2D_G2D 0 x186c#define CLK_CON_DIV_CLKCMU_G2D_MSCL 0 x1870#define CLK_CON_DIV_CLKCMU_G3D00_SWITCH 0 x1874#define CLK_CON_DIV_CLKCMU_G3D01_SWITCH 0 x1878#define CLK_CON_DIV_CLKCMU_G3D1_SWITCH 0 x187c#define CLK_CON_DIV_CLKCMU_ISPB_BUS 0 x1884#define CLK_CON_DIV_CLKCMU_MFC_MFC 0 x1888#define CLK_CON_DIV_CLKCMU_MFC_WFD 0 x188c#define CLK_CON_DIV_CLKCMU_MIF_BUSP 0 x1890#define CLK_CON_DIV_CLKCMU_NPU_BUS 0 x1894#define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0 x1898#define CLK_CON_DIV_CLKCMU_PERIC0_IP 0 x189c#define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0 x18a0#define CLK_CON_DIV_CLKCMU_PERIC1_IP 0 x18a4#define CLK_CON_DIV_CLKCMU_PERIS_BUS 0 x18a8#define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0 x18b4#define CLK_CON_DIV_PLL_SHARED0_DIV2 0 x18b8#define CLK_CON_DIV_PLL_SHARED0_DIV3 0 x18bc#define CLK_CON_DIV_PLL_SHARED1_DIV2 0 x18c0#define CLK_CON_DIV_PLL_SHARED1_DIV3 0 x18c4#define CLK_CON_DIV_PLL_SHARED1_DIV4 0 x18c8#define CLK_CON_DIV_PLL_SHARED2_DIV2 0 x18cc#define CLK_CON_DIV_PLL_SHARED2_DIV3 0 x18d0#define CLK_CON_DIV_PLL_SHARED2_DIV4 0 x18d4#define CLK_CON_DIV_PLL_SHARED4_DIV2 0 x18d4#define CLK_CON_DIV_PLL_SHARED4_DIV4 0 x18d8/* GATE */ #define CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST 0 x2000#define CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST 0 x2004#define CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST 0 x2008#define CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST 0 x2010#define CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST 0 x2018#define CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST 0 x2020#define CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD 0 x2024#define CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH 0 x2028#define CLK_CON_GAT_GATE_CLKCMU_ACC_BUS 0 x202c#define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0 x2030#define CLK_CON_GAT_GATE_CLKCMU_AUD_BUS 0 x2034#define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU 0 x2038#define CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS 0 x203c#define CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS 0 x2044#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0 x2048#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0 x204c#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER 0 x2050#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0 x2058#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER 0 x205c#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0 x2060#define CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS 0 x206c#define CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC 0 x2070#define CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS 0 x2060#define CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS 0 x2064#define CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS 0 x207c#define CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS 0 x2080#define CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE 0 x2084#define CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS 0 x2088#define CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD 0 x208c#define CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS 0 x2090#define CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET 0 x2094#define CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD 0 x2098#define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0 x209c#define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0 x20a0#define CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH 0 x20a4#define CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH 0 x20a8#define CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH 0 x20ac#define CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS 0 x20b4#define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0 x20b8#define CLK_CON_GAT_GATE_CLKCMU_MFC_WFD 0 x20bc#define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0 x20c0#define CLK_CON_GAT_GATE_CLKCMU_NPU_BUS 0 x20c4#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0 x20c8#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0 x20cc#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0 x20d0#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0 x20d4#define CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS 0 x20d8static const unsigned long top_clk_regs[] __initconst = {static const struct samsung_pll_clock top_pll_clks[] __initconst = {/* CMU_TOP_PURECLKCOMP */ "fout_shared0_pll" , "oscclk" ,"fout_shared1_pll" , "oscclk" ,"fout_shared2_pll" , "oscclk" ,"fout_shared3_pll" , "oscclk" ,"fout_shared4_pll" , "oscclk" ,/* List of parent clocks for Muxes in CMU_TOP */ "oscclk" , "fout_shared0_pll" };"oscclk" , "fout_shared1_pll" };"oscclk" , "fout_shared2_pll" };"oscclk" , "fout_shared3_pll" };"oscclk" , "fout_shared4_pll" };"dout_shared2_div3" , "dout_shared1_div4" ,"dout_shared2_div4" , "dout_shared4_div4" };"oscclk" , "dout_cmu_boost" };"dout_shared1_div3" , "dout_shared2_div3" ,"dout_shared1_div4" , "dout_shared2_div4" };"dout_shared2_div3" , "dout_shared1_div4" ,"dout_shared2_div4" , "dout_shared4_div4" };"dout_shared0_div2" , "dout_shared1_div2" ,"dout_shared2_div2" , "dout_shared0_div3" ,"dout_shared4_div2" , "dout_shared1_div3" ,"fout_shared3_pll" };"dout_shared4_div2" , "dout_shared1_div3" ,"dout_shared2_div3" , "dout_shared1_div4" };"dout_shared2_div3" , "dout_shared1_div4" ,"dout_shared2_div4" , "dout_shared4_div4" };"dout_shared0_div2" , "dout_shared1_div2" ,"dout_shared2_div2" , "dout_shared0_div3" ,"dout_shared4_div2" , "dout_shared1_div3" ,"dout_shared2_div3" , "fout_shared3_pll" };"dout_shared0_div2" , "dout_shared1_div2" ,"dout_shared2_div2" , "dout_shared4_div2" };"fout_shared2_pll" , "fout_shared4_pll" ,"dout_shared0_div2" , "dout_shared1_div2" ,"dout_shared2_div2" , "dout_shared4_div2" ,"dout_shared2_div3" , "fout_shared3_pll" };"dout_shared4_div2" , "dout_shared2_div3" ,"dout_shared1_div4" , "dout_shared2_div4" };"oscclk" , "dout_shared2_div3" ,"dout_shared2_div4" , "dout_shared4_div4" };"dout_shared1_div3" , "dout_shared2_div3" ,"dout_shared1_div4" , "dout_shared2_div4" ,"dout_shared4_div4" , "fout_shared3_pll" };"dout_shared4_div2" , "dout_shared2_div3" ,"dout_shared1_div4" , "dout_shared2_div4" };"oscclk" , "dout_shared2_div4" };"dout_shared2_div3" , "dout_shared1_div4" ,"dout_shared2_div4" , "dout_shared4_div4" };"oscclk" , "dout_shared2_div3" ,"dout_shared2_div4" , "dout_shared4_div4" };"oscclk" , "dout_shared2_div2" ,"dout_shared4_div2" , "dout_shared2_div3" };"oscclk" , "dout_shared2_div2" ,"dout_shared0_div3" , "dout_shared2_div3" ,"dout_shared1_div4" , "fout_shared3_pll" };"dout_shared2_div2" , "dout_shared0_div3" ,"dout_shared4_div2" , "dout_shared1_div3" ,"dout_shared2_div3" , "dout_shared1_div4" ,"dout_shared2_div4" , "dout_shared4_div4" };"dout_shared0_div2" , "dout_shared1_div2" ,"dout_shared2_div2" , "dout_shared4_div2" };"dout_shared2_div2" , "dout_shared4_div2" ,"dout_shared2_div3" , "dout_shared1_div4" };"fout_shared0_pll" , "fout_shared1_pll" ,"fout_shared2_pll" , "fout_shared4_pll" ,"dout_shared0_div2" , "dout_shared1_div2" ,"dout_shared2_div2" , "fout_shared3_pll" };"dout_shared1_div2" , "dout_shared2_div2" ,"dout_shared0_div3" , "dout_shared4_div2" ,"dout_shared1_div3" , "dout_shared2_div3" ,"dout_shared1_div4" , "fout_shared3_pll" };"dout_shared2_div3" , "dout_shared2_div4" };static const struct samsung_mux_clock top_mux_clks[] __initconst = {/* CMU_TOP_PURECLKCOMP */ "mout_shared0_pll" , mout_shared0_pll_p,4 , 1 ),"mout_shared1_pll" , mout_shared1_pll_p,4 , 1 ),"mout_shared2_pll" , mout_shared2_pll_p,4 , 1 ),"mout_shared3_pll" , mout_shared3_pll_p,4 , 1 ),"mout_shared4_pll" , mout_shared4_pll_p,4 , 1 ),/* BOOST */ "mout_clkcmu_cmu_boost" ,0 , 2 ),"mout_clkcmu_cmu_cmuref" ,0 , 1 ),/* ACC */ "mout_clkcmu_acc_bus" , mout_clkcmu_acc_bus_p,0 , 2 ),/* APM */ "mout_clkcmu_apm_bus" , mout_clkcmu_apm_bus_p,0 , 2 ),/* AUD */ "mout_clkcmu_aud_cpu" , mout_clkcmu_aud_cpu_p,0 , 3 ),"mout_clkcmu_aud_bus" , mout_clkcmu_aud_bus_p,0 , 2 ),/* BUSC */ "mout_clkcmu_busc_bus" ,0 , 2 ),/* BUSMC */ "mout_clkcmu_busmc_bus" ,0 , 2 ),/* CORE */ "mout_clkcmu_core_bus" ,0 , 3 ),/* CPUCL0 */ "mout_clkcmu_cpucl0_switch" ,0 , 2 ),"mout_clkcmu_cpucl0_cluster" ,0 , 3 ),/* CPUCL1 */ "mout_clkcmu_cpucl1_switch" ,0 , 2 ),"mout_clkcmu_cpucl1_cluster" ,0 , 3 ),/* DPTX */ "mout_clkcmu_dptx_bus" ,0 , 2 ),"mout_clkcmu_dptx_dpgtc" ,0 , 2 ),/* DPUM */ "mout_clkcmu_dpum_bus" ,0 , 3 ),/* DPUS */ "mout_clkcmu_dpus0_bus" ,0 , 3 ),"mout_clkcmu_dpus1_bus" ,0 , 3 ),/* FSYS0 */ "mout_clkcmu_fsys0_bus" ,0 , 2 ),"mout_clkcmu_fsys0_pcie" ,0 , 1 ),/* FSYS1 */ "mout_clkcmu_fsys1_bus" ,0 , 2 ),"mout_clkcmu_fsys1_usbdrd" ,0 , 2 ),"mout_clkcmu_fsys1_mmc_card" ,0 , 2 ),/* FSYS2 */ "mout_clkcmu_fsys2_bus" ,0 , 2 ),"mout_clkcmu_fsys2_ufs_embd" ,0 , 2 ),"mout_clkcmu_fsys2_ethernet" ,0 , 3 ),/* G2D */ "mout_clkcmu_g2d_g2d" , mout_clkcmu_g2d_g2d_p,0 , 3 ),"mout_clkcmu_g2d_mscl" ,0 , 2 ),/* G3D0 */ "mout_clkcmu_g3d00_switch" ,0 , 2 ),"mout_clkcmu_g3d01_switch" ,0 , 2 ),/* G3D1 */ "mout_clkcmu_g3d1_switch" ,0 , 2 ),/* ISPB */ "mout_clkcmu_ispb_bus" ,0 , 2 ),/* MFC */ "mout_clkcmu_mfc_mfc" ,0 , 2 ),"mout_clkcmu_mfc_wfd" ,0 , 2 ),/* MIF */ "mout_clkcmu_mif_switch" ,0 , 3 ),"mout_clkcmu_mif_busp" ,0 , 2 ),/* NPU */ "mout_clkcmu_npu_bus" , mout_clkcmu_npu_bus_p,0 , 3 ),/* PERIC0 */ "mout_clkcmu_peric0_bus" ,0 , 1 ),"mout_clkcmu_peric0_ip" ,0 , 1 ),/* PERIC1 */ "mout_clkcmu_peric1_bus" ,0 , 1 ),"mout_clkcmu_peric1_ip" ,0 , 1 ),/* PERIS */ "mout_clkcmu_peris_bus" ,0 , 1 ),static const struct samsung_div_clock top_div_clks[] __initconst = {/* CMU_TOP_PURECLKCOMP */ "dout_shared0_div3" , "mout_shared0_pll" ,0 , 2 ),"dout_shared0_div2" , "mout_shared0_pll" ,0 , 1 ),"dout_shared1_div3" , "mout_shared1_pll" ,0 , 2 ),"dout_shared1_div2" , "mout_shared1_pll" ,0 , 1 ),"dout_shared1_div4" , "dout_shared1_div2" ,0 , 1 ),"dout_shared2_div3" , "mout_shared2_pll" ,0 , 2 ),"dout_shared2_div2" , "mout_shared2_pll" ,0 , 1 ),"dout_shared2_div4" , "dout_shared2_div2" ,0 , 1 ),"dout_shared4_div2" , "mout_shared4_pll" ,0 , 1 ),"dout_shared4_div4" , "dout_shared4_div2" ,0 , 1 ),/* BOOST */ "dout_clkcmu_cmu_boost" ,"gout_clkcmu_cmu_boost" , CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0 , 2 ),/* ACC */ "dout_clkcmu_acc_bus" , "gout_clkcmu_acc_bus" ,0 , 4 ),/* APM */ "dout_clkcmu_apm_bus" , "gout_clkcmu_apm_bus" ,0 , 3 ),/* AUD */ "dout_clkcmu_aud_cpu" , "gout_clkcmu_aud_cpu" ,0 , 3 ),"dout_clkcmu_aud_bus" , "gout_clkcmu_aud_bus" ,0 , 4 ),/* BUSC */ "dout_clkcmu_busc_bus" ,"gout_clkcmu_busc_bus" , CLK_CON_DIV_CLKCMU_BUSC_BUS, 0 , 4 ),/* BUSMC */ "dout_clkcmu_busmc_bus" ,"gout_clkcmu_busmc_bus" , CLK_CON_DIV_CLKCMU_BUSMC_BUS, 0 , 4 ),/* CORE */ "dout_clkcmu_core_bus" ,"gout_clkcmu_core_bus" , CLK_CON_DIV_CLKCMU_CORE_BUS, 0 , 4 ),/* CPUCL0 */ "dout_clkcmu_cpucl0_switch" ,"gout_clkcmu_cpucl0_switch" , CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,0 , 3 ),"dout_clkcmu_cpucl0_cluster" ,"gout_clkcmu_cpucl0_cluster" , CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER,0 , 3 ),/* CPUCL1 */ "dout_clkcmu_cpucl1_switch" ,"gout_clkcmu_cpucl1_switch" , CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,0 , 3 ),"dout_clkcmu_cpucl1_cluster" ,"gout_clkcmu_cpucl1_cluster" , CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER,0 , 3 ),/* DPTX */ "dout_clkcmu_dptx_bus" ,"gout_clkcmu_dptx_bus" , CLK_CON_DIV_CLKCMU_DPTX_BUS, 0 , 4 ),"dout_clkcmu_dptx_dpgtc" ,"gout_clkcmu_dptx_dpgtc" , CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 0 , 3 ),/* DPUM */ "dout_clkcmu_dpum_bus" ,"gout_clkcmu_dpum_bus" , CLK_CON_DIV_CLKCMU_DPUM_BUS, 0 , 4 ),/* DPUS */ "dout_clkcmu_dpus0_bus" ,"gout_clkcmu_dpus0_bus" , CLK_CON_DIV_CLKCMU_DPUS0_BUS, 0 , 4 ),"dout_clkcmu_dpus1_bus" ,"gout_clkcmu_dpus1_bus" , CLK_CON_DIV_CLKCMU_DPUS1_BUS, 0 , 4 ),/* FSYS0 */ "dout_clkcmu_fsys0_bus" ,"gout_clkcmu_fsys0_bus" , CLK_CON_DIV_CLKCMU_FSYS0_BUS, 0 , 4 ),/* FSYS1 */ "dout_clkcmu_fsys1_bus" ,"gout_clkcmu_fsys1_bus" , CLK_CON_DIV_CLKCMU_FSYS1_BUS, 0 , 4 ),"dout_clkcmu_fsys1_usbdrd" ,"gout_clkcmu_fsys1_usbdrd" , CLK_CON_DIV_CLKCMU_FSYS1_USBDRD, 0 , 4 ),/* FSYS2 */ "dout_clkcmu_fsys2_bus" ,"gout_clkcmu_fsys2_bus" , CLK_CON_DIV_CLKCMU_FSYS2_BUS, 0 , 4 ),"dout_clkcmu_fsys2_ufs_embd" ,"gout_clkcmu_fsys2_ufs_embd" , CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD,0 , 3 ),"dout_clkcmu_fsys2_ethernet" ,"gout_clkcmu_fsys2_ethernet" , CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET,0 , 3 ),/* G2D */ "dout_clkcmu_g2d_g2d" , "gout_clkcmu_g2d_g2d" ,0 , 4 ),"dout_clkcmu_g2d_mscl" ,"gout_clkcmu_g2d_mscl" , CLK_CON_DIV_CLKCMU_G2D_MSCL, 0 , 4 ),/* G3D0 */ "dout_clkcmu_g3d00_switch" ,"gout_clkcmu_g3d00_switch" , CLK_CON_DIV_CLKCMU_G3D00_SWITCH, 0 , 3 ),"dout_clkcmu_g3d01_switch" ,"gout_clkcmu_g3d01_switch" , CLK_CON_DIV_CLKCMU_G3D01_SWITCH, 0 , 3 ),/* G3D1 */ "dout_clkcmu_g3d1_switch" ,"gout_clkcmu_g3d1_switch" , CLK_CON_DIV_CLKCMU_G3D1_SWITCH, 0 , 3 ),/* ISPB */ "dout_clkcmu_ispb_bus" ,"gout_clkcmu_ispb_bus" , CLK_CON_DIV_CLKCMU_ISPB_BUS, 0 , 4 ),/* MFC */ "dout_clkcmu_mfc_mfc" , "gout_clkcmu_mfc_mfc" ,0 , 4 ),"dout_clkcmu_mfc_wfd" , "gout_clkcmu_mfc_wfd" ,0 , 4 ),/* MIF */ "dout_clkcmu_mif_busp" ,"gout_clkcmu_mif_busp" , CLK_CON_DIV_CLKCMU_MIF_BUSP, 0 , 4 ),/* NPU */ "dout_clkcmu_npu_bus" , "gout_clkcmu_npu_bus" ,0 , 4 ),/* PERIC0 */ "dout_clkcmu_peric0_bus" ,"gout_clkcmu_peric0_bus" , CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0 , 4 ),"dout_clkcmu_peric0_ip" ,"gout_clkcmu_peric0_ip" , CLK_CON_DIV_CLKCMU_PERIC0_IP, 0 , 4 ),/* PERIC1 */ "dout_clkcmu_peric1_bus" ,"gout_clkcmu_peric1_bus" , CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0 , 4 ),"dout_clkcmu_peric1_ip" ,"gout_clkcmu_peric1_ip" , CLK_CON_DIV_CLKCMU_PERIC1_IP, 0 , 4 ),/* PERIS */ "dout_clkcmu_peris_bus" ,"gout_clkcmu_peris_bus" , CLK_CON_DIV_CLKCMU_PERIS_BUS, 0 , 4 ),static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {"dout_clkcmu_fsys0_pcie" ,"gout_clkcmu_fsys0_pcie" , 1 , 4 , 0 ),static const struct samsung_gate_clock top_gate_clks[] __initconst = {/* BOOST */ "gout_clkcmu_cmu_boost" ,"mout_clkcmu_cmu_boost" , CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,21 , 0 , 0 ),"gout_clkcmu_cpucl0_boost" ,"dout_cmu_boost" , CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST, 21 , 0 , 0 ),"gout_clkcmu_cpucl1_boost" ,"dout_cmu_boost" , CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST, 21 , 0 , 0 ),"gout_clkcmu_core_boost" ,"dout_cmu_boost" , CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST, 21 , 0 , 0 ),"gout_clkcmu_busc_boost" ,"dout_cmu_boost" , CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST, 21 , 0 , 0 ),"gout_clkcmu_busmc_boost" ,"dout_cmu_boost" , CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST, 21 , 0 , 0 ),"gout_clkcmu_mif_boost" , "dout_cmu_boost" ,21 , 0 , 0 ),/* ACC */ "gout_clkcmu_acc_bus" , "mout_clkcmu_acc_bus" ,21 , 0 , 0 ),/* APM */ "gout_clkcmu_apm_bus" , "mout_clkcmu_apm_bus" ,21 , CLK_IGNORE_UNUSED, 0 ),/* AUD */ "gout_clkcmu_aud_cpu" , "mout_clkcmu_aud_cpu" ,21 , 0 , 0 ),"gout_clkcmu_aud_bus" , "mout_clkcmu_aud_bus" ,21 , 0 , 0 ),/* BUSC */ "gout_clkcmu_busc_bus" ,"mout_clkcmu_busc_bus" , CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS, 21 ,0 ),/* BUSMC */ "gout_clkcmu_busmc_bus" ,"mout_clkcmu_busmc_bus" , CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS, 21 ,0 ),/* CORE */ "gout_clkcmu_core_bus" ,"mout_clkcmu_core_bus" , CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,21 , 0 , 0 ),/* CPUCL0 */ "gout_clkcmu_cpucl0_switch" ,"mout_clkcmu_cpucl0_switch" ,21 , CLK_IGNORE_UNUSED, 0 ),"gout_clkcmu_cpucl0_cluster" ,"mout_clkcmu_cpucl0_cluster" ,21 , CLK_IGNORE_UNUSED, 0 ),/* CPUCL1 */ "gout_clkcmu_cpucl1_switch" ,"mout_clkcmu_cpucl1_switch" ,21 , CLK_IGNORE_UNUSED, 0 ),"gout_clkcmu_cpucl1_cluster" ,"mout_clkcmu_cpucl1_cluster" ,21 , CLK_IGNORE_UNUSED, 0 ),/* DPTX */ "gout_clkcmu_dptx_bus" ,"mout_clkcmu_dptx_bus" , CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS,21 , 0 , 0 ),"gout_clkcmu_dptx_dpgtc" ,"mout_clkcmu_dptx_dpgtc" , CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC,21 , 0 , 0 ),/* DPUM */ "gout_clkcmu_dpum_bus" ,"mout_clkcmu_dpum_bus" , CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS,21 , 0 , 0 ),/* DPUS */ "gout_clkcmu_dpus0_bus" ,"mout_clkcmu_dpus0_bus" , CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS,21 , 0 , 0 ),"gout_clkcmu_dpus1_bus" ,"mout_clkcmu_dpus1_bus" , CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS,21 , 0 , 0 ),/* FSYS0 */ "gout_clkcmu_fsys0_bus" ,"mout_clkcmu_fsys0_bus" , CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS,21 , 0 , 0 ),"gout_clkcmu_fsys0_pcie" ,"mout_clkcmu_fsys0_pcie" , CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE,21 , 0 , 0 ),/* FSYS1 */ "gout_clkcmu_fsys1_bus" ,"mout_clkcmu_fsys1_bus" , CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS,21 , 0 , 0 ),"gout_clkcmu_fsys1_usbdrd" ,"mout_clkcmu_fsys1_usbdrd" , CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD,21 , 0 , 0 ),"gout_clkcmu_fsys1_mmc_card" ,"mout_clkcmu_fsys1_mmc_card" ,21 , 0 , 0 ),/* FSYS2 */ "gout_clkcmu_fsys2_bus" ,"mout_clkcmu_fsys2_bus" , CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS,21 , 0 , 0 ),"gout_clkcmu_fsys2_ufs_embd" ,"mout_clkcmu_fsys2_ufs_embd" ,21 , 0 , 0 ),"gout_clkcmu_fsys2_ethernet" ,"mout_clkcmu_fsys2_ethernet" ,21 , 0 , 0 ),/* G2D */ "gout_clkcmu_g2d_g2d" ,"mout_clkcmu_g2d_g2d" , CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21 , 0 , 0 ),"gout_clkcmu_g2d_mscl" ,"mout_clkcmu_g2d_mscl" , CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,21 , 0 , 0 ),/* G3D0 */ "gout_clkcmu_g3d00_switch" ,"mout_clkcmu_g3d00_switch" , CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH,21 , 0 , 0 ),"gout_clkcmu_g3d01_switch" ,"mout_clkcmu_g3d01_switch" , CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH,21 , 0 , 0 ),/* G3D1 */ "gout_clkcmu_g3d1_switch" ,"mout_clkcmu_g3d1_switch" , CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH,21 , 0 , 0 ),/* ISPB */ "gout_clkcmu_ispb_bus" ,"mout_clkcmu_ispb_bus" , CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS,21 , 0 , 0 ),/* MFC */ "gout_clkcmu_mfc_mfc" , "mout_clkcmu_mfc_mfc" ,21 , 0 , 0 ),"gout_clkcmu_mfc_wfd" , "mout_clkcmu_mfc_wfd" ,21 , 0 , 0 ),/* MIF */ "gout_clkcmu_mif_switch" ,"mout_clkcmu_mif_switch" , CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH,21 , CLK_IGNORE_UNUSED, 0 ),"gout_clkcmu_mif_busp" ,"mout_clkcmu_mif_busp" , CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,21 , CLK_IGNORE_UNUSED, 0 ),/* NPU */ "gout_clkcmu_npu_bus" , "mout_clkcmu_npu_bus" ,21 , 0 , 0 ),/* PERIC0 */ "gout_clkcmu_peric0_bus" ,"mout_clkcmu_peric0_bus" , CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,21 , 0 , 0 ),"gout_clkcmu_peric0_ip" ,"mout_clkcmu_peric0_ip" , CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,21 , 0 , 0 ),/* PERIC1 */ "gout_clkcmu_peric1_bus" ,"mout_clkcmu_peric1_bus" , CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,21 , 0 , 0 ),"gout_clkcmu_peric1_ip" ,"mout_clkcmu_peric1_ip" , CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,21 , 0 , 0 ),/* PERIS */ "gout_clkcmu_peris_bus" ,"mout_clkcmu_peris_bus" , CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,21 , CLK_IGNORE_UNUSED, 0 ),static const struct samsung_cmu_info top_cmu_info __initconst = {static void __init exynosautov9_cmu_top_init(struct device_node *np)/* Register CMU_TOP early, as it's a dependency for other early domains */ "samsung,exynosautov9-cmu-top" ,/* ---- CMU_BUSMC ---------------------------------------------------------- */ /* Register Offset definitions for CMU_BUSMC (0x1b200000) */ #define PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER 0 x0600#define CLK_CON_DIV_DIV_CLK_BUSMC_BUSP 0 x1800#define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK 0 x2078#define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK 0 x2080static const unsigned long busmc_clk_regs[] __initconst = {/* List of parent clocks for Muxes in CMU_BUSMC */ "oscclk" , "dout_clkcmu_busmc_bus" };static const struct samsung_mux_clock busmc_mux_clks[] __initconst = {"mout_busmc_bus_user" ,4 , 1 ),static const struct samsung_div_clock busmc_div_clks[] __initconst = {"dout_busmc_busp" , "mout_busmc_bus_user" ,0 , 3 ),static const struct samsung_gate_clock busmc_gate_clks[] __initconst = {"gout_busmc_pdma0_pclk" ,"dout_busmc_busp" ,21 ,0 , 0 ),"gout_busmc_spdma_pclk" ,"dout_busmc_busp" ,21 ,0 , 0 ),static const struct samsung_cmu_info busmc_cmu_info __initconst = {"dout_clkcmu_busmc_bus" ,/* ---- CMU_CORE ----------------------------------------------------------- */ /* Register Offset definitions for CMU_CORE (0x1b030000) */ #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0 x0600#define CLK_CON_MUX_MUX_CORE_CMUREF 0 x1000#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0 x1800#define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK 0 x2000#define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK 0 x2004#define CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK 0 x2008static const unsigned long core_clk_regs[] __initconst = {/* List of parent clocks for Muxes in CMU_CORE */ "oscclk" , "dout_clkcmu_core_bus" };static const struct samsung_mux_clock core_mux_clks[] __initconst = {"mout_core_bus_user" , mout_core_bus_user_p,4 , 1 ),static const struct samsung_div_clock core_div_clks[] __initconst = {"dout_core_busp" , "mout_core_bus_user" ,0 , 3 ),static const struct samsung_gate_clock core_gate_clks[] __initconst = {"gout_core_cci_clk" , "mout_core_bus_user" ,21 ,0 ),"gout_core_cci_pclk" , "dout_core_busp" ,21 ,0 ),"gout_core_cmu_core_pclk" ,"dout_core_busp" ,21 ,0 ),static const struct samsung_cmu_info core_cmu_info __initconst = {"dout_clkcmu_core_bus" ,/* ---- CMU_DPUM ---------------------------------------------------------- */ /* Register Offset definitions for CMU_DPUM (0x18c00000) */ #define PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER 0 x0600#define CLK_CON_DIV_DIV_CLK_DPUM_BUSP 0 x1800#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON 0 x202c#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA 0 x2030#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP 0 x2034#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1 0 x207c#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1 0 x2084#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1 0 x208c#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1 0 x2094static const unsigned long dpum_clk_regs[] __initconst = {"oscclk" , "dout_clkcmu_dpum_bus" };static const struct samsung_mux_clock dpum_mux_clks[] __initconst = {"mout_dpum_bus_user" ,4 , 1 ),static const struct samsung_div_clock dpum_div_clks[] __initconst = {"dout_dpum_busp" , "mout_dpum_bus_user" ,0 , 3 ),static const struct samsung_gate_clock dpum_gate_clks[] __initconst = {"gout_dpum_decon_aclk" ,"mout_dpum_bus_user" ,21 ,0 , 0 ),"gout_dpum_dma_aclk" , "mout_dpum_bus_user" ,21 ,0 , 0 ),"gout_dpum_dpp_aclk" , "mout_dpum_bus_user" ,21 ,0 , 0 ),"gout_dpum_sysmmu_d0_clk" ,"mout_dpum_bus_user" ,21 ,0 , 0 ),"gout_dpum_sysmmu_d1_clk" ,"mout_dpum_bus_user" ,21 ,0 , 0 ),"gout_dpum_sysmmu_d2_clk" ,"mout_dpum_bus_user" ,21 ,0 , 0 ),"gout_dpum_sysmmu_d3_clk" ,"mout_dpum_bus_user" ,21 ,0 , 0 ),static const struct samsung_cmu_info dpum_cmu_info __initconst = {"bus" ,/* ---- CMU_FSYS0 ---------------------------------------------------------- */ /* Register Offset definitions for CMU_FSYS2 (0x17700000) */ #define PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER 0 x0600#define PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER 0 x0610#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0 x2000#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN 0 x2004#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN 0 x2008#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN 0 x200c#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN 0 x2010#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN 0 x2014#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN 0 x2018#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK 0 x205c#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK 0 x2060#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK 0 x2064#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK 0 x206c#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK 0 x2070#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK 0 x2074#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK 0 x207c#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK 0 x2084#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK 0 x2088#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK 0 x208c#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK 0 x2094#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK 0 x2098#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK 0 x209c#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK 0 x20a4#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK 0 x20ac#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK 0 x20b0#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK 0 x20b4#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK 0 x20bc#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK 0 x20c0#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK 0 x20c4#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK 0 x20cc#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK 0 x20d4#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK 0 x20d8#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK 0 x20dc#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK 0 x20e0#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK 0 x20e4#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK 0 x20e8static const unsigned long fsys0_clk_regs[] __initconst = {/* List of parent clocks for Muxes in CMU_FSYS0 */ "oscclk" , "dout_clkcmu_fsys0_bus" };"oscclk" , "dout_clkcmu_fsys0_pcie" };static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {"mout_fsys0_bus_user" ,4 , 1 ),"mout_fsys0_pcie_user" ,4 , 1 ),static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {"gout_fsys0_bus_pclk" ,"mout_fsys0_bus_user" ,21 , CLK_IGNORE_UNUSED, 0 ),/* Gen3 2L0 */ "gout_fsys0_pcie_gen3_2l0_x1_refclk" , "mout_fsys0_pcie_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_2l0_x2_refclk" , "mout_fsys0_pcie_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_2l0_x1_dbi_aclk" , "mout_fsys0_bus_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_2l0_x1_mstr_aclk" , "mout_fsys0_bus_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_2l0_x1_slv_aclk" , "mout_fsys0_bus_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_2l0_x2_dbi_aclk" , "mout_fsys0_bus_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_2l0_x2_mstr_aclk" , "mout_fsys0_bus_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_2l0_x2_slv_aclk" , "mout_fsys0_bus_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3a_2l0_clk" , "mout_fsys0_pcie_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3b_2l0_clk" , "mout_fsys0_pcie_user" ,21 , 0 , 0 ),/* Gen3 2L1 */ "gout_fsys0_pcie_gen3_2l1_x1_refclk" , "mout_fsys0_pcie_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_2l1_x2_refclk" , "mout_fsys0_pcie_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_2l1_x1_dbi_aclk" , "mout_fsys0_bus_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_2l1_x1_mstr_aclk" , "mout_fsys0_bus_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_2l1_x1_slv_aclk" , "mout_fsys0_bus_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_2l1_x2_dbi_aclk" , "mout_fsys0_bus_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_2l1_x2_mstr_aclk" , "mout_fsys0_bus_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_2l1_x2_slv_aclk" , "mout_fsys0_bus_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3a_2l1_clk" , "mout_fsys0_pcie_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3b_2l1_clk" , "mout_fsys0_pcie_user" ,21 , 0 , 0 ),/* Gen3 4L */ "gout_fsys0_pcie_gen3_4l_x2_refclk" , "mout_fsys0_pcie_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_4l_x4_refclk" , "mout_fsys0_pcie_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_4l_x2_dbi_aclk" , "mout_fsys0_bus_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_4l_x2_mstr_aclk" , "mout_fsys0_bus_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_4l_x2_slv_aclk" , "mout_fsys0_bus_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_4l_x4_dbi_aclk" , "mout_fsys0_bus_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_4l_x4_mstr_aclk" , "mout_fsys0_bus_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3_4l_x4_slv_aclk" , "mout_fsys0_bus_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3a_4l_clk" , "mout_fsys0_pcie_user" ,21 , 0 , 0 ),"gout_fsys0_pcie_gen3b_4l_clk" , "mout_fsys0_pcie_user" ,21 , 0 , 0 ),static const struct samsung_cmu_info fsys0_cmu_info __initconst = {"dout_clkcmu_fsys0_bus" ,/* ---- CMU_FSYS1 ---------------------------------------------------------- */ /* Register Offset definitions for CMU_FSYS1 (0x17040000) */ #define PLL_LOCKTIME_PLL_MMC 0 x0000#define PLL_CON0_PLL_MMC 0 x0100#define PLL_CON3_PLL_MMC 0 x010c#define PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER 0 x0600#define PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER 0 x0610#define PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER 0 x0620#define CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD 0 x1000#define CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD 0 x1800#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0 x2018#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0 x202c#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK 0 x2028#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40 0 x204c#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40 0 x2058#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40 0 x2064#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40 0 x2070#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK 0 x2074#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK 0 x2078#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK 0 x207c#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK 0 x2080static const unsigned long fsys1_clk_regs[] __initconst = {static const struct samsung_pll_clock fsys1_pll_clks[] __initconst = {"fout_mmc_pll" , "oscclk" ,/* List of parent clocks for Muxes in CMU_FSYS1 */ "oscclk" , "dout_clkcmu_fsys1_bus" };"oscclk" , "fout_mmc_pll" };"oscclk" , "gout_clkcmu_fsys1_mmc_card" };"oscclk" , "dout_clkcmu_fsys1_usbdrd" };"mout_fsys1_mmc_card_user" ,"mout_fsys1_mmc_pll" };static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {"mout_fsys1_bus_user" ,4 , 1 ),"mout_fsys1_mmc_pll" , mout_fsys1_mmc_pll_p,4 , 1 ),"mout_fsys1_mmc_card_user" ,4 , 1 ),"mout_fsys1_usbdrd_user" ,4 , 1 ),"mout_fsys1_mmc_card" ,0 , 1 ),static const struct samsung_div_clock fsys1_div_clks[] __initconst = {"dout_fsys1_mmc_card" ,"mout_fsys1_mmc_card" ,0 , 9 ),static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {"gout_fsys1_pclk" , "mout_fsys1_bus_user" ,21 , CLK_IGNORE_UNUSED, 0 ),"gout_fsys1_mmc_card_sdclkin" ,"dout_fsys1_mmc_card" ,21 , CLK_SET_RATE_PARENT, 0 ),"gout_fsys1_mmc_card_aclk" ,"dout_fsys1_mmc_card" ,21 , 0 , 0 ),"gout_fsys1_usb20drd_0_refclk" ,"mout_fsys1_usbdrd_user" ,21 , 0 , 0 ),"gout_fsys1_usb20drd_1_refclk" ,"mout_fsys1_usbdrd_user" ,21 , 0 , 0 ),"gout_fsys1_usb30drd_0_refclk" ,"mout_fsys1_usbdrd_user" ,21 , 0 , 0 ),"gout_fsys1_usb30drd_1_refclk" ,"mout_fsys1_usbdrd_user" ,21 , 0 , 0 ),"gout_fsys1_usb20_0_aclk" ,"mout_fsys1_usbdrd_user" ,21 , 0 , 0 ),"gout_fsys1_usb20_1_aclk" ,"mout_fsys1_usbdrd_user" ,21 , 0 , 0 ),"gout_fsys1_usb30_0_aclk" ,"mout_fsys1_usbdrd_user" ,21 , 0 , 0 ),"gout_fsys1_usb30_1_aclk" ,"mout_fsys1_usbdrd_user" ,21 , 0 , 0 ),static const struct samsung_cmu_info fsys1_cmu_info __initconst = {"dout_clkcmu_fsys1_bus" ,/* ---- CMU_FSYS2 ---------------------------------------------------------- */ /* Register Offset definitions for CMU_FSYS2 (0x17c00000) */ #define PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER 0 x0600#define PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER 0 x0620#define PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER 0 x0610#define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK 0 x2098#define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO 0 x209c#define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK 0 x20a4#define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO 0 x20a8static const unsigned long fsys2_clk_regs[] __initconst = {/* List of parent clocks for Muxes in CMU_FSYS2 */ "oscclk" , "dout_clkcmu_fsys2_bus" };"oscclk" , "dout_clkcmu_fsys2_ufs_embd" };"oscclk" , "dout_clkcmu_fsys2_ethernet" };static const struct samsung_mux_clock fsys2_mux_clks[] __initconst = {"mout_fsys2_bus_user" ,4 , 1 ),"mout_fsys2_ufs_embd_user" ,4 , 1 ),"mout_fsys2_ethernet_user" ,4 , 1 ),static const struct samsung_gate_clock fsys2_gate_clks[] __initconst = {"gout_fsys2_ufs_embd0_aclk" ,"mout_fsys2_ufs_embd_user" ,21 ,0 , 0 ),"gout_fsys2_ufs_embd0_unipro" ,"mout_fsys2_ufs_embd_user" ,21 , 0 , 0 ),"gout_fsys2_ufs_embd1_aclk" ,"mout_fsys2_ufs_embd_user" ,21 ,0 , 0 ),"gout_fsys2_ufs_embd1_unipro" ,"mout_fsys2_ufs_embd_user" ,21 , 0 , 0 ),static const struct samsung_cmu_info fsys2_cmu_info __initconst = {"dout_clkcmu_fsys2_bus" ,/* ---- CMU_PERIC0 --------------------------------------------------------- */ /* Register Offset definitions for CMU_PERIC0 (0x10200000) */ #define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0 x0600#define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER 0 x0610#define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI 0 x1000#define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI 0 x1004#define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI 0 x1008#define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI 0 x100c#define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI 0 x1010#define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI 0 x1014#define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C 0 x1018#define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0 x1800#define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0 x1804#define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0 x1808#define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0 x180c#define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0 x1810#define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0 x1814#define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0 x1818#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0 x2014#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0 x2018#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0 x2024#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0 x2028#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0 x202c#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0 x2030#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0 x2034#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0 x2038#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0 x203c#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0 x2040#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0 x201c#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0 x2020#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0 x2044#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0 x2048#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0 x2058#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0 x205c#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0 x2060#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0 x2064#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0 x2068#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0 x206c#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0 x2070#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0 x2074#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0 x204c#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0 x2050static const unsigned long peric0_clk_regs[] __initconst = {/* List of parent clocks for Muxes in CMU_PERIC0 */ "oscclk" , "dout_clkcmu_peric0_bus" };"oscclk" , "dout_clkcmu_peric0_ip" };"oscclk" , "mout_peric0_ip_user" };static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {"mout_peric0_bus_user" ,4 , 1 ),"mout_peric0_ip_user" ,4 , 1 ),/* USI00 ~ USI05 */ "mout_peric0_usi00_usi" ,0 , 1 ),"mout_peric0_usi01_usi" ,0 , 1 ),"mout_peric0_usi02_usi" ,0 , 1 ),"mout_peric0_usi03_usi" ,0 , 1 ),"mout_peric0_usi04_usi" ,0 , 1 ),"mout_peric0_usi05_usi" ,0 , 1 ),/* USI_I2C */ "mout_peric0_usi_i2c" ,0 , 1 ),static const struct samsung_div_clock peric0_div_clks[] __initconst = {/* USI00 ~ USI05 */ "dout_peric0_usi00_usi" ,"mout_peric0_usi00_usi" , CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,0 , 4 ),"dout_peric0_usi01_usi" ,"mout_peric0_usi01_usi" , CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,0 , 4 ),"dout_peric0_usi02_usi" ,"mout_peric0_usi02_usi" , CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,0 , 4 ),"dout_peric0_usi03_usi" ,"mout_peric0_usi03_usi" , CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,0 , 4 ),"dout_peric0_usi04_usi" ,"mout_peric0_usi04_usi" , CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,0 , 4 ),"dout_peric0_usi05_usi" ,"mout_peric0_usi05_usi" , CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,0 , 4 ),/* USI_I2C */ "dout_peric0_usi_i2c" ,"mout_peric0_usi_i2c" , CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0 , 4 ),static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {/* IPCLK */ "gout_peric0_ipclk_0" ,"dout_peric0_usi00_usi" ,21 , 0 , 0 ),"gout_peric0_ipclk_1" ,"dout_peric0_usi_i2c" ,21 , 0 , 0 ),"gout_peric0_ipclk_2" ,"dout_peric0_usi01_usi" ,21 , 0 , 0 ),"gout_peric0_ipclk_3" ,"dout_peric0_usi_i2c" ,21 , 0 , 0 ),"gout_peric0_ipclk_4" ,"dout_peric0_usi02_usi" ,21 , 0 , 0 ),"gout_peric0_ipclk_5" ,"dout_peric0_usi_i2c" ,21 , 0 , 0 ),"gout_peric0_ipclk_6" ,"dout_peric0_usi03_usi" ,21 , 0 , 0 ),"gout_peric0_ipclk_7" ,"dout_peric0_usi_i2c" ,21 , 0 , 0 ),"gout_peric0_ipclk_8" ,"dout_peric0_usi04_usi" ,21 , 0 , 0 ),"gout_peric0_ipclk_9" ,"dout_peric0_usi_i2c" ,21 , 0 , 0 ),"gout_peric0_ipclk_10" ,"dout_peric0_usi05_usi" ,21 , 0 , 0 ),"gout_peric0_ipclk_11" ,"dout_peric0_usi_i2c" ,21 , 0 , 0 ),/* PCLK */ "gout_peric0_pclk_0" ,"mout_peric0_bus_user" ,21 , 0 , 0 ),"gout_peric0_pclk_1" ,"mout_peric0_bus_user" ,21 , 0 , 0 ),"gout_peric0_pclk_2" ,"mout_peric0_bus_user" ,21 , 0 , 0 ),"gout_peric0_pclk_3" ,"mout_peric0_bus_user" ,21 , 0 , 0 ),"gout_peric0_pclk_4" ,"mout_peric0_bus_user" ,21 , 0 , 0 ),"gout_peric0_pclk_5" ,"mout_peric0_bus_user" ,21 , 0 , 0 ),"gout_peric0_pclk_6" ,"mout_peric0_bus_user" ,21 , 0 , 0 ),"gout_peric0_pclk_7" ,"mout_peric0_bus_user" ,21 , 0 , 0 ),"gout_peric0_pclk_8" ,"mout_peric0_bus_user" ,21 , 0 , 0 ),"gout_peric0_pclk_9" ,"mout_peric0_bus_user" ,21 , 0 , 0 ),"gout_peric0_pclk_10" ,"mout_peric0_bus_user" ,21 , 0 , 0 ),"gout_peric0_pclk_11" ,"mout_peric0_bus_user" ,21 , 0 , 0 ),static const struct samsung_cmu_info peric0_cmu_info __initconst = {"dout_clkcmu_peric0_bus" ,/* ---- CMU_PERIC1 --------------------------------------------------------- */ /* Register Offset definitions for CMU_PERIC1 (0x10800000) */ #define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0 x0600#define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER 0 x0610#define CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI 0 x1000#define CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI 0 x1004#define CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI 0 x1008#define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI 0 x100c#define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI 0 x1010#define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI 0 x1014#define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C 0 x1018#define CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI 0 x1800#define CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI 0 x1804#define CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI 0 x1808#define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0 x180c#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0 x1810#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0 x1814#define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0 x1818#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0 0 x2014#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0 x2018#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0 x2024#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0 x2028#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0 x202c#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0 x2030#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0 x2034#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7 0 x2038#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0 x203c#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9 0 x2040#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10 0 x201c#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11 0 x2020#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0 0 x2044#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0 x2048#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0 x2054#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0 x2058#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0 x205c#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0 x2060#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0 x2064#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7 0 x2068#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0 x206c#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9 0 x2070#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10 0 x204c#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11 0 x2050static const unsigned long peric1_clk_regs[] __initconst = {/* List of parent clocks for Muxes in CMU_PERIC1 */ "oscclk" , "dout_clkcmu_peric1_bus" };"oscclk" , "dout_clkcmu_peric1_ip" };"oscclk" , "mout_peric1_ip_user" };static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {"mout_peric1_bus_user" ,4 , 1 ),"mout_peric1_ip_user" ,4 , 1 ),/* USI06 ~ USI11 */ "mout_peric1_usi06_usi" ,0 , 1 ),"mout_peric1_usi07_usi" ,0 , 1 ),"mout_peric1_usi08_usi" ,0 , 1 ),"mout_peric1_usi09_usi" ,0 , 1 ),"mout_peric1_usi10_usi" ,0 , 1 ),"mout_peric1_usi11_usi" ,0 , 1 ),/* USI_I2C */ "mout_peric1_usi_i2c" ,0 , 1 ),static const struct samsung_div_clock peric1_div_clks[] __initconst = {/* USI06 ~ USI11 */ "dout_peric1_usi06_usi" ,"mout_peric1_usi06_usi" , CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI,0 , 4 ),"dout_peric1_usi07_usi" ,"mout_peric1_usi07_usi" , CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI,0 , 4 ),"dout_peric1_usi08_usi" ,"mout_peric1_usi08_usi" , CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI,0 , 4 ),"dout_peric1_usi09_usi" ,"mout_peric1_usi09_usi" , CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,0 , 4 ),"dout_peric1_usi10_usi" ,"mout_peric1_usi10_usi" , CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,0 , 4 ),"dout_peric1_usi11_usi" ,"mout_peric1_usi11_usi" , CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,0 , 4 ),/* USI_I2C */ "dout_peric1_usi_i2c" ,"mout_peric1_usi_i2c" , CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0 , 4 ),static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {/* IPCLK */ "gout_peric1_ipclk_0" ,"dout_peric1_usi06_usi" ,21 , 0 , 0 ),"gout_peric1_ipclk_1" ,"dout_peric1_usi_i2c" ,21 , 0 , 0 ),"gout_peric1_ipclk_2" ,"dout_peric1_usi07_usi" ,21 , 0 , 0 ),"gout_peric1_ipclk_3" ,"dout_peric1_usi_i2c" ,21 , 0 , 0 ),"gout_peric1_ipclk_4" ,"dout_peric1_usi08_usi" ,21 , 0 , 0 ),"gout_peric1_ipclk_5" ,"dout_peric1_usi_i2c" ,21 , 0 , 0 ),"gout_peric1_ipclk_6" ,"dout_peric1_usi09_usi" ,21 , 0 , 0 ),"gout_peric1_ipclk_7" ,"dout_peric1_usi_i2c" ,21 , 0 , 0 ),"gout_peric1_ipclk_8" ,"dout_peric1_usi10_usi" ,21 , 0 , 0 ),"gout_peric1_ipclk_9" ,"dout_peric1_usi_i2c" ,21 , 0 , 0 ),"gout_peric1_ipclk_10" ,"dout_peric1_usi11_usi" ,21 , 0 , 0 ),"gout_peric1_ipclk_11" ,"dout_peric1_usi_i2c" ,21 , 0 , 0 ),/* PCLK */ "gout_peric1_pclk_0" ,"mout_peric1_bus_user" ,21 , 0 , 0 ),"gout_peric1_pclk_1" ,"mout_peric1_bus_user" ,21 , 0 , 0 ),"gout_peric1_pclk_2" ,"mout_peric1_bus_user" ,21 , 0 , 0 ),"gout_peric1_pclk_3" ,"mout_peric1_bus_user" ,21 , 0 , 0 ),"gout_peric1_pclk_4" ,"mout_peric1_bus_user" ,21 , 0 , 0 ),"gout_peric1_pclk_5" ,"mout_peric1_bus_user" ,21 , 0 , 0 ),"gout_peric1_pclk_6" ,"mout_peric1_bus_user" ,21 , 0 , 0 ),"gout_peric1_pclk_7" ,"mout_peric1_bus_user" ,21 , 0 , 0 ),"gout_peric1_pclk_8" ,"mout_peric1_bus_user" ,21 , 0 , 0 ),"gout_peric1_pclk_9" ,"mout_peric1_bus_user" ,21 , 0 , 0 ),"gout_peric1_pclk_10" ,"mout_peric1_bus_user" ,21 , 0 , 0 ),"gout_peric1_pclk_11" ,"mout_peric1_bus_user" ,21 , 0 , 0 ),static const struct samsung_cmu_info peric1_cmu_info __initconst = {"dout_clkcmu_peric1_bus" ,/* ---- CMU_PERIS ---------------------------------------------------------- */ /* Register Offset definitions for CMU_PERIS (0x10020000) */ #define PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER 0 x0600#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK 0 x2058#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0 x205c#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0 x2060static const unsigned long peris_clk_regs[] __initconst = {/* List of parent clocks for Muxes in CMU_PERIS */ "oscclk" , "dout_clkcmu_peris_bus" };static const struct samsung_mux_clock peris_mux_clks[] __initconst = {"mout_peris_bus_user" ,4 , 1 ),static const struct samsung_gate_clock peris_gate_clks[] __initconst = {"gout_sysreg_peris_pclk" ,"mout_peris_bus_user" ,21 , CLK_IGNORE_UNUSED, 0 ),"gout_wdt_cluster0" , "mout_peris_bus_user" ,21 , 0 , 0 ),"gout_wdt_cluster1" , "mout_peris_bus_user" ,21 , 0 , 0 ),static const struct samsung_cmu_info peris_cmu_info __initconst = {"dout_clkcmu_peris_bus" ,static int __init exynosautov9_cmu_probe(struct platform_device *pdev)const struct samsung_cmu_info *info;struct device *dev = &pdev->dev;return 0 ;static const struct of_device_id exynosautov9_cmu_of_match[] = {"samsung,exynosautov9-cmu-busmc" ,"samsung,exynosautov9-cmu-core" ,"samsung,exynosautov9-cmu-dpum" ,"samsung,exynosautov9-cmu-fsys0" ,"samsung,exynosautov9-cmu-fsys1" ,"samsung,exynosautov9-cmu-fsys2" ,"samsung,exynosautov9-cmu-peric0" ,"samsung,exynosautov9-cmu-peric1" ,"samsung,exynosautov9-cmu-peris" ,static struct platform_driver exynosautov9_cmu_driver __refdata = {"exynosautov9-cmu" ,true ,static int __init exynosautov9_cmu_init(void )return platform_driver_register(&exynosautov9_cmu_driver);
Messung V0.5 in Prozent C=96 H=98 G=96
¤ Dauer der Verarbeitung: 0.29 Sekunden
(vorverarbeitet am 2026-10-11)
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