// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013 Samsung Electronics Co., Ltd. * Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com> * * Based on clock drivers for S3C64xx and Exynos4 SoCs. * * Common Clock Framework support for all S5PC110/S5PV210 SoCs. #include <linux/clk-provider.h>#include <linux/of_address.h>#include "clk.h" #include "clk-pll.h" #include <dt-bindings/clock/s5pv210.h>/* S5PC110/S5PV210 clock controller register offsets */ #define APLL_LOCK 0x0000#define MPLL_LOCK 0x0008#define EPLL_LOCK 0x0010#define VPLL_LOCK 0x0020#define APLL_CON0 0x0100#define APLL_CON1 0x0104#define MPLL_CON 0x0108#define EPLL_CON0 0x0110#define EPLL_CON1 0x0114#define VPLL_CON 0x0120#define CLK_SRC0 0x0200#define CLK_SRC1 0x0204#define CLK_SRC2 0x0208#define CLK_SRC3 0x020c#define CLK_SRC4 0x0210#define CLK_SRC5 0x0214#define CLK_SRC6 0x0218#define CLK_SRC_MASK0 0x0280#define CLK_SRC_MASK1 0x0284#define CLK_DIV0 0x0300#define CLK_DIV1 0x0304#define CLK_DIV2 0x0308#define CLK_DIV3 0x030c#define CLK_DIV4 0x0310#define CLK_DIV5 0x0314#define CLK_DIV6 0x0318#define CLK_DIV7 0x031c#define CLK_GATE_MAIN0 0x0400#define CLK_GATE_MAIN1 0x0404#define CLK_GATE_MAIN2 0x0408#define CLK_GATE_PERI0 0x0420#define CLK_GATE_PERI1 0x0424#define CLK_GATE_SCLK0 0x0440#define CLK_GATE_SCLK1 0x0444#define CLK_GATE_IP0 0x0460#define CLK_GATE_IP1 0x0464#define CLK_GATE_IP2 0x0468#define CLK_GATE_IP3 0x046c#define CLK_GATE_IP4 0x0470#define CLK_GATE_BLOCK 0x0480#define CLK_GATE_IP5 0x0484#define CLK_OUT 0x0500#define MISC 0xe000#define OM_STAT 0xe100/* IDs of PLLs available on S5PV210/S5P6442 SoCs */ enum {/* IDs of external clocks (used for legacy boards) */ enum {static void __iomem *reg_base;/* List of registers that need to be preserved across suspend/resume. */ static unsigned long s5pv210_clk_regs[] __initdata = {/* Mux parent lists. */ static const char *const fin_pll_p[] __initconst = {"xxti" ,"xusbxti" static const char *const mout_apll_p[] __initconst = {"fin_pll" ,"fout_apll" static const char *const mout_mpll_p[] __initconst = {"fin_pll" ,"fout_mpll" static const char *const mout_epll_p[] __initconst = {"fin_pll" ,"fout_epll" static const char *const mout_vpllsrc_p[] __initconst = {"fin_pll" ,"sclk_hdmi27m" static const char *const mout_vpll_p[] __initconst = {"mout_vpllsrc" ,"fout_vpll" static const char *const mout_group1_p[] __initconst = {"dout_a2m" ,"mout_mpll" ,"mout_epll" ,"mout_vpll" static const char *const mout_group2_p[] __initconst = {"xxti" ,"xusbxti" ,"sclk_hdmi27m" ,"sclk_usbphy0" ,"sclk_usbphy1" ,"sclk_hdmiphy" ,"mout_mpll" ,"mout_epll" ,"mout_vpll" ,static const char *const mout_audio0_p[] __initconst = {"xxti" ,"pcmcdclk0" ,"sclk_hdmi27m" ,"sclk_usbphy0" ,"sclk_usbphy1" ,"sclk_hdmiphy" ,"mout_mpll" ,"mout_epll" ,"mout_vpll" ,static const char *const mout_audio1_p[] __initconst = {"i2scdclk1" ,"pcmcdclk1" ,"sclk_hdmi27m" ,"sclk_usbphy0" ,"sclk_usbphy1" ,"sclk_hdmiphy" ,"mout_mpll" ,"mout_epll" ,"mout_vpll" ,static const char *const mout_audio2_p[] __initconst = {"i2scdclk2" ,"pcmcdclk2" ,"sclk_hdmi27m" ,"sclk_usbphy0" ,"sclk_usbphy1" ,"sclk_hdmiphy" ,"mout_mpll" ,"mout_epll" ,"mout_vpll" ,static const char *const mout_spdif_p[] __initconst = {"dout_audio0" ,"dout_audio1" ,"dout_audio3" ,static const char *const mout_group3_p[] __initconst = {"mout_apll" ,"mout_mpll" static const char *const mout_group4_p[] __initconst = {"mout_mpll" ,"dout_a2m" static const char *const mout_flash_p[] __initconst = {"dout_hclkd" ,"dout_hclkp" static const char *const mout_dac_p[] __initconst = {"mout_vpll" ,"sclk_hdmiphy" static const char *const mout_hdmi_p[] __initconst = {"sclk_hdmiphy" ,"dout_tblk" static const char *const mout_mixer_p[] __initconst = {"mout_dac" ,"mout_hdmi" static const char *const mout_vpll_6442_p[] __initconst = {"fin_pll" ,"fout_vpll" static const char *const mout_mixer_6442_p[] __initconst = {"mout_vpll" ,"dout_mixer" static const char *const mout_d0sync_6442_p[] __initconst = {"mout_dsys" ,"div_apll" static const char *const mout_d1sync_6442_p[] __initconst = {"mout_psys" ,"div_apll" static const char *const mout_group2_6442_p[] __initconst = {"fin_pll" ,"none" ,"none" ,"sclk_usbphy0" ,"none" ,"none" ,"mout_mpll" ,"mout_epll" ,"mout_vpll" ,static const char *const mout_audio0_6442_p[] __initconst = {"fin_pll" ,"pcmcdclk0" ,"none" ,"sclk_usbphy0" ,"none" ,"none" ,"mout_mpll" ,"mout_epll" ,"mout_vpll" ,static const char *const mout_audio1_6442_p[] __initconst = {"i2scdclk1" ,"pcmcdclk1" ,"none" ,"sclk_usbphy0" ,"none" ,"none" ,"mout_mpll" ,"mout_epll" ,"mout_vpll" ,"fin_pll" ,static const char *const mout_clksel_p[] __initconst = {"fout_apll_clkout" ,"fout_mpll_clkout" ,"fout_epll" ,"fout_vpll" ,"sclk_usbphy0" ,"sclk_usbphy1" ,"sclk_hdmiphy" ,"rtc" ,"rtc_tick" ,"dout_hclkm" ,"dout_pclkm" ,"dout_hclkd" ,"dout_pclkd" ,"dout_hclkp" ,"dout_pclkp" ,"dout_apll_clkout" ,"dout_hpm" ,"xxti" ,"xusbxti" ,"div_dclk" static const char *const mout_clksel_6442_p[] __initconst = {"fout_apll_clkout" ,"fout_mpll_clkout" ,"fout_epll" ,"fout_vpll" ,"sclk_usbphy0" ,"none" ,"none" ,"rtc" ,"rtc_tick" ,"none" ,"none" ,"dout_hclkd" ,"dout_pclkd" ,"dout_hclkp" ,"dout_pclkp" ,"dout_apll_clkout" ,"none" ,"fin_pll" ,"none" ,"div_dclk" static const char *const mout_clkout_p[] __initconst = {"dout_clkout" ,"none" ,"xxti" ,"xusbxti" /* Common fixed factor clocks. */ static const struct samsung_fixed_factor_clock ffactor_clks[] __initconst = {"fout_apll_clkout" , "fout_apll" , 1, 4, 0),"fout_mpll_clkout" , "fout_mpll" , 1, 2, 0),"dout_apll_clkout" , "dout_apll" , 1, 4, 0),/* PLL input mux (fin_pll), which needs to be registered before PLLs. */ static const struct samsung_mux_clock early_mux_clks[] __initconst = {"fin_pll" , fin_pll_p, OM_STAT, 0, 1,/* Common clock muxes. */ static const struct samsung_mux_clock mux_clks[] __initconst = {"mout_flash" , mout_flash_p, CLK_SRC0, 28, 1),"mout_psys" , mout_group4_p, CLK_SRC0, 24, 1),"mout_dsys" , mout_group4_p, CLK_SRC0, 20, 1),"mout_msys" , mout_group3_p, CLK_SRC0, 16, 1),"mout_epll" , mout_epll_p, CLK_SRC0, 8, 1),"mout_mpll" , mout_mpll_p, CLK_SRC0, 4, 1),"mout_apll" , mout_apll_p, CLK_SRC0, 0, 1),"mout_clkout" , mout_clkout_p, MISC, 8, 2),/* S5PV210-specific clock muxes. */ static const struct samsung_mux_clock s5pv210_mux_clks[] __initconst = {"mout_vpll" , mout_vpll_p, CLK_SRC0, 12, 1),"mout_vpllsrc" , mout_vpllsrc_p, CLK_SRC1, 28, 1),"mout_csis" , mout_group2_p, CLK_SRC1, 24, 4),"mout_fimd" , mout_group2_p, CLK_SRC1, 20, 4),"mout_cam1" , mout_group2_p, CLK_SRC1, 16, 4),"mout_cam0" , mout_group2_p, CLK_SRC1, 12, 4),"mout_dac" , mout_dac_p, CLK_SRC1, 8, 1),"mout_mixer" , mout_mixer_p, CLK_SRC1, 4, 1),"mout_hdmi" , mout_hdmi_p, CLK_SRC1, 0, 1),"mout_g2d" , mout_group1_p, CLK_SRC2, 8, 2),"mout_mfc" , mout_group1_p, CLK_SRC2, 4, 2),"mout_g3d" , mout_group1_p, CLK_SRC2, 0, 2),"mout_fimc2" , mout_group2_p, CLK_SRC3, 20, 4),"mout_fimc1" , mout_group2_p, CLK_SRC3, 16, 4),"mout_fimc0" , mout_group2_p, CLK_SRC3, 12, 4),"mout_uart3" , mout_group2_p, CLK_SRC4, 28, 4),"mout_uart2" , mout_group2_p, CLK_SRC4, 24, 4),"mout_uart1" , mout_group2_p, CLK_SRC4, 20, 4),"mout_uart0" , mout_group2_p, CLK_SRC4, 16, 4),"mout_mmc3" , mout_group2_p, CLK_SRC4, 12, 4),"mout_mmc2" , mout_group2_p, CLK_SRC4, 8, 4),"mout_mmc1" , mout_group2_p, CLK_SRC4, 4, 4),"mout_mmc0" , mout_group2_p, CLK_SRC4, 0, 4),"mout_pwm" , mout_group2_p, CLK_SRC5, 12, 4),"mout_spi1" , mout_group2_p, CLK_SRC5, 4, 4),"mout_spi0" , mout_group2_p, CLK_SRC5, 0, 4),"mout_dmc0" , mout_group1_p, CLK_SRC6, 24, 2),"mout_pwi" , mout_group2_p, CLK_SRC6, 20, 4),"mout_hpm" , mout_group3_p, CLK_SRC6, 16, 1),"mout_spdif" , mout_spdif_p, CLK_SRC6, 12, 2),"mout_audio2" , mout_audio2_p, CLK_SRC6, 8, 4),"mout_audio1" , mout_audio1_p, CLK_SRC6, 4, 4),"mout_audio0" , mout_audio0_p, CLK_SRC6, 0, 4),"mout_clksel" , mout_clksel_p, CLK_OUT, 12, 5),/* S5P6442-specific clock muxes. */ static const struct samsung_mux_clock s5p6442_mux_clks[] __initconst = {"mout_vpll" , mout_vpll_6442_p, CLK_SRC0, 12, 1),"mout_fimd" , mout_group2_6442_p, CLK_SRC1, 20, 4),"mout_cam1" , mout_group2_6442_p, CLK_SRC1, 16, 4),"mout_cam0" , mout_group2_6442_p, CLK_SRC1, 12, 4),"mout_mixer" , mout_mixer_6442_p, CLK_SRC1, 4, 1),"mout_d0sync" , mout_d0sync_6442_p, CLK_SRC2, 28, 1),"mout_d1sync" , mout_d1sync_6442_p, CLK_SRC2, 24, 1),"mout_fimc2" , mout_group2_6442_p, CLK_SRC3, 20, 4),"mout_fimc1" , mout_group2_6442_p, CLK_SRC3, 16, 4),"mout_fimc0" , mout_group2_6442_p, CLK_SRC3, 12, 4),"mout_uart2" , mout_group2_6442_p, CLK_SRC4, 24, 4),"mout_uart1" , mout_group2_6442_p, CLK_SRC4, 20, 4),"mout_uart0" , mout_group2_6442_p, CLK_SRC4, 16, 4),"mout_mmc2" , mout_group2_6442_p, CLK_SRC4, 8, 4),"mout_mmc1" , mout_group2_6442_p, CLK_SRC4, 4, 4),"mout_mmc0" , mout_group2_6442_p, CLK_SRC4, 0, 4),"mout_pwm" , mout_group2_6442_p, CLK_SRC5, 12, 4),"mout_spi0" , mout_group2_6442_p, CLK_SRC5, 0, 4),"mout_audio1" , mout_audio1_6442_p, CLK_SRC6, 4, 4),"mout_audio0" , mout_audio0_6442_p, CLK_SRC6, 0, 4),"mout_clksel" , mout_clksel_6442_p, CLK_OUT, 12, 5),/* S5PV210-specific fixed rate clocks generated inside the SoC. */ static const struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initconst = {"sclk_hdmi27m" , NULL, 0, 27000000),"sclk_hdmiphy" , NULL, 0, 27000000),"sclk_usbphy0" , NULL, 0, 48000000),"sclk_usbphy1" , NULL, 0, 48000000),/* S5P6442-specific fixed rate clocks generated inside the SoC. */ static const struct samsung_fixed_rate_clock s5p6442_frate_clks[] __initconst = {"sclk_usbphy0" , NULL, 0, 30000000),/* Common clock dividers. */ static const struct samsung_div_clock div_clks[] __initconst = {"dout_pclkp" , "dout_hclkp" , CLK_DIV0, 28, 3),"dout_pclkd" , "dout_hclkd" , CLK_DIV0, 20, 3),"dout_a2m" , "mout_apll" , CLK_DIV0, 4, 3),"dout_apll" , "mout_msys" , CLK_DIV0, 0, 3),"dout_fimd" , "mout_fimd" , CLK_DIV1, 20, 4),"dout_cam1" , "mout_cam1" , CLK_DIV1, 16, 4),"dout_cam0" , "mout_cam0" , CLK_DIV1, 12, 4),"dout_fimc2" , "mout_fimc2" , CLK_DIV3, 20, 4),"dout_fimc1" , "mout_fimc1" , CLK_DIV3, 16, 4),"dout_fimc0" , "mout_fimc0" , CLK_DIV3, 12, 4),"dout_uart2" , "mout_uart2" , CLK_DIV4, 24, 4),"dout_uart1" , "mout_uart1" , CLK_DIV4, 20, 4),"dout_uart0" , "mout_uart0" , CLK_DIV4, 16, 4),"dout_mmc2" , "mout_mmc2" , CLK_DIV4, 8, 4),"dout_mmc1" , "mout_mmc1" , CLK_DIV4, 4, 4),"dout_mmc0" , "mout_mmc0" , CLK_DIV4, 0, 4),"dout_pwm" , "mout_pwm" , CLK_DIV5, 12, 4),"dout_spi0" , "mout_spi0" , CLK_DIV5, 0, 4),"dout_flash" , "mout_flash" , CLK_DIV6, 12, 3),"dout_audio1" , "mout_audio1" , CLK_DIV6, 4, 4),"dout_audio0" , "mout_audio0" , CLK_DIV6, 0, 4),"dout_clkout" , "mout_clksel" , CLK_OUT, 20, 4),/* S5PV210-specific clock dividers. */ static const struct samsung_div_clock s5pv210_div_clks[] __initconst = {"dout_hclkp" , "mout_psys" , CLK_DIV0, 24, 4),"dout_hclkd" , "mout_dsys" , CLK_DIV0, 16, 4),"dout_pclkm" , "dout_hclkm" , CLK_DIV0, 12, 3),"dout_hclkm" , "dout_apll" , CLK_DIV0, 8, 3),"dout_csis" , "mout_csis" , CLK_DIV1, 28, 4),"dout_tblk" , "mout_vpll" , CLK_DIV1, 0, 4),"dout_g2d" , "mout_g2d" , CLK_DIV2, 8, 4),"dout_mfc" , "mout_mfc" , CLK_DIV2, 4, 4),"dout_g3d" , "mout_g3d" , CLK_DIV2, 0, 4),"dout_uart3" , "mout_uart3" , CLK_DIV4, 28, 4),"dout_mmc3" , "mout_mmc3" , CLK_DIV4, 12, 4),"dout_spi1" , "mout_spi1" , CLK_DIV5, 4, 4),"dout_dmc0" , "mout_dmc0" , CLK_DIV6, 28, 4),"dout_pwi" , "mout_pwi" , CLK_DIV6, 24, 4),"dout_hpm" , "dout_copy" , CLK_DIV6, 20, 3),"dout_copy" , "mout_hpm" , CLK_DIV6, 16, 3),"dout_audio2" , "mout_audio2" , CLK_DIV6, 8, 4),"dout_dpm" , "dout_pclkp" , CLK_DIV7, 8, 7),"dout_dvsem" , "dout_pclkp" , CLK_DIV7, 0, 7),/* S5P6442-specific clock dividers. */ static const struct samsung_div_clock s5p6442_div_clks[] __initconst = {"dout_hclkp" , "mout_d1sync" , CLK_DIV0, 24, 4),"dout_hclkd" , "mout_d0sync" , CLK_DIV0, 16, 4),"dout_mixer" , "mout_vpll" , CLK_DIV1, 0, 4),/* Common clock gates. */ static const struct samsung_gate_clock gate_clks[] __initconst = {"rotator" , "dout_hclkd" , CLK_GATE_IP0, 29, 0, 0),"fimc2" , "dout_hclkd" , CLK_GATE_IP0, 26, 0, 0),"fimc1" , "dout_hclkd" , CLK_GATE_IP0, 25, 0, 0),"fimc0" , "dout_hclkd" , CLK_GATE_IP0, 24, 0, 0),"pdma0" , "dout_hclkp" , CLK_GATE_IP0, 3, 0, 0),"mdma" , "dout_hclkd" , CLK_GATE_IP0, 2, 0, 0),"sromc" , "dout_hclkp" , CLK_GATE_IP1, 26, 0, 0),"nandxl" , "dout_hclkp" , CLK_GATE_IP1, 24, 0, 0),"usb_otg" , "dout_hclkp" , CLK_GATE_IP1, 16, 0, 0),"tvenc" , "dout_hclkd" , CLK_GATE_IP1, 10, 0, 0),"mixer" , "dout_hclkd" , CLK_GATE_IP1, 9, 0, 0),"vp" , "dout_hclkd" , CLK_GATE_IP1, 8, 0, 0),"fimd" , "dout_hclkd" , CLK_GATE_IP1, 0, 0, 0),"hsmmc2" , "dout_hclkp" , CLK_GATE_IP2, 18, 0, 0),"hsmmc1" , "dout_hclkp" , CLK_GATE_IP2, 17, 0, 0),"hsmmc0" , "dout_hclkp" , CLK_GATE_IP2, 16, 0, 0),"modemif" , "dout_hclkp" , CLK_GATE_IP2, 9, 0, 0),"secss" , "dout_hclkp" , CLK_GATE_IP2, 0, 0, 0),"pcm1" , "dout_pclkp" , CLK_GATE_IP3, 29, 0, 0),"pcm0" , "dout_pclkp" , CLK_GATE_IP3, 28, 0, 0),"tsadc" , "dout_pclkp" , CLK_GATE_IP3, 24, 0, 0),"pwm" , "dout_pclkp" , CLK_GATE_IP3, 23, 0, 0),"watchdog" , "dout_pclkp" , CLK_GATE_IP3, 22, 0, 0),"keyif" , "dout_pclkp" , CLK_GATE_IP3, 21, 0, 0),"uart2" , "dout_pclkp" , CLK_GATE_IP3, 19, 0, 0),"uart1" , "dout_pclkp" , CLK_GATE_IP3, 18, 0, 0),"uart0" , "dout_pclkp" , CLK_GATE_IP3, 17, 0, 0),"systimer" , "dout_pclkp" , CLK_GATE_IP3, 16, 0, 0),"rtc" , "dout_pclkp" , CLK_GATE_IP3, 15, 0, 0),"spi0" , "dout_pclkp" , CLK_GATE_IP3, 12, 0, 0),"i2c2" , "dout_pclkp" , CLK_GATE_IP3, 9, 0, 0),"i2c0" , "dout_pclkp" , CLK_GATE_IP3, 7, 0, 0),"i2s1" , "dout_pclkp" , CLK_GATE_IP3, 5, 0, 0),"i2s0" , "dout_pclkp" , CLK_GATE_IP3, 4, 0, 0),"seckey" , "dout_pclkp" , CLK_GATE_IP4, 3, 0, 0),"chipid" , "dout_pclkp" , CLK_GATE_IP4, 0, 0, 0),"sclk_audio1" , "dout_audio1" , CLK_SRC_MASK0, 25,"sclk_audio0" , "dout_audio0" , CLK_SRC_MASK0, 24,"sclk_pwm" , "dout_pwm" , CLK_SRC_MASK0, 19,"sclk_spi0" , "dout_spi0" , CLK_SRC_MASK0, 16,"sclk_uart2" , "dout_uart2" , CLK_SRC_MASK0, 14,"sclk_uart1" , "dout_uart1" , CLK_SRC_MASK0, 13,"sclk_uart0" , "dout_uart0" , CLK_SRC_MASK0, 12,"sclk_mmc2" , "dout_mmc2" , CLK_SRC_MASK0, 10,"sclk_mmc1" , "dout_mmc1" , CLK_SRC_MASK0, 9,"sclk_mmc0" , "dout_mmc0" , CLK_SRC_MASK0, 8,"sclk_fimd" , "dout_fimd" , CLK_SRC_MASK0, 5,"sclk_cam1" , "dout_cam1" , CLK_SRC_MASK0, 4,"sclk_cam0" , "dout_cam0" , CLK_SRC_MASK0, 3,"sclk_mixer" , "mout_mixer" , CLK_SRC_MASK0, 1,"sclk_fimc2" , "dout_fimc2" , CLK_SRC_MASK1, 4,"sclk_fimc1" , "dout_fimc1" , CLK_SRC_MASK1, 3,"sclk_fimc0" , "dout_fimc0" , CLK_SRC_MASK1, 2,/* S5PV210-specific clock gates. */ static const struct samsung_gate_clock s5pv210_gate_clks[] __initconst = {"clk_csis" , "dout_hclkd" , CLK_GATE_IP0, 31, 0, 0),"mfc" , "dout_hclkm" , CLK_GATE_IP0, 16, 0, 0),"g2d" , "dout_hclkd" , CLK_GATE_IP0, 12, 0, 0),"g3d" , "dout_hclkm" , CLK_GATE_IP0, 8, 0, 0),"imem" , "dout_hclkm" , CLK_GATE_IP0, 5, 0, 0),"pdma1" , "dout_hclkp" , CLK_GATE_IP0, 4, 0, 0),"nfcon" , "dout_hclkp" , CLK_GATE_IP1, 28, 0, 0),"cfcon" , "dout_hclkp" , CLK_GATE_IP1, 25, 0, 0),"usb_host" , "dout_hclkp" , CLK_GATE_IP1, 17, 0, 0),"hdmi" , "dout_hclkd" , CLK_GATE_IP1, 11, 0, 0),"dsim" , "dout_pclkd" , CLK_GATE_IP1, 2, 0, 0),"tzic3" , "dout_hclkm" , CLK_GATE_IP2, 31, 0, 0),"tzic2" , "dout_hclkm" , CLK_GATE_IP2, 30, 0, 0),"tzic1" , "dout_hclkm" , CLK_GATE_IP2, 29, 0, 0),"tzic0" , "dout_hclkm" , CLK_GATE_IP2, 28, 0, 0),"tsi" , "dout_hclkd" , CLK_GATE_IP2, 20, 0, 0),"hsmmc3" , "dout_hclkp" , CLK_GATE_IP2, 19, 0, 0),"jtag" , "dout_hclkp" , CLK_GATE_IP2, 11, 0, 0),"coresight" , "dout_pclkp" , CLK_GATE_IP2, 8, 0, 0),"sdm" , "dout_pclkm" , CLK_GATE_IP2, 1, 0, 0),"pcm2" , "dout_pclkp" , CLK_GATE_IP3, 30, 0, 0),"uart3" , "dout_pclkp" , CLK_GATE_IP3, 20, 0, 0),"spi1" , "dout_pclkp" , CLK_GATE_IP3, 13, 0, 0),"i2c_hdmi_phy" , "dout_pclkd" ,"i2c1" , "dout_pclkd" , CLK_GATE_IP3, 10, 0, 0),"i2s2" , "dout_pclkp" , CLK_GATE_IP3, 6, 0, 0),"ac97" , "dout_pclkp" , CLK_GATE_IP3, 1, 0, 0),"spdif" , "dout_pclkp" , CLK_GATE_IP3, 0, 0, 0),"tzpc.3" , "dout_pclkd" , CLK_GATE_IP4, 8, 0, 0),"tzpc.2" , "dout_pclkd" , CLK_GATE_IP4, 7, 0, 0),"tzpc.1" , "dout_pclkp" , CLK_GATE_IP4, 6, 0, 0),"tzpc.0" , "dout_pclkm" , CLK_GATE_IP4, 5, 0, 0),"iem_apc" , "dout_pclkp" , CLK_GATE_IP4, 2, 0, 0),"iem_iec" , "dout_pclkp" , CLK_GATE_IP4, 1, 0, 0),"jpeg" , "dout_hclkd" , CLK_GATE_IP5, 29, 0, 0),"sclk_spdif" , "mout_spdif" , CLK_SRC_MASK0, 27,"sclk_audio2" , "dout_audio2" , CLK_SRC_MASK0, 26,"sclk_spi1" , "dout_spi1" , CLK_SRC_MASK0, 17,"sclk_uart3" , "dout_uart3" , CLK_SRC_MASK0, 15,"sclk_mmc3" , "dout_mmc3" , CLK_SRC_MASK0, 11,"sclk_csis" , "dout_csis" , CLK_SRC_MASK0, 6,"sclk_dac" , "mout_dac" , CLK_SRC_MASK0, 2,"sclk_hdmi" , "mout_hdmi" , CLK_SRC_MASK0, 0,/* S5P6442-specific clock gates. */ static const struct samsung_gate_clock s5p6442_gate_clks[] __initconst = {"jpeg" , "dout_hclkd" , CLK_GATE_IP0, 28, 0, 0),"mfc" , "dout_hclkd" , CLK_GATE_IP0, 16, 0, 0),"g2d" , "dout_hclkd" , CLK_GATE_IP0, 12, 0, 0),"g3d" , "dout_hclkd" , CLK_GATE_IP0, 8, 0, 0),"imem" , "dout_hclkd" , CLK_GATE_IP0, 5, 0, 0),"etb" , "dout_hclkd" , CLK_GATE_IP1, 31, 0, 0),"etm" , "dout_hclkd" , CLK_GATE_IP1, 30, 0, 0),"i2c1" , "dout_pclkp" , CLK_GATE_IP3, 8, 0, 0),"sclk_dac" , "mout_vpll" , CLK_SRC_MASK0, 2,/* * Clock aliases for legacy clkdev look-up. * NOTE: Needed only to support legacy board files. static const struct samsung_clock_alias s5pv210_aliases[] __initconst = {"armclk" ),"hclk_msys" ),"sclk_dmc0" ),/* S5PV210-specific PLLs. */ static const struct samsung_pll_clock s5pv210_pll_clks[] __initconst = {"fout_apll" , "fin_pll" ,"fout_mpll" , "fin_pll" ,"fout_epll" , "fin_pll" ,"fout_vpll" , "mout_vpllsrc" ,/* S5P6442-specific PLLs. */ static const struct samsung_pll_clock s5p6442_pll_clks[] __initconst = {"fout_apll" , "fin_pll" ,"fout_mpll" , "fin_pll" ,"fout_epll" , "fin_pll" ,"fout_vpll" , "fin_pll" ,static void __init __s5pv210_clk_init(struct device_node *np,unsigned long xxti_f,unsigned long xusbxti_f,bool is_s5p6442)struct samsung_clk_provider *ctx;struct clk_hw **hws;if (is_s5p6442) {else {"%s clocks: mout_apll = %ld, mout_mpll = %ld\n" "\tmout_epll = %ld, mout_vpll = %ld\n" ,"S5P6442" : "S5PV210" ,static void __init s5pv210_clk_dt_init(struct device_node *np)if (!reg_base)"%s: failed to map registers\n" , __func__);false );"samsung,s5pv210-clock" , s5pv210_clk_dt_init);static void __init s5p6442_clk_dt_init(struct device_node *np)if (!reg_base)"%s: failed to map registers\n" , __func__);true );"samsung,s5p6442-clock" , s5p6442_clk_dt_init);
Messung V0.5 C=96 H=95 G=95
