/* * Cavium ThunderX memory controller kernel module * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright Cavium, Inc. (C) 2015-2017. All rights reserved. * #include <linux/module.h>#include <linux/pci.h>#include <linux/edac.h>#include <linux/interrupt.h>#include <linux/string.h>#include <linux/stop_machine.h>#include <linux/delay.h>#include <linux/sizes.h>#include <linux/atomic.h>#include <linux/bitfield.h>#include <linux/circ_buf.h>#include <asm /page.h>#include "edac_module.h" #define phys_to_pfn(phys) (PFN_DOWN(phys))#define THUNDERX_NODE GENMASK(45, 44)enum {struct error_descr {int type;char *descr;static void decode_register(char *str, size_t size,const struct error_descr *descr,const uint64_t reg)int ret = 0;while (descr->type && descr->mask && descr->descr) {if (reg & descr->mask) {"\n\t%s, %s" ,"Corrected" : "Uncorrected" ,static unsigned long get_bits(unsigned long data, int pos, int width)return (data >> pos) & ((1 << width) - 1);#define L2C_CTL 0x87E080800000#define L2C_CTL_DISIDXALIAS BIT(0)#define PCI_DEVICE_ID_THUNDER_LMC 0xa022#define LMC_FADR 0x20#define LMC_FADR_FDIMM(x) ((x >> 37) & 0x1)#define LMC_FADR_FBUNK(x) ((x >> 36) & 0x1)#define LMC_FADR_FBANK(x) ((x >> 32) & 0xf)#define LMC_FADR_FROW(x) ((x >> 14) & 0xffff)#define LMC_FADR_FCOL(x) ((x >> 0) & 0x1fff)#define LMC_NXM_FADR 0x28#define LMC_ECC_SYND 0x38#define LMC_ECC_PARITY_TEST 0x108#define LMC_INT_W1S 0x150#define LMC_INT_ENA_W1C 0x158#define LMC_INT_ENA_W1S 0x160#define LMC_CONFIG 0x188#define LMC_CONFIG_BG2 BIT(62)#define LMC_CONFIG_RANK_ENA BIT(42)#define LMC_CONFIG_PBANK_LSB(x) (((x) >> 5) & 0xF)#define LMC_CONFIG_ROW_LSB(x) (((x) >> 2) & 0x7)#define LMC_CONTROL 0x190#define LMC_CONTROL_XOR_BANK BIT(16)#define LMC_INT 0x1F0#define LMC_INT_DDR_ERR BIT(11)#define LMC_INT_DED_ERR (0xFUL << 5)#define LMC_INT_SEC_ERR (0xFUL << 1)#define LMC_INT_NXM_WR_MASK BIT(0)#define LMC_DDR_PLL_CTL 0x258#define LMC_DDR_PLL_CTL_DDR4 BIT(29)#define LMC_FADR_SCRAMBLED 0x330#define LMC_INT_UE (LMC_INT_DDR_ERR | LMC_INT_DED_ERR | \#define LMC_INT_CE (LMC_INT_SEC_ERR)static const struct error_descr lmc_errors[] = {"Single-bit ECC error" ,"DDR chip error" ,"Double-bit ECC error" ,"Non-existent memory write" ,#define LMC_INT_EN_DDR_ERROR_ALERT_ENA BIT(5)#define LMC_INT_EN_DLCRAM_DED_ERR BIT(4)#define LMC_INT_EN_DLCRAM_SEC_ERR BIT(3)#define LMC_INT_INTR_DED_ENA BIT(2)#define LMC_INT_INTR_SEC_ENA BIT(1)#define LMC_INT_INTR_NXM_WR_ENA BIT(0)#define LMC_INT_ENA_ALL GENMASK(5, 0)#define LMC_DDR_PLL_CTL 0x258#define LMC_DDR_PLL_CTL_DDR4 BIT(29)#define LMC_CONTROL 0x190#define LMC_CONTROL_RDIMM BIT(0)#define LMC_SCRAM_FADR 0x330#define LMC_CHAR_MASK0 0x228#define LMC_CHAR_MASK2 0x238#define RING_ENTRIES 8struct debugfs_entry {const char *name;const struct file_operations fops;struct lmc_err_ctx {struct thunderx_lmc {void __iomem *regs;struct pci_dev *pdev;struct msix_entry msix_ent;int xbits;int bank_width;int pbank_lsb;int dimm_lsb;int rank_lsb;int bank_lsb;int row_lsb;int col_hi_lsb;int xor_bank;int l2c_alias;struct page *mem;struct lmc_err_ctx err_ctx[RING_ENTRIES];unsigned long ring_head;unsigned long ring_tail;#define ring_pos(pos, size) ((pos) & (size - 1))#define DEBUGFS_STRUCT(_name, _mode, _write, _read) \static struct debugfs_entry debugfs_## _name = { \#define DEBUGFS_FIELD_ATTR(_type, _field) \static ssize_t thunderx_## _type## _## _field## _read(struct file *file, \char __user *data, \struct thunderx_## _type *pdata = file->private_data; \char buf[20]; \"0x%016llx" , pdata->_field); \return simple_read_from_buffer(data, count, ppos, \sizeof (buf)); \static ssize_t thunderx_## _type## _## _field## _write(struct file *file, \const char __user *data, \struct thunderx_## _type *pdata = file->private_data; \int res; \return res ? res : count; \## _type## _## _field## _write, \## _type## _## _field## _read) \#define DEBUGFS_REG_ATTR(_type, _name, _reg) \static ssize_t thunderx_## _type## _## _name## _read(struct file *file, \char __user *data, \struct thunderx_## _type *pdata = file->private_data; \char buf[20]; \"0x%016llx" , readq(pdata->regs + _reg)); \return simple_read_from_buffer(data, count, ppos, \sizeof (buf)); \static ssize_t thunderx_## _type## _## _name## _write(struct file *file, \const char __user *data, \struct thunderx_## _type *pdata = file->private_data; \int res; \if (!res) { \return res; \## _type## _## _name## _write, \## _type## _## _name## _read)#define LMC_DEBUGFS_ENT(_field) DEBUGFS_FIELD_ATTR(lmc, _field)/* * To get an ECC error injected, the following steps are needed: * - Setup the ECC injection by writing the appropriate parameters: * echo <bit mask value> > /sys/kernel/debug/<device number>/ecc_mask0 * echo <bit mask value> > /sys/kernel/debug/<device number>/ecc_mask2 * echo 0x802 > /sys/kernel/debug/<device number>/ecc_parity_test * - Do the actual injection: * echo 1 > /sys/kernel/debug/<device number>/inject_ecc static ssize_t thunderx_lmc_inject_int_write(struct file *file,const char __user *data,struct thunderx_lmc *lmc = file->private_data;int res;if (!res) {/* Trigger the interrupt */ return res;static ssize_t thunderx_lmc_int_read(struct file *file,char __user *data,struct thunderx_lmc *lmc = file->private_data;char buf[20];sizeof (buf), "0x%016llx" , lmc_int);return simple_read_from_buffer(data, count, ppos, buf, sizeof (buf));#define TEST_PATTERN 0xa5static int inject_ecc_fn(void *arg)struct thunderx_lmc *lmc = arg;unsigned int cline_size = cache_line_size();const unsigned int lines = PAGE_SIZE / cline_size;unsigned int i, cl_idx;for (i = 0; i < lines; i++) {void *)addr, TEST_PATTERN, cline_size);/* * Flush L1 cachelines to the PoC (L2). * This will cause cacheline eviction to the L2. asm volatile ("dc civac, %0\n" "dsb sy\n" "r" (addr + i * cline_size));for (i = 0; i < lines; i++) {/* * Flush L2 cachelines to the DRAM. * This will cause cacheline eviction to the DRAM * and ECC corruption according to the masks set. volatile ("sys #0,c11,C1,#2, %0\n" "r" (phys + i * cline_size));for (i = 0; i < lines; i++) {/* * Invalidate L2 cachelines. * The subsequent load will cause cacheline fetch * from the DRAM and an error interrupt volatile ("sys #0,c11,C1,#1, %0" "r" (phys + i * cline_size));for (i = 0; i < lines; i++) {/* * Invalidate L1 cachelines. * The subsequent load will cause cacheline fetch * from the L2 and/or DRAM asm volatile ("dc ivac, %0\n" "dsb sy\n" "r" (addr + i * cline_size));return 0;static ssize_t thunderx_lmc_inject_ecc_write(struct file *file,const char __user *data,struct thunderx_lmc *lmc = file->private_data;unsigned int cline_size = cache_line_size();void __iomem *addr;unsigned int offs, timeout = 100000;if (!lmc->mem)return -ENOMEM;if (!tmp) {return -ENOMEM;while (!atomic_read(&lmc->ecc_int) && timeout--) {for (offs = 0; offs < PAGE_SIZE; offs += cline_size) {/* * Do a load from the previously rigged location * This should generate an error interrupt. asm volatile ("dsb ld\n" );return count;static struct debugfs_entry *lmc_dfs_ents[] = {static int thunderx_create_debugfs_nodes(struct dentry *parent,struct debugfs_entry *attrs[],void *data,int i;struct dentry *ent;if (!IS_ENABLED(CONFIG_EDAC_DEBUG))return 0;if (!parent)return -ENOENT;for (i = 0; i < num; i++) {if (IS_ERR(ent))break ;return i;static phys_addr_t thunderx_faddr_to_phys(u64 faddr, struct thunderx_lmc *lmc)int bank, xbits;if (lmc->xor_bank)if (lmc->l2c_alias)return addr;static unsigned int thunderx_get_num_lmcs(unsigned int node)unsigned int number = 0;struct pci_dev *pdev = NULL;do {if (pdev) {#ifdef CONFIG_NUMAif (pdev->dev.numa_node == node)#else #endif while (pdev);return number;#define LMC_MESSAGE_SIZE 120#define LMC_OTHER_SIZE (50 * ARRAY_SIZE(lmc_errors))static irqreturn_t thunderx_lmc_err_isr(int irq, void *dev_id)struct mem_ctl_info *mci = dev_id;struct thunderx_lmc *lmc = mci->pvt_info;unsigned long head = ring_pos(lmc->ring_head, ARRAY_SIZE(lmc->err_ctx));struct lmc_err_ctx *ctx = &lmc->err_ctx[head];/* Clear the interrupt */ return IRQ_WAKE_THREAD;static irqreturn_t thunderx_lmc_threaded_isr(int irq, void *dev_id)struct mem_ctl_info *mci = dev_id;struct thunderx_lmc *lmc = mci->pvt_info;unsigned long tail;struct lmc_err_ctx *ctx;char *msg;char *other;if (!msg || !other)goto err_free;while (CIRC_CNT(lmc->ring_head, lmc->ring_tail,"LMC_INT: %016llx\n" ,"LMC_FADR: %016llx\n" ,"LMC_NXM_FADR: %016llx\n" ,"LMC_SCRAM_FADR: %016llx\n" ,"LMC_ECC_SYND: %016llx\n" ,"DIMM %lld rank %lld bank %lld row %lld col %lld" ,if (ctx->reg_int & LMC_INT_UE)else if (ctx->reg_int & LMC_INT_CE)return ret;static const struct pci_device_id thunderx_lmc_pci_tbl[] = {static inline int pci_dev_to_mc_idx(struct pci_dev *pdev)int node = dev_to_node(&pdev->dev);int ret = PCI_FUNC(pdev->devfn);return ret;static int thunderx_lmc_probe(struct pci_dev *pdev,const struct pci_device_id *id)struct thunderx_lmc *lmc;struct edac_mc_layer layer;struct mem_ctl_info *mci;int ret;void *l2c_ioaddr;false ;if (ret) {"Cannot enable PCI device: %d\n" , ret);return ret;"thunderx_lmc" );if (ret) {"Cannot map PCI resources: %d\n" , ret);return ret;sizeof (struct thunderx_lmc));if (!mci)return -ENOMEM;if (lmc_control & LMC_CONTROL_RDIMM) {else {"thunderx-lmc" ;"thunderx-lmc" ;if (ret) {"Cannot enable interrupt: %d\n" , ret);goto err_free;"[EDAC] ThunderX LMC" , mci);if (ret) {"Cannot set ISR: %d\n" , ret);goto err_free;if (!l2c_ioaddr) {"Cannot map L2C_CTL\n" );goto err_free;if (ret) {"Cannot add the MC: %d\n" , ret);goto err_free;if (IS_ENABLED(CONFIG_EDAC_DEBUG)) {if (ret != ARRAY_SIZE(lmc_dfs_ents)) {"Error creating debugfs entries: %d%s\n" ," created" : "" );return 0;return ret;static void thunderx_lmc_remove(struct pci_dev *pdev)struct mem_ctl_info *mci = pci_get_drvdata(pdev);struct thunderx_lmc *lmc = mci->pvt_info;static struct pci_driver thunderx_lmc_driver = {"thunderx_lmc_edac" ,/*---------------------- OCX driver ---------------------------------*/ #define PCI_DEVICE_ID_THUNDER_OCX 0xa013#define OCX_LINK_INTS 3#define OCX_INTS (OCX_LINK_INTS + 1)#define OCX_RX_LANES 24#define OCX_RX_LANE_STATS 15#define OCX_COM_INT 0x100#define OCX_COM_INT_W1S 0x108#define OCX_COM_INT_ENA_W1S 0x110#define OCX_COM_INT_ENA_W1C 0x118#define OCX_COM_IO_BADID BIT(54)#define OCX_COM_MEM_BADID BIT(53)#define OCX_COM_COPR_BADID BIT(52)#define OCX_COM_WIN_REQ_BADID BIT(51)#define OCX_COM_WIN_REQ_TOUT BIT(50)#define OCX_COM_RX_LANE GENMASK(23, 0)#define OCX_COM_INT_CE (OCX_COM_IO_BADID | \static const struct error_descr ocx_com_errors[] = {"Invalid IO transaction node ID" ,"Invalid memory transaction node ID" ,"Invalid coprocessor transaction node ID" ,"Invalid SLI transaction node ID" ,"Window/core request timeout" ,#define OCX_COM_LINKX_INT(x) (0x120 + (x) * 8)#define OCX_COM_LINKX_INT_W1S(x) (0x140 + (x) * 8)#define OCX_COM_LINKX_INT_ENA_W1S(x) (0x160 + (x) * 8)#define OCX_COM_LINKX_INT_ENA_W1C(x) (0x180 + (x) * 8)#define OCX_COM_LINK_BAD_WORD BIT(13)#define OCX_COM_LINK_ALIGN_FAIL BIT(12)#define OCX_COM_LINK_ALIGN_DONE BIT(11)#define OCX_COM_LINK_UP BIT(10)#define OCX_COM_LINK_STOP BIT(9)#define OCX_COM_LINK_BLK_ERR BIT(8)#define OCX_COM_LINK_REINIT BIT(7)#define OCX_COM_LINK_LNK_DATA BIT(6)#define OCX_COM_LINK_RXFIFO_DBE BIT(5)#define OCX_COM_LINK_RXFIFO_SBE BIT(4)#define OCX_COM_LINK_TXFIFO_DBE BIT(3)#define OCX_COM_LINK_TXFIFO_SBE BIT(2)#define OCX_COM_LINK_REPLAY_DBE BIT(1)#define OCX_COM_LINK_REPLAY_SBE BIT(0)static const struct error_descr ocx_com_link_errors[] = {"Replay buffer single-bit error" ,"TX FIFO single-bit error" ,"RX FIFO single-bit error" ,"Block code error" ,"Link alignment failure" ,"Bad code word" ,"Replay buffer double-bit error" ,"TX FIFO double-bit error" ,"RX FIFO double-bit error" ,"Link stopped" ,#define OCX_COM_LINK_INT_UE (OCX_COM_LINK_REPLAY_DBE | \#define OCX_COM_LINK_INT_CE (OCX_COM_LINK_REPLAY_SBE | \#define OCX_LNE_INT(x) (0x8018 + (x) * 0x100)#define OCX_LNE_INT_EN(x) (0x8020 + (x) * 0x100)#define OCX_LNE_BAD_CNT(x) (0x8028 + (x) * 0x100)#define OCX_LNE_CFG(x) (0x8000 + (x) * 0x100)#define OCX_LNE_STAT(x, y) (0x8040 + (x) * 0x100 + (y) * 8)#define OCX_LNE_CFG_RX_BDRY_LOCK_DIS BIT(8)#define OCX_LNE_CFG_RX_STAT_WRAP_DIS BIT(2)#define OCX_LNE_CFG_RX_STAT_RDCLR BIT(1)#define OCX_LNE_CFG_RX_STAT_ENA BIT(0)#define OCX_LANE_BAD_64B67B BIT(8)#define OCX_LANE_DSKEW_FIFO_OVFL BIT(5)#define OCX_LANE_SCRM_SYNC_LOSS BIT(4)#define OCX_LANE_UKWN_CNTL_WORD BIT(3)#define OCX_LANE_CRC32_ERR BIT(2)#define OCX_LANE_BDRY_SYNC_LOSS BIT(1)#define OCX_LANE_SERDES_LOCK_LOSS BIT(0)#define OCX_COM_LANE_INT_UE (0)#define OCX_COM_LANE_INT_CE (OCX_LANE_SERDES_LOCK_LOSS | \static const struct error_descr ocx_lane_errors[] = {"RX SerDes lock lost" ,"RX word boundary lost" ,"CRC32 error" ,"Unknown control word" ,"Scrambler synchronization lost" ,"RX deskew FIFO overflow" ,"Bad 64B/67B codeword" ,#define OCX_LNE_INT_ENA_ALL (GENMASK(9, 8) | GENMASK(6, 0))#define OCX_COM_INT_ENA_ALL (GENMASK(54, 50) | GENMASK(23, 0))#define OCX_COM_LINKX_INT_ENA_ALL (GENMASK(13, 12) | \#define OCX_TLKX_ECC_CTL(x) (0x10018 + (x) * 0x2000)#define OCX_RLKX_ECC_CTL(x) (0x18018 + (x) * 0x2000)struct ocx_com_err_ctx {struct ocx_link_err_ctx {int link;struct thunderx_ocx {void __iomem *regs;int com_link;struct pci_dev *pdev;struct edac_device_ctl_info *edac_dev;struct dentry *debugfs;struct msix_entry msix_ent[OCX_INTS];struct ocx_com_err_ctx com_err_ctx[RING_ENTRIES];struct ocx_link_err_ctx link_err_ctx[RING_ENTRIES];unsigned long com_ring_head;unsigned long com_ring_tail;unsigned long link_ring_head;unsigned long link_ring_tail;#define OCX_MESSAGE_SIZE SZ_1K#define OCX_OTHER_SIZE (50 * ARRAY_SIZE(ocx_com_link_errors))/* This handler is threaded */ static irqreturn_t thunderx_ocx_com_isr(int irq, void *irq_id)struct msix_entry *msix = irq_id;struct thunderx_ocx *ocx = container_of(msix, struct thunderx_ocx,int lane;unsigned long head = ring_pos(ocx->com_ring_head,struct ocx_com_err_ctx *ctx = &ocx->com_err_ctx[head];for (lane = 0; lane < OCX_RX_LANES; lane++) {return IRQ_WAKE_THREAD;static irqreturn_t thunderx_ocx_com_threaded_isr(int irq, void *irq_id)struct msix_entry *msix = irq_id;struct thunderx_ocx *ocx = container_of(msix, struct thunderx_ocx,unsigned long tail;struct ocx_com_err_ctx *ctx;int lane;char *msg;char *other;if (!msg || !other)goto err_free;while (CIRC_CNT(ocx->com_ring_head, ocx->com_ring_tail,"%s: OCX_COM_INT: %016llx" ,for (lane = 0; lane < OCX_RX_LANES; lane++)if (ctx->reg_com_int & BIT(lane)) {"\n\tOCX_LNE_INT[%02d]: %016llx OCX_LNE_STAT11[%02d]: %016llx" ,if (ctx->reg_com_int & OCX_COM_INT_CE)return ret;static irqreturn_t thunderx_ocx_lnk_isr(int irq, void *irq_id)struct msix_entry *msix = irq_id;struct thunderx_ocx *ocx = container_of(msix, struct thunderx_ocx,unsigned long head = ring_pos(ocx->link_ring_head,struct ocx_link_err_ctx *ctx = &ocx->link_err_ctx[head];return IRQ_WAKE_THREAD;static irqreturn_t thunderx_ocx_lnk_threaded_isr(int irq, void *irq_id)struct msix_entry *msix = irq_id;struct thunderx_ocx *ocx = container_of(msix, struct thunderx_ocx,unsigned long tail;struct ocx_link_err_ctx *ctx;char *msg;char *other;if (!msg || !other)goto err_free;while (CIRC_CNT(ocx->link_ring_head, ocx->link_ring_tail,"%s: OCX_COM_LINK_INT[%d]: %016llx" ,if (ctx->reg_com_link_int & OCX_COM_LINK_INT_UE)else if (ctx->reg_com_link_int & OCX_COM_LINK_INT_CE)return ret;#define OCX_DEBUGFS_ATTR(_name, _reg) DEBUGFS_REG_ATTR(ocx, _name, _reg)static struct debugfs_entry *ocx_dfs_ents[] = {static const struct pci_device_id thunderx_ocx_pci_tbl[] = {static void thunderx_ocx_clearstats(struct thunderx_ocx *ocx)int lane, stat, cfg;for (lane = 0; lane < OCX_RX_LANES; lane++) {for (stat = 0; stat < OCX_RX_LANE_STATS; stat++)static int thunderx_ocx_probe(struct pci_dev *pdev,const struct pci_device_id *id)struct thunderx_ocx *ocx;struct edac_device_ctl_info *edac_dev;char name[32];int idx;int i;int ret;if (ret) {"Cannot enable PCI device: %d\n" , ret);return ret;"thunderx_ocx" );if (ret) {"Cannot map PCI resources: %d\n" , ret);return ret;sizeof (name), "OCX%d" , idx);sizeof (struct thunderx_ocx),"CCPI" , 1, 0, idx);if (!edac_dev) {"Cannot allocate EDAC device\n" );return -ENOMEM;if (!ocx->regs) {"Cannot map PCI resources\n" );goto err_free;for (i = 0; i < OCX_INTS; i++) {if (ret) {"Cannot enable interrupt: %d\n" , ret);goto err_free;for (i = 0; i < OCX_INTS; i++) {"[EDAC] ThunderX OCX" ,if (ret)goto err_free;"thunderx-ocx" ;"thunderx-ocx" ;if (ret) {"Cannot add EDAC device: %d\n" , ret);goto err_free;if (IS_ENABLED(CONFIG_EDAC_DEBUG)) {if (ret != ARRAY_SIZE(ocx_dfs_ents)) {"Error creating debugfs entries: %d%s\n" ," created" : "" );for (i = 0; i < OCX_RX_LANES; i++) {for (i = 0; i < OCX_LINK_INTS; i++) {return 0;return ret;static void thunderx_ocx_remove(struct pci_dev *pdev)struct edac_device_ctl_info *edac_dev = pci_get_drvdata(pdev);struct thunderx_ocx *ocx = edac_dev->pvt_info;int i;for (i = 0; i < OCX_INTS; i++) {static struct pci_driver thunderx_ocx_driver = {"thunderx_ocx_edac" ,/*---------------------- L2C driver ---------------------------------*/ #define PCI_DEVICE_ID_THUNDER_L2C_TAD 0xa02e#define PCI_DEVICE_ID_THUNDER_L2C_CBC 0xa02f#define PCI_DEVICE_ID_THUNDER_L2C_MCI 0xa030#define L2C_TAD_INT_W1C 0x40000#define L2C_TAD_INT_W1S 0x40008#define L2C_TAD_INT_ENA_W1C 0x40020#define L2C_TAD_INT_ENA_W1S 0x40028#define L2C_TAD_INT_L2DDBE BIT(1)#define L2C_TAD_INT_SBFSBE BIT(2)#define L2C_TAD_INT_SBFDBE BIT(3)#define L2C_TAD_INT_FBFSBE BIT(4)#define L2C_TAD_INT_FBFDBE BIT(5)#define L2C_TAD_INT_TAGDBE BIT(9)#define L2C_TAD_INT_RDDISLMC BIT(15)#define L2C_TAD_INT_WRDISLMC BIT(16)#define L2C_TAD_INT_LFBTO BIT(17)#define L2C_TAD_INT_GSYNCTO BIT(18)#define L2C_TAD_INT_RTGSBE BIT(32)#define L2C_TAD_INT_RTGDBE BIT(33)#define L2C_TAD_INT_RDDISOCI BIT(34)#define L2C_TAD_INT_WRDISOCI BIT(35)#define L2C_TAD_INT_ECC (L2C_TAD_INT_L2DDBE | \#define L2C_TAD_INT_CE (L2C_TAD_INT_SBFSBE | \#define L2C_TAD_INT_UE (L2C_TAD_INT_L2DDBE | \static const struct error_descr l2_tad_errors[] = {"SBF single-bit error" ,"FBF single-bit error" ,"L2D double-bit error" ,"SBF double-bit error" ,"FBF double-bit error" ,"TAG double-bit error" ,"RTG double-bit error" ,"Write to a disabled CCPI" ,"Read from a disabled CCPI" ,"Write to a disabled LMC" ,"Read from a disabled LMC" ,"LFB entry timeout" ,"Global sync CCPI timeout" ,#define L2C_TAD_INT_TAG (L2C_TAD_INT_TAGDBE)#define L2C_TAD_INT_RTG (L2C_TAD_INT_RTGDBE)#define L2C_TAD_INT_DISLMC (L2C_TAD_INT_WRDISLMC | L2C_TAD_INT_RDDISLMC)#define L2C_TAD_INT_DISOCI (L2C_TAD_INT_WRDISOCI | L2C_TAD_INT_RDDISOCI)#define L2C_TAD_INT_ENA_ALL (L2C_TAD_INT_ECC | L2C_TAD_INT_TAG | \#define L2C_TAD_TIMETWO 0x50000#define L2C_TAD_TIMEOUT 0x50100#define L2C_TAD_ERR 0x60000#define L2C_TAD_TQD_ERR 0x60100#define L2C_TAD_TTG_ERR 0x60200#define L2C_CBC_INT_W1C 0x60000#define L2C_CBC_INT_RSDSBE BIT(0)#define L2C_CBC_INT_RSDDBE BIT(1)#define L2C_CBC_INT_RSD (L2C_CBC_INT_RSDSBE | L2C_CBC_INT_RSDDBE)#define L2C_CBC_INT_MIBSBE BIT(4)#define L2C_CBC_INT_MIBDBE BIT(5)#define L2C_CBC_INT_MIB (L2C_CBC_INT_MIBSBE | L2C_CBC_INT_MIBDBE)#define L2C_CBC_INT_IORDDISOCI BIT(6)#define L2C_CBC_INT_IOWRDISOCI BIT(7)#define L2C_CBC_INT_IODISOCI (L2C_CBC_INT_IORDDISOCI | \#define L2C_CBC_INT_CE (L2C_CBC_INT_RSDSBE | L2C_CBC_INT_MIBSBE)#define L2C_CBC_INT_UE (L2C_CBC_INT_RSDDBE | L2C_CBC_INT_MIBDBE)static const struct error_descr l2_cbc_errors[] = {"RSD single-bit error" ,"MIB single-bit error" ,"RSD double-bit error" ,"MIB double-bit error" ,"Read from a disabled CCPI" ,"Write to a disabled CCPI" ,#define L2C_CBC_INT_W1S 0x60008#define L2C_CBC_INT_ENA_W1C 0x60020#define L2C_CBC_INT_ENA_ALL (L2C_CBC_INT_RSD | L2C_CBC_INT_MIB | \#define L2C_CBC_INT_ENA_W1S 0x60028#define L2C_CBC_IODISOCIERR 0x80008#define L2C_CBC_IOCERR 0x80010#define L2C_CBC_RSDERR 0x80018#define L2C_CBC_MIBERR 0x80020#define L2C_MCI_INT_W1C 0x0#define L2C_MCI_INT_VBFSBE BIT(0)#define L2C_MCI_INT_VBFDBE BIT(1)static const struct error_descr l2_mci_errors[] = {"VBF single-bit error" ,"VBF double-bit error" ,#define L2C_MCI_INT_W1S 0x8#define L2C_MCI_INT_ENA_W1C 0x20#define L2C_MCI_INT_ENA_ALL (L2C_MCI_INT_VBFSBE | L2C_MCI_INT_VBFDBE)#define L2C_MCI_INT_ENA_W1S 0x28#define L2C_MCI_ERR 0x10000#define L2C_MESSAGE_SIZE SZ_1K#define L2C_OTHER_SIZE (50 * ARRAY_SIZE(l2_tad_errors))struct l2c_err_ctx {char *reg_ext_name;struct thunderx_l2c {void __iomem *regs;struct pci_dev *pdev;struct edac_device_ctl_info *edac_dev;struct dentry *debugfs;int index;struct msix_entry msix_ent;struct l2c_err_ctx err_ctx[RING_ENTRIES];unsigned long ring_head;unsigned long ring_tail;static irqreturn_t thunderx_l2c_tad_isr(int irq, void *irq_id)struct msix_entry *msix = irq_id;struct thunderx_l2c *tad = container_of(msix, struct thunderx_l2c,unsigned long head = ring_pos(tad->ring_head, ARRAY_SIZE(tad->err_ctx));struct l2c_err_ctx *ctx = &tad->err_ctx[head];if (ctx->reg_int & L2C_TAD_INT_ECC) {"TQD_ERR" ;else if (ctx->reg_int & L2C_TAD_INT_TAG) {"TTG_ERR" ;else if (ctx->reg_int & L2C_TAD_INT_LFBTO) {"TIMEOUT" ;else if (ctx->reg_int & L2C_TAD_INT_DISOCI) {"ERR" ;return IRQ_WAKE_THREAD;static irqreturn_t thunderx_l2c_cbc_isr(int irq, void *irq_id)struct msix_entry *msix = irq_id;struct thunderx_l2c *cbc = container_of(msix, struct thunderx_l2c,unsigned long head = ring_pos(cbc->ring_head, ARRAY_SIZE(cbc->err_ctx));struct l2c_err_ctx *ctx = &cbc->err_ctx[head];if (ctx->reg_int & L2C_CBC_INT_RSD) {"RSDERR" ;else if (ctx->reg_int & L2C_CBC_INT_MIB) {"MIBERR" ;else if (ctx->reg_int & L2C_CBC_INT_IODISOCI) {"IODISOCIERR" ;return IRQ_WAKE_THREAD;static irqreturn_t thunderx_l2c_mci_isr(int irq, void *irq_id)struct msix_entry *msix = irq_id;struct thunderx_l2c *mci = container_of(msix, struct thunderx_l2c,unsigned long head = ring_pos(mci->ring_head, ARRAY_SIZE(mci->err_ctx));struct l2c_err_ctx *ctx = &mci->err_ctx[head];"ERR" ;return IRQ_WAKE_THREAD;static irqreturn_t thunderx_l2c_threaded_isr(int irq, void *irq_id)struct msix_entry *msix = irq_id;struct thunderx_l2c *l2c = container_of(msix, struct thunderx_l2c,unsigned long tail = ring_pos(l2c->ring_tail, ARRAY_SIZE(l2c->err_ctx));struct l2c_err_ctx *ctx = &l2c->err_ctx[tail];const struct error_descr *l2_errors;char *reg_int_name;char *msg;char *other;if (!msg || !other)goto err_free;switch (l2c->pdev->device) {case PCI_DEVICE_ID_THUNDER_L2C_TAD:"L2C_TAD_INT" ;break ;case PCI_DEVICE_ID_THUNDER_L2C_CBC:"L2C_CBC_INT" ;break ;case PCI_DEVICE_ID_THUNDER_L2C_MCI:"L2C_MCI_INT" ;break ;default :"Unsupported device: %04x\n" ,goto err_free;while (CIRC_CNT(l2c->ring_head, l2c->ring_tail,"%s: %s: %016llx, %s: %016llx" ,if (ctx->reg_int & mask_ue)else if (ctx->reg_int & mask_ce)return ret;#define L2C_DEBUGFS_ATTR(_name, _reg) DEBUGFS_REG_ATTR(l2c, _name, _reg)static struct debugfs_entry *l2c_tad_dfs_ents[] = {static struct debugfs_entry *l2c_cbc_dfs_ents[] = {static struct debugfs_entry *l2c_mci_dfs_ents[] = {static const struct pci_device_id thunderx_l2c_pci_tbl[] = {static int thunderx_l2c_probe(struct pci_dev *pdev,const struct pci_device_id *id)struct thunderx_l2c *l2c;struct edac_device_ctl_info *edac_dev;struct debugfs_entry **l2c_devattr;int , void *) = NULL;char name[32];const char *fmt;int idx;int ret;if (ret) {"Cannot enable PCI device: %d\n" , ret);return ret;"thunderx_l2c" );if (ret) {"Cannot map PCI resources: %d\n" , ret);return ret;switch (pdev->device) {case PCI_DEVICE_ID_THUNDER_L2C_TAD:"L2C-TAD%d" ;break ;case PCI_DEVICE_ID_THUNDER_L2C_CBC:"L2C-CBC%d" ;break ;case PCI_DEVICE_ID_THUNDER_L2C_MCI:"L2C-MCI%d" ;break ;default ://Should never ever get here "Unsupported PCI device: %04x\n" ,return -EINVAL;sizeof (name), fmt, idx);sizeof (struct thunderx_l2c),"L2C" , 1, 0, idx);if (!edac_dev) {"Cannot allocate EDAC device\n" );return -ENOMEM;if (!l2c->regs) {"Cannot map PCI resources\n" );goto err_free;if (ret) {"Cannot enable interrupt: %d\n" , ret);goto err_free;"[EDAC] ThunderX L2C" ,if (ret)goto err_free;"thunderx-l2c" ;"thunderx-l2c" ;if (ret) {"Cannot add EDAC device: %d\n" , ret);goto err_free;if (IS_ENABLED(CONFIG_EDAC_DEBUG)) {if (ret != dfs_entries) {"Error creating debugfs entries: %d%s\n" ," created" : "" );return 0;return ret;static void thunderx_l2c_remove(struct pci_dev *pdev)struct edac_device_ctl_info *edac_dev = pci_get_drvdata(pdev);struct thunderx_l2c *l2c = edac_dev->pvt_info;switch (pdev->device) {case PCI_DEVICE_ID_THUNDER_L2C_TAD:break ;case PCI_DEVICE_ID_THUNDER_L2C_CBC:break ;case PCI_DEVICE_ID_THUNDER_L2C_MCI:break ;static struct pci_driver thunderx_l2c_driver = {"thunderx_l2c_edac" ,static int __init thunderx_edac_init(void )int rc = 0;if (ghes_get_devices())return -EBUSY;if (rc)return rc;if (rc)goto err_lmc;if (rc)goto err_ocx;return rc;return rc;static void __exit thunderx_edac_exit(void )"GPL v2" );"Cavium, Inc." );"EDAC Driver for Cavium ThunderX" );
Messung V0.5 C=95 H=84 G=89
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