/* * Copyright 2022 Advanced Micro Devices , Inc . * * Permission is hereby granted , free of charge , to any person obtaining a * copy of this software and associated documentation files ( the " Software " ) , * to deal in the Software without restriction , including without limitation * the rights to use , copy , modify , merge , publish , distribute , sublicense , * and / or sell copies of the Software , and to permit persons to whom the * Software is furnished to do so , subject to the following conditions : * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software . * * THE SOFTWARE IS PROVIDED " AS IS " , WITHOUT WARRANTY OF ANY KIND , EXPRESS OR * IMPLIED , INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY , * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT . IN NO EVENT SHALL * THE COPYRIGHT HOLDER ( S ) OR AUTHOR ( S ) BE LIABLE FOR ANY CLAIM , DAMAGES OR * OTHER LIABILITY , WHETHER IN AN ACTION OF CONTRACT , TORT OR OTHERWISE , * ARISING FROM , OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE . * #include "amdgpu.h" #include "mmhub_v1_8.h" #include "mmhub/mmhub_1_8_0_offset.h" #include "mmhub/mmhub_1_8_0_sh_mask.h" #include "vega10_enum.h" #include "soc15_common.h" #include "soc15.h" #include "amdgpu_ras.h" #include "amdgpu_psp.h" #define regVM_L2_CNTL3_DEFAULT 0 x80100007#define regVM_L2_CNTL4_DEFAULT 0 x000000c1static u64 mmhub_v1_8_get_fb_location(struct amdgpu_device *adev)0 , regMC_VM_FB_LOCATION_BASE);0 , regMC_VM_FB_LOCATION_TOP);24 ;24 ;return base;static void mmhub_v1_8_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,struct amdgpu_vmhub *hub;int i;static void mmhub_v1_8_init_gart_aperture_regs(struct amdgpu_device *adev)int i;if (adev->gmc.pdb0_bo)else 0 , pt_base);/* If use GART for FB translation, vmid0 page table covers both * vram and system memory ( gart ) if (adev->gmc.pdb0_bo) {12 ));44 ));12 ));44 ));else {12 ));44 ));12 ));44 ));static void mmhub_v1_8_init_system_aperture_regs(struct amdgpu_device *adev)int i;if (amdgpu_sriov_vf(adev))return ;/* Program the AGP BAR */ 0 );24 );24 );/* Program the system aperture low logical page number. */ 18 );18 );/* In the case squeezing vram into GART aperture, we don't use * FB aperture and AGP aperture . Disable them . if (adev->gmc.pdb0_bo) {0 xFFFFFF);0 );0 );0 x00FFFFFF);0 x3FFFFFFF);0 );/* Set default page address. */ 12 ));44 ));/* Program "protection fault". */ 12 ));44 ));1 );static void mmhub_v1_8_init_tlb_regs(struct amdgpu_device *adev)int i;if (amdgpu_sriov_reg_indirect_l1_tlb_cntl(adev)) {0 , regMC_VM_MX_L1_TLB_CNTL);1 );3 );1 );0 );/* XXX for emulation. */ 1 );else {1 );3 );1 );0 );/* XXX for emulation. */ 1 );/* Set snoop bit for SDMA so that SDMA writes probe-invalidates RW lines */ static void mmhub_v1_8_init_snoop_override_regs(struct amdgpu_device *adev)int i, j;if (amdgpu_sriov_vf(adev))return ;for (j = 0 ; j < 5 ; j++) { /* DAGB instances */ 1 << 15 ); /* SDMA client is BIT15 */ 1 << 15 );static void mmhub_v1_8_init_cache_regs(struct amdgpu_device *adev)int i;if (amdgpu_sriov_vf(adev))return ;/* Setup L2 cache */ 1 );1 );/* XXX for emulation, Refer to closed source code.*/ 0 );0 );1 );0 );1 );1 );if (adev->gmc.translate_further) {12 );9 );else {9 );6 );/* For AMD APP APUs setup WC memory */ if (adev->gmc.xgmi.connected_to_cpu || adev->gmc.is_app_apu) {1 );1 );else {0 );0 );static void mmhub_v1_8_enable_system_domain(struct amdgpu_device *adev)int i;1 );0 );static void mmhub_v1_8_disable_identity_aperture(struct amdgpu_device *adev)int i;if (amdgpu_sriov_vf(adev))return ;0 XFFFFFFFF);0 x0000000F);0 );0 );0 );0 );static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev)struct amdgpu_vmhub *hub;unsigned int num_level, block_size;int i, j;if (adev->gmc.translate_further)1 ;else 9 ;for (i = 0 ; i <= 14 ; i++) {1 );1 );1 );1 );1 );1 );1 );1 );/* On 9.4.3, XNACK can be enabled in the SQ * per - process . Retry faults need to be enabled for * that to work . 1 );0 );0 );1 ));1 ));static void mmhub_v1_8_program_invalidation(struct amdgpu_device *adev)struct amdgpu_vmhub *hub;for (i = 0 ; i < 18 ; ++i) {0 xffffffff);0 x1f);static int mmhub_v1_8_gart_enable(struct amdgpu_device *adev)/* GART Enable. */ return 0 ;static void mmhub_v1_8_disable_l1_tlb(struct amdgpu_device *adev)if (amdgpu_sriov_reg_indirect_l1_tlb_cntl(adev)) {0 , regMC_VM_MX_L1_TLB_CNTL);0 );0 );else {0 );0 );static void mmhub_v1_8_gart_disable(struct amdgpu_device *adev)struct amdgpu_vmhub *hub;/* Disable all tables */ for (i = 0 ; i < 16 ; i++)0 );if (!amdgpu_sriov_vf(adev)) {/* Setup L2 cache */ 0 );0 );/** * mmhub_v1_8_set_fault_enable_default - update GART / VM fault handling * * @ adev : amdgpu_device pointer * @ value : true redirects VM faults to the default page static void mmhub_v1_8_set_fault_enable_default(struct amdgpu_device *adev, bool value)int i;if (amdgpu_sriov_vf(adev))return ;if (!value) {1 );1 );static void mmhub_v1_8_init(struct amdgpu_device *adev)struct amdgpu_vmhub *hub;int i;static int mmhub_v1_8_set_clockgating(struct amdgpu_device *adev,enum amd_clockgating_state state)return 0 ;static void mmhub_v1_8_get_clockgating(struct amdgpu_device *adev, u64 *flags)const struct amdgpu_mmhub_funcs mmhub_v1_8_funcs = {static const struct amdgpu_ras_err_status_reg_entry mmhub_v1_8_ce_reg_list[] = {0 , regMMEA0_CE_ERR_STATUS_LO, regMMEA0_CE_ERR_STATUS_HI),1 , (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "MMEA0" },0 , regMMEA1_CE_ERR_STATUS_LO, regMMEA1_CE_ERR_STATUS_HI),1 , (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "MMEA1" },0 , regMMEA2_CE_ERR_STATUS_LO, regMMEA2_CE_ERR_STATUS_HI),1 , (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "MMEA2" },0 , regMMEA3_CE_ERR_STATUS_LO, regMMEA3_CE_ERR_STATUS_HI),1 , (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "MMEA3" },0 , regMMEA4_CE_ERR_STATUS_LO, regMMEA4_CE_ERR_STATUS_HI),1 , (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "MMEA4" },0 , regMM_CANE_CE_ERR_STATUS_LO, regMM_CANE_CE_ERR_STATUS_HI),1 , 0 , "MM_CANE" },static const struct amdgpu_ras_err_status_reg_entry mmhub_v1_8_ue_reg_list[] = {0 , regMMEA0_UE_ERR_STATUS_LO, regMMEA0_UE_ERR_STATUS_HI),1 , (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "MMEA0" },0 , regMMEA1_UE_ERR_STATUS_LO, regMMEA1_UE_ERR_STATUS_HI),1 , (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "MMEA1" },0 , regMMEA2_UE_ERR_STATUS_LO, regMMEA2_UE_ERR_STATUS_HI),1 , (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "MMEA2" },0 , regMMEA3_UE_ERR_STATUS_LO, regMMEA3_UE_ERR_STATUS_HI),1 , (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "MMEA3" },0 , regMMEA4_UE_ERR_STATUS_LO, regMMEA4_UE_ERR_STATUS_HI),1 , (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "MMEA4" },0 , regMM_CANE_UE_ERR_STATUS_LO, regMM_CANE_UE_ERR_STATUS_HI),1 , 0 , "MM_CANE" },static const struct amdgpu_ras_memory_id_entry mmhub_v1_8_ras_memory_list[] = {"MMEA_WGMI_PAGEMEM" },"MMEA_RGMI_PAGEMEM" },"MMEA_WDRAM_PAGEMEM" },"MMEA_RDRAM_PAGEMEM" },"MMEA_WIO_CMDMEM" },"MMEA_RIO_CMDMEM" },"MMEA_WGMI_CMDMEM" },"MMEA_RGMI_CMDMEM" },"MMEA_WDRAM_CMDMEM" },"MMEA_RDRAM_CMDMEM" },"MMEA_MAM_DMEM0" },"MMEA_MAM_DMEM1" },"MMEA_MAM_DMEM2" },"MMEA_MAM_DMEM3" },"MMEA_WRET_TAGMEM" },"MMEA_RRET_TAGMEM" },"MMEA_WIO_DATAMEM" },"MMEA_WGMI_DATAMEM" },"MMEA_WDRAM_DATAMEM" },static void mmhub_v1_8_inst_query_ras_error_count(struct amdgpu_device *adev,void *ras_err_status)struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status;unsigned long ue_count = 0 , ce_count = 0 ;/* NOTE: mmhub is converted by aid_mask and the range is 0-3, struct amdgpu_smuio_mcm_config_info mcm_info = {static void mmhub_v1_8_query_ras_error_count(struct amdgpu_device *adev,void *ras_err_status)if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {"MMHUB RAS is not supported\n" );return ;static void mmhub_v1_8_inst_reset_ras_error_count(struct amdgpu_device *adev,static void mmhub_v1_8_reset_ras_error_count(struct amdgpu_device *adev)if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {"MMHUB RAS is not supported\n" );return ;static const struct amdgpu_ras_block_hw_ops mmhub_v1_8_ras_hw_ops = {static int mmhub_v1_8_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,enum aca_smu_type type, void *data)struct aca_bank_info info;int ret;if (ret)return ret;switch (type) {case ACA_SMU_TYPE_UE:1 ULL);break ;case ACA_SMU_TYPE_CE:break ;default :return -EINVAL;return ret;/* reference to smu driver if header file */ static int mmhub_v1_8_err_codes[] = {0 , 1 , 2 , 3 , 4 , /* CODE_DAGB0 - 4 */ 5 , 6 , 7 , 8 , 9 , /* CODE_EA0 - 4 */ 10 , /* CODE_UTCL2_ROUTER */ 11 , /* CODE_VML2 */ 12 , /* CODE_VML2_WALKER */ 13 , /* CODE_MMCANE */ static bool mmhub_v1_8_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,enum aca_smu_type type, void *data)31 , 1 );if (instlo != mmSMNAID_AID0_MCA_SMU)return false ;if (aca_bank_check_error_codes(handle->adev, bank,return false ;return true ;static const struct aca_bank_ops mmhub_v1_8_aca_bank_ops = {static const struct aca_info mmhub_v1_8_aca_info = {static int mmhub_v1_8_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)int r;if (r)return r;if (r)goto late_fini;return 0 ;return r;struct amdgpu_mmhub_ras mmhub_v1_8_ras = {
Messung V0.5 in Prozent C=96 H=95 G=95
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(vorverarbeitet am 2026-10-12)
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