/* * DCE_11_0 Register documentation * * Copyright (C) 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef DCE_11_0_ENUM_H#define DCE_11_0_ENUM_Htypedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK {typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {typedef enum CRTC_CONTROL_CRTC_MASTER_EN {typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {0x0,x1,typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {typedef enum CRTC_V_SYNC_A_POL {typedef enum CRTC_H_SYNC_A_POL {typedef enum CRTC_HORZ_REPETITION_COUNT {typedef enum PERFCOUNTER_CVALUE_SEL {typedef enum PERFCOUNTER_INC_MODE {typedef enum PERFCOUNTER_HW_CNTL_SEL {typedef enum PERFCOUNTER_RUNEN_MODE {typedef enum PERFCOUNTER_CNTOFF_START_DIS {typedef enum PERFCOUNTER_RESTART_EN {typedef enum PERFCOUNTER_INT_EN {typedef enum PERFCOUNTER_OFF_MASK {typedef enum PERFCOUNTER_ACTIVE {typedef enum PERFCOUNTER_INT_TYPE {typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {typedef enum PERFCOUNTER_CNTL_SEL {typedef enum PERFCOUNTER_CNT0_STATE {typedef enum PERFCOUNTER_STATE_SEL0 {typedef enum PERFCOUNTER_CNT1_STATE {typedef enum PERFCOUNTER_STATE_SEL1 {typedef enum PERFCOUNTER_CNT2_STATE {typedef enum PERFCOUNTER_STATE_SEL2 {typedef enum PERFCOUNTER_CNT3_STATE {typedef enum PERFCOUNTER_STATE_SEL3 {typedef enum PERFCOUNTER_CNT4_STATE {typedef enum PERFCOUNTER_STATE_SEL4 {typedef enum PERFCOUNTER_CNT5_STATE {typedef enum PERFCOUNTER_STATE_SEL5 {typedef enum PERFCOUNTER_CNT6_STATE {typedef enum PERFCOUNTER_STATE_SEL6 {typedef enum PERFCOUNTER_CNT7_STATE {typedef enum PERFCOUNTER_STATE_SEL7 {typedef enum PERFMON_STATE {typedef enum PERFMON_CNTOFF_AND_OR {typedef enum PERFMON_CNTOFF_INT_EN {typedef enum PERFMON_CNTOFF_INT_TYPE {typedef enum LptNumBanks {typedef enum DCIO_DC_GENERICA_SEL {typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {typedef enum DCIO_DC_GENERICB_SEL {typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {typedef enum DCIO_DC_GPIO_VIP_DEBUG {typedef enum DCIO_DC_GPIO_MACRO_DEBUG {typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {typedef enum DCIO_GSL_SEL {typedef enum DCIO_GENLK_CLK_GSL_MASK {typedef enum DCIO_GENLK_VSYNC_GSL_MASK {typedef enum DCIO_SWAPLOCK_A_GSL_MASK {typedef enum DCIO_SWAPLOCK_B_GSL_MASK {typedef enum DCIO_GSL_VSYNC_SEL {typedef enum DCIO_GSL0_TIMING_SYNC_SEL {typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {typedef enum DCIO_GSL1_TIMING_SYNC_SEL {typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {typedef enum DCIO_GSL2_TIMING_SYNC_SEL {typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {typedef enum DCIO_DC_GPU_TIMER_START_POSITION {typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {typedef enum DCIO_DCO_EXT_VSYNC_MASK {typedef enum DCIO_DBG_OUT_PIN_SEL {typedef enum DCIO_DBG_OUT_12BIT_SEL {typedef enum DCIO_DSYNC_SOFT_RESET {typedef enum DCIO_DACA_SOFT_RESET {typedef enum DCIO_DCRXPHY_SOFT_RESET {typedef enum DCIO_DPHY_LANE_SEL {typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
Messung V0.5 C=94 H=97 G=95
¤ Dauer der Verarbeitung: 0.16 Sekunden
(vorverarbeitet)
¤ *© Formatika GbR, Deutschland
