/* * Copyright (C) 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef _gc_9_0_SH_MASK_HEADER#define _gc_9_0_SH_MASK_HEADER//GCEA_EDC_CNT #define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L// addressBlock: gc_cppdec2 //CPF_EDC_TAG_CNT #define CPF_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0#define CPF_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2#define CPF_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L#define CPF_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL//CPF_EDC_ROQ_CNT #define CPF_EDC_ROQ_CNT__COUNT_ME1__SHIFT 0x0#define CPF_EDC_ROQ_CNT__COUNT_ME2__SHIFT 0x2#define CPF_EDC_ROQ_CNT__COUNT_ME1_MASK 0x00000003L#define CPF_EDC_ROQ_CNT__COUNT_ME2_MASK 0x0000000CL//CPG_EDC_TAG_CNT #define CPG_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0#define CPG_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2#define CPG_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L#define CPG_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL//CPG_EDC_DMA_CNT #define CPG_EDC_DMA_CNT__ROQ_COUNT__SHIFT 0x0#define CPG_EDC_DMA_CNT__TAG_DED_COUNT__SHIFT 0x2#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT__SHIFT 0x4#define CPG_EDC_DMA_CNT__ROQ_COUNT_MASK 0x00000003L#define CPG_EDC_DMA_CNT__TAG_DED_COUNT_MASK 0x0000000CL#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT_MASK 0x00000030L//CPC_EDC_SCRATCH_CNT #define CPC_EDC_SCRATCH_CNT__DED_COUNT__SHIFT 0x0#define CPC_EDC_SCRATCH_CNT__SEC_COUNT__SHIFT 0x2#define CPC_EDC_SCRATCH_CNT__DED_COUNT_MASK 0x00000003L#define CPC_EDC_SCRATCH_CNT__SEC_COUNT_MASK 0x0000000CL//CPC_EDC_UCODE_CNT #define CPC_EDC_UCODE_CNT__DED_COUNT__SHIFT 0x0#define CPC_EDC_UCODE_CNT__SEC_COUNT__SHIFT 0x2#define CPC_EDC_UCODE_CNT__DED_COUNT_MASK 0x00000003L#define CPC_EDC_UCODE_CNT__SEC_COUNT_MASK 0x0000000CL//DC_EDC_STATE_CNT #define DC_EDC_STATE_CNT__COUNT_ME1__SHIFT 0x0#define DC_EDC_STATE_CNT__COUNT_ME1_MASK 0x00000003L//DC_EDC_CSINVOC_CNT #define DC_EDC_CSINVOC_CNT__COUNT_ME1__SHIFT 0x0#define DC_EDC_CSINVOC_CNT__COUNT_ME1_MASK 0x00000003L//DC_EDC_RESTORE_CNT #define DC_EDC_RESTORE_CNT__COUNT_ME1__SHIFT 0x0#define DC_EDC_RESTORE_CNT__COUNT_ME1_MASK 0x00000003L// addressBlock: gc_grbmdec //GRBM_CNTL #define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L//GRBM_SKEW_CNTL #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L//GRBM_STATUS2 #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf#define GRBM_STATUS2__EA_BUSY__SHIFT 0x10#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12#define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e#define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L#define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L#define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L#define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L#define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L//GRBM_PWR_CNTL #define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L//GRBM_STATUS #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0#define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd#define GRBM_STATUS__TA_BUSY__SHIFT 0xe#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12#define GRBM_STATUS__IA_BUSY__SHIFT 0x13#define GRBM_STATUS__SX_BUSY__SHIFT 0x14#define GRBM_STATUS__WD_BUSY__SHIFT 0x15#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17#define GRBM_STATUS__SC_BUSY__SHIFT 0x18#define GRBM_STATUS__PA_BUSY__SHIFT 0x19#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL#define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L//GRBM_STATUS_SE0 #define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L#define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L//GRBM_STATUS_SE1 #define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L#define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L//GRBM_SOFT_RESET #define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x15#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L//GRBM_CGTT_CLK_CNTL #define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L//GRBM_GFX_CLKEN_CNTL #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L//GRBM_WAIT_IDLE_CLOCKS #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL//GRBM_STATUS_SE2 #define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L#define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L//GRBM_STATUS_SE3 #define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L#define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L//GRBM_READ_ERROR #define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L//GRBM_READ_ERROR2 #define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x11#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f#define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L//GRBM_INT_CNTL #define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L//GRBM_TRAP_OP #define GRBM_TRAP_OP__RW__SHIFT 0x0#define GRBM_TRAP_OP__RW_MASK 0x00000001L//GRBM_TRAP_ADDR #define GRBM_TRAP_ADDR__DATA__SHIFT 0x0#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL//GRBM_TRAP_ADDR_MSK #define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL//GRBM_TRAP_WD #define GRBM_TRAP_WD__DATA__SHIFT 0x0#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL//GRBM_TRAP_WD_MSK #define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL//GRBM_DSM_BYPASS #define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L//GRBM_WRITE_ERROR #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT 0x1#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK 0x00000002L#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000001E0L#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L//GRBM_IOV_ERROR #define GRBM_IOV_ERROR__IOV_ADDR__SHIFT 0x2#define GRBM_IOV_ERROR__IOV_VFID__SHIFT 0x14#define GRBM_IOV_ERROR__IOV_VF__SHIFT 0x1a#define GRBM_IOV_ERROR__IOV_OP__SHIFT 0x1b#define GRBM_IOV_ERROR__IOV_ERROR__SHIFT 0x1f#define GRBM_IOV_ERROR__IOV_ADDR_MASK 0x000FFFFCL#define GRBM_IOV_ERROR__IOV_VFID_MASK 0x03F00000L#define GRBM_IOV_ERROR__IOV_VF_MASK 0x04000000L#define GRBM_IOV_ERROR__IOV_OP_MASK 0x08000000L#define GRBM_IOV_ERROR__IOV_ERROR_MASK 0x80000000L//GRBM_CHIP_REVISION #define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL//GRBM_GFX_CNTL #define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0#define GRBM_GFX_CNTL__MEID__SHIFT 0x2#define GRBM_GFX_CNTL__VMID__SHIFT 0x4#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L//GRBM_RSMU_CFG #define GRBM_RSMU_CFG__APERTURE_ID__SHIFT 0x0#define GRBM_RSMU_CFG__QOS__SHIFT 0xc#define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x10#define GRBM_RSMU_CFG__DEBUG_MASK__SHIFT 0x11#define GRBM_RSMU_CFG__APERTURE_ID_MASK 0x00000FFFL#define GRBM_RSMU_CFG__QOS_MASK 0x0000F000L#define GRBM_RSMU_CFG__POSTED_WR_MASK 0x00010000L#define GRBM_RSMU_CFG__DEBUG_MASK_MASK 0x00020000L//GRBM_IH_CREDIT #define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L//GRBM_PWR_CNTL2 #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L//GRBM_UTCL2_INVAL_RANGE_START #define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL//GRBM_UTCL2_INVAL_RANGE_END #define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL//GRBM_RSMU_READ_ERROR #define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT 0x2#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT 0x14#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT 0x15#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT 0x1b#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT 0x1f#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK 0x000FFFFCL#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK 0x00100000L#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK 0x07E00000L#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK 0x08000000L#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK 0x80000000L//GRBM_CHICKEN_BITS #define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT 0x0#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK 0x00000001L//GRBM_NOWHERE #define GRBM_NOWHERE__DATA__SHIFT 0x0#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL//GRBM_SCRATCH_REG0 #define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL//GRBM_SCRATCH_REG1 #define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL//GRBM_SCRATCH_REG2 #define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL//GRBM_SCRATCH_REG3 #define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL//GRBM_SCRATCH_REG4 #define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL//GRBM_SCRATCH_REG5 #define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL//GRBM_SCRATCH_REG6 #define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL//GRBM_SCRATCH_REG7 #define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL// addressBlock: gc_cpdec //CP_CPC_STATUS #define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L//CP_CPC_BUSY_STAT #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L//CP_CPC_STALLED_STAT1 #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L//CP_CPF_STATUS #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L//CP_CPF_BUSY_STAT #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x00000200L#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L//CP_CPF_STALLED_STAT1 #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L//CP_CPC_GRBM_FREE_COUNT #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL//CP_MEC_CNTL #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L//CP_MEC_ME1_HEADER_DUMP #define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL//CP_MEC_ME2_HEADER_DUMP #define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL//CP_CPC_SCRATCH_INDEX #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL//CP_CPC_SCRATCH_DATA #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL//CP_CPF_GRBM_FREE_COUNT #define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L//CP_CPC_HALT_HYST_COUNT #define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL//CP_PRT_LOD_STATS_CNTL0 #define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xFFFFFFFFL//CP_PRT_LOD_STATS_CNTL1 #define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xFFFFFFFFL//CP_PRT_LOD_STATS_CNTL2 #define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x000003FFL//CP_PRT_LOD_STATS_CNTL3 #define CP_PRT_LOD_STATS_CNTL3__INTERVAL__SHIFT 0x2#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT__SHIFT 0xa#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE__SHIFT 0x12#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET__SHIFT 0x13#define CP_PRT_LOD_STATS_CNTL3__MC_VMID__SHIFT 0x17#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY__SHIFT 0x1c#define CP_PRT_LOD_STATS_CNTL3__INTERVAL_MASK 0x000003FCL#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT_MASK 0x0003FC00L#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE_MASK 0x00040000L#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET_MASK 0x00080000L#define CP_PRT_LOD_STATS_CNTL3__MC_VMID_MASK 0x07800000L#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY_MASK 0x10000000L//CP_CE_COMPARE_COUNT #define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL//CP_CE_DE_COUNT #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL//CP_DE_CE_COUNT #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL//CP_DE_LAST_INVAL_COUNT #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL//CP_DE_DE_COUNT #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL//CP_STALLED_STAT3 #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L//CP_STALLED_STAT1 #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L//CP_STALLED_STAT2 #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L//CP_BUSY_STAT #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L//CP_STAT #define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc#define CP_STAT__DC_BUSY__SHIFT 0xd#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe#define CP_STAT__PFP_BUSY__SHIFT 0xf#define CP_STAT__MEQ_BUSY__SHIFT 0x10#define CP_STAT__ME_BUSY__SHIFT 0x11#define CP_STAT__QUERY_BUSY__SHIFT 0x12#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15#define CP_STAT__DMA_BUSY__SHIFT 0x16#define CP_STAT__RCIU_BUSY__SHIFT 0x17#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18#define CP_STAT__CE_BUSY__SHIFT 0x1a#define CP_STAT__TCIU_BUSY__SHIFT 0x1b#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e#define CP_STAT__CP_BUSY__SHIFT 0x1f#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L#define CP_STAT__DC_BUSY_MASK 0x00002000L#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L#define CP_STAT__PFP_BUSY_MASK 0x00008000L#define CP_STAT__MEQ_BUSY_MASK 0x00010000L#define CP_STAT__ME_BUSY_MASK 0x00020000L#define CP_STAT__QUERY_BUSY_MASK 0x00040000L#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L#define CP_STAT__DMA_BUSY_MASK 0x00400000L#define CP_STAT__RCIU_BUSY_MASK 0x00800000L#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L#define CP_STAT__CE_BUSY_MASK 0x04000000L#define CP_STAT__TCIU_BUSY_MASK 0x08000000L#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L#define CP_STAT__CP_BUSY_MASK 0x80000000L//CP_ME_HEADER_DUMP #define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL//CP_PFP_HEADER_DUMP #define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL//CP_GRBM_FREE_COUNT #define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L//CP_CE_HEADER_DUMP #define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xFFFFFFFFL//CP_PFP_INSTR_PNTR #define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL//CP_ME_INSTR_PNTR #define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL//CP_CE_INSTR_PNTR #define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0#define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL//CP_MEC1_INSTR_PNTR #define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL//CP_MEC2_INSTR_PNTR #define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL//CP_CSF_STAT #define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L//CP_ME_CNTL #define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15#define CP_ME_CNTL__CE_HALT__SHIFT 0x18#define CP_ME_CNTL__CE_STEP__SHIFT 0x19#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L//CP_CNTX_STAT #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L//CP_ME_PREEMPTION #define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L//CP_ROQ_THRESHOLDS #define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L//CP_MEQ_STQ_THRESHOLD #define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL//CP_RB2_RPTR #define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0#define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL//CP_RB1_RPTR #define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0#define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL//CP_RB0_RPTR #define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL//CP_RB_RPTR #define CP_RB_RPTR__RB_RPTR__SHIFT 0x0#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL//CP_RB_WPTR_DELAY #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L//CP_RB_WPTR_POLL_CNTL #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L//CP_ROQ1_THRESHOLDS #define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000FFL#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000FF00L#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00FF0000L#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xFF000000L//CP_ROQ2_THRESHOLDS #define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000FFL#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000FF00L#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xFF000000L//CP_STQ_THRESHOLDS #define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L//CP_QUEUE_THRESHOLDS #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L//CP_MEQ_THRESHOLDS #define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L//CP_ROQ_AVAIL #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007FFL#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07FF0000L//CP_STQ_AVAIL #define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL//CP_ROQ2_AVAIL #define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007FFL//CP_MEQ_AVAIL #define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL//CP_CMD_INDEX #define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L//CP_CMD_DATA #define CP_CMD_DATA__CMD_DATA__SHIFT 0x0#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL//CP_ROQ_RB_STAT #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003FFL#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03FF0000L//CP_ROQ_IB1_STAT #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003FFL#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03FF0000L//CP_ROQ_IB2_STAT #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003FFL#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03FF0000L//CP_STQ_STAT #define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL//CP_STQ_WR_STAT #define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL//CP_MEQ_STAT #define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L//CP_CEQ1_AVAIL #define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007FFL#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07FF0000L//CP_CEQ2_AVAIL #define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007FFL//CP_CE_ROQ_RB_STAT #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003FFL#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03FF0000L//CP_CE_ROQ_IB1_STAT #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003FFL#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03FF0000L//CP_CE_ROQ_IB2_STAT #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003FFL#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03FF0000L//CP_INT_STAT_DEBUG #define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe#define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x00000800L#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L#define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x00040000L#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x00080000L#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x00100000L#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x00200000L#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L// addressBlock: gc_padec //VGT_VTX_VECT_EJECT_REG #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000007FL//VGT_DMA_DATA_FIFO_DEPTH #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001FFL#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x0007FE00L//VGT_DMA_REQ_FIFO_DEPTH #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL//VGT_DRAW_INIT_FIFO_DEPTH #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL//VGT_LAST_COPY_STATE #define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L//VGT_CACHE_INVALIDATION #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L//VGT_RESET_DEBUG #define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2#define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x00000001L#define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x00000002L#define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x00000004L//VGT_STRMOUT_DELAY #define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L//VGT_FIFO_DEPTHS #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x0FC00000L//VGT_GS_VERTEX_REUSE #define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL//VGT_MC_LAT_CNTL #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL//IA_CNTL_STATUS #define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L//VGT_CNTL_STATUS #define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L//WD_CNTL_STATUS #define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3#define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L//CC_GC_PRIM_CONFIG #define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L//GC_USER_PRIM_CONFIG #define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L//WD_QOS #define WD_QOS__DRAW_STALL__SHIFT 0x0#define WD_QOS__DRAW_STALL_MASK 0x00000001L//WD_UTCL1_CNTL #define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L//WD_UTCL1_STATUS #define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L//IA_UTCL1_CNTL #define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L//IA_UTCL1_STATUS #define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L//VGT_SYS_CONFIG #define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L//VGT_VS_MAX_WAVE_ID #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL//VGT_GS_MAX_WAVE_ID #define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL//GFX_PIPE_CONTROL #define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL#define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L//CC_GC_SHADER_ARRAY_CONFIG #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L//GC_USER_SHADER_ARRAY_CONFIG #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L//VGT_DMA_PRIMITIVE_TYPE #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL//VGT_DMA_CONTROL #define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11#define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT 0x15#define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT 0x16#define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT 0x17#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L#define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK 0x00200000L#define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK 0x00400000L#define VGT_DMA_CONTROL__HW_USE_ONLY_MASK 0x00800000L//VGT_DMA_LS_HS_CONFIG #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L//WD_BUF_RESOURCE_1 #define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10#define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L//WD_BUF_RESOURCE_2 #define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0#define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL#define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L//PA_CL_CNTL_STATUS #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L//PA_CL_ENHANCE #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x00000020L#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L//PA_CL_RESET_DEBUG #define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x00000001L//PA_SU_CNTL_STATUS #define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L//PA_SC_FIFO_DEPTH_CNTL #define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL//PA_SC_P3D_TRAP_SCREEN_HV_LOCK #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L//PA_SC_TRAP_SCREEN_HV_LOCK #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L//PA_SC_FORCE_EOV_MAX_CNTS #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L//PA_SC_BINNER_EVENT_CNTL_0 #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L//PA_SC_BINNER_EVENT_CNTL_1 #define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT 0x1a#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK 0x0C000000L#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L//PA_SC_BINNER_EVENT_CNTL_2 #define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT 0x6#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT 0x12#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK 0x000000C0L#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK 0x000C0000L#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L//PA_SC_BINNER_EVENT_CNTL_3 #define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT 0x4#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT 0xc#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT 0x1e#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK 0x00000030L#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK 0x00003000L#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK 0xC0000000L//PA_SC_BINNER_TIMEOUT_COUNTER #define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL//PA_SC_BINNER_PERF_CNTL_0 #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L//PA_SC_BINNER_PERF_CNTL_1 #define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L//PA_SC_BINNER_PERF_CNTL_2 #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L//PA_SC_BINNER_PERF_CNTL_3 #define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL//PA_SC_FIFO_SIZE #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L//PA_SC_IF_FIFO_SIZE #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L//PA_SC_PKR_WAVE_TABLE_CNTL #define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL//PA_UTCL1_CNTL1 #define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2#define PA_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3#define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5#define PA_UTCL1_CNTL1__CLIENTID__SHIFT 0x7#define PA_UTCL1_CNTL1__SPARE__SHIFT 0x10#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12#define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17#define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT 0x19#define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a#define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L#define PA_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L#define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L#define PA_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L#define PA_UTCL1_CNTL1__SPARE_MASK 0x00010000L#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L#define PA_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L#define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK 0x02000000L#define PA_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L#define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L//PA_UTCL1_CNTL2 #define PA_UTCL1_CNTL2__SPARE1__SHIFT 0x0#define PA_UTCL1_CNTL2__SPARE2__SHIFT 0x8#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9#define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa#define PA_UTCL1_CNTL2__SPARE3__SHIFT 0xb#define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT 0xd#define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf#define PA_UTCL1_CNTL2__SPARE4__SHIFT 0x10#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14#define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15#define PA_UTCL1_CNTL2__SPARE5__SHIFT 0x19#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a#define PA_UTCL1_CNTL2__RESERVED__SHIFT 0x1b#define PA_UTCL1_CNTL2__SPARE1_MASK 0x000000FFL#define PA_UTCL1_CNTL2__SPARE2_MASK 0x00000100L#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L#define PA_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L#define PA_UTCL1_CNTL2__SPARE3_MASK 0x00000800L#define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK 0x00002000L#define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L#define PA_UTCL1_CNTL2__SPARE4_MASK 0x00030000L#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L#define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L#define PA_UTCL1_CNTL2__SPARE5_MASK 0x02000000L#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L#define PA_UTCL1_CNTL2__RESERVED_MASK 0xF8000000L//PA_SIDEBAND_REQUEST_DELAYS #define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L//PA_SC_ENHANCE #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L//PA_SC_ENHANCE_1 #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb#define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK__SHIFT 0xc#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xd#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16#define PA_SC_ENHANCE_1__RSVD__SHIFT 0x17#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L#define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK_MASK 0x00001000L#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00002000L#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L#define PA_SC_ENHANCE_1__RSVD_MASK 0xFF800000L//PA_SC_DSM_CNTL #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L//PA_SC_TILE_STEERING_CREST_OVERRIDE #define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L// addressBlock: gc_sqdec //SQ_CONFIG #define SQ_CONFIG__DISABLE_BARRIER_WAITCNT__SHIFT 0x0#define SQ_CONFIG__UNUSED__SHIFT 0x1#define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT 0x7#define SQ_CONFIG__DEBUG_EN__SHIFT 0x8#define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT 0x9#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT 0xa#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT 0x1c#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT 0x1e#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT 0x1f#define SQ_CONFIG__DISABLE_BARRIER_WAITCNT_MASK 0x00000001L#define SQ_CONFIG__UNUSED_MASK 0x0000007EL#define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK 0x00000080L#define SQ_CONFIG__DEBUG_EN_MASK 0x00000100L#define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK 0x00000200L#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK 0x00000400L#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x00010000L#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x00020000L#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK 0x10000000L#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK 0x40000000L#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK 0x80000000L//SQC_CONFIG #define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10#define SQC_CONFIG__INST_PRF_COUNT__SHIFT 0x18#define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT 0x1a#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L#define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L#define SQC_CONFIG__INST_PRF_COUNT_MASK 0x03000000L#define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK 0x04000000L//LDS_CONFIG #define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L//SQ_RANDOM_WAVE_PRI #define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x007FFC00L//SQ_REG_CREDITS #define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003FL#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000F00L#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L//SQ_FIFO_SIZES #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000F00L#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L//SQ_DSM_CNTL #define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L//SQ_DSM_CNTL2 #define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L//SQ_RUNTIME_CONFIG #define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT 0x0#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK 0x00000001L//SH_MEM_BASES #define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L//SH_MEM_CONFIG #define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3#define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0xc#define SH_MEM_CONFIG__PRIVATE_NV__SHIFT 0xd#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000018L#define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00001000L#define SH_MEM_CONFIG__PRIVATE_NV_MASK 0x00002000L//CC_GC_SHADER_RATE_CONFIG #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L//GC_USER_SHADER_RATE_CONFIG #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L//SQ_INTERRUPT_AUTO_MASK #define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL//SQ_INTERRUPT_MSG_CTRL #define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L//SQ_UTCL1_CNTL1 #define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2#define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5#define SQ_UTCL1_CNTL1__CLIENTID__SHIFT 0x7#define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT 0x19#define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L#define SQ_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L#define SQ_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L#define SQ_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK 0x02000000L#define SQ_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L//SQ_UTCL1_CNTL2 #define SQ_UTCL1_CNTL2__SPARE__SHIFT 0x0#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9#define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa#define SQ_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd#define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf#define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT 0x10#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a#define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT 0x1c#define SQ_UTCL1_CNTL2__SPARE_MASK 0x000000FFL#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L#define SQ_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L#define SQ_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L#define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L#define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK 0x007F0000L#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L#define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK 0xF0000000L//SQ_UTCL1_STATUS #define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0#define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1#define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2#define SQ_UTCL1_STATUS__RESERVED__SHIFT 0x3#define SQ_UTCL1_STATUS__UNUSED__SHIFT 0x10#define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L#define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L#define SQ_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L#define SQ_UTCL1_STATUS__RESERVED_MASK 0x0000FFF8L#define SQ_UTCL1_STATUS__UNUSED_MASK 0xFFFF0000L//SQ_SHADER_TBA_LO #define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL//SQ_SHADER_TBA_HI #define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL//SQ_SHADER_TMA_LO #define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL//SQ_SHADER_TMA_HI #define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL//SQC_DSM_CNTL #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x3#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x5#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x9#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0xb#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0xf#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x11#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x12#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000018L#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000020L#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000600L#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000800L#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00018000L#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00020000L#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L//SQC_DSM_CNTLA #define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L//SQC_DSM_CNTLB #define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L//SQC_DSM_CNTL2 #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x2#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x3#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x5#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x9#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0xb#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xe#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0xf#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x11#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x12#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x14#define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000018L#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000020L#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000600L#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000800L#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00018000L#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00020000L#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00100000L#define SQC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L//SQC_DSM_CNTL2A #define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L//SQC_DSM_CNTL2B #define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L//SQC_EDC_FUE_CNTL #define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L//SQC_EDC_CNT2 #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x0#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT 0x2#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0x4#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT 0x6#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x8#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT 0xa#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0xc#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT 0xe#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x12#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT__SHIFT 0x14#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x16#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1a#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1c#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000003L#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK 0x0000000CL#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00000030L#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK 0x000000C0L#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000300L#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK 0x00000C00L#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00003000L#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK 0x0000C000L#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT_MASK 0x000C0000L#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT_MASK 0x00300000L#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT_MASK 0x00C00000L#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 0x0C000000L#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK 0x30000000L//SQC_EDC_CNT3 #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x0#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT 0x2#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0x4#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT 0x6#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x8#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT 0xa#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0xc#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT 0xe#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x12#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT__SHIFT 0x14#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x16#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000003L#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK 0x0000000CL#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00000030L#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK 0x000000C0L#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000300L#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK 0x00000C00L#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00003000L#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK 0x0000C000L#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT_MASK 0x000C0000L#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT_MASK 0x00300000L#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT_MASK 0x00C00000L#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L//SQ_REG_TIMESTAMP #define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL//SQ_CMD_TIMESTAMP #define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL//SQ_IND_INDEX #define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf#define SQ_IND_INDEX__INDEX__SHIFT 0x10#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000FL#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000FC0L#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L//SQ_IND_DATA #define SQ_IND_DATA__DATA__SHIFT 0x0#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL//SQ_CMD #define SQ_CMD__CMD__SHIFT 0x0#define SQ_CMD__MODE__SHIFT 0x4#define SQ_CMD__CHECK_VMID__SHIFT 0x7#define SQ_CMD__DATA__SHIFT 0x8#define SQ_CMD__WAVE_ID__SHIFT 0x10#define SQ_CMD__SIMD_ID__SHIFT 0x14#define SQ_CMD__QUEUE_ID__SHIFT 0x18#define SQ_CMD__VM_ID__SHIFT 0x1c#define SQ_CMD__CMD_MASK 0x00000007L#define SQ_CMD__MODE_MASK 0x00000070L#define SQ_CMD__CHECK_VMID_MASK 0x00000080L#define SQ_CMD__DATA_MASK 0x00000F00L#define SQ_CMD__WAVE_ID_MASK 0x000F0000L#define SQ_CMD__SIMD_ID_MASK 0x00300000L#define SQ_CMD__QUEUE_ID_MASK 0x07000000L#define SQ_CMD__VM_ID_MASK 0xF0000000L//SQ_TIME_HI #define SQ_TIME_HI__TIME__SHIFT 0x0#define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL//SQ_TIME_LO #define SQ_TIME_LO__TIME__SHIFT 0x0#define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL//SQ_DS_0 #define SQ_DS_0__OFFSET0__SHIFT 0x0#define SQ_DS_0__OFFSET1__SHIFT 0x8#define SQ_DS_0__GDS__SHIFT 0x10#define SQ_DS_0__OP__SHIFT 0x11#define SQ_DS_0__ENCODING__SHIFT 0x1a#define SQ_DS_0__OFFSET0_MASK 0x000000FFL#define SQ_DS_0__OFFSET1_MASK 0x0000FF00L#define SQ_DS_0__GDS_MASK 0x00010000L#define SQ_DS_0__OP_MASK 0x01FE0000L#define SQ_DS_0__ENCODING_MASK 0xFC000000L//SQ_DS_1 #define SQ_DS_1__ADDR__SHIFT 0x0#define SQ_DS_1__DATA0__SHIFT 0x8#define SQ_DS_1__DATA1__SHIFT 0x10#define SQ_DS_1__VDST__SHIFT 0x18#define SQ_DS_1__ADDR_MASK 0x000000FFL#define SQ_DS_1__DATA0_MASK 0x0000FF00L#define SQ_DS_1__DATA1_MASK 0x00FF0000L#define SQ_DS_1__VDST_MASK 0xFF000000L//SQ_EXP_0 #define SQ_EXP_0__EN__SHIFT 0x0#define SQ_EXP_0__TGT__SHIFT 0x4#define SQ_EXP_0__COMPR__SHIFT 0xa#define SQ_EXP_0__DONE__SHIFT 0xb#define SQ_EXP_0__VM__SHIFT 0xc#define SQ_EXP_0__ENCODING__SHIFT 0x1a#define SQ_EXP_0__EN_MASK 0x0000000FL#define SQ_EXP_0__TGT_MASK 0x000003F0L#define SQ_EXP_0__COMPR_MASK 0x00000400L#define SQ_EXP_0__DONE_MASK 0x00000800L#define SQ_EXP_0__VM_MASK 0x00001000L#define SQ_EXP_0__ENCODING_MASK 0xFC000000L//SQ_EXP_1 #define SQ_EXP_1__VSRC0__SHIFT 0x0#define SQ_EXP_1__VSRC1__SHIFT 0x8#define SQ_EXP_1__VSRC2__SHIFT 0x10#define SQ_EXP_1__VSRC3__SHIFT 0x18#define SQ_EXP_1__VSRC0_MASK 0x000000FFL#define SQ_EXP_1__VSRC1_MASK 0x0000FF00L#define SQ_EXP_1__VSRC2_MASK 0x00FF0000L#define SQ_EXP_1__VSRC3_MASK 0xFF000000L//SQ_FLAT_0 #define SQ_FLAT_0__OFFSET__SHIFT 0x0#define SQ_FLAT_0__LDS__SHIFT 0xd#define SQ_FLAT_0__SEG__SHIFT 0xe#define SQ_FLAT_0__GLC__SHIFT 0x10#define SQ_FLAT_0__SLC__SHIFT 0x11#define SQ_FLAT_0__OP__SHIFT 0x12#define SQ_FLAT_0__ENCODING__SHIFT 0x1a#define SQ_FLAT_0__OFFSET_MASK 0x00000FFFL#define SQ_FLAT_0__LDS_MASK 0x00002000L#define SQ_FLAT_0__SEG_MASK 0x0000C000L#define SQ_FLAT_0__GLC_MASK 0x00010000L#define SQ_FLAT_0__SLC_MASK 0x00020000L#define SQ_FLAT_0__OP_MASK 0x01FC0000L#define SQ_FLAT_0__ENCODING_MASK 0xFC000000L//SQ_FLAT_1 #define SQ_FLAT_1__ADDR__SHIFT 0x0#define SQ_FLAT_1__DATA__SHIFT 0x8#define SQ_FLAT_1__SADDR__SHIFT 0x10#define SQ_FLAT_1__NV__SHIFT 0x17#define SQ_FLAT_1__VDST__SHIFT 0x18#define SQ_FLAT_1__ADDR_MASK 0x000000FFL#define SQ_FLAT_1__DATA_MASK 0x0000FF00L#define SQ_FLAT_1__SADDR_MASK 0x007F0000L#define SQ_FLAT_1__NV_MASK 0x00800000L#define SQ_FLAT_1__VDST_MASK 0xFF000000L//SQ_GLBL_0 #define SQ_GLBL_0__OFFSET__SHIFT 0x0#define SQ_GLBL_0__LDS__SHIFT 0xd#define SQ_GLBL_0__SEG__SHIFT 0xe#define SQ_GLBL_0__GLC__SHIFT 0x10#define SQ_GLBL_0__SLC__SHIFT 0x11#define SQ_GLBL_0__OP__SHIFT 0x12#define SQ_GLBL_0__ENCODING__SHIFT 0x1a#define SQ_GLBL_0__OFFSET_MASK 0x00001FFFL#define SQ_GLBL_0__LDS_MASK 0x00002000L#define SQ_GLBL_0__SEG_MASK 0x0000C000L#define SQ_GLBL_0__GLC_MASK 0x00010000L#define SQ_GLBL_0__SLC_MASK 0x00020000L#define SQ_GLBL_0__OP_MASK 0x01FC0000L#define SQ_GLBL_0__ENCODING_MASK 0xFC000000L//SQ_GLBL_1 #define SQ_GLBL_1__ADDR__SHIFT 0x0#define SQ_GLBL_1__DATA__SHIFT 0x8#define SQ_GLBL_1__SADDR__SHIFT 0x10#define SQ_GLBL_1__NV__SHIFT 0x17#define SQ_GLBL_1__VDST__SHIFT 0x18#define SQ_GLBL_1__ADDR_MASK 0x000000FFL#define SQ_GLBL_1__DATA_MASK 0x0000FF00L#define SQ_GLBL_1__SADDR_MASK 0x007F0000L#define SQ_GLBL_1__NV_MASK 0x00800000L#define SQ_GLBL_1__VDST_MASK 0xFF000000L//SQ_INST #define SQ_INST__ENCODING__SHIFT 0x0#define SQ_INST__ENCODING_MASK 0xFFFFFFFFL//SQ_MIMG_0 #define SQ_MIMG_0__OPM__SHIFT 0x0#define SQ_MIMG_0__DMASK__SHIFT 0x8#define SQ_MIMG_0__UNORM__SHIFT 0xc#define SQ_MIMG_0__GLC__SHIFT 0xd#define SQ_MIMG_0__DA__SHIFT 0xe#define SQ_MIMG_0__A16__SHIFT 0xf#define SQ_MIMG_0__TFE__SHIFT 0x10#define SQ_MIMG_0__LWE__SHIFT 0x11#define SQ_MIMG_0__OP__SHIFT 0x12#define SQ_MIMG_0__SLC__SHIFT 0x19#define SQ_MIMG_0__ENCODING__SHIFT 0x1a#define SQ_MIMG_0__OPM_MASK 0x00000001L#define SQ_MIMG_0__DMASK_MASK 0x00000F00L#define SQ_MIMG_0__UNORM_MASK 0x00001000L#define SQ_MIMG_0__GLC_MASK 0x00002000L#define SQ_MIMG_0__DA_MASK 0x00004000L#define SQ_MIMG_0__A16_MASK 0x00008000L#define SQ_MIMG_0__TFE_MASK 0x00010000L#define SQ_MIMG_0__LWE_MASK 0x00020000L#define SQ_MIMG_0__OP_MASK 0x01FC0000L#define SQ_MIMG_0__SLC_MASK 0x02000000L#define SQ_MIMG_0__ENCODING_MASK 0xFC000000L//SQ_MIMG_1 #define SQ_MIMG_1__VADDR__SHIFT 0x0#define SQ_MIMG_1__VDATA__SHIFT 0x8#define SQ_MIMG_1__SRSRC__SHIFT 0x10#define SQ_MIMG_1__SSAMP__SHIFT 0x15#define SQ_MIMG_1__D16__SHIFT 0x1f#define SQ_MIMG_1__VADDR_MASK 0x000000FFL#define SQ_MIMG_1__VDATA_MASK 0x0000FF00L#define SQ_MIMG_1__SRSRC_MASK 0x001F0000L#define SQ_MIMG_1__SSAMP_MASK 0x03E00000L#define SQ_MIMG_1__D16_MASK 0x80000000L//SQ_MTBUF_0 #define SQ_MTBUF_0__OFFSET__SHIFT 0x0#define SQ_MTBUF_0__OFFEN__SHIFT 0xc#define SQ_MTBUF_0__IDXEN__SHIFT 0xd#define SQ_MTBUF_0__GLC__SHIFT 0xe#define SQ_MTBUF_0__OP__SHIFT 0xf#define SQ_MTBUF_0__DFMT__SHIFT 0x13#define SQ_MTBUF_0__NFMT__SHIFT 0x17#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a#define SQ_MTBUF_0__OFFSET_MASK 0x00000FFFL#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L#define SQ_MTBUF_0__GLC_MASK 0x00004000L#define SQ_MTBUF_0__OP_MASK 0x00078000L#define SQ_MTBUF_0__DFMT_MASK 0x00780000L#define SQ_MTBUF_0__NFMT_MASK 0x03800000L#define SQ_MTBUF_0__ENCODING_MASK 0xFC000000L//SQ_MTBUF_1 #define SQ_MTBUF_1__VADDR__SHIFT 0x0#define SQ_MTBUF_1__VDATA__SHIFT 0x8#define SQ_MTBUF_1__SRSRC__SHIFT 0x10#define SQ_MTBUF_1__SLC__SHIFT 0x16#define SQ_MTBUF_1__TFE__SHIFT 0x17#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18#define SQ_MTBUF_1__VADDR_MASK 0x000000FFL#define SQ_MTBUF_1__VDATA_MASK 0x0000FF00L#define SQ_MTBUF_1__SRSRC_MASK 0x001F0000L#define SQ_MTBUF_1__SLC_MASK 0x00400000L#define SQ_MTBUF_1__TFE_MASK 0x00800000L#define SQ_MTBUF_1__SOFFSET_MASK 0xFF000000L//SQ_MUBUF_0 #define SQ_MUBUF_0__OFFSET__SHIFT 0x0#define SQ_MUBUF_0__OFFEN__SHIFT 0xc#define SQ_MUBUF_0__IDXEN__SHIFT 0xd#define SQ_MUBUF_0__GLC__SHIFT 0xe#define SQ_MUBUF_0__LDS__SHIFT 0x10#define SQ_MUBUF_0__SLC__SHIFT 0x11#define SQ_MUBUF_0__OP__SHIFT 0x12#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a#define SQ_MUBUF_0__OFFSET_MASK 0x00000FFFL#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L#define SQ_MUBUF_0__GLC_MASK 0x00004000L#define SQ_MUBUF_0__LDS_MASK 0x00010000L#define SQ_MUBUF_0__SLC_MASK 0x00020000L#define SQ_MUBUF_0__OP_MASK 0x01FC0000L#define SQ_MUBUF_0__ENCODING_MASK 0xFC000000L//SQ_MUBUF_1 #define SQ_MUBUF_1__VADDR__SHIFT 0x0#define SQ_MUBUF_1__VDATA__SHIFT 0x8#define SQ_MUBUF_1__SRSRC__SHIFT 0x10#define SQ_MUBUF_1__TFE__SHIFT 0x17#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18#define SQ_MUBUF_1__VADDR_MASK 0x000000FFL#define SQ_MUBUF_1__VDATA_MASK 0x0000FF00L#define SQ_MUBUF_1__SRSRC_MASK 0x001F0000L#define SQ_MUBUF_1__TFE_MASK 0x00800000L#define SQ_MUBUF_1__SOFFSET_MASK 0xFF000000L//SQ_SCRATCH_0 #define SQ_SCRATCH_0__OFFSET__SHIFT 0x0#define SQ_SCRATCH_0__LDS__SHIFT 0xd#define SQ_SCRATCH_0__SEG__SHIFT 0xe#define SQ_SCRATCH_0__GLC__SHIFT 0x10#define SQ_SCRATCH_0__SLC__SHIFT 0x11#define SQ_SCRATCH_0__OP__SHIFT 0x12#define SQ_SCRATCH_0__ENCODING__SHIFT 0x1a#define SQ_SCRATCH_0__OFFSET_MASK 0x00001FFFL#define SQ_SCRATCH_0__LDS_MASK 0x00002000L#define SQ_SCRATCH_0__SEG_MASK 0x0000C000L#define SQ_SCRATCH_0__GLC_MASK 0x00010000L#define SQ_SCRATCH_0__SLC_MASK 0x00020000L#define SQ_SCRATCH_0__OP_MASK 0x01FC0000L#define SQ_SCRATCH_0__ENCODING_MASK 0xFC000000L//SQ_SCRATCH_1 #define SQ_SCRATCH_1__ADDR__SHIFT 0x0#define SQ_SCRATCH_1__DATA__SHIFT 0x8#define SQ_SCRATCH_1__SADDR__SHIFT 0x10#define SQ_SCRATCH_1__NV__SHIFT 0x17#define SQ_SCRATCH_1__VDST__SHIFT 0x18#define SQ_SCRATCH_1__ADDR_MASK 0x000000FFL#define SQ_SCRATCH_1__DATA_MASK 0x0000FF00L#define SQ_SCRATCH_1__SADDR_MASK 0x007F0000L#define SQ_SCRATCH_1__NV_MASK 0x00800000L#define SQ_SCRATCH_1__VDST_MASK 0xFF000000L//SQ_SMEM_0 #define SQ_SMEM_0__SBASE__SHIFT 0x0#define SQ_SMEM_0__SDATA__SHIFT 0x6#define SQ_SMEM_0__SOFFSET_EN__SHIFT 0xe#define SQ_SMEM_0__NV__SHIFT 0xf#define SQ_SMEM_0__GLC__SHIFT 0x10#define SQ_SMEM_0__IMM__SHIFT 0x11#define SQ_SMEM_0__OP__SHIFT 0x12#define SQ_SMEM_0__ENCODING__SHIFT 0x1a#define SQ_SMEM_0__SBASE_MASK 0x0000003FL#define SQ_SMEM_0__SDATA_MASK 0x00001FC0L#define SQ_SMEM_0__SOFFSET_EN_MASK 0x00004000L#define SQ_SMEM_0__NV_MASK 0x00008000L#define SQ_SMEM_0__GLC_MASK 0x00010000L#define SQ_SMEM_0__IMM_MASK 0x00020000L#define SQ_SMEM_0__OP_MASK 0x03FC0000L#define SQ_SMEM_0__ENCODING_MASK 0xFC000000L//SQ_SMEM_1 #define SQ_SMEM_1__OFFSET__SHIFT 0x0#define SQ_SMEM_1__SOFFSET__SHIFT 0x19#define SQ_SMEM_1__OFFSET_MASK 0x001FFFFFL#define SQ_SMEM_1__SOFFSET_MASK 0xFE000000L//SQ_SOP1 #define SQ_SOP1__SSRC0__SHIFT 0x0#define SQ_SOP1__OP__SHIFT 0x8#define SQ_SOP1__SDST__SHIFT 0x10#define SQ_SOP1__ENCODING__SHIFT 0x17#define SQ_SOP1__SSRC0_MASK 0x000000FFL#define SQ_SOP1__OP_MASK 0x0000FF00L#define SQ_SOP1__SDST_MASK 0x007F0000L#define SQ_SOP1__ENCODING_MASK 0xFF800000L//SQ_SOP2 #define SQ_SOP2__SSRC0__SHIFT 0x0#define SQ_SOP2__SSRC1__SHIFT 0x8#define SQ_SOP2__SDST__SHIFT 0x10#define SQ_SOP2__OP__SHIFT 0x17#define SQ_SOP2__ENCODING__SHIFT 0x1e#define SQ_SOP2__SSRC0_MASK 0x000000FFL#define SQ_SOP2__SSRC1_MASK 0x0000FF00L#define SQ_SOP2__SDST_MASK 0x007F0000L#define SQ_SOP2__OP_MASK 0x3F800000L#define SQ_SOP2__ENCODING_MASK 0xC0000000L//SQ_SOPC #define SQ_SOPC__SSRC0__SHIFT 0x0#define SQ_SOPC__SSRC1__SHIFT 0x8#define SQ_SOPC__OP__SHIFT 0x10#define SQ_SOPC__ENCODING__SHIFT 0x17#define SQ_SOPC__SSRC0_MASK 0x000000FFL#define SQ_SOPC__SSRC1_MASK 0x0000FF00L#define SQ_SOPC__OP_MASK 0x007F0000L#define SQ_SOPC__ENCODING_MASK 0xFF800000L//SQ_SOPK #define SQ_SOPK__SIMM16__SHIFT 0x0#define SQ_SOPK__SDST__SHIFT 0x10#define SQ_SOPK__OP__SHIFT 0x17#define SQ_SOPK__ENCODING__SHIFT 0x1c#define SQ_SOPK__SIMM16_MASK 0x0000FFFFL#define SQ_SOPK__SDST_MASK 0x007F0000L#define SQ_SOPK__OP_MASK 0x0F800000L#define SQ_SOPK__ENCODING_MASK 0xF0000000L//SQ_SOPP #define SQ_SOPP__SIMM16__SHIFT 0x0#define SQ_SOPP__OP__SHIFT 0x10#define SQ_SOPP__ENCODING__SHIFT 0x17#define SQ_SOPP__SIMM16_MASK 0x0000FFFFL#define SQ_SOPP__OP_MASK 0x007F0000L#define SQ_SOPP__ENCODING_MASK 0xFF800000L//SQ_VINTRP #define SQ_VINTRP__VSRC__SHIFT 0x0#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8#define SQ_VINTRP__ATTR__SHIFT 0xa#define SQ_VINTRP__OP__SHIFT 0x10#define SQ_VINTRP__VDST__SHIFT 0x12#define SQ_VINTRP__ENCODING__SHIFT 0x1a#define SQ_VINTRP__VSRC_MASK 0x000000FFL#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L#define SQ_VINTRP__ATTR_MASK 0x0000FC00L#define SQ_VINTRP__OP_MASK 0x00030000L#define SQ_VINTRP__VDST_MASK 0x03FC0000L#define SQ_VINTRP__ENCODING_MASK 0xFC000000L//SQ_VOP1 #define SQ_VOP1__SRC0__SHIFT 0x0#define SQ_VOP1__OP__SHIFT 0x9#define SQ_VOP1__VDST__SHIFT 0x11#define SQ_VOP1__ENCODING__SHIFT 0x19#define SQ_VOP1__SRC0_MASK 0x000001FFL#define SQ_VOP1__OP_MASK 0x0001FE00L#define SQ_VOP1__VDST_MASK 0x01FE0000L#define SQ_VOP1__ENCODING_MASK 0xFE000000L//SQ_VOP2 #define SQ_VOP2__SRC0__SHIFT 0x0#define SQ_VOP2__VSRC1__SHIFT 0x9#define SQ_VOP2__VDST__SHIFT 0x11#define SQ_VOP2__OP__SHIFT 0x19#define SQ_VOP2__ENCODING__SHIFT 0x1f#define SQ_VOP2__SRC0_MASK 0x000001FFL#define SQ_VOP2__VSRC1_MASK 0x0001FE00L#define SQ_VOP2__VDST_MASK 0x01FE0000L#define SQ_VOP2__OP_MASK 0x7E000000L#define SQ_VOP2__ENCODING_MASK 0x80000000L//SQ_VOP3P_0 #define SQ_VOP3P_0__VDST__SHIFT 0x0#define SQ_VOP3P_0__NEG_HI__SHIFT 0x8#define SQ_VOP3P_0__OP_SEL__SHIFT 0xb#define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT 0xe#define SQ_VOP3P_0__CLAMP__SHIFT 0xf#define SQ_VOP3P_0__OP__SHIFT 0x10#define SQ_VOP3P_0__ENCODING__SHIFT 0x17#define SQ_VOP3P_0__VDST_MASK 0x000000FFL#define SQ_VOP3P_0__NEG_HI_MASK 0x00000700L#define SQ_VOP3P_0__OP_SEL_MASK 0x00003800L#define SQ_VOP3P_0__OP_SEL_HI_2_MASK 0x00004000L#define SQ_VOP3P_0__CLAMP_MASK 0x00008000L#define SQ_VOP3P_0__OP_MASK 0x007F0000L#define SQ_VOP3P_0__ENCODING_MASK 0xFF800000L//SQ_VOP3P_1 #define SQ_VOP3P_1__SRC0__SHIFT 0x0#define SQ_VOP3P_1__SRC1__SHIFT 0x9#define SQ_VOP3P_1__SRC2__SHIFT 0x12#define SQ_VOP3P_1__OP_SEL_HI__SHIFT 0x1b#define SQ_VOP3P_1__NEG__SHIFT 0x1d#define SQ_VOP3P_1__SRC0_MASK 0x000001FFL#define SQ_VOP3P_1__SRC1_MASK 0x0003FE00L#define SQ_VOP3P_1__SRC2_MASK 0x07FC0000L#define SQ_VOP3P_1__OP_SEL_HI_MASK 0x18000000L#define SQ_VOP3P_1__NEG_MASK 0xE0000000L//SQ_VOP3_0 #define SQ_VOP3_0__VDST__SHIFT 0x0#define SQ_VOP3_0__ABS__SHIFT 0x8#define SQ_VOP3_0__OP_SEL__SHIFT 0xb#define SQ_VOP3_0__CLAMP__SHIFT 0xf#define SQ_VOP3_0__OP__SHIFT 0x10#define SQ_VOP3_0__ENCODING__SHIFT 0x1a#define SQ_VOP3_0__VDST_MASK 0x000000FFL#define SQ_VOP3_0__ABS_MASK 0x00000700L#define SQ_VOP3_0__OP_SEL_MASK 0x00007800L#define SQ_VOP3_0__CLAMP_MASK 0x00008000L#define SQ_VOP3_0__OP_MASK 0x03FF0000L#define SQ_VOP3_0__ENCODING_MASK 0xFC000000L//SQ_VOP3_0_SDST_ENC #define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000FFL#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007F00L#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x00008000L#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03FF0000L#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xFC000000L//SQ_VOP3_1 #define SQ_VOP3_1__SRC0__SHIFT 0x0#define SQ_VOP3_1__SRC1__SHIFT 0x9#define SQ_VOP3_1__SRC2__SHIFT 0x12#define SQ_VOP3_1__OMOD__SHIFT 0x1b#define SQ_VOP3_1__NEG__SHIFT 0x1d#define SQ_VOP3_1__SRC0_MASK 0x000001FFL#define SQ_VOP3_1__SRC1_MASK 0x0003FE00L#define SQ_VOP3_1__SRC2_MASK 0x07FC0000L#define SQ_VOP3_1__OMOD_MASK 0x18000000L#define SQ_VOP3_1__NEG_MASK 0xE0000000L//SQ_VOPC #define SQ_VOPC__SRC0__SHIFT 0x0#define SQ_VOPC__VSRC1__SHIFT 0x9#define SQ_VOPC__OP__SHIFT 0x11#define SQ_VOPC__ENCODING__SHIFT 0x19#define SQ_VOPC__SRC0_MASK 0x000001FFL#define SQ_VOPC__VSRC1_MASK 0x0001FE00L#define SQ_VOPC__OP_MASK 0x01FE0000L#define SQ_VOPC__ENCODING_MASK 0xFE000000L//SQ_VOP_DPP #define SQ_VOP_DPP__SRC0__SHIFT 0x0#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c#define SQ_VOP_DPP__SRC0_MASK 0x000000FFL#define SQ_VOP_DPP__DPP_CTRL_MASK 0x0001FF00L#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x00080000L#define SQ_VOP_DPP__SRC0_NEG_MASK 0x00100000L#define SQ_VOP_DPP__SRC0_ABS_MASK 0x00200000L#define SQ_VOP_DPP__SRC1_NEG_MASK 0x00400000L#define SQ_VOP_DPP__SRC1_ABS_MASK 0x00800000L#define SQ_VOP_DPP__BANK_MASK_MASK 0x0F000000L#define SQ_VOP_DPP__ROW_MASK_MASK 0xF0000000L//SQ_VOP_SDWA #define SQ_VOP_SDWA__SRC0__SHIFT 0x0#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd#define SQ_VOP_SDWA__OMOD__SHIFT 0xe#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15#define SQ_VOP_SDWA__S0__SHIFT 0x17#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d#define SQ_VOP_SDWA__S1__SHIFT 0x1f#define SQ_VOP_SDWA__SRC0_MASK 0x000000FFL#define SQ_VOP_SDWA__DST_SEL_MASK 0x00000700L#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x00001800L#define SQ_VOP_SDWA__CLAMP_MASK 0x00002000L#define SQ_VOP_SDWA__OMOD_MASK 0x0000C000L#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x00070000L#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x00080000L#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x00100000L#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x00200000L#define SQ_VOP_SDWA__S0_MASK 0x00800000L#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x07000000L#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x08000000L#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000L#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000L#define SQ_VOP_SDWA__S1_MASK 0x80000000L//SQ_VOP_SDWA_SDST_ENC #define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT 0x0#define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT 0x8#define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT 0xf#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT 0x10#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT 0x13#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT 0x14#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT 0x15#define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT 0x17#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT 0x18#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT 0x1b#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT 0x1c#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT 0x1d#define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT 0x1f#define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK 0x000000FFL#define SQ_VOP_SDWA_SDST_ENC__SDST_MASK 0x00007F00L#define SQ_VOP_SDWA_SDST_ENC__SD_MASK 0x00008000L#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK 0x00070000L#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK 0x00080000L#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK 0x00100000L#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK 0x00200000L#define SQ_VOP_SDWA_SDST_ENC__S0_MASK 0x00800000L#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK 0x07000000L#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK 0x08000000L#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK 0x10000000L#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK 0x20000000L#define SQ_VOP_SDWA_SDST_ENC__S1_MASK 0x80000000L//SQ_LB_CTR_CTRL #define SQ_LB_CTR_CTRL__START__SHIFT 0x0#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L//SQ_LB_DATA0 #define SQ_LB_DATA0__DATA__SHIFT 0x0#define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL//SQ_LB_DATA1 #define SQ_LB_DATA1__DATA__SHIFT 0x0#define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL//SQ_LB_DATA2 #define SQ_LB_DATA2__DATA__SHIFT 0x0#define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL//SQ_LB_DATA3 #define SQ_LB_DATA3__DATA__SHIFT 0x0#define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL//SQ_LB_CTR_SEL #define SQ_LB_CTR_SEL__SEL0__SHIFT 0x0#define SQ_LB_CTR_SEL__SEL1__SHIFT 0x4#define SQ_LB_CTR_SEL__SEL2__SHIFT 0x8#define SQ_LB_CTR_SEL__SEL3__SHIFT 0xc#define SQ_LB_CTR_SEL__SEL0_MASK 0x0000000FL#define SQ_LB_CTR_SEL__SEL1_MASK 0x000000F0L#define SQ_LB_CTR_SEL__SEL2_MASK 0x00000F00L#define SQ_LB_CTR_SEL__SEL3_MASK 0x0000F000L//SQ_LB_CTR0_CU #define SQ_LB_CTR0_CU__SH0_MASK__SHIFT 0x0#define SQ_LB_CTR0_CU__SH1_MASK__SHIFT 0x10#define SQ_LB_CTR0_CU__SH0_MASK_MASK 0x0000FFFFL#define SQ_LB_CTR0_CU__SH1_MASK_MASK 0xFFFF0000L//SQ_LB_CTR1_CU #define SQ_LB_CTR1_CU__SH0_MASK__SHIFT 0x0#define SQ_LB_CTR1_CU__SH1_MASK__SHIFT 0x10#define SQ_LB_CTR1_CU__SH0_MASK_MASK 0x0000FFFFL#define SQ_LB_CTR1_CU__SH1_MASK_MASK 0xFFFF0000L//SQ_LB_CTR2_CU #define SQ_LB_CTR2_CU__SH0_MASK__SHIFT 0x0#define SQ_LB_CTR2_CU__SH1_MASK__SHIFT 0x10#define SQ_LB_CTR2_CU__SH0_MASK_MASK 0x0000FFFFL#define SQ_LB_CTR2_CU__SH1_MASK_MASK 0xFFFF0000L//SQ_LB_CTR3_CU #define SQ_LB_CTR3_CU__SH0_MASK__SHIFT 0x0#define SQ_LB_CTR3_CU__SH1_MASK__SHIFT 0x10#define SQ_LB_CTR3_CU__SH0_MASK_MASK 0x0000FFFFL#define SQ_LB_CTR3_CU__SH1_MASK_MASK 0xFFFF0000L//SQC_EDC_CNT #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x0#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x2#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x4#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT 0x6#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x8#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT 0xa#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT 0xc#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT 0xe#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x10#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x12#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x14#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT 0x16#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x18#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x1a#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1c#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1e#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000003L#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK 0x0000000CL#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK 0x00000030L#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK 0x000000C0L#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000300L#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK 0x00000C00L#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK 0x00003000L#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK 0x0000C000L#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00030000L#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK 0x000C0000L#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK 0x00300000L#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK 0x00C00000L#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK 0x03000000L#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK 0x0C000000L#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK 0x30000000L#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK 0xC0000000L//SQ_EDC_SEC_CNT #define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0x000000FFL#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0x0000FF00L#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0x00FF0000L//SQ_EDC_DED_CNT #define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10#define SQ_EDC_DED_CNT__LDS_DED_MASK 0x000000FFL#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0x0000FF00L#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0x00FF0000L//SQ_EDC_INFO #define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4#define SQ_EDC_INFO__SOURCE__SHIFT 0x6#define SQ_EDC_INFO__VM_ID__SHIFT 0x9#define SQ_EDC_INFO__WAVE_ID_MASK 0x0000000FL#define SQ_EDC_INFO__SIMD_ID_MASK 0x00000030L#define SQ_EDC_INFO__SOURCE_MASK 0x000001C0L#define SQ_EDC_INFO__VM_ID_MASK 0x00001E00L//SQ_EDC_CNT #define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0#define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2#define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4#define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6#define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8#define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa#define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc#define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe#define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10#define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12#define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14#define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16#define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18#define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a#define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L#define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL#define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L#define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L#define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L#define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L#define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L#define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L#define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L#define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L#define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L#define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L#define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L#define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L//SQ_EDC_FUE_CNTL #define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L//SQ_THREAD_TRACE_WORD_CMN #define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x000FL#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x0010L//SQ_THREAD_TRACE_WORD_EVENT #define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x000FL#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x0010L#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x0020L#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x01C0L#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xFC00L//SQ_THREAD_TRACE_WORD_INST #define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x000FL#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x0010L#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x01E0L#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x0600L#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xF800L//SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT 0xf#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001E0L#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK 0x00008000L#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xFFFF0000L//SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003C0L#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003C00L#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000C000L#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xFFFF0000L//SQ_THREAD_TRACE_WORD_ISSUE #define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000FL#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000C00L#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000C000L#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000C0000L#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00C00000L#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0C000000L//SQ_THREAD_TRACE_WORD_MISC #define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x000FL#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x0FF0L#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000L#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xE000L//SQ_THREAD_TRACE_WORD_PERF_1_OF_2 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003C0L#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000C00L#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01FFF000L#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xFE000000L//SQ_THREAD_TRACE_WORD_REG_1_OF_2 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001C00L#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xFFFF0000L//SQ_THREAD_TRACE_WORD_REG_2_OF_2 #define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xFFFFFFFFL//SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x00000010L#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x00000060L#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x00000180L#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0x0000FE00L#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xFFFF0000L//SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 #define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0x0000FFFFL//SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xFFFF0000L//SQ_THREAD_TRACE_WORD_WAVE #define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x000FL#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x0010L#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x0020L#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x03C0L#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3C00L#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xC000L//SQ_THREAD_TRACE_WORD_WAVE_START #define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000FL#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003C0L#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003C00L#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000C000L#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001F0000L#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1FC00000L#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xE0000000L//SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 #define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00FFFFFFL//SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xFFFFL//SQ_THREAD_TRACE_WORD_PERF_2_OF_2 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003FL#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007FFC0L#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xFFF80000L//SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xFFFFFFFFL//SQ_WREXEC_EXEC_HI #define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x08000000L#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L//SQ_WREXEC_EXEC_LO #define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL//SQ_BUF_RSRC_WORD0 #define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL//SQ_BUF_RSRC_WORD1 #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000FFFFL#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3FFF0000L#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L//SQ_BUF_RSRC_WORD2 #define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xFFFFFFFFL//SQ_BUF_RSRC_WORD3 #define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT 0x13#define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT 0x14#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17#define SQ_BUF_RSRC_WORD3__NV__SHIFT 0x1b#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK 0x00080000L#define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK 0x00100000L#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L#define SQ_BUF_RSRC_WORD3__NV_MASK 0x08000000L#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xC0000000L//SQ_IMG_RSRC_WORD0 #define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL//SQ_IMG_RSRC_WORD1 #define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a#define SQ_IMG_RSRC_WORD1__NV__SHIFT 0x1e#define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT 0x1f#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000FFL#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000FFF00L#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03F00000L#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3C000000L#define SQ_IMG_RSRC_WORD1__NV_MASK 0x40000000L#define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK 0x80000000L//SQ_IMG_RSRC_WORD2 #define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003FFFL#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0FFFC000L#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L//SQ_IMG_RSRC_WORD3 #define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10#define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT 0x14#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000F000L#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000F0000L#define SQ_IMG_RSRC_WORD3__SW_MODE_MASK 0x01F00000L#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xF0000000L//SQ_IMG_RSRC_WORD4 #define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT 0x1d#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001FFFL#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x1FFFE000L#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK 0xE0000000L//SQ_IMG_RSRC_WORD5 #define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT 0xd#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT 0x11#define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT 0x19#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT 0x1a#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT 0x1b#define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT 0x1c#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001FFFL#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK 0x0001E000L#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK 0x01FE0000L#define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK 0x02000000L#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK 0x04000000L#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK 0x08000000L#define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK 0xF0000000L//SQ_IMG_RSRC_WORD6 #define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000FFFL#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000FF000L#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x00200000L#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x00400000L#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x00800000L#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0x0F000000L#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xF0000000L//SQ_IMG_RSRC_WORD7 #define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xFFFFFFFFL//SQ_IMG_SAMP_WORD0 #define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001C0L#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000E00L#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07E00000L#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000L//SQ_IMG_SAMP_WORD1 #define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000FFFL#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00FFF000L#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0F000000L#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xF0000000L//SQ_IMG_SAMP_WORD2 #define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT 0x1d#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003FFFL#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000FC000L#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00C00000L#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0C000000L#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK 0x20000000L#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000L//SQ_IMG_SAMP_WORD3 #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT 0xc#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000FFFL#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK 0x00001000L#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xC0000000L//SQ_FLAT_SCRATCH_WORD0 #define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x0007FFFFL//SQ_FLAT_SCRATCH_WORD1 #define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0x00FFFFFFL//SQ_M0_GPR_IDX_WORD #define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0x000000FFL#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x00001000L#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x00002000L#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x00004000L#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x00008000L//SQC_ICACHE_UTCL1_CNTL1 #define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L//SQC_ICACHE_UTCL1_CNTL2 #define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a#define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L//SQC_DCACHE_UTCL1_CNTL1 #define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L//SQC_DCACHE_UTCL1_CNTL2 #define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a#define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L//SQC_ICACHE_UTCL1_STATUS #define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L//SQC_DCACHE_UTCL1_STATUS #define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L// addressBlock: gc_shsdec //SX_DEBUG_BUSY #define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x0#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x1#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x2#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x3#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x4#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x5#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x6#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x7#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x8#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x9#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0xa#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0xb#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0xc#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0xd#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0xe#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0xf#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x10#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x11#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x12#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x13#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x15#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x16#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x17#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x18#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x19#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x1a#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x1f#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x00000001L#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x00000002L#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x00000004L#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x00000008L#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x00000010L#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x00000020L#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x00000040L#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x00000080L#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x00000100L#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x00000200L#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x00000400L#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x00000800L#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x00001000L#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x00002000L#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x00004000L#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x00008000L#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x00010000L#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x00020000L#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x00040000L#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x00080000L#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x00100000L#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x00200000L#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x00400000L#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x00800000L#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x01000000L#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x02000000L#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x04000000L#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x08000000L#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000L#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000L#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000L#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000L//SX_DEBUG_BUSY_2 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x0#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x2#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x3#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x4#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x5#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x6#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x7#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x8#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x9#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0xa#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0xb#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0xc#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0xd#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0xe#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0xf#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x10#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0x11#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0x12#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0x13#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0x14#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0x15#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0x16#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x17#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x18#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x19#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x1a#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x1b#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x1c#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x1d#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x1e#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x1f#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x00000001L#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x00000002L#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x00000004L#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x00000008L#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x00000010L#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x00000020L#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x00000040L#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x00000080L#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x00000100L#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x00000200L#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x00000400L#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x00000800L#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x00001000L#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x00002000L#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x00004000L#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x00008000L#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x00010000L#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x00020000L#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x00040000L#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x00080000L#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x00100000L#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x00200000L#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x00400000L#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x00800000L#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x01000000L#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x02000000L#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x04000000L#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x08000000L#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x10000000L#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x20000000L#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x40000000L#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x80000000L//SX_DEBUG_BUSY_3 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x0#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x2#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x3#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x4#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x5#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x6#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x7#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x8#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x9#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0xa#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0xb#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0xc#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0xd#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0xe#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0xf#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x10#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0x11#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0x12#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0x13#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0x14#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0x15#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0x16#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x17#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x18#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x19#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x1a#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x1b#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x1c#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x1d#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x1e#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x1f#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x00000001L#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x00000002L#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x00000004L#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x00000008L#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x00000010L#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x00000020L#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x00000040L#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x00000080L#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x00000100L#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x00000200L#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x00000400L#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x00000800L#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x00001000L#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x00002000L#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x00004000L#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x00008000L#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x00010000L#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x00020000L#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x00040000L#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x00080000L#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x00100000L#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x00200000L#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x00400000L#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x00800000L#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x01000000L#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x02000000L#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x04000000L#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x08000000L#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x10000000L#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x20000000L#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x40000000L#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x80000000L//SX_DEBUG_BUSY_4 #define SX_DEBUG_BUSY_4__COL_SCBD_BUSY__SHIFT 0x0#define SX_DEBUG_BUSY_4__COL_REQ3_FREECNT_NE0__SHIFT 0x1#define SX_DEBUG_BUSY_4__COL_REQ3_IDLE__SHIFT 0x2#define SX_DEBUG_BUSY_4__COL_REQ3_BUSY__SHIFT 0x3#define SX_DEBUG_BUSY_4__COL_REQ3_CREDIT_BUSY__SHIFT 0x4#define SX_DEBUG_BUSY_4__COL_REQ2_FREECNT_NE0__SHIFT 0x5#define SX_DEBUG_BUSY_4__COL_REQ2_IDLE__SHIFT 0x6#define SX_DEBUG_BUSY_4__COL_REQ2_BUSY__SHIFT 0x7#define SX_DEBUG_BUSY_4__COL_REQ2_CREDIT_BUSY__SHIFT 0x8#define SX_DEBUG_BUSY_4__COL_REQ1_FREECNT_NE0__SHIFT 0x9#define SX_DEBUG_BUSY_4__COL_REQ1_IDLE__SHIFT 0xa#define SX_DEBUG_BUSY_4__COL_REQ1_BUSY__SHIFT 0xb#define SX_DEBUG_BUSY_4__COL_REQ1_CREDIT_BUSY__SHIFT 0xc#define SX_DEBUG_BUSY_4__COL_REQ0_FREECNT_NE0__SHIFT 0xd#define SX_DEBUG_BUSY_4__COL_REQ0_IDLE__SHIFT 0xe#define SX_DEBUG_BUSY_4__COL_REQ0_BUSY__SHIFT 0xf#define SX_DEBUG_BUSY_4__COL_REQ0_CREDIT_BUSY__SHIFT 0x10#define SX_DEBUG_BUSY_4__COL_DBIF3_SENDFREE_BUSY__SHIFT 0x11#define SX_DEBUG_BUSY_4__COL_DBIF3_FIFO_BUSY__SHIFT 0x12#define SX_DEBUG_BUSY_4__COL_DBIF3_QUAD_FREE__SHIFT 0x13#define SX_DEBUG_BUSY_4__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x14#define SX_DEBUG_BUSY_4__COL_DBIF2_FIFO_BUSY__SHIFT 0x15#define SX_DEBUG_BUSY_4__COL_DBIF2_QUAD_FREE__SHIFT 0x16#define SX_DEBUG_BUSY_4__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x17#define SX_DEBUG_BUSY_4__COL_DBIF1_FIFO_BUSY__SHIFT 0x18#define SX_DEBUG_BUSY_4__COL_DBIF1_QUAD_FREE__SHIFT 0x19#define SX_DEBUG_BUSY_4__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x1a#define SX_DEBUG_BUSY_4__COL_DBIF0_FIFO_BUSY__SHIFT 0x1b#define SX_DEBUG_BUSY_4__COL_DBIF0_QUAD_FREE__SHIFT 0x1c#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1__SHIFT 0x1d#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_ADJ__SHIFT 0x1e#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ2__SHIFT 0x1f#define SX_DEBUG_BUSY_4__COL_SCBD_BUSY_MASK 0x00000001L#define SX_DEBUG_BUSY_4__COL_REQ3_FREECNT_NE0_MASK 0x00000002L#define SX_DEBUG_BUSY_4__COL_REQ3_IDLE_MASK 0x00000004L#define SX_DEBUG_BUSY_4__COL_REQ3_BUSY_MASK 0x00000008L#define SX_DEBUG_BUSY_4__COL_REQ3_CREDIT_BUSY_MASK 0x00000010L#define SX_DEBUG_BUSY_4__COL_REQ2_FREECNT_NE0_MASK 0x00000020L#define SX_DEBUG_BUSY_4__COL_REQ2_IDLE_MASK 0x00000040L#define SX_DEBUG_BUSY_4__COL_REQ2_BUSY_MASK 0x00000080L#define SX_DEBUG_BUSY_4__COL_REQ2_CREDIT_BUSY_MASK 0x00000100L#define SX_DEBUG_BUSY_4__COL_REQ1_FREECNT_NE0_MASK 0x00000200L#define SX_DEBUG_BUSY_4__COL_REQ1_IDLE_MASK 0x00000400L#define SX_DEBUG_BUSY_4__COL_REQ1_BUSY_MASK 0x00000800L#define SX_DEBUG_BUSY_4__COL_REQ1_CREDIT_BUSY_MASK 0x00001000L#define SX_DEBUG_BUSY_4__COL_REQ0_FREECNT_NE0_MASK 0x00002000L#define SX_DEBUG_BUSY_4__COL_REQ0_IDLE_MASK 0x00004000L#define SX_DEBUG_BUSY_4__COL_REQ0_BUSY_MASK 0x00008000L#define SX_DEBUG_BUSY_4__COL_REQ0_CREDIT_BUSY_MASK 0x00010000L#define SX_DEBUG_BUSY_4__COL_DBIF3_SENDFREE_BUSY_MASK 0x00020000L#define SX_DEBUG_BUSY_4__COL_DBIF3_FIFO_BUSY_MASK 0x00040000L#define SX_DEBUG_BUSY_4__COL_DBIF3_QUAD_FREE_MASK 0x00080000L#define SX_DEBUG_BUSY_4__COL_DBIF2_SENDFREE_BUSY_MASK 0x00100000L#define SX_DEBUG_BUSY_4__COL_DBIF2_FIFO_BUSY_MASK 0x00200000L#define SX_DEBUG_BUSY_4__COL_DBIF2_QUAD_FREE_MASK 0x00400000L#define SX_DEBUG_BUSY_4__COL_DBIF1_SENDFREE_BUSY_MASK 0x00800000L#define SX_DEBUG_BUSY_4__COL_DBIF1_FIFO_BUSY_MASK 0x01000000L#define SX_DEBUG_BUSY_4__COL_DBIF1_QUAD_FREE_MASK 0x02000000L#define SX_DEBUG_BUSY_4__COL_DBIF0_SENDFREE_BUSY_MASK 0x04000000L#define SX_DEBUG_BUSY_4__COL_DBIF0_FIFO_BUSY_MASK 0x08000000L#define SX_DEBUG_BUSY_4__COL_DBIF0_QUAD_FREE_MASK 0x10000000L#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_MASK 0x20000000L#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_ADJ_MASK 0x40000000L#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ2_MASK 0x80000000L//SX_DEBUG_BUSY_5 #define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ3__SHIFT 0x0#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ4__SHIFT 0x1#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ5__SHIFT 0x2#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALID_O__SHIFT 0x3#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1__SHIFT 0x4#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_ADJ__SHIFT 0x5#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ2__SHIFT 0x6#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ3__SHIFT 0x7#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ4__SHIFT 0x8#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ5__SHIFT 0x9#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALID_O__SHIFT 0xa#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1__SHIFT 0xb#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_ADJ__SHIFT 0xc#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ2__SHIFT 0xd#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ3__SHIFT 0xe#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ4__SHIFT 0xf#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ5__SHIFT 0x10#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALID_O__SHIFT 0x11#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1__SHIFT 0x12#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_ADJ__SHIFT 0x13#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ2__SHIFT 0x14#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ3__SHIFT 0x15#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ4__SHIFT 0x16#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ5__SHIFT 0x17#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALID_O__SHIFT 0x18#define SX_DEBUG_BUSY_5__RESERVED__SHIFT 0x19#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ3_MASK 0x00000001L#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ4_MASK 0x00000002L#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ5_MASK 0x00000004L#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALID_O_MASK 0x00000008L#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_MASK 0x00000010L#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_ADJ_MASK 0x00000020L#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ2_MASK 0x00000040L#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ3_MASK 0x00000080L#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ4_MASK 0x00000100L#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ5_MASK 0x00000200L#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALID_O_MASK 0x00000400L#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_MASK 0x00000800L#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_ADJ_MASK 0x00001000L#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ2_MASK 0x00002000L#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ3_MASK 0x00004000L#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ4_MASK 0x00008000L#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ5_MASK 0x00010000L#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALID_O_MASK 0x00020000L#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_MASK 0x00040000L#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_ADJ_MASK 0x00080000L#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ2_MASK 0x00100000L#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ3_MASK 0x00200000L#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ4_MASK 0x00400000L#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ5_MASK 0x00800000L#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALID_O_MASK 0x01000000L#define SX_DEBUG_BUSY_5__RESERVED_MASK 0xFE000000L//SX_DEBUG_1 #define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc#define SX_DEBUG_1__PC_CFG__SHIFT 0xd#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0xe#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L#define SX_DEBUG_1__PC_CFG_MASK 0x00002000L#define SX_DEBUG_1__DEBUG_DATA_MASK 0xFFFFC000L//SPI_PS_MAX_WAVE_ID #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L//SPI_START_PHASE #define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x00000003L#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0x0000000CL#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x00000030L//SPI_GFX_CNTL #define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L//SPI_DEBUG_READ #define SPI_DEBUG_READ__DATA__SHIFT 0x0#define SPI_DEBUG_READ__DATA_MASK 0xFFFFFFFFL//SPI_DSM_CNTL #define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L#define SPI_DSM_CNTL__UNUSED_MASK 0xFFFFFFF8L//SPI_DSM_CNTL2 #define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x4#define SPI_DSM_CNTL2__UNUSED__SHIFT 0xa#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000003F0L#define SPI_DSM_CNTL2__UNUSED_MASK 0xFFFFFC00L//SPI_EDC_CNT #define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT 0x0#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK 0x00000003L//SPI_DEBUG_BUSY #define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x0#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x1#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x2#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x3#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x4#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x5#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x6#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x7#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x12#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x13#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x15#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x16#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x17#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x00000001L#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x00000002L#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x00000004L#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x00000008L#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x00000010L#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x00000020L#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x00000040L#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x00000080L#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x00000100L#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x00000200L#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x00000400L#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x00000800L#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x00001000L#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x00002000L#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x00004000L#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x00008000L#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x00010000L#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x00020000L#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x00040000L#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x00080000L#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x00100000L#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x00200000L#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x00400000L#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x00800000L//SPI_CONFIG_PS_CU_EN #define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT 0x0#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT 0x1#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT 0x10#define SPI_CONFIG_PS_CU_EN__ENABLE_MASK 0x00000001L#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK 0x0000FFFEL#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK 0xFFFF0000L//SPI_WF_LIFETIME_CNTL #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L//SPI_WF_LIFETIME_LIMIT_0 #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L//SPI_WF_LIFETIME_LIMIT_1 #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L//SPI_WF_LIFETIME_LIMIT_2 #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L//SPI_WF_LIFETIME_LIMIT_3 #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L//SPI_WF_LIFETIME_LIMIT_4 #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L//SPI_WF_LIFETIME_LIMIT_5 #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L//SPI_WF_LIFETIME_LIMIT_6 #define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L//SPI_WF_LIFETIME_LIMIT_7 #define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L//SPI_WF_LIFETIME_LIMIT_8 #define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L//SPI_WF_LIFETIME_LIMIT_9 #define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_0 #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_1 #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_2 #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_3 #define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_4 #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_5 #define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_6 #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_7 #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_8 #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_9 #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_10 #define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_11 #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_12 #define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_13 #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_14 #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_15 #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_16 #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_17 #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_18 #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_19 #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_STATUS_20 #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L//SPI_WF_LIFETIME_DEBUG #define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7FFFFFFFL#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000L//SPI_LB_CTR_CTRL #define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L//SPI_LB_CU_MASK #define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0#define SPI_LB_CU_MASK__CU_MASK_MASK 0xFFFFL//SPI_LB_DATA_REG #define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL//SPI_PG_ENABLE_STATIC_CU_MASK #define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xFFFFL//SPI_GDS_CREDITS #define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L#define SPI_GDS_CREDITS__UNUSED_MASK 0xFFFF0000L//SPI_SX_EXPORT_BUFFER_SIZES #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L//SPI_SX_SCOREBOARD_BUFFER_SIZES #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L//SPI_CSQ_WF_ACTIVE_STATUS #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL//SPI_CSQ_WF_ACTIVE_COUNT_0 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L//SPI_CSQ_WF_ACTIVE_COUNT_1 #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L//SPI_CSQ_WF_ACTIVE_COUNT_2 #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L//SPI_CSQ_WF_ACTIVE_COUNT_3 #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L//SPI_CSQ_WF_ACTIVE_COUNT_4 #define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000007FFL#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x07FF0000L//SPI_CSQ_WF_ACTIVE_COUNT_5 #define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000007FFL#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x07FF0000L//SPI_CSQ_WF_ACTIVE_COUNT_6 #define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000007FFL#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x07FF0000L//SPI_CSQ_WF_ACTIVE_COUNT_7 #define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000007FFL#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x07FF0000L//SPI_LB_DATA_WAVES #define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L//SPI_LB_DATA_PERCU_WAVE_HSGS #define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT 0x0#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT 0x10#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK 0x0000FFFFL#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK 0xFFFF0000L//SPI_LB_DATA_PERCU_WAVE_VSPS #define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT 0x0#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT 0x10#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK 0x0000FFFFL#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK 0xFFFF0000L//SPI_LB_DATA_PERCU_WAVE_CS #define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT 0x0#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK 0xFFFFL//SPIS_DEBUG_READ #define SPIS_DEBUG_READ__DATA__SHIFT 0x0#define SPIS_DEBUG_READ__DATA_MASK 0xFFFFFFFFL//BCI_DEBUG_READ #define BCI_DEBUG_READ__DATA__SHIFT 0x0#define BCI_DEBUG_READ__DATA_MASK 0xFFFFFFL//SPI_P0_TRAP_SCREEN_PSBA_LO #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL//SPI_P0_TRAP_SCREEN_PSBA_HI #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL//SPI_P0_TRAP_SCREEN_PSMA_LO #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL//SPI_P0_TRAP_SCREEN_PSMA_HI #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL//SPI_P0_TRAP_SCREEN_GPR_MIN #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L//SPI_P1_TRAP_SCREEN_PSBA_LO #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL//SPI_P1_TRAP_SCREEN_PSBA_HI #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL//SPI_P1_TRAP_SCREEN_PSMA_LO #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL//SPI_P1_TRAP_SCREEN_PSMA_HI #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL//SPI_P1_TRAP_SCREEN_GPR_MIN #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L// addressBlock: gc_tpdec //TD_CNTL #define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT__SHIFT 0x18#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT_MASK 0x01000000L//TD_STATUS #define TD_STATUS__BUSY__SHIFT 0x1f#define TD_STATUS__BUSY_MASK 0x80000000L//TD_DSM_CNTL #define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L//TD_DSM_CNTL2 #define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8#define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L#define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L//TD_SCRATCH #define TD_SCRATCH__SCRATCH__SHIFT 0x0#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL//TA_CNTL #define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0#define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x9#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007FL#define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x00001E00L#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000E000L#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L//TA_CNTL_AUX #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0#define TA_CNTL_AUX__RESERVED__SHIFT 0x1#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS__SHIFT 0x9#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT 0x1b#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L#define TA_CNTL_AUX__RESERVED_MASK 0x0000000EL#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS_MASK 0x00000200L#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x00080000L#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK 0x08000000L#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L//TA_RESERVED_010C #define TA_RESERVED_010C__Unused__SHIFT 0x0#define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL//TA_STATUS #define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16#define TA_STATUS__IN_BUSY__SHIFT 0x18#define TA_STATUS__FG_BUSY__SHIFT 0x19#define TA_STATUS__LA_BUSY__SHIFT 0x1a#define TA_STATUS__FL_BUSY__SHIFT 0x1b#define TA_STATUS__TA_BUSY__SHIFT 0x1c#define TA_STATUS__FA_BUSY__SHIFT 0x1d#define TA_STATUS__AL_BUSY__SHIFT 0x1e#define TA_STATUS__BUSY__SHIFT 0x1f#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L#define TA_STATUS__IN_BUSY_MASK 0x01000000L#define TA_STATUS__FG_BUSY_MASK 0x02000000L#define TA_STATUS__LA_BUSY_MASK 0x04000000L#define TA_STATUS__FL_BUSY_MASK 0x08000000L#define TA_STATUS__TA_BUSY_MASK 0x10000000L#define TA_STATUS__FA_BUSY_MASK 0x20000000L#define TA_STATUS__AL_BUSY_MASK 0x40000000L#define TA_STATUS__BUSY_MASK 0x80000000L//TA_SCRATCH #define TA_SCRATCH__SCRATCH__SHIFT 0x0#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL// addressBlock: gc_gdsdec //GDS_CONFIG #define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L//GDS_CNTL_STATUS #define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L//GDS_ENHANCE2 #define GDS_ENHANCE2__MISC__SHIFT 0x0#define GDS_ENHANCE2__UNUSED__SHIFT 0x10#define GDS_ENHANCE2__MISC_MASK 0x0000FFFFL#define GDS_ENHANCE2__UNUSED_MASK 0xFFFF0000L//GDS_PROTECTION_FAULT #define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L#define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L//GDS_VM_PROTECTION_FAULT #define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4#define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT 0x5#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L#define GDS_VM_PROTECTION_FAULT__TMZ_MASK 0x00000020L#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L//GDS_EDC_CNT #define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT 0x2#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4#define GDS_EDC_CNT__UNUSED__SHIFT 0x6#define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK 0x0000000CL#define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L#define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L//GDS_EDC_GRBM_CNT #define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4#define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L#define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL#define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L//GDS_EDC_OA_DED
Messung V0.5 in Prozent C=91 H=100 G=95
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