/* * GFX_8_0 Register documentation * * Copyright (C) 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef GFX_8_0_ENUM_H#define GFX_8_0_ENUM_Htypedef enum SurfaceNumber {typedef enum SurfaceSwap {typedef enum CBMode {typedef enum RoundMode {typedef enum SourceFormat {typedef enum BlendOp {typedef enum CombFunc {typedef enum BlendOpt {typedef enum CmaskCode {typedef enum CmaskAddr {typedef enum CBPerfSel {= 0x112,= 0x113,typedef enum CBPerfOpFilterSel {typedef enum CBPerfClearFilterSel {typedef enum CP_RING_ID {typedef enum CP_PIPE_ID {typedef enum CP_ME_ID {typedef enum SPM_PERFMON_STATE {typedef enum CP_PERFMON_STATE {typedef enum CP_PERFMON_ENABLE_MODE {typedef enum CPG_PERFCOUNT_SEL {typedef enum CPF_PERFCOUNT_SEL {typedef enum CPC_PERFCOUNT_SEL {typedef enum CP_ALPHA_TAG_RAM_SEL {#define SEM_ECC_ERROR 0x0#define SEM_RESERVED 0x1#define SEM_FAILED 0x2#define SEM_PASSED 0x3#define IQ_QUEUE_SLEEP 0x0#define IQ_OFFLOAD_RETRY 0x1#define IQ_SCH_WAVE_MSG 0x2#define IQ_SEM_REARM 0x3#define IQ_DEQUEUE_RETRY 0x4#define IQ_INTR_TYPE_PQ 0x0#define IQ_INTR_TYPE_IB 0x1#define IQ_INTR_TYPE_MQD 0x2#define VMID_SZ 0x4#define CONFIG_SPACE_START 0x2000#define CONFIG_SPACE_END 0x9fff#define CONFIG_SPACE1_START 0x2000#define CONFIG_SPACE1_END 0x2bff#define CONFIG_SPACE2_START 0x3000#define CONFIG_SPACE2_END 0x9fff#define UCONFIG_SPACE_START 0xc000#define UCONFIG_SPACE_END 0xffff#define PERSISTENT_SPACE_START 0x2c00#define PERSISTENT_SPACE_END 0x2fff#define CONTEXT_SPACE_START 0xa000#define CONTEXT_SPACE_END 0xbffftypedef enum ForceControl {typedef enum ZSamplePosition {typedef enum ZOrder {typedef enum ZpassControl {typedef enum ZModeForce {typedef enum ZLimitSumm {typedef enum CompareFrag {typedef enum StencilOp {typedef enum ConservativeZExport {typedef enum DbPSLControl {typedef enum PerfCounter_Vals {typedef enum RingCounterControl {typedef enum PixelPipeCounterId {typedef enum PixelPipeStride {typedef enum GB_EDC_DED_MODE {#define GB_TILING_CONFIG_TABLE_SIZE 0x20#define GB_TILING_CONFIG_MACROTABLE_SIZE 0x10typedef enum GRBM_PERF_SEL {typedef enum GRBM_SE0_PERF_SEL {typedef enum GRBM_SE1_PERF_SEL {typedef enum GRBM_SE2_PERF_SEL {typedef enum GRBM_SE3_PERF_SEL {typedef enum SU_PERFCNT_SEL {typedef enum SC_PERFCNT_SEL {typedef enum SePairXsel {typedef enum SePairYsel {typedef enum SePairMap {typedef enum SeXsel {typedef enum SeYsel {typedef enum SeMap {typedef enum ScXsel {typedef enum ScYsel {typedef enum ScMap {typedef enum PkrXsel2 {typedef enum PkrXsel {typedef enum PkrYsel {typedef enum PkrMap {typedef enum RbXsel {typedef enum RbYsel {typedef enum RbXsel2 {typedef enum RbMap {typedef enum CSDATA_TYPE {#define CSDATA_TYPE_WIDTH 0x2#define CSDATA_ADDR_WIDTH 0x7#define CSDATA_DATA_WIDTH 0x20typedef enum SPI_SAMPLE_CNTL {typedef enum SPI_FOG_MODE {typedef enum SPI_PNT_SPRITE_OVERRIDE {typedef enum SPI_PERFCNT_SEL {typedef enum SPI_SHADER_FORMAT {typedef enum SPI_SHADER_EX_FORMAT {typedef enum CLKGATE_SM_MODE {typedef enum CLKGATE_BASE_MODE {typedef enum SQ_TEX_CLAMP {typedef enum SQ_TEX_XY_FILTER {typedef enum SQ_TEX_Z_FILTER {typedef enum SQ_TEX_MIP_FILTER {typedef enum SQ_TEX_ANISO_RATIO {typedef enum SQ_TEX_DEPTH_COMPARE {typedef enum SQ_TEX_BORDER_COLOR {typedef enum SQ_RSRC_BUF_TYPE {typedef enum SQ_RSRC_IMG_TYPE {typedef enum SQ_RSRC_FLAT_TYPE {typedef enum SQ_IMG_FILTER_TYPE {typedef enum SQ_SEL_XYZW01 {typedef enum SQ_WAVE_TYPE {typedef enum SQ_THREAD_TRACE_TOKEN_TYPE {typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE {typedef enum SQ_THREAD_TRACE_INST_TYPE {typedef enum SQ_THREAD_TRACE_REG_TYPE {typedef enum SQ_THREAD_TRACE_REG_OP {typedef enum SQ_THREAD_TRACE_MODE_SEL {typedef enum SQ_THREAD_TRACE_CAPTURE_MODE {typedef enum SQ_THREAD_TRACE_VM_ID_MASK {typedef enum SQ_THREAD_TRACE_WAVE_MASK {typedef enum SQ_THREAD_TRACE_ISSUE {typedef enum SQ_THREAD_TRACE_ISSUE_MASK {typedef enum SQ_PERF_SEL {typedef enum SQ_CAC_POWER_SEL {typedef enum SQ_IND_CMD_CMD {typedef enum SQ_IND_CMD_MODE {typedef enum SQ_EDC_INFO_SOURCE {typedef enum SQ_ROUND_MODE {typedef enum SQ_INTERRUPT_WORD_ENCODING {typedef enum ENUM_SQ_EXPORT_RAT_INST {typedef enum SQ_IBUF_ST {typedef enum SQ_INST_STR_ST {typedef enum SQ_WAVE_IB_ECC_ST {typedef enum SH_MEM_ADDRESS_MODE {typedef enum SH_MEM_ALIGNMENT_MODE {typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX {#define SQ_WAVE_TYPE_PS0 0x0#define SQIND_GLOBAL_REGS_OFFSET 0x0#define SQIND_GLOBAL_REGS_SIZE 0x8#define SQIND_LOCAL_REGS_OFFSET 0x8#define SQIND_LOCAL_REGS_SIZE 0x8#define SQIND_WAVE_HWREGS_OFFSET 0x10#define SQIND_WAVE_HWREGS_SIZE 0x1f0#define SQIND_WAVE_SGPRS_OFFSET 0x200#define SQIND_WAVE_SGPRS_SIZE 0x200#define SQ_GFXDEC_BEGIN 0xa000#define SQ_GFXDEC_END 0xc000#define SQ_GFXDEC_STATE_ID_SHIFT 0xa#define SQDEC_BEGIN 0x2300#define SQDEC_END 0x23ff#define SQPERFSDEC_BEGIN 0xd9c0#define SQPERFSDEC_END 0xda40#define SQPERFDDEC_BEGIN 0xd1c0#define SQPERFDDEC_END 0xd240#define SQGFXUDEC_BEGIN 0xc330#define SQGFXUDEC_END 0xc380#define SQPWRDEC_BEGIN 0xf08c#define SQPWRDEC_END 0xf094#define SQ_DISPATCHER_GFX_MIN 0x10#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x8#define SQ_MAX_PGM_SGPRS 0x68#define SQ_MAX_PGM_VGPRS 0x100#define SQ_THREAD_TRACE_TIME_UNIT 0x4#define SQ_EX_MODE_EXCP_VALU_BASE 0x0#define SQ_EX_MODE_EXCP_VALU_SIZE 0x7#define SQ_EX_MODE_EXCP_INVALID 0x0#define SQ_EX_MODE_EXCP_INPUT_DENORM 0x1#define SQ_EX_MODE_EXCP_DIV0 0x2#define SQ_EX_MODE_EXCP_OVERFLOW 0x3#define SQ_EX_MODE_EXCP_UNDERFLOW 0x4#define SQ_EX_MODE_EXCP_INEXACT 0x5#define SQ_EX_MODE_EXCP_INT_DIV0 0x6#define SQ_EX_MODE_EXCP_ADDR_WATCH 0x7#define SQ_EX_MODE_EXCP_MEM_VIOL 0x8#define INST_ID_PRIV_START 0x80000000#define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0#define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1#define INST_ID_HW_TRAP 0xfffffff2#define INST_ID_KILL_SEQ 0xfffffff3#define INST_ID_SPI_WREXEC 0xfffffff4#define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe#define SQ_ENC_SOP1_BITS 0xbe800000#define SQ_ENC_SOP1_MASK 0xff800000#define SQ_ENC_SOP1_FIELD 0x17d#define SQ_ENC_SOPC_BITS 0xbf000000#define SQ_ENC_SOPC_MASK 0xff800000#define SQ_ENC_SOPC_FIELD 0x17e#define SQ_ENC_SOPP_BITS 0xbf800000#define SQ_ENC_SOPP_MASK 0xff800000#define SQ_ENC_SOPP_FIELD 0x17f#define SQ_ENC_SOPK_BITS 0xb0000000#define SQ_ENC_SOPK_MASK 0xf0000000#define SQ_ENC_SOPK_FIELD 0xb#define SQ_ENC_SOP2_BITS 0x80000000#define SQ_ENC_SOP2_MASK 0xc0000000#define SQ_ENC_SOP2_FIELD 0x2#define SQ_ENC_SMEM_BITS 0xc0000000#define SQ_ENC_SMEM_MASK 0xfc000000#define SQ_ENC_SMEM_FIELD 0x30#define SQ_ENC_VOP1_BITS 0x7e000000#define SQ_ENC_VOP1_MASK 0xfe000000#define SQ_ENC_VOP1_FIELD 0x3f#define SQ_ENC_VOPC_BITS 0x7c000000#define SQ_ENC_VOPC_MASK 0xfe000000#define SQ_ENC_VOPC_FIELD 0x3e#define SQ_ENC_VOP2_BITS 0x0#define SQ_ENC_VOP2_MASK 0x80000000#define SQ_ENC_VOP2_FIELD 0x0#define SQ_ENC_VINTRP_BITS 0xd4000000#define SQ_ENC_VINTRP_MASK 0xfc000000#define SQ_ENC_VINTRP_FIELD 0x35#define SQ_ENC_VOP3_BITS 0xd0000000#define SQ_ENC_VOP3_MASK 0xfc000000#define SQ_ENC_VOP3_FIELD 0x34#define SQ_ENC_DS_BITS 0xd8000000#define SQ_ENC_DS_MASK 0xfc000000#define SQ_ENC_DS_FIELD 0x36#define SQ_ENC_MUBUF_BITS 0xe0000000#define SQ_ENC_MUBUF_MASK 0xfc000000#define SQ_ENC_MUBUF_FIELD 0x38#define SQ_ENC_MTBUF_BITS 0xe8000000#define SQ_ENC_MTBUF_MASK 0xfc000000#define SQ_ENC_MTBUF_FIELD 0x3a#define SQ_ENC_MIMG_BITS 0xf0000000#define SQ_ENC_MIMG_MASK 0xfc000000#define SQ_ENC_MIMG_FIELD 0x3c#define SQ_ENC_EXP_BITS 0xc4000000#define SQ_ENC_EXP_MASK 0xfc000000#define SQ_ENC_EXP_FIELD 0x31#define SQ_ENC_FLAT_BITS 0xdc000000#define SQ_ENC_FLAT_MASK 0xfc000000#define SQ_ENC_FLAT_FIELD 0x37#define SQ_V_OP3_INTRP_OFFSET 0x274#define SQ_WAITCNT_VM_SHIFT 0x0#define SQ_SENDMSG_STREAMID_SIZE 0x2#define SQ_V_OPC_COUNT 0x100#define SQ_V_OP3_INTRP_COUNT 0xc#define SQ_XLATE_VOP3_TO_VOP2_OFFSET 0x100#define SQ_HWREG_OFFSET_SIZE 0x5#define SQ_HWREG_OFFSET_SHIFT 0x6#define SQ_V_OP3_3IN_OFFSET 0x1c0#define SQ_NUM_ATTR 0x21#define SQ_NUM_VGPR 0x100#define SQ_XLATE_VOP3_TO_VINTRP_COUNT 0x4#define SQ_SENDMSG_MSG_SIZE 0x4#define SQ_NUM_TTMP 0xc#define SQ_HWREG_ID_SIZE 0x6#define SQ_SENDMSG_GSOP_SIZE 0x2#define SQ_NUM_SGPR 0x66#define SQ_EXP_NUM_MRT 0x8#define SQ_SENDMSG_SYSTEM_SIZE 0x3#define SQ_WAITCNT_LGKM_SHIFT 0x8#define SQ_XLATE_VOP3_TO_VOP2_COUNT 0x40#define SQ_V_OP3_3IN_COUNT 0xb0#define SQ_V_INTRP_COUNT 0x4#define SQ_WAITCNT_EXP_SIZE 0x3#define SQ_SENDMSG_SYSTEM_SHIFT 0x4#define SQ_EXP_NUM_GDS 0x5#define SQ_HWREG_SIZE_SHIFT 0xb#define SQ_XLATE_VOP3_TO_VOPC_OFFSET 0x0#define SQ_V_OP3_2IN_COUNT 0x80#define SQ_XLATE_VOP3_TO_VINTRP_OFFSET 0x270#define SQ_SENDMSG_MSG_SHIFT 0x0#define SQ_WAITCNT_EXP_SHIFT 0x4#define SQ_WAITCNT_VM_SIZE 0x4#define SQ_XLATE_VOP3_TO_VOP1_OFFSET 0x140#define SQ_SENDMSG_GSOP_SHIFT 0x4#define SQ_XLATE_VOP3_TO_VOP1_COUNT 0x80#define SQ_SRC_VGPR_BIT 0x100#define SQ_V_OP2_COUNT 0x40#define SQ_EXP_NUM_PARAM 0x20#define SQ_V_OP1_COUNT 0x80#define SQ_SENDMSG_STREAMID_SHIFT 0x8#define SQ_V_OP3_2IN_OFFSET 0x280#define SQ_WAITCNT_LGKM_SIZE 0x4#define SQ_XLATE_VOP3_TO_VOPC_COUNT 0x100#define SQ_EXP_NUM_POS 0x4#define SQ_HWREG_SIZE_SIZE 0x5#define SQ_HWREG_ID_SHIFT 0x0#define SQ_S_MOV_B32 0x0#define SQ_S_MOV_B64 0x1#define SQ_S_CMOV_B32 0x2#define SQ_S_CMOV_B64 0x3#define SQ_S_NOT_B32 0x4#define SQ_S_NOT_B64 0x5#define SQ_S_WQM_B32 0x6#define SQ_S_WQM_B64 0x7#define SQ_S_BREV_B32 0x8#define SQ_S_BREV_B64 0x9#define SQ_S_BCNT0_I32_B32 0xa#define SQ_S_BCNT0_I32_B64 0xb#define SQ_S_BCNT1_I32_B32 0xc#define SQ_S_BCNT1_I32_B64 0xd#define SQ_S_FF0_I32_B32 0xe#define SQ_S_FF0_I32_B64 0xf#define SQ_S_FF1_I32_B32 0x10#define SQ_S_FF1_I32_B64 0x11#define SQ_S_FLBIT_I32_B32 0x12#define SQ_S_FLBIT_I32_B64 0x13#define SQ_S_FLBIT_I32 0x14#define SQ_S_FLBIT_I32_I64 0x15#define SQ_S_SEXT_I32_I8 0x16#define SQ_S_SEXT_I32_I16 0x17#define SQ_S_BITSET0_B32 0x18#define SQ_S_BITSET0_B64 0x19#define SQ_S_BITSET1_B32 0x1a#define SQ_S_BITSET1_B64 0x1b#define SQ_S_GETPC_B64 0x1c#define SQ_S_SETPC_B64 0x1d#define SQ_S_SWAPPC_B64 0x1e#define SQ_S_RFE_B64 0x1f#define SQ_S_AND_SAVEEXEC_B64 0x20#define SQ_S_OR_SAVEEXEC_B64 0x21#define SQ_S_XOR_SAVEEXEC_B64 0x22#define SQ_S_ANDN2_SAVEEXEC_B64 0x23#define SQ_S_ORN2_SAVEEXEC_B64 0x24#define SQ_S_NAND_SAVEEXEC_B64 0x25#define SQ_S_NOR_SAVEEXEC_B64 0x26#define SQ_S_XNOR_SAVEEXEC_B64 0x27#define SQ_S_QUADMASK_B32 0x28#define SQ_S_QUADMASK_B64 0x29#define SQ_S_MOVRELS_B32 0x2a#define SQ_S_MOVRELS_B64 0x2b#define SQ_S_MOVRELD_B32 0x2c#define SQ_S_MOVRELD_B64 0x2d#define SQ_S_CBRANCH_JOIN 0x2e#define SQ_S_MOV_REGRD_B32 0x2f#define SQ_S_ABS_I32 0x30#define SQ_S_MOV_FED_B32 0x31#define SQ_S_SET_GPR_IDX_IDX 0x32#define SQ_ATTR0 0x0#define SQ_S_MOVK_I32 0x0#define SQ_S_CMOVK_I32 0x1#define SQ_S_CMPK_EQ_I32 0x2#define SQ_S_CMPK_LG_I32 0x3#define SQ_S_CMPK_GT_I32 0x4#define SQ_S_CMPK_GE_I32 0x5#define SQ_S_CMPK_LT_I32 0x6#define SQ_S_CMPK_LE_I32 0x7#define SQ_S_CMPK_EQ_U32 0x8#define SQ_S_CMPK_LG_U32 0x9#define SQ_S_CMPK_GT_U32 0xa#define SQ_S_CMPK_GE_U32 0xb#define SQ_S_CMPK_LT_U32 0xc#define SQ_S_CMPK_LE_U32 0xd#define SQ_S_ADDK_I32 0xe#define SQ_S_MULK_I32 0xf#define SQ_S_CBRANCH_I_FORK 0x10#define SQ_S_GETREG_B32 0x11#define SQ_S_SETREG_B32 0x12#define SQ_S_GETREG_REGRD_B32 0x13#define SQ_S_SETREG_IMM32_B32 0x14#define SQ_TBA_LO 0x6c#define SQ_TBA_HI 0x6d#define SQ_TMA_LO 0x6e#define SQ_TMA_HI 0x6f#define SQ_TTMP0 0x70#define SQ_TTMP1 0x71#define SQ_TTMP2 0x72#define SQ_TTMP3 0x73#define SQ_TTMP4 0x74#define SQ_TTMP5 0x75#define SQ_TTMP6 0x76#define SQ_TTMP7 0x77#define SQ_TTMP8 0x78#define SQ_TTMP9 0x79#define SQ_TTMP10 0x7a#define SQ_TTMP11 0x7b#define SQ_VGPR0 0x0#define SQ_EXP 0x0#define SQ_EXP_MRT0 0x0#define SQ_EXP_MRTZ 0x8#define SQ_EXP_NULL 0x9#define SQ_EXP_POS0 0xc#define SQ_EXP_PARAM0 0x20#define SQ_CNT1 0x0#define SQ_CNT2 0x1#define SQ_CNT3 0x2#define SQ_CNT4 0x3#define SQ_S_LOAD_DWORD 0x0#define SQ_S_LOAD_DWORDX2 0x1#define SQ_S_LOAD_DWORDX4 0x2#define SQ_S_LOAD_DWORDX8 0x3#define SQ_S_LOAD_DWORDX16 0x4#define SQ_S_BUFFER_LOAD_DWORD 0x8#define SQ_S_BUFFER_LOAD_DWORDX2 0x9#define SQ_S_BUFFER_LOAD_DWORDX4 0xa#define SQ_S_BUFFER_LOAD_DWORDX8 0xb#define SQ_S_BUFFER_LOAD_DWORDX16 0xc#define SQ_S_STORE_DWORD 0x10#define SQ_S_STORE_DWORDX2 0x11#define SQ_S_STORE_DWORDX4 0x12#define SQ_S_BUFFER_STORE_DWORD 0x18#define SQ_S_BUFFER_STORE_DWORDX2 0x19#define SQ_S_BUFFER_STORE_DWORDX4 0x1a#define SQ_S_DCACHE_INV 0x20#define SQ_S_DCACHE_WB 0x21#define SQ_S_DCACHE_INV_VOL 0x22#define SQ_S_DCACHE_WB_VOL 0x23#define SQ_S_MEMTIME 0x24#define SQ_S_MEMREALTIME 0x25#define SQ_S_ATC_PROBE 0x26#define SQ_S_ATC_PROBE_BUFFER 0x27#define SQ_S_BUFFER_ATOMIC_SWAP 0x40#define SQ_S_BUFFER_ATOMIC_CMPSWAP 0x41#define SQ_S_BUFFER_ATOMIC_ADD 0x42#define SQ_S_BUFFER_ATOMIC_SUB 0x43#define SQ_S_BUFFER_ATOMIC_SMIN 0x44#define SQ_S_BUFFER_ATOMIC_UMIN 0x45#define SQ_S_BUFFER_ATOMIC_SMAX 0x46#define SQ_S_BUFFER_ATOMIC_UMAX 0x47#define SQ_S_BUFFER_ATOMIC_AND 0x48#define SQ_S_BUFFER_ATOMIC_OR 0x49#define SQ_S_BUFFER_ATOMIC_XOR 0x4a#define SQ_S_BUFFER_ATOMIC_INC 0x4b#define SQ_S_BUFFER_ATOMIC_DEC 0x4c#define SQ_S_BUFFER_ATOMIC_SWAP_X2 0x60#define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2 0x61#define SQ_S_BUFFER_ATOMIC_ADD_X2 0x62#define SQ_S_BUFFER_ATOMIC_SUB_X2 0x63#define SQ_S_BUFFER_ATOMIC_SMIN_X2 0x64#define SQ_S_BUFFER_ATOMIC_UMIN_X2 0x65#define SQ_S_BUFFER_ATOMIC_SMAX_X2 0x66#define SQ_S_BUFFER_ATOMIC_UMAX_X2 0x67#define SQ_S_BUFFER_ATOMIC_AND_X2 0x68#define SQ_S_BUFFER_ATOMIC_OR_X2 0x69#define SQ_S_BUFFER_ATOMIC_XOR_X2 0x6a#define SQ_S_BUFFER_ATOMIC_INC_X2 0x6b#define SQ_S_BUFFER_ATOMIC_DEC_X2 0x6c#define SQ_F 0x0#define SQ_LT 0x1#define SQ_EQ 0x2#define SQ_LE 0x3#define SQ_GT 0x4#define SQ_LG 0x5#define SQ_GE 0x6#define SQ_O 0x7#define SQ_U 0x8#define SQ_NGE 0x9#define SQ_NLG 0xa#define SQ_NGT 0xb#define SQ_NLE 0xc#define SQ_NEQ 0xd#define SQ_NLT 0xe#define SQ_TRU 0xf#define SQ_V_CMP_CLASS_F32 0x10#define SQ_V_CMPX_CLASS_F32 0x11#define SQ_V_CMP_CLASS_F64 0x12#define SQ_V_CMPX_CLASS_F64 0x13#define SQ_V_CMP_CLASS_F16 0x14#define SQ_V_CMPX_CLASS_F16 0x15#define SQ_V_CMP_F_F16 0x20#define SQ_V_CMP_LT_F16 0x21#define SQ_V_CMP_EQ_F16 0x22#define SQ_V_CMP_LE_F16 0x23#define SQ_V_CMP_GT_F16 0x24#define SQ_V_CMP_LG_F16 0x25#define SQ_V_CMP_GE_F16 0x26#define SQ_V_CMP_O_F16 0x27#define SQ_V_CMP_U_F16 0x28#define SQ_V_CMP_NGE_F16 0x29#define SQ_V_CMP_NLG_F16 0x2a#define SQ_V_CMP_NGT_F16 0x2b#define SQ_V_CMP_NLE_F16 0x2c#define SQ_V_CMP_NEQ_F16 0x2d#define SQ_V_CMP_NLT_F16 0x2e#define SQ_V_CMP_TRU_F16 0x2f#define SQ_V_CMPX_F_F16 0x30#define SQ_V_CMPX_LT_F16 0x31#define SQ_V_CMPX_EQ_F16 0x32#define SQ_V_CMPX_LE_F16 0x33#define SQ_V_CMPX_GT_F16 0x34#define SQ_V_CMPX_LG_F16 0x35#define SQ_V_CMPX_GE_F16 0x36#define SQ_V_CMPX_O_F16 0x37#define SQ_V_CMPX_U_F16 0x38#define SQ_V_CMPX_NGE_F16 0x39#define SQ_V_CMPX_NLG_F16 0x3a#define SQ_V_CMPX_NGT_F16 0x3b#define SQ_V_CMPX_NLE_F16 0x3c#define SQ_V_CMPX_NEQ_F16 0x3d#define SQ_V_CMPX_NLT_F16 0x3e#define SQ_V_CMPX_TRU_F16 0x3f#define SQ_V_CMP_F_F32 0x40#define SQ_V_CMP_LT_F32 0x41#define SQ_V_CMP_EQ_F32 0x42#define SQ_V_CMP_LE_F32 0x43#define SQ_V_CMP_GT_F32 0x44#define SQ_V_CMP_LG_F32 0x45#define SQ_V_CMP_GE_F32 0x46#define SQ_V_CMP_O_F32 0x47#define SQ_V_CMP_U_F32 0x48#define SQ_V_CMP_NGE_F32 0x49#define SQ_V_CMP_NLG_F32 0x4a#define SQ_V_CMP_NGT_F32 0x4b#define SQ_V_CMP_NLE_F32 0x4c#define SQ_V_CMP_NEQ_F32 0x4d#define SQ_V_CMP_NLT_F32 0x4e#define SQ_V_CMP_TRU_F32 0x4f#define SQ_V_CMPX_F_F32 0x50#define SQ_V_CMPX_LT_F32 0x51#define SQ_V_CMPX_EQ_F32 0x52#define SQ_V_CMPX_LE_F32 0x53#define SQ_V_CMPX_GT_F32 0x54#define SQ_V_CMPX_LG_F32 0x55#define SQ_V_CMPX_GE_F32 0x56#define SQ_V_CMPX_O_F32 0x57#define SQ_V_CMPX_U_F32 0x58#define SQ_V_CMPX_NGE_F32 0x59#define SQ_V_CMPX_NLG_F32 0x5a#define SQ_V_CMPX_NGT_F32 0x5b#define SQ_V_CMPX_NLE_F32 0x5c#define SQ_V_CMPX_NEQ_F32 0x5d#define SQ_V_CMPX_NLT_F32 0x5e#define SQ_V_CMPX_TRU_F32 0x5f#define SQ_V_CMP_F_F64 0x60#define SQ_V_CMP_LT_F64 0x61#define SQ_V_CMP_EQ_F64 0x62#define SQ_V_CMP_LE_F64 0x63#define SQ_V_CMP_GT_F64 0x64#define SQ_V_CMP_LG_F64 0x65#define SQ_V_CMP_GE_F64 0x66#define SQ_V_CMP_O_F64 0x67#define SQ_V_CMP_U_F64 0x68#define SQ_V_CMP_NGE_F64 0x69#define SQ_V_CMP_NLG_F64 0x6a#define SQ_V_CMP_NGT_F64 0x6b#define SQ_V_CMP_NLE_F64 0x6c#define SQ_V_CMP_NEQ_F64 0x6d#define SQ_V_CMP_NLT_F64 0x6e#define SQ_V_CMP_TRU_F64 0x6f#define SQ_V_CMPX_F_F64 0x70#define SQ_V_CMPX_LT_F64 0x71#define SQ_V_CMPX_EQ_F64 0x72#define SQ_V_CMPX_LE_F64 0x73#define SQ_V_CMPX_GT_F64 0x74#define SQ_V_CMPX_LG_F64 0x75#define SQ_V_CMPX_GE_F64 0x76#define SQ_V_CMPX_O_F64 0x77#define SQ_V_CMPX_U_F64 0x78#define SQ_V_CMPX_NGE_F64 0x79#define SQ_V_CMPX_NLG_F64 0x7a#define SQ_V_CMPX_NGT_F64 0x7b#define SQ_V_CMPX_NLE_F64 0x7c#define SQ_V_CMPX_NEQ_F64 0x7d#define SQ_V_CMPX_NLT_F64 0x7e#define SQ_V_CMPX_TRU_F64 0x7f#define SQ_V_CMP_F_I16 0xa0#define SQ_V_CMP_LT_I16 0xa1#define SQ_V_CMP_EQ_I16 0xa2#define SQ_V_CMP_LE_I16 0xa3#define SQ_V_CMP_GT_I16 0xa4#define SQ_V_CMP_NE_I16 0xa5#define SQ_V_CMP_GE_I16 0xa6#define SQ_V_CMP_T_I16 0xa7#define SQ_V_CMP_F_U16 0xa8#define SQ_V_CMP_LT_U16 0xa9#define SQ_V_CMP_EQ_U16 0xaa#define SQ_V_CMP_LE_U16 0xab#define SQ_V_CMP_GT_U16 0xac#define SQ_V_CMP_NE_U16 0xad#define SQ_V_CMP_GE_U16 0xae#define SQ_V_CMP_T_U16 0xaf#define SQ_V_CMPX_F_I16 0xb0#define SQ_V_CMPX_LT_I16 0xb1#define SQ_V_CMPX_EQ_I16 0xb2#define SQ_V_CMPX_LE_I16 0xb3#define SQ_V_CMPX_GT_I16 0xb4#define SQ_V_CMPX_NE_I16 0xb5#define SQ_V_CMPX_GE_I16 0xb6#define SQ_V_CMPX_T_I16 0xb7#define SQ_V_CMPX_F_U16 0xb8#define SQ_V_CMPX_LT_U16 0xb9#define SQ_V_CMPX_EQ_U16 0xba#define SQ_V_CMPX_LE_U16 0xbb#define SQ_V_CMPX_GT_U16 0xbc#define SQ_V_CMPX_NE_U16 0xbd#define SQ_V_CMPX_GE_U16 0xbe#define SQ_V_CMPX_T_U16 0xbf#define SQ_V_CMP_F_I32 0xc0#define SQ_V_CMP_LT_I32 0xc1#define SQ_V_CMP_EQ_I32 0xc2#define SQ_V_CMP_LE_I32 0xc3#define SQ_V_CMP_GT_I32 0xc4#define SQ_V_CMP_NE_I32 0xc5#define SQ_V_CMP_GE_I32 0xc6#define SQ_V_CMP_T_I32 0xc7#define SQ_V_CMP_F_U32 0xc8#define SQ_V_CMP_LT_U32 0xc9#define SQ_V_CMP_EQ_U32 0xca#define SQ_V_CMP_LE_U32 0xcb#define SQ_V_CMP_GT_U32 0xcc#define SQ_V_CMP_NE_U32 0xcd#define SQ_V_CMP_GE_U32 0xce#define SQ_V_CMP_T_U32 0xcf#define SQ_V_CMPX_F_I32 0xd0#define SQ_V_CMPX_LT_I32 0xd1#define SQ_V_CMPX_EQ_I32 0xd2#define SQ_V_CMPX_LE_I32 0xd3#define SQ_V_CMPX_GT_I32 0xd4#define SQ_V_CMPX_NE_I32 0xd5#define SQ_V_CMPX_GE_I32 0xd6#define SQ_V_CMPX_T_I32 0xd7#define SQ_V_CMPX_F_U32 0xd8#define SQ_V_CMPX_LT_U32 0xd9#define SQ_V_CMPX_EQ_U32 0xda#define SQ_V_CMPX_LE_U32 0xdb#define SQ_V_CMPX_GT_U32 0xdc#define SQ_V_CMPX_NE_U32 0xdd#define SQ_V_CMPX_GE_U32 0xde#define SQ_V_CMPX_T_U32 0xdf#define SQ_V_CMP_F_I64 0xe0#define SQ_V_CMP_LT_I64 0xe1#define SQ_V_CMP_EQ_I64 0xe2#define SQ_V_CMP_LE_I64 0xe3#define SQ_V_CMP_GT_I64 0xe4#define SQ_V_CMP_NE_I64 0xe5#define SQ_V_CMP_GE_I64 0xe6#define SQ_V_CMP_T_I64 0xe7#define SQ_V_CMP_F_U64 0xe8#define SQ_V_CMP_LT_U64 0xe9#define SQ_V_CMP_EQ_U64 0xea#define SQ_V_CMP_LE_U64 0xeb#define SQ_V_CMP_GT_U64 0xec#define SQ_V_CMP_NE_U64 0xed#define SQ_V_CMP_GE_U64 0xee#define SQ_V_CMP_T_U64 0xef#define SQ_V_CMPX_F_I64 0xf0#define SQ_V_CMPX_LT_I64 0xf1#define SQ_V_CMPX_EQ_I64 0xf2#define SQ_V_CMPX_LE_I64 0xf3#define SQ_V_CMPX_GT_I64 0xf4#define SQ_V_CMPX_NE_I64 0xf5#define SQ_V_CMPX_GE_I64 0xf6#define SQ_V_CMPX_T_I64 0xf7#define SQ_V_CMPX_F_U64 0xf8#define SQ_V_CMPX_LT_U64 0xf9#define SQ_V_CMPX_EQ_U64 0xfa#define SQ_V_CMPX_LE_U64 0xfb#define SQ_V_CMPX_GT_U64 0xfc#define SQ_V_CMPX_NE_U64 0xfd#define SQ_V_CMPX_GE_U64 0xfe#define SQ_V_CMPX_T_U64 0xff#define SQ_L1 0x1#define SQ_L2 0x2#define SQ_L3 0x3#define SQ_L4 0x4#define SQ_L5 0x5#define SQ_L6 0x6#define SQ_L7 0x7#define SQ_L8 0x8#define SQ_L9 0x9#define SQ_L10 0xa#define SQ_L11 0xb#define SQ_L12 0xc#define SQ_L13 0xd#define SQ_L14 0xe#define SQ_L15 0xf#define SQ_SGPR0 0x0#define SQ_SDWA_UNUSED_PAD 0x0#define SQ_SDWA_UNUSED_SEXT 0x1#define SQ_SDWA_UNUSED_PRESERVE 0x2#define SQ_F 0x0#define SQ_LT 0x1#define SQ_EQ 0x2#define SQ_LE 0x3#define SQ_GT 0x4#define SQ_NE 0x5#define SQ_GE 0x6#define SQ_T 0x7#define SQ_SRC_64_INT 0xc0#define SQ_SRC_M_1_INT 0xc1#define SQ_SRC_M_2_INT 0xc2#define SQ_SRC_M_3_INT 0xc3#define SQ_SRC_M_4_INT 0xc4#define SQ_SRC_M_5_INT 0xc5#define SQ_SRC_M_6_INT 0xc6#define SQ_SRC_M_7_INT 0xc7#define SQ_SRC_M_8_INT 0xc8#define SQ_SRC_M_9_INT 0xc9#define SQ_SRC_M_10_INT 0xca#define SQ_SRC_M_11_INT 0xcb#define SQ_SRC_M_12_INT 0xcc#define SQ_SRC_M_13_INT 0xcd#define SQ_SRC_M_14_INT 0xce#define SQ_SRC_M_15_INT 0xcf#define SQ_SRC_M_16_INT 0xd0#define SQ_SRC_0_5 0xf0#define SQ_SRC_M_0_5 0xf1#define SQ_SRC_1 0xf2#define SQ_SRC_M_1 0xf3#define SQ_SRC_2 0xf4#define SQ_SRC_M_2 0xf5#define SQ_SRC_4 0xf6#define SQ_SRC_M_4 0xf7#define SQ_SRC_INV_2PI 0xf8#define SQ_SRC_0 0x80#define SQ_SRC_1_INT 0x81#define SQ_SRC_2_INT 0x82#define SQ_SRC_3_INT 0x83#define SQ_SRC_4_INT 0x84#define SQ_SRC_5_INT 0x85#define SQ_SRC_6_INT 0x86#define SQ_SRC_7_INT 0x87#define SQ_SRC_8_INT 0x88#define SQ_SRC_9_INT 0x89#define SQ_SRC_10_INT 0x8a#define SQ_SRC_11_INT 0x8b#define SQ_SRC_12_INT 0x8c#define SQ_SRC_13_INT 0x8d#define SQ_SRC_14_INT 0x8e#define SQ_SRC_15_INT 0x8f#define SQ_SRC_16_INT 0x90#define SQ_SRC_17_INT 0x91#define SQ_SRC_18_INT 0x92#define SQ_SRC_19_INT 0x93#define SQ_SRC_20_INT 0x94#define SQ_SRC_21_INT 0x95#define SQ_SRC_22_INT 0x96#define SQ_SRC_23_INT 0x97#define SQ_SRC_24_INT 0x98#define SQ_SRC_25_INT 0x99#define SQ_SRC_26_INT 0x9a#define SQ_SRC_27_INT 0x9b#define SQ_SRC_28_INT 0x9c#define SQ_SRC_29_INT 0x9d#define SQ_SRC_30_INT 0x9e#define SQ_SRC_31_INT 0x9f#define SQ_SRC_32_INT 0xa0#define SQ_SRC_33_INT 0xa1#define SQ_SRC_34_INT 0xa2#define SQ_SRC_35_INT 0xa3#define SQ_SRC_36_INT 0xa4#define SQ_SRC_37_INT 0xa5#define SQ_SRC_38_INT 0xa6#define SQ_SRC_39_INT 0xa7#define SQ_SRC_40_INT 0xa8#define SQ_SRC_41_INT 0xa9#define SQ_SRC_42_INT 0xaa#define SQ_SRC_43_INT 0xab#define SQ_SRC_44_INT 0xac#define SQ_SRC_45_INT 0xad#define SQ_SRC_46_INT 0xae#define SQ_SRC_47_INT 0xaf#define SQ_SRC_48_INT 0xb0#define SQ_SRC_49_INT 0xb1#define SQ_SRC_50_INT 0xb2#define SQ_SRC_51_INT 0xb3#define SQ_SRC_52_INT 0xb4#define SQ_SRC_53_INT 0xb5#define SQ_SRC_54_INT 0xb6#define SQ_SRC_55_INT 0xb7#define SQ_SRC_56_INT 0xb8#define SQ_SRC_57_INT 0xb9#define SQ_SRC_58_INT 0xba#define SQ_SRC_59_INT 0xbb#define SQ_SRC_60_INT 0xbc#define SQ_SRC_61_INT 0xbd#define SQ_SRC_62_INT 0xbe#define SQ_SRC_63_INT 0xbf#define SQ_DS_ADD_U32 0x0#define SQ_DS_SUB_U32 0x1#define SQ_DS_RSUB_U32 0x2#define SQ_DS_INC_U32 0x3#define SQ_DS_DEC_U32 0x4#define SQ_DS_MIN_I32 0x5#define SQ_DS_MAX_I32 0x6#define SQ_DS_MIN_U32 0x7#define SQ_DS_MAX_U32 0x8#define SQ_DS_AND_B32 0x9#define SQ_DS_OR_B32 0xa#define SQ_DS_XOR_B32 0xb#define SQ_DS_MSKOR_B32 0xc#define SQ_DS_WRITE_B32 0xd#define SQ_DS_WRITE2_B32 0xe#define SQ_DS_WRITE2ST64_B32 0xf#define SQ_DS_CMPST_B32 0x10#define SQ_DS_CMPST_F32 0x11#define SQ_DS_MIN_F32 0x12#define SQ_DS_MAX_F32 0x13#define SQ_DS_NOP 0x14#define SQ_DS_ADD_F32 0x15#define SQ_DS_WRITE_B8 0x1e#define SQ_DS_WRITE_B16 0x1f#define SQ_DS_ADD_RTN_U32 0x20#define SQ_DS_SUB_RTN_U32 0x21#define SQ_DS_RSUB_RTN_U32 0x22#define SQ_DS_INC_RTN_U32 0x23#define SQ_DS_DEC_RTN_U32 0x24#define SQ_DS_MIN_RTN_I32 0x25#define SQ_DS_MAX_RTN_I32 0x26#define SQ_DS_MIN_RTN_U32 0x27#define SQ_DS_MAX_RTN_U32 0x28#define SQ_DS_AND_RTN_B32 0x29#define SQ_DS_OR_RTN_B32 0x2a#define SQ_DS_XOR_RTN_B32 0x2b#define SQ_DS_MSKOR_RTN_B32 0x2c#define SQ_DS_WRXCHG_RTN_B32 0x2d#define SQ_DS_WRXCHG2_RTN_B32 0x2e#define SQ_DS_WRXCHG2ST64_RTN_B32 0x2f#define SQ_DS_CMPST_RTN_B32 0x30#define SQ_DS_CMPST_RTN_F32 0x31#define SQ_DS_MIN_RTN_F32 0x32#define SQ_DS_MAX_RTN_F32 0x33#define SQ_DS_WRAP_RTN_B32 0x34#define SQ_DS_ADD_RTN_F32 0x35#define SQ_DS_READ_B32 0x36#define SQ_DS_READ2_B32 0x37#define SQ_DS_READ2ST64_B32 0x38#define SQ_DS_READ_I8 0x39#define SQ_DS_READ_U8 0x3a#define SQ_DS_READ_I16 0x3b#define SQ_DS_READ_U16 0x3c#define SQ_DS_SWIZZLE_B32 0x3d#define SQ_DS_PERMUTE_B32 0x3e#define SQ_DS_BPERMUTE_B32 0x3f#define SQ_DS_ADD_U64 0x40#define SQ_DS_SUB_U64 0x41#define SQ_DS_RSUB_U64 0x42#define SQ_DS_INC_U64 0x43#define SQ_DS_DEC_U64 0x44#define SQ_DS_MIN_I64 0x45#define SQ_DS_MAX_I64 0x46#define SQ_DS_MIN_U64 0x47#define SQ_DS_MAX_U64 0x48#define SQ_DS_AND_B64 0x49#define SQ_DS_OR_B64 0x4a#define SQ_DS_XOR_B64 0x4b#define SQ_DS_MSKOR_B64 0x4c#define SQ_DS_WRITE_B64 0x4d#define SQ_DS_WRITE2_B64 0x4e#define SQ_DS_WRITE2ST64_B64 0x4f#define SQ_DS_CMPST_B64 0x50#define SQ_DS_CMPST_F64 0x51#define SQ_DS_MIN_F64 0x52#define SQ_DS_MAX_F64 0x53#define SQ_DS_ADD_RTN_U64 0x60#define SQ_DS_SUB_RTN_U64 0x61#define SQ_DS_RSUB_RTN_U64 0x62#define SQ_DS_INC_RTN_U64 0x63#define SQ_DS_DEC_RTN_U64 0x64#define SQ_DS_MIN_RTN_I64 0x65#define SQ_DS_MAX_RTN_I64 0x66#define SQ_DS_MIN_RTN_U64 0x67#define SQ_DS_MAX_RTN_U64 0x68#define SQ_DS_AND_RTN_B64 0x69#define SQ_DS_OR_RTN_B64 0x6a#define SQ_DS_XOR_RTN_B64 0x6b#define SQ_DS_MSKOR_RTN_B64 0x6c#define SQ_DS_WRXCHG_RTN_B64 0x6d#define SQ_DS_WRXCHG2_RTN_B64 0x6e#define SQ_DS_WRXCHG2ST64_RTN_B64 0x6f#define SQ_DS_CMPST_RTN_B64 0x70#define SQ_DS_CMPST_RTN_F64 0x71#define SQ_DS_MIN_RTN_F64 0x72#define SQ_DS_MAX_RTN_F64 0x73#define SQ_DS_READ_B64 0x76#define SQ_DS_READ2_B64 0x77#define SQ_DS_READ2ST64_B64 0x78#define SQ_DS_CONDXCHG32_RTN_B64 0x7e#define SQ_DS_ADD_SRC2_U32 0x80#define SQ_DS_SUB_SRC2_U32 0x81#define SQ_DS_RSUB_SRC2_U32 0x82#define SQ_DS_INC_SRC2_U32 0x83#define SQ_DS_DEC_SRC2_U32 0x84#define SQ_DS_MIN_SRC2_I32 0x85#define SQ_DS_MAX_SRC2_I32 0x86#define SQ_DS_MIN_SRC2_U32 0x87#define SQ_DS_MAX_SRC2_U32 0x88#define SQ_DS_AND_SRC2_B32 0x89#define SQ_DS_OR_SRC2_B32 0x8a#define SQ_DS_XOR_SRC2_B32 0x8b#define SQ_DS_WRITE_SRC2_B32 0x8d#define SQ_DS_MIN_SRC2_F32 0x92#define SQ_DS_MAX_SRC2_F32 0x93#define SQ_DS_ADD_SRC2_F32 0x95#define SQ_DS_GWS_SEMA_RELEASE_ALL 0x98#define SQ_DS_GWS_INIT 0x99#define SQ_DS_GWS_SEMA_V 0x9a#define SQ_DS_GWS_SEMA_BR 0x9b#define SQ_DS_GWS_SEMA_P 0x9c#define SQ_DS_GWS_BARRIER 0x9d#define SQ_DS_CONSUME 0xbd#define SQ_DS_APPEND 0xbe#define SQ_DS_ORDERED_COUNT 0xbf#define SQ_DS_ADD_SRC2_U64 0xc0#define SQ_DS_SUB_SRC2_U64 0xc1#define SQ_DS_RSUB_SRC2_U64 0xc2#define SQ_DS_INC_SRC2_U64 0xc3#define SQ_DS_DEC_SRC2_U64 0xc4#define SQ_DS_MIN_SRC2_I64 0xc5#define SQ_DS_MAX_SRC2_I64 0xc6#define SQ_DS_MIN_SRC2_U64 0xc7#define SQ_DS_MAX_SRC2_U64 0xc8#define SQ_DS_AND_SRC2_B64 0xc9#define SQ_DS_OR_SRC2_B64 0xca#define SQ_DS_XOR_SRC2_B64 0xcb#define SQ_DS_WRITE_SRC2_B64 0xcd#define SQ_DS_MIN_SRC2_F64 0xd2#define SQ_DS_MAX_SRC2_F64 0xd3#define SQ_DS_WRITE_B96 0xde#define SQ_DS_WRITE_B128 0xdf#define SQ_DS_CONDXCHG32_RTN_B128 0xfd#define SQ_DS_READ_B96 0xfe#define SQ_DS_READ_B128 0xff#define SQ_BUFFER_LOAD_FORMAT_X 0x0#define SQ_BUFFER_LOAD_FORMAT_XY 0x1#define SQ_BUFFER_LOAD_FORMAT_XYZ 0x2#define SQ_BUFFER_LOAD_FORMAT_XYZW 0x3#define SQ_BUFFER_STORE_FORMAT_X 0x4#define SQ_BUFFER_STORE_FORMAT_XY 0x5#define SQ_BUFFER_STORE_FORMAT_XYZ 0x6#define SQ_BUFFER_STORE_FORMAT_XYZW 0x7#define SQ_BUFFER_LOAD_FORMAT_D16_X 0x8#define SQ_BUFFER_LOAD_FORMAT_D16_XY 0x9#define SQ_BUFFER_LOAD_FORMAT_D16_XYZ 0xa#define SQ_BUFFER_LOAD_FORMAT_D16_XYZW 0xb#define SQ_BUFFER_STORE_FORMAT_D16_X 0xc#define SQ_BUFFER_STORE_FORMAT_D16_XY 0xd#define SQ_BUFFER_STORE_FORMAT_D16_XYZ 0xe#define SQ_BUFFER_STORE_FORMAT_D16_XYZW 0xf#define SQ_BUFFER_LOAD_UBYTE 0x10#define SQ_BUFFER_LOAD_SBYTE 0x11#define SQ_BUFFER_LOAD_USHORT 0x12#define SQ_BUFFER_LOAD_SSHORT 0x13#define SQ_BUFFER_LOAD_DWORD 0x14#define SQ_BUFFER_LOAD_DWORDX2 0x15#define SQ_BUFFER_LOAD_DWORDX3 0x16#define SQ_BUFFER_LOAD_DWORDX4 0x17#define SQ_BUFFER_STORE_BYTE 0x18#define SQ_BUFFER_STORE_SHORT 0x1a#define SQ_BUFFER_STORE_DWORD 0x1c#define SQ_BUFFER_STORE_DWORDX2 0x1d#define SQ_BUFFER_STORE_DWORDX3 0x1e#define SQ_BUFFER_STORE_DWORDX4 0x1f#define SQ_BUFFER_STORE_LDS_DWORD 0x3d#define SQ_BUFFER_WBINVL1 0x3e#define SQ_BUFFER_WBINVL1_VOL 0x3f#define SQ_BUFFER_ATOMIC_SWAP 0x40#define SQ_BUFFER_ATOMIC_CMPSWAP 0x41#define SQ_BUFFER_ATOMIC_ADD 0x42#define SQ_BUFFER_ATOMIC_SUB 0x43#define SQ_BUFFER_ATOMIC_SMIN 0x44#define SQ_BUFFER_ATOMIC_UMIN 0x45#define SQ_BUFFER_ATOMIC_SMAX 0x46#define SQ_BUFFER_ATOMIC_UMAX 0x47#define SQ_BUFFER_ATOMIC_AND 0x48#define SQ_BUFFER_ATOMIC_OR 0x49#define SQ_BUFFER_ATOMIC_XOR 0x4a#define SQ_BUFFER_ATOMIC_INC 0x4b#define SQ_BUFFER_ATOMIC_DEC 0x4c#define SQ_BUFFER_ATOMIC_SWAP_X2 0x60#define SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x61#define SQ_BUFFER_ATOMIC_ADD_X2 0x62#define SQ_BUFFER_ATOMIC_SUB_X2 0x63#define SQ_BUFFER_ATOMIC_SMIN_X2 0x64#define SQ_BUFFER_ATOMIC_UMIN_X2 0x65#define SQ_BUFFER_ATOMIC_SMAX_X2 0x66#define SQ_BUFFER_ATOMIC_UMAX_X2 0x67#define SQ_BUFFER_ATOMIC_AND_X2 0x68#define SQ_BUFFER_ATOMIC_OR_X2 0x69#define SQ_BUFFER_ATOMIC_XOR_X2 0x6a#define SQ_BUFFER_ATOMIC_INC_X2 0x6b#define SQ_BUFFER_ATOMIC_DEC_X2 0x6c#define SQ_EXEC_LO 0x7e#define SQ_EXEC_HI 0x7f#define SQ_SRC_SCC 0xfd#define SQ_OMOD_OFF 0x0#define SQ_OMOD_M2 0x1#define SQ_OMOD_M4 0x2#define SQ_OMOD_D2 0x3#define SQ_DPP_QUAD_PERM 0x0#define SQ_DPP_ROW_SL1 0x101#define SQ_DPP_ROW_SL2 0x102#define SQ_DPP_ROW_SL3 0x103#define SQ_DPP_ROW_SL4 0x104#define SQ_DPP_ROW_SL5 0x105#define SQ_DPP_ROW_SL6 0x106#define SQ_DPP_ROW_SL7 0x107#define SQ_DPP_ROW_SL8 0x108#define SQ_DPP_ROW_SL9 0x109#define SQ_DPP_ROW_SL10 0x10a#define SQ_DPP_ROW_SL11 0x10b#define SQ_DPP_ROW_SL12 0x10c#define SQ_DPP_ROW_SL13 0x10d#define SQ_DPP_ROW_SL14 0x10e#define SQ_DPP_ROW_SL15 0x10f#define SQ_DPP_ROW_SR1 0x111#define SQ_DPP_ROW_SR2 0x112#define SQ_DPP_ROW_SR3 0x113#define SQ_DPP_ROW_SR4 0x114#define SQ_DPP_ROW_SR5 0x115#define SQ_DPP_ROW_SR6 0x116#define SQ_DPP_ROW_SR7 0x117#define SQ_DPP_ROW_SR8 0x118#define SQ_DPP_ROW_SR9 0x119#define SQ_DPP_ROW_SR10 0x11a#define SQ_DPP_ROW_SR11 0x11b#define SQ_DPP_ROW_SR12 0x11c#define SQ_DPP_ROW_SR13 0x11d#define SQ_DPP_ROW_SR14 0x11e#define SQ_DPP_ROW_SR15 0x11f#define SQ_DPP_ROW_RR1 0x121#define SQ_DPP_ROW_RR2 0x122#define SQ_DPP_ROW_RR3 0x123#define SQ_DPP_ROW_RR4 0x124#define SQ_DPP_ROW_RR5 0x125#define SQ_DPP_ROW_RR6 0x126#define SQ_DPP_ROW_RR7 0x127#define SQ_DPP_ROW_RR8 0x128#define SQ_DPP_ROW_RR9 0x129#define SQ_DPP_ROW_RR10 0x12a#define SQ_DPP_ROW_RR11 0x12b#define SQ_DPP_ROW_RR12 0x12c#define SQ_DPP_ROW_RR13 0x12d#define SQ_DPP_ROW_RR14 0x12e#define SQ_DPP_ROW_RR15 0x12f#define SQ_DPP_WF_SL1 0x130#define SQ_DPP_WF_RL1 0x134#define SQ_DPP_WF_SR1 0x138#define SQ_DPP_WF_RR1 0x13c#define SQ_DPP_ROW_MIRROR 0x140#define SQ_DPP_ROW_HALF_MIRROR 0x141#define SQ_DPP_ROW_BCAST15 0x142#define SQ_DPP_ROW_BCAST31 0x143#define SQ_EXP_GDS0 0x18#define SQ_GS_OP_NOP 0x0#define SQ_GS_OP_CUT 0x1#define SQ_GS_OP_EMIT 0x2#define SQ_GS_OP_EMIT_CUT 0x3#define SQ_IMAGE_LOAD 0x0#define SQ_IMAGE_LOAD_MIP 0x1#define SQ_IMAGE_LOAD_PCK 0x2#define SQ_IMAGE_LOAD_PCK_SGN 0x3#define SQ_IMAGE_LOAD_MIP_PCK 0x4#define SQ_IMAGE_LOAD_MIP_PCK_SGN 0x5#define SQ_IMAGE_STORE 0x8#define SQ_IMAGE_STORE_MIP 0x9#define SQ_IMAGE_STORE_PCK 0xa#define SQ_IMAGE_STORE_MIP_PCK 0xb#define SQ_IMAGE_GET_RESINFO 0xe#define SQ_IMAGE_ATOMIC_SWAP 0x10#define SQ_IMAGE_ATOMIC_CMPSWAP 0x11#define SQ_IMAGE_ATOMIC_ADD 0x12#define SQ_IMAGE_ATOMIC_SUB 0x13#define SQ_IMAGE_ATOMIC_SMIN 0x14#define SQ_IMAGE_ATOMIC_UMIN 0x15#define SQ_IMAGE_ATOMIC_SMAX 0x16#define SQ_IMAGE_ATOMIC_UMAX 0x17#define SQ_IMAGE_ATOMIC_AND 0x18#define SQ_IMAGE_ATOMIC_OR 0x19#define SQ_IMAGE_ATOMIC_XOR 0x1a#define SQ_IMAGE_ATOMIC_INC 0x1b#define SQ_IMAGE_ATOMIC_DEC 0x1c#define SQ_IMAGE_SAMPLE 0x20#define SQ_IMAGE_SAMPLE_CL 0x21#define SQ_IMAGE_SAMPLE_D 0x22#define SQ_IMAGE_SAMPLE_D_CL 0x23#define SQ_IMAGE_SAMPLE_L 0x24#define SQ_IMAGE_SAMPLE_B 0x25#define SQ_IMAGE_SAMPLE_B_CL 0x26#define SQ_IMAGE_SAMPLE_LZ 0x27#define SQ_IMAGE_SAMPLE_C 0x28#define SQ_IMAGE_SAMPLE_C_CL 0x29#define SQ_IMAGE_SAMPLE_C_D 0x2a#define SQ_IMAGE_SAMPLE_C_D_CL 0x2b#define SQ_IMAGE_SAMPLE_C_L 0x2c#define SQ_IMAGE_SAMPLE_C_B 0x2d#define SQ_IMAGE_SAMPLE_C_B_CL 0x2e#define SQ_IMAGE_SAMPLE_C_LZ 0x2f#define SQ_IMAGE_SAMPLE_O 0x30#define SQ_IMAGE_SAMPLE_CL_O 0x31#define SQ_IMAGE_SAMPLE_D_O 0x32#define SQ_IMAGE_SAMPLE_D_CL_O 0x33#define SQ_IMAGE_SAMPLE_L_O 0x34#define SQ_IMAGE_SAMPLE_B_O 0x35#define SQ_IMAGE_SAMPLE_B_CL_O 0x36#define SQ_IMAGE_SAMPLE_LZ_O 0x37#define SQ_IMAGE_SAMPLE_C_O 0x38#define SQ_IMAGE_SAMPLE_C_CL_O 0x39#define SQ_IMAGE_SAMPLE_C_D_O 0x3a#define SQ_IMAGE_SAMPLE_C_D_CL_O 0x3b#define SQ_IMAGE_SAMPLE_C_L_O 0x3c#define SQ_IMAGE_SAMPLE_C_B_O 0x3d#define SQ_IMAGE_SAMPLE_C_B_CL_O 0x3e#define SQ_IMAGE_SAMPLE_C_LZ_O 0x3f#define SQ_IMAGE_GATHER4 0x40#define SQ_IMAGE_GATHER4_CL 0x41#define SQ_IMAGE_GATHER4_L 0x44#define SQ_IMAGE_GATHER4_B 0x45#define SQ_IMAGE_GATHER4_B_CL 0x46#define SQ_IMAGE_GATHER4_LZ 0x47#define SQ_IMAGE_GATHER4_C 0x48#define SQ_IMAGE_GATHER4_C_CL 0x49#define SQ_IMAGE_GATHER4_C_L 0x4c#define SQ_IMAGE_GATHER4_C_B 0x4d#define SQ_IMAGE_GATHER4_C_B_CL 0x4e#define SQ_IMAGE_GATHER4_C_LZ 0x4f#define SQ_IMAGE_GATHER4_O 0x50#define SQ_IMAGE_GATHER4_CL_O 0x51#define SQ_IMAGE_GATHER4_L_O 0x54#define SQ_IMAGE_GATHER4_B_O 0x55#define SQ_IMAGE_GATHER4_B_CL_O 0x56#define SQ_IMAGE_GATHER4_LZ_O 0x57#define SQ_IMAGE_GATHER4_C_O 0x58#define SQ_IMAGE_GATHER4_C_CL_O 0x59#define SQ_IMAGE_GATHER4_C_L_O 0x5c#define SQ_IMAGE_GATHER4_C_B_O 0x5d#define SQ_IMAGE_GATHER4_C_B_CL_O 0x5e#define SQ_IMAGE_GATHER4_C_LZ_O 0x5f#define SQ_IMAGE_GET_LOD 0x60#define SQ_IMAGE_SAMPLE_CD 0x68#define SQ_IMAGE_SAMPLE_CD_CL 0x69#define SQ_IMAGE_SAMPLE_C_CD 0x6a#define SQ_IMAGE_SAMPLE_C_CD_CL 0x6b#define SQ_IMAGE_SAMPLE_CD_O 0x6c#define SQ_IMAGE_SAMPLE_CD_CL_O 0x6d#define SQ_IMAGE_SAMPLE_C_CD_O 0x6e#define SQ_IMAGE_SAMPLE_C_CD_CL_O 0x6f#define SQ_IMAGE_RSRC256 0x7e#define SQ_IMAGE_SAMPLER 0x7f#define SQ_SRC_VCCZ 0xfb#define SQ_SRC_VGPR0 0x100#define SQ_SDWA_BYTE_0 0x0#define SQ_SDWA_BYTE_1 0x1#define SQ_SDWA_BYTE_2 0x2#define SQ_SDWA_BYTE_3 0x3#define SQ_SDWA_WORD_0 0x4#define SQ_SDWA_WORD_1 0x5#define SQ_SDWA_DWORD 0x6#define SQ_XNACK_MASK_LO 0x68#define SQ_XNACK_MASK_HI 0x69#define SQ_TBUFFER_LOAD_FORMAT_X 0x0#define SQ_TBUFFER_LOAD_FORMAT_XY 0x1#define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x2#define SQ_TBUFFER_LOAD_FORMAT_XYZW 0x3#define SQ_TBUFFER_STORE_FORMAT_X 0x4#define SQ_TBUFFER_STORE_FORMAT_XY 0x5#define SQ_TBUFFER_STORE_FORMAT_XYZ 0x6#define SQ_TBUFFER_STORE_FORMAT_XYZW 0x7#define SQ_TBUFFER_LOAD_FORMAT_D16_X 0x8#define SQ_TBUFFER_LOAD_FORMAT_D16_XY 0x9#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ 0xa#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW 0xb#define SQ_TBUFFER_STORE_FORMAT_D16_X 0xc#define SQ_TBUFFER_STORE_FORMAT_D16_XY 0xd#define SQ_TBUFFER_STORE_FORMAT_D16_XYZ 0xe#define SQ_TBUFFER_STORE_FORMAT_D16_XYZW 0xf#define SQ_CHAN_X 0x0#define SQ_CHAN_Y 0x1#define SQ_CHAN_Z 0x2#define SQ_CHAN_W 0x3#define SQ_V_NOP 0x0#define SQ_V_MOV_B32 0x1#define SQ_V_READFIRSTLANE_B32 0x2#define SQ_V_CVT_I32_F64 0x3#define SQ_V_CVT_F64_I32 0x4#define SQ_V_CVT_F32_I32 0x5#define SQ_V_CVT_F32_U32 0x6#define SQ_V_CVT_U32_F32 0x7#define SQ_V_CVT_I32_F32 0x8#define SQ_V_MOV_FED_B32 0x9#define SQ_V_CVT_F16_F32 0xa#define SQ_V_CVT_F32_F16 0xb#define SQ_V_CVT_RPI_I32_F32 0xc#define SQ_V_CVT_FLR_I32_F32 0xd#define SQ_V_CVT_OFF_F32_I4 0xe#define SQ_V_CVT_F32_F64 0xf#define SQ_V_CVT_F64_F32 0x10#define SQ_V_CVT_F32_UBYTE0 0x11#define SQ_V_CVT_F32_UBYTE1 0x12#define SQ_V_CVT_F32_UBYTE2 0x13#define SQ_V_CVT_F32_UBYTE3 0x14#define SQ_V_CVT_U32_F64 0x15#define SQ_V_CVT_F64_U32 0x16#define SQ_V_TRUNC_F64 0x17#define SQ_V_CEIL_F64 0x18#define SQ_V_RNDNE_F64 0x19#define SQ_V_FLOOR_F64 0x1a#define SQ_V_FRACT_F32 0x1b#define SQ_V_TRUNC_F32 0x1c#define SQ_V_CEIL_F32 0x1d#define SQ_V_RNDNE_F32 0x1e#define SQ_V_FLOOR_F32 0x1f#define SQ_V_EXP_F32 0x20#define SQ_V_LOG_F32 0x21#define SQ_V_RCP_F32 0x22#define SQ_V_RCP_IFLAG_F32 0x23#define SQ_V_RSQ_F32 0x24#define SQ_V_RCP_F64 0x25#define SQ_V_RSQ_F64 0x26#define SQ_V_SQRT_F32 0x27#define SQ_V_SQRT_F64 0x28#define SQ_V_SIN_F32 0x29#define SQ_V_COS_F32 0x2a#define SQ_V_NOT_B32 0x2b#define SQ_V_BFREV_B32 0x2c#define SQ_V_FFBH_U32 0x2d#define SQ_V_FFBL_B32 0x2e#define SQ_V_FFBH_I32 0x2f#define SQ_V_FREXP_EXP_I32_F64 0x30#define SQ_V_FREXP_MANT_F64 0x31#define SQ_V_FRACT_F64 0x32#define SQ_V_FREXP_EXP_I32_F32 0x33#define SQ_V_FREXP_MANT_F32 0x34#define SQ_V_CLREXCP 0x35#define SQ_V_MOVRELD_B32 0x36#define SQ_V_MOVRELS_B32 0x37#define SQ_V_MOVRELSD_B32 0x38#define SQ_V_CVT_F16_U16 0x39#define SQ_V_CVT_F16_I16 0x3a#define SQ_V_CVT_U16_F16 0x3b#define SQ_V_CVT_I16_F16 0x3c#define SQ_V_RCP_F16 0x3d#define SQ_V_SQRT_F16 0x3e#define SQ_V_RSQ_F16 0x3f#define SQ_V_LOG_F16 0x40#define SQ_V_EXP_F16 0x41#define SQ_V_FREXP_MANT_F16 0x42#define SQ_V_FREXP_EXP_I16_F16 0x43#define SQ_V_FLOOR_F16 0x44#define SQ_V_CEIL_F16 0x45#define SQ_V_TRUNC_F16 0x46#define SQ_V_RNDNE_F16 0x47#define SQ_V_FRACT_F16 0x48#define SQ_V_SIN_F16 0x49#define SQ_V_COS_F16 0x4a#define SQ_V_EXP_LEGACY_F32 0x4b#define SQ_V_LOG_LEGACY_F32 0x4c#define SQ_SRC_SDWA 0xf9#define SQ_V_OPC_OFFSET 0x0#define SQ_V_OP2_OFFSET 0x100#define SQ_V_OP1_OFFSET 0x140#define SQ_V_INTRP_OFFSET 0x270#define SQ_V_INTERP_P1_F32 0x0#define SQ_V_INTERP_P2_F32 0x1#define SQ_V_INTERP_MOV_F32 0x2#define SQ_S_NOP 0x0#define SQ_S_ENDPGM 0x1#define SQ_S_BRANCH 0x2#define SQ_S_WAKEUP 0x3#define SQ_S_CBRANCH_SCC0 0x4#define SQ_S_CBRANCH_SCC1 0x5#define SQ_S_CBRANCH_VCCZ 0x6#define SQ_S_CBRANCH_VCCNZ 0x7#define SQ_S_CBRANCH_EXECZ 0x8#define SQ_S_CBRANCH_EXECNZ 0x9#define SQ_S_BARRIER 0xa#define SQ_S_SETKILL 0xb#define SQ_S_WAITCNT 0xc#define SQ_S_SETHALT 0xd#define SQ_S_SLEEP 0xe#define SQ_S_SETPRIO 0xf#define SQ_S_SENDMSG 0x10#define SQ_S_SENDMSGHALT 0x11#define SQ_S_TRAP 0x12#define SQ_S_ICACHE_INV 0x13#define SQ_S_INCPERFLEVEL 0x14#define SQ_S_DECPERFLEVEL 0x15#define SQ_S_TTRACEDATA 0x16#define SQ_S_CBRANCH_CDBGSYS 0x17#define SQ_S_CBRANCH_CDBGUSER 0x18#define SQ_S_CBRANCH_CDBGSYS_OR_USER 0x19#define SQ_S_CBRANCH_CDBGSYS_AND_USER 0x1a#define SQ_S_ENDPGM_SAVED 0x1b#define SQ_S_SET_GPR_IDX_OFF 0x1c#define SQ_S_SET_GPR_IDX_MODE 0x1d#define SQ_SRC_DPP 0xfa#define SQ_SRC_LITERAL 0xff#define SQ_VCC_LO 0x6a#define SQ_VCC_HI 0x6b#define SQ_PARAM_P10 0x0#define SQ_PARAM_P20 0x1#define SQ_PARAM_P0 0x2#define SQ_SRC_LDS_DIRECT 0xfe#define SQ_V_CNDMASK_B32 0x0#define SQ_V_ADD_F32 0x1#define SQ_V_SUB_F32 0x2#define SQ_V_SUBREV_F32 0x3#define SQ_V_MUL_LEGACY_F32 0x4#define SQ_V_MUL_F32 0x5#define SQ_V_MUL_I32_I24 0x6#define SQ_V_MUL_HI_I32_I24 0x7#define SQ_V_MUL_U32_U24 0x8#define SQ_V_MUL_HI_U32_U24 0x9#define SQ_V_MIN_F32 0xa#define SQ_V_MAX_F32 0xb#define SQ_V_MIN_I32 0xc#define SQ_V_MAX_I32 0xd#define SQ_V_MIN_U32 0xe#define SQ_V_MAX_U32 0xf#define SQ_V_LSHRREV_B32 0x10#define SQ_V_ASHRREV_I32 0x11#define SQ_V_LSHLREV_B32 0x12#define SQ_V_AND_B32 0x13#define SQ_V_OR_B32 0x14#define SQ_V_XOR_B32 0x15#define SQ_V_MAC_F32 0x16#define SQ_V_MADMK_F32 0x17#define SQ_V_MADAK_F32 0x18#define SQ_V_ADD_U32 0x19#define SQ_V_SUB_U32 0x1a#define SQ_V_SUBREV_U32 0x1b#define SQ_V_ADDC_U32 0x1c#define SQ_V_SUBB_U32 0x1d#define SQ_V_SUBBREV_U32 0x1e#define SQ_V_ADD_F16 0x1f#define SQ_V_SUB_F16 0x20#define SQ_V_SUBREV_F16 0x21#define SQ_V_MUL_F16 0x22#define SQ_V_MAC_F16 0x23#define SQ_V_MADMK_F16 0x24#define SQ_V_MADAK_F16 0x25#define SQ_V_ADD_U16 0x26#define SQ_V_SUB_U16 0x27#define SQ_V_SUBREV_U16 0x28#define SQ_V_MUL_LO_U16 0x29#define SQ_V_LSHLREV_B16 0x2a#define SQ_V_LSHRREV_B16 0x2b#define SQ_V_ASHRREV_I16 0x2c#define SQ_V_MAX_F16 0x2d#define SQ_V_MIN_F16 0x2e#define SQ_V_MAX_U16 0x2f#define SQ_V_MAX_I16 0x30#define SQ_V_MIN_U16 0x31#define SQ_V_MIN_I16 0x32#define SQ_V_LDEXP_F16 0x33#define SQ_FLAT_LOAD_UBYTE 0x10#define SQ_FLAT_LOAD_SBYTE 0x11#define SQ_FLAT_LOAD_USHORT 0x12#define SQ_FLAT_LOAD_SSHORT 0x13#define SQ_FLAT_LOAD_DWORD 0x14#define SQ_FLAT_LOAD_DWORDX2 0x15#define SQ_FLAT_LOAD_DWORDX3 0x16#define SQ_FLAT_LOAD_DWORDX4 0x17#define SQ_FLAT_STORE_BYTE 0x18#define SQ_FLAT_STORE_SHORT 0x1a#define SQ_FLAT_STORE_DWORD 0x1c#define SQ_FLAT_STORE_DWORDX2 0x1d#define SQ_FLAT_STORE_DWORDX3 0x1e#define SQ_FLAT_STORE_DWORDX4 0x1f#define SQ_FLAT_ATOMIC_SWAP 0x40#define SQ_FLAT_ATOMIC_CMPSWAP 0x41#define SQ_FLAT_ATOMIC_ADD 0x42#define SQ_FLAT_ATOMIC_SUB 0x43#define SQ_FLAT_ATOMIC_SMIN 0x44#define SQ_FLAT_ATOMIC_UMIN 0x45#define SQ_FLAT_ATOMIC_SMAX 0x46#define SQ_FLAT_ATOMIC_UMAX 0x47#define SQ_FLAT_ATOMIC_AND 0x48#define SQ_FLAT_ATOMIC_OR 0x49#define SQ_FLAT_ATOMIC_XOR 0x4a#define SQ_FLAT_ATOMIC_INC 0x4b#define SQ_FLAT_ATOMIC_DEC 0x4c#define SQ_FLAT_ATOMIC_SWAP_X2 0x60#define SQ_FLAT_ATOMIC_CMPSWAP_X2 0x61#define SQ_FLAT_ATOMIC_ADD_X2 0x62#define SQ_FLAT_ATOMIC_SUB_X2 0x63#define SQ_FLAT_ATOMIC_SMIN_X2 0x64#define SQ_FLAT_ATOMIC_UMIN_X2 0x65#define SQ_FLAT_ATOMIC_SMAX_X2 0x66#define SQ_FLAT_ATOMIC_UMAX_X2 0x67#define SQ_FLAT_ATOMIC_AND_X2 0x68#define SQ_FLAT_ATOMIC_OR_X2 0x69#define SQ_FLAT_ATOMIC_XOR_X2 0x6a#define SQ_FLAT_ATOMIC_INC_X2 0x6b#define SQ_FLAT_ATOMIC_DEC_X2 0x6c#define SQ_S_CMP_EQ_I32 0x0#define SQ_S_CMP_LG_I32 0x1#define SQ_S_CMP_GT_I32 0x2#define SQ_S_CMP_GE_I32 0x3#define SQ_S_CMP_LT_I32 0x4#define SQ_S_CMP_LE_I32 0x5#define SQ_S_CMP_EQ_U32 0x6#define SQ_S_CMP_LG_U32 0x7#define SQ_S_CMP_GT_U32 0x8#define SQ_S_CMP_GE_U32 0x9#define SQ_S_CMP_LT_U32 0xa#define SQ_S_CMP_LE_U32 0xb#define SQ_S_BITCMP0_B32 0xc#define SQ_S_BITCMP1_B32 0xd#define SQ_S_BITCMP0_B64 0xe#define SQ_S_BITCMP1_B64 0xf#define SQ_S_SETVSKIP 0x10#define SQ_S_SET_GPR_IDX_ON 0x11#define SQ_S_CMP_EQ_U64 0x12#define SQ_S_CMP_LG_U64 0x13#define SQ_M0 0x7c#define SQ_V_MAD_LEGACY_F32 0x1c0#define SQ_V_MAD_F32 0x1c1#define SQ_V_MAD_I32_I24 0x1c2#define SQ_V_MAD_U32_U24 0x1c3#define SQ_V_CUBEID_F32 0x1c4#define SQ_V_CUBESC_F32 0x1c5#define SQ_V_CUBETC_F32 0x1c6#define SQ_V_CUBEMA_F32 0x1c7#define SQ_V_BFE_U32 0x1c8#define SQ_V_BFE_I32 0x1c9#define SQ_V_BFI_B32 0x1ca#define SQ_V_FMA_F32 0x1cb#define SQ_V_FMA_F64 0x1cc#define SQ_V_LERP_U8 0x1cd#define SQ_V_ALIGNBIT_B32 0x1ce#define SQ_V_ALIGNBYTE_B32 0x1cf#define SQ_V_MIN3_F32 0x1d0#define SQ_V_MIN3_I32 0x1d1#define SQ_V_MIN3_U32 0x1d2#define SQ_V_MAX3_F32 0x1d3#define SQ_V_MAX3_I32 0x1d4#define SQ_V_MAX3_U32 0x1d5#define SQ_V_MED3_F32 0x1d6#define SQ_V_MED3_I32 0x1d7#define SQ_V_MED3_U32 0x1d8#define SQ_V_SAD_U8 0x1d9#define SQ_V_SAD_HI_U8 0x1da#define SQ_V_SAD_U16 0x1db#define SQ_V_SAD_U32 0x1dc#define SQ_V_CVT_PK_U8_F32 0x1dd#define SQ_V_DIV_FIXUP_F32 0x1de#define SQ_V_DIV_FIXUP_F64 0x1df#define SQ_V_DIV_SCALE_F32 0x1e0#define SQ_V_DIV_SCALE_F64 0x1e1#define SQ_V_DIV_FMAS_F32 0x1e2#define SQ_V_DIV_FMAS_F64 0x1e3#define SQ_V_MSAD_U8 0x1e4#define SQ_V_QSAD_PK_U16_U8 0x1e5#define SQ_V_MQSAD_PK_U16_U8 0x1e6#define SQ_V_MQSAD_U32_U8 0x1e7#define SQ_V_MAD_U64_U32 0x1e8#define SQ_V_MAD_I64_I32 0x1e9#define SQ_V_MAD_F16 0x1ea#define SQ_V_MAD_U16 0x1eb#define SQ_V_MAD_I16 0x1ec#define SQ_V_PERM_B32 0x1ed#define SQ_V_FMA_F16 0x1ee#define SQ_V_DIV_FIXUP_F16 0x1ef#define SQ_V_CVT_PKACCUM_U8_F32 0x1f0#define SQ_V_INTERP_P1LL_F16 0x274#define SQ_V_INTERP_P1LV_F16 0x275#define SQ_V_INTERP_P2_F16 0x276#define SQ_V_ADD_F64 0x280#define SQ_V_MUL_F64 0x281#define SQ_V_MIN_F64 0x282#define SQ_V_MAX_F64 0x283#define SQ_V_LDEXP_F64 0x284#define SQ_V_MUL_LO_U32 0x285#define SQ_V_MUL_HI_U32 0x286#define SQ_V_MUL_HI_I32 0x287#define SQ_V_LDEXP_F32 0x288#define SQ_V_READLANE_B32 0x289#define SQ_V_WRITELANE_B32 0x28a#define SQ_V_BCNT_U32_B32 0x28b#define SQ_V_MBCNT_LO_U32_B32 0x28c#define SQ_V_MBCNT_HI_U32_B32 0x28d#define SQ_V_MAC_LEGACY_F32 0x28e#define SQ_V_LSHLREV_B64 0x28f#define SQ_V_LSHRREV_B64 0x290#define SQ_V_ASHRREV_I64 0x291#define SQ_V_TRIG_PREOP_F64 0x292#define SQ_V_BFM_B32 0x293#define SQ_V_CVT_PKNORM_I16_F32 0x294#define SQ_V_CVT_PKNORM_U16_F32 0x295#define SQ_V_CVT_PKRTZ_F16_F32 0x296#define SQ_V_CVT_PK_U16_U32 0x297#define SQ_V_CVT_PK_I16_I32 0x298#define SQ_VCC_ALL 0x0#define SQ_SRC_EXECZ 0xfc#define SQ_FLAT_SCRATCH_LO 0x66#define SQ_FLAT_SCRATCH_HI 0x67#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x1#define SQ_SYSMSG_OP_REG_RD 0x2#define SQ_SYSMSG_OP_HOST_TRAP_ACK 0x3#define SQ_SYSMSG_OP_TTRACE_PC 0x4#define SQ_HW_REG_MODE 0x1#define SQ_HW_REG_STATUS 0x2#define SQ_HW_REG_TRAPSTS 0x3#define SQ_HW_REG_HW_ID 0x4#define SQ_HW_REG_GPR_ALLOC 0x5#define SQ_HW_REG_LDS_ALLOC 0x6#define SQ_HW_REG_IB_STS 0x7#define SQ_HW_REG_PC_LO 0x8#define SQ_HW_REG_PC_HI 0x9#define SQ_HW_REG_INST_DW0 0xa#define SQ_HW_REG_INST_DW1 0xb#define SQ_HW_REG_IB_DBG0 0xc#define SQ_HW_REG_IB_DBG1 0xd#define SQ_DPP_BOUND_OFF 0x0#define SQ_DPP_BOUND_ZERO 0x1#define SQ_R1 0x1#define SQ_R2 0x2#define SQ_R3 0x3#define SQ_R4 0x4#define SQ_R5 0x5#define SQ_R6 0x6#define SQ_R7 0x7#define SQ_R8 0x8#define SQ_R9 0x9#define SQ_R10 0xa#define SQ_R11 0xb#define SQ_R12 0xc#define SQ_R13 0xd#define SQ_R14 0xe#define SQ_R15 0xf#define SQ_S_ADD_U32 0x0#define SQ_S_SUB_U32 0x1#define SQ_S_ADD_I32 0x2#define SQ_S_SUB_I32 0x3#define SQ_S_ADDC_U32 0x4#define SQ_S_SUBB_U32 0x5#define SQ_S_MIN_I32 0x6#define SQ_S_MIN_U32 0x7#define SQ_S_MAX_I32 0x8#define SQ_S_MAX_U32 0x9#define SQ_S_CSELECT_B32 0xa#define SQ_S_CSELECT_B64 0xb#define SQ_S_AND_B32 0xc#define SQ_S_AND_B64 0xd#define SQ_S_OR_B32 0xe#define SQ_S_OR_B64 0xf#define SQ_S_XOR_B32 0x10#define SQ_S_XOR_B64 0x11#define SQ_S_ANDN2_B32 0x12#define SQ_S_ANDN2_B64 0x13#define SQ_S_ORN2_B32 0x14#define SQ_S_ORN2_B64 0x15#define SQ_S_NAND_B32 0x16#define SQ_S_NAND_B64 0x17#define SQ_S_NOR_B32 0x18#define SQ_S_NOR_B64 0x19#define SQ_S_XNOR_B32 0x1a#define SQ_S_XNOR_B64 0x1b#define SQ_S_LSHL_B32 0x1c#define SQ_S_LSHL_B64 0x1d#define SQ_S_LSHR_B32 0x1e#define SQ_S_LSHR_B64 0x1f#define SQ_S_ASHR_I32 0x20#define SQ_S_ASHR_I64 0x21#define SQ_S_BFM_B32 0x22#define SQ_S_BFM_B64 0x23#define SQ_S_MUL_I32 0x24#define SQ_S_BFE_U32 0x25#define SQ_S_BFE_I32 0x26#define SQ_S_BFE_U64 0x27#define SQ_S_BFE_I64 0x28#define SQ_S_CBRANCH_G_FORK 0x29#define SQ_S_ABSDIFF_I32 0x2a#define SQ_S_RFE_RESTORE_B64 0x2b#define SQ_MSG_INTERRUPT 0x1#define SQ_MSG_GS 0x2#define SQ_MSG_GS_DONE 0x3#define SQ_MSG_SAVEWAVE 0x4#define SQ_MSG_SYSMSG 0xftypedef enum TEX_BORDER_COLOR_TYPE {typedef enum TEX_CHROMA_KEY {typedef enum TEX_CLAMP {typedef enum TEX_COORD_TYPE {typedef enum TEX_DEPTH_COMPARE_FUNCTION {typedef enum TEX_DIM {typedef enum TEX_FORMAT_COMP {typedef enum TEX_MAX_ANISO_RATIO {typedef enum TEX_MIP_FILTER {typedef enum TEX_REQUEST_SIZE {typedef enum TEX_SAMPLER_TYPE {typedef enum TEX_XY_FILTER {typedef enum TEX_Z_FILTER {typedef enum VTX_CLAMP {typedef enum VTX_FETCH_TYPE {typedef enum VTX_FORMAT_COMP_ALL {typedef enum VTX_MEM_REQUEST_SIZE {typedef enum TVX_DATA_FORMAT {typedef enum TVX_DST_SEL {typedef enum TVX_ENDIAN_SWAP {typedef enum TVX_INST {typedef enum TVX_NUM_FORMAT_ALL {typedef enum TVX_SRC_SEL {typedef enum TVX_SRF_MODE_ALL {typedef enum TVX_TYPE {typedef enum TC_OP_MASKS {typedef enum TC_OP {typedef enum TC_CHUB_REQ_CREDITS_ENUM {typedef enum CHUB_TC_RET_CREDITS_ENUM {typedef enum TC_NACKS {typedef enum TCC_PERF_SEL {typedef enum TCA_PERF_SEL {typedef enum TA_TC_ADDR_MODES {typedef enum TA_PERFCOUNT_SEL {typedef enum TD_PERFCOUNT_SEL {typedef enum TCP_PERFCOUNT_SELECT {typedef enum TCP_CACHE_POLICIES {typedef enum TCP_CACHE_STORE_POLICIES {typedef enum TCP_WATCH_MODES {typedef enum TCP_DSM_DATA_SEL {typedef enum TCP_DSM_SINGLE_WRITE {typedef enum VGT_OUT_PRIM_TYPE {typedef enum VGT_DI_PRIM_TYPE {typedef enum VGT_DI_SOURCE_SELECT {typedef enum VGT_DI_MAJOR_MODE_SELECT {typedef enum VGT_DI_INDEX_SIZE {typedef enum VGT_EVENT_TYPE {typedef enum VGT_DMA_SWAP_MODE {typedef enum VGT_INDEX_TYPE_MODE {typedef enum VGT_DMA_BUF_TYPE {typedef enum VGT_OUTPATH_SELECT {typedef enum VGT_GRP_PRIM_TYPE {typedef enum VGT_GRP_PRIM_ORDER {typedef enum VGT_GROUP_CONV_SEL {typedef enum VGT_GS_MODE_TYPE {typedef enum VGT_GS_CUT_MODE {typedef enum VGT_GS_OUTPRIM_TYPE {typedef enum VGT_CACHE_INVALID_MODE {typedef enum VGT_TESS_TYPE {typedef enum VGT_TESS_PARTITION {typedef enum VGT_TESS_TOPOLOGY {typedef enum VGT_RDREQ_POLICY {typedef enum VGT_DIST_MODE {typedef enum VGT_STAGES_LS_EN {typedef enum VGT_STAGES_HS_EN {typedef enum VGT_STAGES_ES_EN {typedef enum VGT_STAGES_GS_EN {typedef enum VGT_STAGES_VS_EN {typedef enum VGT_PERFCOUNT_SELECT {typedef enum IA_PERFCOUNT_SELECT {typedef enum WD_PERFCOUNT_SELECT {typedef enum WD_IA_DRAW_TYPE {typedef enum WD_IA_DRAW_SOURCE {#define GSTHREADID_SIZE 0x2typedef enum SurfaceEndian {typedef enum ArrayMode {typedef enum PipeTiling {typedef enum BankTiling {typedef enum GroupInterleave {typedef enum RowTiling {typedef enum BankSwapBytes {typedef enum SampleSplitBytes {typedef enum NumPipes {typedef enum PipeInterleaveSize {typedef enum BankInterleaveSize {typedef enum NumShaderEngines {typedef enum ShaderEngineTileSize {typedef enum NumGPUs {typedef enum MultiGPUTileSize {typedef enum RowSize {typedef enum NumLowerPipes {typedef enum DebugBlockId {typedef enum DebugBlockId_OLD {typedef enum DebugBlockId_BY2 {typedef enum DebugBlockId_BY4 {typedef enum DebugBlockId_BY8 {typedef enum DebugBlockId_BY16 {typedef enum ColorTransform {typedef enum CompareRef {typedef enum ReadSize {typedef enum DepthFormat {typedef enum ZFormat {typedef enum StencilFormat {typedef enum CmaskMode {typedef enum QuadExportFormat {typedef enum QuadExportFormatOld {typedef enum ColorFormat {typedef enum SurfaceFormat {typedef enum BUF_DATA_FORMAT {typedef enum IMG_DATA_FORMAT {typedef enum BUF_NUM_FORMAT {typedef enum IMG_NUM_FORMAT {typedef enum TileType {typedef enum NonDispTilingOrder {typedef enum MicroTileMode {typedef enum TileSplit {typedef enum SampleSplit {typedef enum PipeConfig {typedef enum NumBanks {typedef enum BankWidth {typedef enum BankHeight {typedef enum BankWidthHeight {typedef enum MacroTileAspect {typedef enum GATCL1RequestType {typedef enum TCC_CACHE_POLICIES {typedef enum MTYPE {typedef enum PERFMON_COUNTER_MODE {typedef enum PERFMON_SPM_MODE {typedef enum SurfaceTiling {typedef enum SurfaceArray {typedef enum ColorArray {typedef enum DepthArray {typedef enum ENUM_NUM_SIMD_PER_CU {typedef enum MEM_PWR_FORCE_CTRL {typedef enum MEM_PWR_FORCE_CTRL2 {typedef enum MEM_PWR_DIS_CTRL {typedef enum MEM_PWR_SEL_CTRL {typedef enum MEM_PWR_SEL_CTRL2 {#endif /* GFX_8_0_ENUM_H */
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