/** * struct intel_guc - Top level structure of GuC. * * It handles firmware loading and manages client pool. intel_guc owns an * i915_sched_engine for submission.
*/ struct intel_guc { /** @fw: the GuC firmware */ struct intel_uc_fw fw; /** @log: sub-structure containing GuC log related data and objects */ struct intel_guc_log log; /** @ct: the command transport communication channel */ struct intel_guc_ct ct; /** @slpc: sub-structure containing SLPC related data and objects */ struct intel_guc_slpc slpc; /** @capture: the error-state-capture module's data and objects */ struct intel_guc_state_capture *capture;
/** @sched_engine: Global engine used to submit requests to GuC */ struct i915_sched_engine *sched_engine; /** * @stalled_request: if GuC can't process a request for any reason, we * save it until GuC restarts processing. No other request can be * submitted until the stalled request is processed.
*/ struct i915_request *stalled_request; /** * @submission_stall_reason: reason why submission is stalled
*/ enum {
STALL_NONE,
STALL_REGISTER_CONTEXT,
STALL_MOVE_LRC_TAIL,
STALL_ADD_REQUEST,
} submission_stall_reason;
/* intel_guc_recv interrupt related state */ /** @irq_lock: protects GuC irq state */
spinlock_t irq_lock; /** * @msg_enabled_mask: mask of events that are processed when receiving * an INTEL_GUC_ACTION_DEFAULT G2H message.
*/ unsignedint msg_enabled_mask;
/** * @outstanding_submission_g2h: number of outstanding GuC to Host * responses related to GuC submission, used to determine if the GT is * idle
*/
atomic_t outstanding_submission_g2h;
/** @tlb_lookup: xarray to store all pending TLB invalidation requests */ struct xarray tlb_lookup;
/** * @serial_slot: id to the initial waiter created in tlb_lookup, * which is used only when failed to allocate new waiter.
*/
u32 serial_slot;
/** @next_seqno: the next id (sequence number) to allocate. */
u32 next_seqno;
/** * @submission_state: sub-structure for submission state protected by * single lock
*/ struct { /** * @submission_state.lock: protects everything in * submission_state, ce->guc_id.id, and ce->guc_id.ref * when transitioning in and out of zero
*/
spinlock_t lock; /** * @submission_state.guc_ids: used to allocate new * guc_ids, single-lrc
*/ struct ida guc_ids; /** * @submission_state.num_guc_ids: Number of guc_ids, selftest * feature to be able to reduce this number while testing.
*/ int num_guc_ids; /** * @submission_state.guc_ids_bitmap: used to allocate * new guc_ids, multi-lrc
*/ unsignedlong *guc_ids_bitmap; /** * @submission_state.guc_id_list: list of intel_context * with valid guc_ids but no refs
*/ struct list_head guc_id_list; /** * @submission_state.guc_ids_in_use: Number single-lrc * guc_ids in use
*/ unsignedint guc_ids_in_use; /** * @submission_state.destroyed_contexts: list of contexts * waiting to be destroyed (deregistered with the GuC)
*/ struct list_head destroyed_contexts; /** * @submission_state.destroyed_worker: worker to deregister * contexts, need as we need to take a GT PM reference and * can't from destroy function as it might be in an atomic * context (no sleeping)
*/ struct work_struct destroyed_worker; /** * @submission_state.reset_fail_worker: worker to trigger * a GT reset after an engine reset fails
*/ struct work_struct reset_fail_worker; /** * @submission_state.reset_fail_mask: mask of engines that * failed to reset
*/
intel_engine_mask_t reset_fail_mask; /** * @submission_state.sched_disable_delay_ms: schedule * disable delay, in ms, for contexts
*/ unsignedint sched_disable_delay_ms; /** * @submission_state.sched_disable_gucid_threshold: * threshold of min remaining available guc_ids before * we start bypassing the schedule disable delay
*/ unsignedint sched_disable_gucid_threshold;
} submission_state;
/** * @submission_supported: tracks whether we support GuC submission on * the current platform
*/ bool submission_supported; /** @submission_selected: tracks whether the user enabled GuC submission */ bool submission_selected; /** @submission_initialized: tracks whether GuC submission has been initialised */ bool submission_initialized; /** @submission_version: Submission API version of the currently loaded firmware */ struct intel_uc_fw_ver submission_version;
/** * @rc_supported: tracks whether we support GuC rc on the current platform
*/ bool rc_supported; /** @rc_selected: tracks whether the user enabled GuC rc */ bool rc_selected;
/** @ads_vma: object allocated to hold the GuC ADS */ struct i915_vma *ads_vma; /** @ads_map: contents of the GuC ADS */ struct iosys_map ads_map; /** @ads_regset_size: size of the save/restore regsets in the ADS */
u32 ads_regset_size; /** * @ads_regset_count: number of save/restore registers in the ADS for * each engine
*/
u32 ads_regset_count[I915_NUM_ENGINES]; /** @ads_regset: save/restore regsets in the ADS */ struct guc_mmio_reg *ads_regset; /** @ads_golden_ctxt_size: size of the golden contexts in the ADS */
u32 ads_golden_ctxt_size; /** @ads_waklv_size: size of workaround KLVs */
u32 ads_waklv_size; /** @ads_capture_size: size of register lists in the ADS used for error capture */
u32 ads_capture_size;
/** @lrc_desc_pool_v69: object allocated to hold the GuC LRC descriptor pool */ struct i915_vma *lrc_desc_pool_v69; /** @lrc_desc_pool_vaddr_v69: contents of the GuC LRC descriptor pool */ void *lrc_desc_pool_vaddr_v69;
/** * @context_lookup: used to resolve intel_context from guc_id, if a * context is present in this structure it is registered with the GuC
*/ struct xarray context_lookup;
/** @params: Control params for fw initialization */
u32 params[GUC_CTL_MAX_DWORDS];
/** @send_regs: GuC's FW specific registers used for sending MMIO H2G */ struct {
u32 base; unsignedint count; enum forcewake_domains fw_domains;
} send_regs;
/** @notify_reg: register used to send interrupts to the GuC FW */
i915_reg_t notify_reg;
/** * @mmio_msg: notification bitmask that the GuC writes in one of its * registers when the CT channel is disabled, to be processed when the * channel is back up.
*/
u32 mmio_msg;
/** @send_mutex: used to serialize the intel_guc_send actions */ struct mutex send_mutex;
/** * @timestamp: GT timestamp object that stores a copy of the timestamp * and adjusts it for overflow using a worker.
*/ struct { /** * @timestamp.lock: Lock protecting the below fields and * the engine stats.
*/
spinlock_t lock;
/** * @timestamp.gt_stamp: 64-bit extended value of the GT * timestamp.
*/
u64 gt_stamp;
/** * @timestamp.ping_delay: Period for polling the GT * timestamp for overflow.
*/ unsignedlong ping_delay;
/** * @timestamp.work: Periodic work to adjust GT timestamp, * engine and context usage for overflows.
*/ struct delayed_work work;
/** * @timestamp.shift: Right shift value for the gpm timestamp
*/
u32 shift;
/** * @timestamp.last_stat_jiffies: jiffies at last actual * stats collection time. We use this timestamp to ensure * we don't oversample the stats because runtime power * management events can trigger stats collection at much * higher rates than required.
*/ unsignedlong last_stat_jiffies;
} timestamp;
/** * @dead_guc_worker: Asynchronous worker thread for forcing a GuC reset. * Specifically used when the G2H handler wants to issue a reset. Resets * require flushing the G2H queue. So, the G2H processing itself must not * trigger a reset directly. Instead, go via this worker.
*/ struct work_struct dead_guc_worker; /** * @last_dead_guc_jiffies: timestamp of previous 'dead guc' occurrence * used to prevent a fundamentally broken system from continuously * reloading the GuC.
*/ unsignedlong last_dead_guc_jiffies;
#ifdef CONFIG_DRM_I915_SELFTEST /** * @number_guc_id_stolen: The number of guc_ids that have been stolen
*/ int number_guc_id_stolen; /** * @fast_response_selftest: Backdoor to CT handler for fast response selftest
*/
u32 fast_response_selftest; #endif
};
/* * FIXME: Have caller pass in if we are in an atomic context to avoid * using in_atomic(). It is likely safe here as we check for irqs * disabled which basically all the spin locks in the i915 do but * regardless this should be cleaned up.
*/
/* No sleeping with spin locks, just busy loop */
might_sleep_if(loop && not_atomic);
/* Only call this from the interrupt handler code */ staticinlinevoid intel_guc_to_host_event_handler(struct intel_guc *guc)
{ if (guc->interrupts.enabled)
intel_guc_ct_event_handler(&guc->ct);
}
/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */ #define GUC_GGTT_TOP 0xFEE00000
/** * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma * @guc: intel_guc structure. * @vma: i915 graphics virtual memory area. * * GuC does not allow any gfx GGTT address that falls into range * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM. * Currently, in order to exclude [0, ggtt.pin_bias) address space from * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma() * and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias. * * Return: GGTT offset of the @vma.
*/ staticinline u32 intel_guc_ggtt_offset(struct intel_guc *guc, struct i915_vma *vma)
{
u32 offset = i915_ggtt_offset(vma);
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