<enum name="vgt_event_type" varset="chip">
<value name="VS_DEALLOC" value="0"/>
<value name="PS_DEALLOC" value="1" variants="A2XX-A6XX"/>
<value name="VS_DONE_TS" value="2"/>
<value name="PS_DONE_TS" value="3"/>
<doc>
Flushes dirty data from UCHE, and also writes a GPU timestamp to
the address if one is provided.
</doc>
<value name="CACHE_FLUSH_TS" value="4"/>
<value name="CONTEXT_DONE" value="5"/>
<value name="CACHE_FLUSH" value="6" variants="A2XX-A4XX"/>
<value name="VIZQUERY_START" value="7" variants="A2XX"/>
<value name="HLSQ_FLUSH" value="7" variants="A3XX-A4XX"/>
<value name="VIZQUERY_END" value="8" variants="A2XX"/>
<value name="SC_WAIT_WC" value="9" variants="A2XX"/>
<value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX-"/>
<value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX-"/>
<value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX-"/> <!-- Not sure that these 4 events don't have the same meaning as on A5XX+ -->
<value name="RST_PIX_CNT" value="13" variants="A2XX-A4XX"/>
<value name="RST_VTX_CNT" value="14" variants="A2XX-A4XX"/>
<value name="TILE_FLUSH" value="15" variants="A2XX-A4XX"/>
<value name="STAT_EVENT" value="16" variants="A2XX-A4XX"/>
<value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX-A4XX"/>
<doc>
If A6XX_RB_SAMPLE_COUNTER_CNTL.copy is true, writes OQ Z passed
sample counts to RB_SAMPLE_COUNTER_BASE. This writes to main
memory, skipping UCHE.
</doc>
<value name="ZPASS_DONE" value="21"/>
<value name="CACHE_FLUSH_AND_INV_EVENT" value="22" variants="A2XX"/>
<doc>
Writes the GPU timestamp to the address that follows, once RB
access and flushes are complete.
</doc>
<value name="RB_DONE_TS" value="22" variants="A3XX-"/>
<doc>
Invalidates depth attachment data from the CCU. We assume this
happens in the last stage.
</doc>
<value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX-"/>
<doc>
Invalidates color attachment data from the CCU. We assume this
happens in the last stage.
</doc>
<value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX-"/>
<doc>
Flushes the small cache used by CP_EVENT_WRITE::BLIT (which,
along with its registers, would be better named RESOLVE).
</doc>
<value name="PC_CCU_RESOLVE_TS" value="26" variants="A6XX"/>
<doc>
Flushes depth attachment data from the CCU. We assume this
happens in the last stage.
</doc>
<value name="PC_CCU_FLUSH_DEPTH_TS" value="28" variants="A5XX-"/>
<doc>
Flushes color attachment data from the CCU. We assume this
happens in the last stage.
</doc>
<value name="PC_CCU_FLUSH_COLOR_TS" value="29" variants="A5XX-"/>
<doc>
2D blit to resolve GMEM to system memory (skipping CCU) at the
end of a render pass. Compare to CP_BLIT's BLIT_OP_SCALE for
more general blitting.
</doc>
<value name="BLIT" value="30" variants="A5XX-"/>
<doc>
Flip between the primary and secondary LRZ buffers. This is used
for concurrent binning, so that BV can write to one buffer while
BR reads from the other.
</doc>
<value name="LRZ_FLIP_BUFFER" value="36" variants="A7XX"/>
<doc>
Clears based on GRAS_LRZ_CNTL configuration, could clear
fast-clear buffer or LRZ direction.
LRZ direction is stored at lrz_fc_offset + 0x200, has 1 byte which
could be expressed by enum:
CUR_DIR_DISABLED = 0x0
CUR_DIR_GE = 0x1
CUR_DIR_LE = 0x2
CUR_DIR_UNSET = 0x3
Clear of direction means setting the direction to CUR_DIR_UNSET.
</doc>
<value name="LRZ_CLEAR" value="37" variants="A5XX-"/>
<!-- Note that in some cases, the same packet id is recycled on a later generation, so variants attribute is used to distinguish. They may not be completely accurate, we would probably have to analyze the pfp and me/pm4 firmware to verify the packet is actually handled on a particular generation. But it is at least enough to disambiguate the packet-id's that were re-used for different packets starting with a5xx.
-->
<enum name="adreno_pm4_type3_packets" varset="chip">
<doc>initialize CP's micro-engine</doc>
<value name="CP_ME_INIT" value="0x48"/>
<doc>skip N 32-bit words to get to the next packet</doc>
<value name="CP_NOP" value="0x10"/>
<doc>
indirect buffer dispatch. prefetch parser uses this packet type to determine whether to pre-fetch the IB
</doc>
<value name="CP_PREEMPT_ENABLE" value="0x1c" variants="A5XX"/>
<value name="CP_PREEMPT_TOKEN" value="0x1e" variants="A5XX"/>
<value name="CP_INDIRECT_BUFFER" value="0x3f"/>
<doc>
Takes the same arguments as CP_INDIRECT_BUFFER, but jumps to
another buffer at the same level. Must be at the end of IB, and
doesn't work with draw state IB's.
</doc>
<value name="CP_INDIRECT_BUFFER_CHAIN" value="0x57" variants="A5XX-"/>
<doc>indirect buffer dispatch. same as IB, but init is pipelined</doc>
<value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/>
<doc>
Waits for the IDLE state of the engine before further drawing.
This is pipelined, so the CP may continue.
</doc>
<value name="CP_WAIT_FOR_IDLE" value="0x26"/>
<doc>wait until a register or memory location is a specific value</doc>
<value name="CP_WAIT_REG_MEM" value="0x3c"/>
<doc>wait until a register location is equal to a specific value</doc>
<value name="CP_WAIT_REG_EQ" value="0x52"/>
<doc>wait until a register location is >= a specific value</doc>
<value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX-A4XX"/>
<doc>wait until a read completes</doc>
<value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX-A4XX"/>
<doc>wait until all base/size writes from an IB_PFD packet have completed</doc> <!-- NOTE: CP_WAIT_IB_PFD_COMPLETE unimplemented at least since a5xx fw, and recycled for something new on a7xx
-->
<value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d" varset="chip" variants="A2XX-A4XX"/>
<doc>register read/modify/write</doc>
<value name="CP_REG_RMW" value="0x21"/>
<doc>Set binning configuration registers</doc>
<value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX-A4XX"/>
<value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX-"/>
<doc>reads register in chip and writes to memory</doc>
<value name="CP_REG_TO_MEM" value="0x3e"/>
<doc>write N 32-bit words to memory</doc>
<value name="CP_MEM_WRITE" value="0x3d"/>
<doc>write CP_PROG_COUNTER value to memory</doc>
<value name="CP_MEM_WRITE_CNTR" value="0x4f"/>
<doc>conditional execution of a sequence of packets</doc>
<value name="CP_COND_EXEC" value="0x44"/>
<doc>conditional write to memory or register</doc>
<value name="CP_COND_WRITE" value="0x45" variants="A2XX-A4XX"/>
<value name="CP_COND_WRITE5" value="0x45" variants="A5XX-"/>
<doc>generate an event that creates a write to memory when completed</doc>
<value name="CP_EVENT_WRITE" value="0x46" variants="A2XX-A6XX"/>
<value name="CP_EVENT_WRITE7" value="0x46" variants="A7XX-"/>
<doc>generate a VS|PS_done event</doc>
<value name="CP_EVENT_WRITE_SHD" value="0x58"/>
<doc>generate a cache flush done event</doc>
<value name="CP_EVENT_WRITE_CFL" value="0x59"/>
<doc>generate a z_pass done event</doc>
<value name="CP_EVENT_WRITE_ZPD" value="0x5b"/>
<doc>
not sure the real name, but this seems to be what is used for
opencl, instead of CP_DRAW_INDX..
</doc>
<value name="CP_RUN_OPENCL" value="0x31"/>
<doc>initiate fetch of index buffer and draw</doc>
<value name="CP_DRAW_INDX" value="0x22"/>
<doc>draw using supplied indices in packet</doc>
<value name="CP_DRAW_INDX_2" value="0x36" variants="A2XX-A4XX"/> <!-- this is something different on a6xx and unused on a5xx -->
<doc>initiate fetch of index buffer and binIDs and draw</doc>
<value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX-A4XX"/>
<doc>initiate fetch of bin IDs and draw using supplied indices</doc>
<value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX-A4XX"/>
<doc>begin/end initiator for viz query extent processing</doc>
<value name="CP_VIZ_QUERY" value="0x23" variants="A2XX-A4XX"/>
<doc>fetch state sub-blocks and initiate shader code DMAs</doc>
<value name="CP_SET_STATE" value="0x25"/>
<doc>load constant into chip and to memory</doc>
<value name="CP_SET_CONSTANT" value="0x2d" variants="A2XX"/>
<doc>load sequencer instruction memory (pointer-based)</doc>
<value name="CP_IM_LOAD" value="0x27"/>
<doc>load sequencer instruction memory (code embedded in packet)</doc>
<value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
<doc>load constants from a location in memory</doc>
<value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" variants="A2XX"/>
<doc>selective invalidation of state pointers</doc>
<value name="CP_INVALIDATE_STATE" value="0x3b"/>
<doc>dynamically changes shader instruction memory partition</doc>
<value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX-A4XX"/>
<doc>sets the 64-bit BIN_MASK register in the PFP</doc>
<value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX-A4XX"/>
<doc>sets the 64-bit BIN_SELECT register in the PFP</doc>
<value name="CP_SET_BIN_SELECT" value="0x51" variants="A2XX-A4XX"/>
<doc>updates the current context, if needed</doc>
<value name="CP_CONTEXT_UPDATE" value="0x5e"/>
<doc>generate interrupt from the command stream</doc>
<value name="CP_INTERRUPT" value="0x40"/>
<doc>copy sequencer instruction memory to system memory</doc>
<value name="CP_IM_STORE" value="0x2c" variants="A2XX"/>
<!-- For a20x --> <!-- TODO handle variants.. <doc> Program an offset that will added to the BIN_BASE value of the 3D_DRAW_INDX_BIN packet </doc> <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/>
-->
<!-- for a22x -->
<doc>
sets draw initiator flags register in PFP, gets bitwise-ORed into
every draw initiator
</doc>
<value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/>
<doc>sets the register protection mode</doc>
<value name="CP_SET_PROTECTED_MODE" value="0x5f"/>
<value name="CP_BOOTSTRAP_UCODE" value="0x6f"/>
<!-- for a3xx -->
<doc>load high level sequencer command</doc>
<value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/>
<value name="CP_LOAD_STATE4" value="0x30" variants="A4XX-A5XX"/>
<doc>Conditionally load a IB based on a flag, prefetch enabled</doc>
<value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a" variants="A3XX-A5XX"/>
<doc>Conditionally load a IB based on a flag, prefetch disabled</doc>
<value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/>
<doc>Load a buffer with pre-fetch enabled</doc>
<value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/>
<doc>Set bin (?)</doc>
<value name="CP_SET_BIN" value="0x4c" variants="A2XX"/>
<doc>Write register, ignoring context state for context sensitive registers</doc>
<value name="CP_REG_WR_NO_CTXT" value="0x78"/>
<doc>Record the real-time when this packet is processed by PFP</doc>
<value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/>
<!-- Used to switch GPU between secure and non-secure modes -->
<value name="CP_SET_SECURE_MODE" value="0x66"/>
<doc>PFP waits until the FIFO between the PFP and the ME is empty</doc>
<value name="CP_WAIT_FOR_ME" value="0x13"/>
<!-- for a4xx -->
<doc>
Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple
groups of registers. Looks like it can be used to create state
objects in GPU memory, and on state change only emit pointer
(via CP_SET_DRAW_STATE), which should be nice for reducing CPU
overhead:
(A4x) save PM4 stream pointers to execute upon a visible draw
</doc>
<value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX-"/>
<value name="CP_DRAW_INDX_OFFSET" value="0x38"/>
<value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX-"/>
<value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX-"/>
<value name="CP_DRAW_INDIRECT_MULTI" value="0x2a" variants="A6XX-"/>
<value name="CP_DRAW_AUTO" value="0x24"/>
<doc>
Enable or disable predication globally. Also resets the
predicate to "passing" and the local bit to enabled when
enabling global predication.
</doc>
<value name="CP_DRAW_PRED_ENABLE_GLOBAL" value="0x19"/>
<doc>
Enable or disable predication locally. Unlike globally enabling
predication, this packet doesn't touch any other state.
Predication only happens when enabled globally and locally and a
predicate has been set. This should be used for internal draws
which aren't supposed to use the predication state:
CP_DRAW_PRED_ENABLE_LOCAL(0)
... do draw...
CP_DRAW_PRED_ENABLE_LOCAL(1)
</doc>
<value name="CP_DRAW_PRED_ENABLE_LOCAL" value="0x1a"/>
<doc>
Latch a draw predicate into the internal register.
</doc>
<value name="CP_DRAW_PRED_SET" value="0x4e"/>
<doc>
for A4xx
Write to register with address that does not fit into type-0 pkt
</doc>
<value name="CP_WIDE_REG_WRITE" value="0x74" variants="A4XX"/>
<doc>copy from ME scratch RAM to a register</doc>
<value name="CP_SCRATCH_TO_REG" value="0x4d"/>
<doc>Copy from REG to ME scratch RAM</doc>
<value name="CP_REG_TO_SCRATCH" value="0x4a"/>
<doc>Wait for memory writes to complete</doc>
<value name="CP_WAIT_MEM_WRITES" value="0x12"/>
<doc>Conditional execution based on register comparison</doc>
<value name="CP_COND_REG_EXEC" value="0x47"/>
<doc>Memory to REG copy</doc>
<value name="CP_MEM_TO_REG" value="0x42"/>
<doc>
for a5xx
</doc>
<value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/> <!-- switches SMMU pagetable, used on a5xx+ only -->
<value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX-"/> <!-- for a6xx -->
<doc>Tells CP the current mode of GPU operation</doc>
<value name="CP_SET_MARKER" value="0x65" variants="A6XX-"/>
<doc>Instruct CP to set a few internal CP registers</doc>
<value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX-"/> <!-- pairs of regid and value.. seems to be used to program some TF related regs:
-->
<value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX-"/> <!-- A5XX Enable yield in RB only -->
<value name="CP_YIELD_ENABLE" value="0x1c" variants="A5XX"/>
<doc>
Enables IB2 skipping. If both GLOBAL and LOCAL are 1 and
nothing is left in the visibility stream, then
CP_INDIRECT_BUFFER will be skipped, and draws will early return
from their IB.
</doc>
<value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX-"/>
<value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX-"/>
<value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX-"/>
<value name="CP_WHERE_AM_I" value="0x62" variants="A5XX-"/>
<value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX-"/> <!-- Enable/Disable/Defer A5x global preemption model -->
<value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" variants="A5XX"/> <!-- Enable/Disable A5x local preemption model -->
<value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" variants="A5XX"/> <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx -->
<value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX-"/> <!-- Inform CP about current render mode (needed for a5xx preemption) -->
<value name="CP_SET_RENDER_MODE" value="0x6c" variants="A5XX"/>
<value name="CP_COMPUTE_CHECKPOINT" value="0x6e" variants="A5XX"/> <!-- check if this works on earlier.. -->
<value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX-"/>
<doc>
General purpose 2D blit engine for image transfers and mipmap
generation. Reads through UCHE, writes through the CCU cache in
the PS stage.
</doc>
<value name="CP_BLIT" value="0x2c" variants="A5XX-"/>
<!-- Test specified bit in specified register and set predicate -->
<value name="CP_REG_TEST" value="0x39" variants="A5XX-"/>
<!-- Seems to set the mode flags which control which CP_SET_DRAW_STATE packets are executed, based on their ENABLE_MASK values CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE packets w/ ENABLE_MASK & 0x6 to execute immediately
-->
<value name="CP_SET_MODE" value="0x63" variants="A6XX-"/>
<!-- Seems like there are now separate blocks of state for VS vs FS/CS (probably these amounts to geometry vs fragments so that geometry stage of the pipeline for next draw can start while fragment stage of current draw is still running. The format of the payload of the packets is the same, the only difference is the offsets of the regs the firmware code that handles the packet writes.
Note that for CL, starting with a6xx, the preferred # of local threads is no longer the same as the max, implying that the shader core can now run warps from unrelated shaders (ie. CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs CL_KERNEL_WORK_GROUP_SIZE)
-->
<value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX-"/>
<value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX-"/> <!-- Note: For UAV state (Image/SSBOs) which have shared state across shader stages, for 3d pipeline CP_LOAD_STATE6 is used. But for compute shaders, CP_LOAD_STATE6_FRAG is used. Possibly they are interchangable.
-->
<value name="CP_LOAD_STATE6" value="0x36" variants="A6XX-"/>
<!-- internal jumptable entries on a6xx+, possibly a5xx: -->
<!-- jmptable entry used to handle type4 packet on a5xx+: -->
<value name="PKT4" value="0x04" variants="A5XX-"/> <!-- called when ROQ is empty, "returns" from an IB or merged sequence of IBs -->
<value name="IN_IB_END" value="0x0a" variants="A6XX-"/> <!-- handles IFPC save/restore -->
<value name="IN_GMU_INTERRUPT" value="0x0b" variants="A6XX-"/> <!-- preemption/context-swtich routine -->
<value name="IN_PREEMPT" value="0x0f" variants="A6XX-"/>
<!-- TODO do these exist on A5xx? -->
<value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX-"/>
<value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" variants="A6XX-"/>
<value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" variants="A6XX-"/>
<value name="CP_WAIT_MEM_GTE" value="0x14" variants="A6XX"/>
<value name="CP_WAIT_TWO_REGS" value="0x70" variants="A6XX"/>
<value name="CP_MEMCPY" value="0x75" variants="A6XX-"/>
<value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" variants="A6XX-"/> <!-- A750+, set in place of CP_SET_BIN_DATA5_OFFSET but has different values -->
<value name="CP_SET_UNK_BIN_DATA" value="0x2d" variants="A7XX-"/>
<doc>
Write CP_CONTEXT_SWITCH_*_INFO from CP to the following dwords,
and forcibly switch to the indicated context.
</doc>
<value name="CP_CONTEXT_SWITCH" value="0x54" variants="A6XX"/>
<value name="CP_SET_AMBLE" value="0x55" variants="A6XX-"/>
<!-- Seems to always have the payload: 00000002 00008801 00004010 or: 00000002 00008801 00004090 or: 00000002 00008801 00000010 00000002 00008801 00010010 00000002 00008801 00d64010 ... Note set for compute shaders.. Is 0x8801 a register offset? This appears to be a special sort of register write packet more or less, but the firmware has some special handling.. Seems like it intercepts/modifies certain register offsets, but others are treated like a normal PKT4 reg write. I guess there are some registers that the fw controls certain bits.
-->
<value name="CP_REG_WRITE" value="0x6d" variants="A6XX"/>
<doc>
These first appear in a650_sqe.bin. They can in theory be used
to loop any sequence of IB1 commands, but in practice they are
used to loop over bins. There is a fixed-size per-iteration
prefix, used to set per-bin state, and then the following IB1
commands are executed until CP_END_BIN which are always the same
for each iteration and usually contain a list of
CP_INDIRECT_BUFFER calls to IB2 commands which setup state and
execute restore/draw/save commands. This replaces the previous
technique of just repeating the CP_INDIRECT_BUFFER calls and "unrolling" the loop.
</doc>
<value name="CP_START_BIN" value="0x50" variants="A6XX-"/>
<value name="CP_END_BIN" value="0x51" variants="A6XX-"/>
<doc> Make next dword 1 to disable preemption, 0 to re-enable it. </doc>
<value name="CP_PREEMPT_DISABLE" value="0x6c" variants="A6XX"/>
<value name="CP_WAIT_TIMESTAMP" value="0x14" variants="A7XX-"/>
<value name="CP_GLOBAL_TIMESTAMP" value="0x15" variants="A7XX-"/> <!-- payload 1 dword -->
<value name="CP_LOCAL_TIMESTAMP" value="0x16" variants="A7XX-"/> <!-- payload 1 dword, follows 0x15 -->
<value name="CP_THREAD_CONTROL" value="0x17" variants="A7XX-"/> <!-- payload 4 dwords, last two could be render target addr (one pkt per MRT), possibly used for GMEM save/restore?-->
<value name="CP_RESOURCE_LIST" value="0x18" variants="A7XX-"/>
<doc> Can clear BV/BR counters, or wait until one catches up to another </doc>
<value name="CP_BV_BR_COUNT_OPS" value="0x1b" variants="A7XX-"/>
<doc> Clears, adds to local, or adds to global timestamp </doc>
<value name="CP_MODIFY_TIMESTAMP" value="0x1c" variants="A7XX-"/> <!-- similar to CP_CONTEXT_REG_BUNCH, but discards first two dwords?? -->
<value name="CP_CONTEXT_REG_BUNCH2" value="0x5d" variants="A7XX-"/>
<doc>
Write to a scratch memory that is read by CP_REG_TEST with
SOURCE_SCRATCH_MEM set. It's not the same scratch as scratch registers.
However it uses the same memory space.
</doc>
<value name="CP_MEM_TO_SCRATCH_MEM" value="0x49" variants="A7XX-"/>
<doc>
Executes an array of fixed-size command buffers where each
buffer is assumed to have one draw call, skipping buffers with
non-visible draw calls.
</doc>
<value name="CP_FIXED_STRIDE_DRAW_TABLE" value="0x7f" variants="A7XX-"/>
<doc>Reset various on-chip state used for synchronization</doc>
<value name="CP_RESET_CONTEXT_STATE" value="0x1f" variants="A7XX-"/>
<doc>Invalidates the "CCHE" introduced on a740</doc>
<value name="CP_CCHE_INVALIDATE" value="0x3a" variants="A7XX-"/>
<domain name="CP_LOAD_STATE4" width="32" varset="chip">
<doc>Load state, a4xx+</doc>
<enum name="a4xx_state_block"> <!-- unknown: 0x7 and 0xf <- seen in compute shader
STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption? Seen in some GL shaders. Payload is NUM_UNIT dwords, and it contains the gpuaddr of the following shader constants block. DST_OFF seems to specify which shader stage:
<domain name="CP_DRAW_PRED_SET" width="32" varset="chip">
<enum name="cp_draw_pred_src"> <!-- Sources 1-4 seem to be about combining reading SO/primitive queries and setting the predicate, which is a DX11-specific optimization (since in DX11 you can only predicate on the result of queries).
-->
<value name="PRED_SRC_MEM" value="5">
<doc>
Read a 64-bit value at the given address and
test if it equals/doesn't equal 0.
</doc>
</value>
</enum>
<enum name="cp_draw_pred_test">
<value name="NE_0_PASS" value="0"/>
<value name="EQ_0_PASS" value="1"/>
</enum>
<reg32 offset="0" name="0">
<bitfield name="SRC" low="4" high="7"type="cp_draw_pred_src"/>
<bitfield name="TEST" pos="8"type="cp_draw_pred_test"/>
</reg32>
<reg64 offset="1" name="MEM_ADDR"type="address"/>
</domain>
<domain name="CP_SET_BIN_DATA5" width="32">
<reg32 offset="0" name="0">
<bitfield name="VSC_MASK" low="0" high="15"type="hex">
<doc>
A mask of bins, starting at VSC_N, whose
visibility is OR'd together. A value of 0 is
interpreted as 1 (i.e. just use VSC_N for
visbility) for backwards compatibility. Only
exists on a7xx.
</doc>
</bitfield> <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
<bitfield name="VSC_SIZE" low="16" high="21"type="uint"/> <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
<bitfield name="VSC_N" low="22" high="26"type="uint"/>
<bitfield name="ABS_MASK" pos="28"type="a7xx_abs_mask_mode" addvariant="yes">
<doc>
If this field is 1, VSC_MASK and VSC_N are
ignored and instead a new ordinal immediately
after specifies the full 32-bit mask of bins
to use. The mask is "absolute" instead of
relative to VSC_N.
</doc>
</bitfield>
</reg32>
<stripe varset="a7xx_abs_mask_mode" variants="NO_ABS_MASK"> <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
<reg32 offset="1" name="1">
<bitfield name="BIN_DATA_ADDR_LO" low="0" high="31"type="hex"/>
</reg32>
<reg32 offset="2" name="2">
<bitfield name="BIN_DATA_ADDR_HI" low="0" high="31"type="hex"/>
</reg32> <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
<reg32 offset="3" name="3">
<bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
</reg32>
<reg32 offset="4" name="4">
<bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
</reg32> <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: -->
<reg32 offset="5" name="5">
<bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/>
</reg32>
<reg32 offset="6" name="6">
<bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/>
</reg32> <!-- a7xx adds a few more addresses to the end of the pkt
-->
<reg64 offset="7" name="7"/>
<reg64 offset="9" name="9"/>
</stripe>
<stripe varset="a7xx_abs_mask_mode" variants="ABS_MASK">
<reg32 offset="1" name="ABS_MASK"/> <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
<reg32 offset="2" name="2">
<bitfield name="BIN_DATA_ADDR_LO" low="0" high="31"type="hex"/>
</reg32>
<reg32 offset="3" name="3">
<bitfield name="BIN_DATA_ADDR_HI" low="0" high="31"type="hex"/>
</reg32> <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
<reg32 offset="4" name="4">
<bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
</reg32>
<reg32 offset="5" name="5">
<bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
</reg32> <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: -->
<reg32 offset="6" name="6">
<bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/>
</reg32>
<reg32 offset="7" name="7">
<bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/>
</reg32> <!-- a7xx adds a few more addresses to the end of the pkt
-->
<reg64 offset="8" name="8"/>
<reg64 offset="10" name="10"/>
</stripe>
</domain>
<domain name="CP_SET_BIN_DATA5_OFFSET" width="32">
<doc>
Like CP_SET_BIN_DATA5, but set the pointers as offsets from the
pointers stored in VSC_PIPE_{DATA,DATA2,SIZE}_ADDRESS. Useful
for Vulkan where these values aren't known when the command
stream is recorded.
</doc>
<reg32 offset="0" name="0">
<bitfield name="VSC_MASK" low="0" high="15"type="hex"/> <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
<bitfield name="VSC_SIZE" low="16" high="21"type="uint"/> <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
<bitfield name="VSC_N" low="22" high="26"type="uint"/>
<bitfield name="ABS_MASK" pos="28"type="a7xx_abs_mask_mode" addvariant="yes"/>
</reg32>
<stripe varset="a7xx_abs_mask_mode" variants="NO_ABS_MASK"> <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
<reg32 offset="1" name="1">
<bitfield name="BIN_DATA_OFFSET" low="0" high="31"type="uint"/>
</reg32> <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
<reg32 offset="2" name="2">
<bitfield name="BIN_SIZE_OFFSET" low="0" high="31"type="uint"/>
</reg32> <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS -->
<reg32 offset="3" name="3">
<bitfield name="BIN_DATA2_OFFSET" low="0" high="31"type="uint"/>
</reg32>
</stripe>
<stripe varset="a7xx_abs_mask_mode" variants="ABS_MASK">
<reg32 offset="1" name="ABS_MASK"/> <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
<reg32 offset="2" name="2">
<bitfield name="BIN_DATA_OFFSET" low="0" high="31"type="uint"/>
</reg32> <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
<reg32 offset="3" name="3">
<bitfield name="BIN_SIZE_OFFSET" low="0" high="31"type="uint"/>
</reg32> <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS -->
<reg32 offset="4" name="4">
<bitfield name="BIN_DATA2_OFFSET" low="0" high="31"type="uint"/>
</reg32>
</stripe>
</domain>
<domain name="CP_REG_RMW" width="32">
<doc>
Modifies DST_REG using two sources that can either be registers
or immediates. If SRC1_ADD is set, then do the following:
<domain name="CP_REG_TO_MEM_OFFSET_REG" width="32">
<doc>
Like CP_REG_TO_MEM, but the memory address to write to can be
offsetted using either one or two registers or scratch
registers.
</doc>
<reg32 offset="0" name="0">
<bitfield name="REG" low="0" high="17"type="hex"/> <!-- number of registers/dwords copied is max(CNT, 1). -->
<bitfield name="CNT" low="18" high="29"type="uint"/>
<bitfield name="64B" pos="30"type="boolean"/>
<bitfield name="ACCUMULATE" pos="31"type="boolean"/>
</reg32>
<reg32 offset="1" name="1">
<bitfield name="DEST" low="0" high="31"/>
</reg32>
<reg32 offset="2" name="2" varset="chip" variants="A5XX-">
<bitfield name="DEST_HI" low="0" high="31"/>
</reg32>
<reg32 offset="3" name="3">
<bitfield name="OFFSET0" low="0" high="17"type="hex"/>
<bitfield name="OFFSET0_SCRATCH" pos="19"type="boolean"/>
</reg32> <!-- followed by an optional identical OFFSET1 dword -->
</domain>
<domain name="CP_REG_TO_MEM_OFFSET_MEM" width="32">
<doc>
Like CP_REG_TO_MEM, but the memory address to write to can be
offsetted using a DWORD in memory.
</doc>
<reg32 offset="0" name="0">
<bitfield name="REG" low="0" high="17"type="hex"/> <!-- number of registers/dwords copied is max(CNT, 1). -->
<bitfield name="CNT" low="18" high="29"type="uint"/>
<bitfield name="64B" pos="30"type="boolean"/>
<bitfield name="ACCUMULATE" pos="31"type="boolean"/>
</reg32>
<reg32 offset="1" name="1">
<bitfield name="DEST" low="0" high="31"/>
</reg32>
<reg32 offset="2" name="2" varset="chip" variants="A5XX-">
<bitfield name="DEST_HI" low="0" high="31"/>
</reg32>
<reg32 offset="3" name="3">
<bitfield name="OFFSET_LO" low="0" high="31"type="hex"/>
</reg32>
<reg32 offset="4" name="4">
<bitfield name="OFFSET_HI" low="0" high="31"type="hex"/>
</reg32>
</domain>
<domain name="CP_MEM_TO_REG" width="32">
<reg32 offset="0" name="0">
<bitfield name="REG" low="0" high="17"type="hex"/> <!-- number of registers/dwords copied is max(CNT, 1). -->
<bitfield name="CNT" low="19" high="29"type="uint"/> <!-- shift each DWORD left by 2 while copying -->
<bitfield name="SHIFT_BY_2" pos="30"type="boolean"/> <!-- does the same thing as CP_MEM_TO_MEM::UNK31 -->
<bitfield name="UNK31" pos="31"type="boolean"/>
</reg32>
<reg32 offset="1" name="1">
<bitfield name="SRC" low="0" high="31"/>
</reg32>
<reg32 offset="2" name="2" varset="chip" variants="A5XX-">
<bitfield name="SRC_HI" low="0" high="31"/>
</reg32>
</domain>
<domain name="CP_MEM_TO_MEM" width="32">
<reg32 offset="0" name="0"> <!-- not sure how many src operands we have, but the low bits negate the n'th src argument.
-->
<bitfield name="NEG_A" pos="0"type="boolean"/>
<bitfield name="NEG_B" pos="1"type="boolean"/>
<bitfield name="NEG_C" pos="2"type="boolean"/>
<!-- if set treat src/dst as 64bit values -->
<bitfield name="DOUBLE" pos="29"type="boolean"/> <!-- execute CP_WAIT_FOR_MEM_WRITES beforehand -->
<bitfield name="WAIT_FOR_MEM_WRITES" pos="30"type="boolean"/> <!-- some other kind of wait -->
<bitfield name="UNK31" pos="31"type="boolean"/>
</reg32> <!-- followed by sequence of addresses.. the first is the destination and the rest are N src addresses which are summed (after being negated if NEG_x bit set) allowing to do things like 'result += end - start' (which turns out to be useful for queries and accumulating results across multiple tiles)
-->
</domain>
<domain name="CP_SCRATCH_TO_REG" width="32">
<reg32 offset="0" name="0">
<bitfield name="REG" low="0" high="17"type="hex"/> <!-- note: CP_MEM_TO_REG always sets this when writing to the register -->
<bitfield name="UNK18" pos="18"type="boolean"/>
<bitfield name="SCRATCH" low="20" high="22"type="uint"/> <!-- number of registers/dwords copied is CNT + 1. -->
<bitfield name="CNT" low="24" high="26"type="uint"/>
</reg32>
</domain>
<domain name="CP_SCRATCH_WRITE" width="32">
<reg32 offset="0" name="0">
<bitfield name="SCRATCH" low="20" high="22"type="uint"/>
</reg32> <!-- followed by one or more DWORDs to write to scratch registers -->
</domain>
<domain name="CP_MEM_WRITE" width="32">
<reg32 offset="0" name="0">
<bitfield name="ADDR_LO" low="0" high="31"/>
</reg32>
<reg32 offset="1" name="1">
<bitfield name="ADDR_HI" low="0" high="31"/>
</reg32> <!-- followed by the DWORDs to write -->
</domain>
<!-- Next 4 flags are valid to set only when concurrent binning is enabled --> <!-- Increment 16b BV counter. Valid only in BV pipe -->
<bitfield name="INC_BV_COUNT" pos="16"type="boolean"/> <!-- Increment 16b BR counter. Valid only in BR pipe -->
<bitfield name="INC_BR_COUNT" pos="17"type="boolean"/>
<bitfield name="CLEAR_RENDER_RESOURCE" pos="18"type="boolean"/>
<bitfield name="CLEAR_LRZ_RESOURCE" pos="19"type="boolean"/>
<domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
<doc>Tell CP the current operation mode, indicates save and restore procedure</doc>
<enum name="set_marker_mode">
<value value="0" name="SET_RENDER_MODE"/> <!-- IFPC - inter-frame power collapse -->
<value value="1" name="SET_IFPC_MODE"/>
</enum>
<enum name="a6xx_ifpc_mode">
<value value="0" name="IFPC_ENABLE"/>
<value value="1" name="IFPC_DISABLE"/>
</enum>
<enum name="a6xx_marker">
<value value="1" name="RM6_DIRECT_RENDER"/>
<value value="2" name="RM6_BIN_VISIBILITY"/>
<value value="3" name="RM6_BIN_DIRECT"/>
<value value="4" name="RM6_BIN_RENDER_START"/>
<value value="5" name="RM6_BIN_END_OF_DRAWS"/>
<value value="6" name="RM6_BIN_RESOLVE"/>
<value value="7" name="RM6_BIN_RENDER_END"/>
<value value="8" name="RM6_COMPUTE"/>
<value value="0xc" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) -->
<!-- These values come from a6xx_set_marker() in the downstream kernel, and they can only be set by the kernel
-->
<value value="0xd" name="RM6_IB1LIST_START"/>
<value value="0xe" name="RM6_IB1LIST_END"/>
</enum>
<reg32 offset="0" name="0"> <!-- if b8 is set, the low bits are interpreted differently (and b4 ignored) -->
<bitfield name="MARKER_MODE" pos="8"type="set_marker_mode" addvariant="yes"/>
<bitfield name="MODE" low="0" high="3"type="a6xx_marker" varset="set_marker_mode" variants="SET_RENDER_MODE"/> <!-- used by preemption to determine if GMEM needs to be saved or not -->
<bitfield name="USES_GMEM" pos="4"type="boolean" varset="set_marker_mode" variants="SET_RENDER_MODE"/>
<!-- CP_SET_MARKER is used with these bits to create a critical section around a workaround for ray tracing. The workaround happens after BVH building, and appears to invalidate the RTU's BVH node cache. It makes sure that only one of BR/BV/LPAC is executing the workaround at a time, and no draws using RT on BV/LPAC are executing while the workaround is executed on BR (or vice versa, that no draws on BV/BR using RT are executed while the workaround executes on LPAC), by hooking subsequent CP_EVENT_WRITE/CP_DRAW_*/CP_EXEC_CS. The blob usage is:
<domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-">
<doc>Set internal CP registers, used to indicate context save data addresses</doc>
<enum name="pseudo_reg">
<value value="0" name="SMMU_INFO"/>
<value value="1" name="NON_SECURE_SAVE_ADDR"/>
<value value="2" name="SECURE_SAVE_ADDR"/>
<value value="3" name="NON_PRIV_SAVE_ADDR"/>
<value value="4" name="COUNTER"/>
<!-- On a6xx the registers are set directly and CP_SET_BIN_DATA5_OFFSET reads them, but that doesn't work with concurrent binning because BR will be reading from a different set of streams than BV is writing, so on a7xx we have these pseudo-regs instead, which do the right thing.
The corresponding VSC registers exist, and they're written by BV when it encounters CP_SET_PSEUDO_REG. When BR later encounters the same CP_SET_PSEUDO_REG it will only write some private scratch registers which are read by CP_SET_BIN_DATA5_OFFSET.
If concurrent binning is disabled then BR also does binning so it will also write the "real" registers in BR.
-->
<value value="8" name="VSC_PIPE_DATA_DRAW_BASE"/>
<value value="9" name="VSC_SIZE_BASE"/>
<value value="10" name="VSC_PIPE_DATA_PRIM_BASE"/>
<value value="11" name="UNK_STRM_ADDRESS"/>
<value value="12" name="UNK_STRM_SIZE_ADDRESS"/>
<domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-">
<doc>
Tests bit in specified register and sets predicate for CP_COND_REG_EXEC.
So:
Will execute the CP_INDIRECT_BUFFER only if b0 in the register at
offset 0x0c10 is 1
</doc>
<enum name="source_type">
<value value="0" name="SOURCE_REG"/> <!-- Don't confuse with scratch registers, this is a separate memory
written into by CP_MEM_TO_SCRATCH_MEM. -->
<value value="1" name="SOURCE_SCRATCH_MEM" varset="chip" variants="A7XX-"/>
</enum>
<reg32 offset="0" name="0"> <!-- the register to test -->
<bitfield name="REG" low="0" high="17" varset="source_type" variants="SOURCE_REG"/>
<bitfield name="SCRATCH_MEM_OFFSET" low="0" high="17" varset="source_type" variants="SOURCE_SCRATCH_MEM"/>
<bitfield name="SOURCE" pos="18"type="source_type" addvariant="yes"/> <!-- the bit to test -->
<bitfield name="BIT" low="20" high="24"type="uint"/> <!-- skip implied CP_WAIT_FOR_ME -->
<bitfield name="SKIP_WAIT_FOR_ME" pos="25"type="boolean"/> <!-- the predicate bit to set (new in gen3+) -->
<bitfield name="PRED_BIT" low="26" high="30"type="uint"/> <!-- update the predicate reg directly (new in gen3+) -->
<bitfield name="PRED_UPDATE" pos="31"type="boolean"/>
</reg32>
<!-- In PRED_UPDATE mode, the predicate reg is updated directly using two more dwords, ignoring other bits:
<!-- I *think* this existed at least as far back as a4xx -->
<domain name="CP_COND_REG_EXEC" width="32">
<enum name="compare_mode"> <!-- use the predicate bit set by CP_REG_TEST -->
<value value="1" name="PRED_TEST"/> <!-- compare two registers directly for equality -->
<value value="2" name="REG_COMPARE"/> <!-- test if certain render modes are set via CP_SET_MARKER -->
<value value="3" name="RENDER_MODE" varset="chip" variants="A6XX-"/> <!-- compare REG0 for equality with immediate -->
<value value="4" name="REG_COMPARE_IMM" varset="chip" variants="A7XX-"/> <!-- test which of BR/BV are enabled -->
<value value="5" name="THREAD_MODE" varset="chip" variants="A7XX-"/>
</enum>
<reg32 offset="0" name="0" varset="compare_mode">
<bitfield name="REG0" low="0" high="17" variants="REG_COMPARE"type="hex"/>
<!-- the predicate bit to test (new in gen3+) -->
<bitfield name="PRED_BIT" low="18" high="22" variants="PRED_TEST"type="uint"/>
<bitfield name="SKIP_WAIT_FOR_ME" pos="23" varset="chip" variants="A7XX-"type="boolean"/> <!-- With REG_COMPARE instead of register read from ONCHIP memory -->
<bitfield name="ONCHIP_MEM" pos="24" varset="chip" variants="A7XX-"type="boolean"/>
<!-- Note: these bits have the same meaning, and use the same internal mechanism as the bits in CP_SET_DRAW_STATE. When RENDER_MODE is selected, they're used as a bitmask of which modes pass the test.
-->
<domain name="CP_COND_EXEC" width="32">
<doc>
Executes the following DWORDs of commands if the dword at ADDR0
is not equal to 0 and the dword at ADDR1 is less than REF
(signed comparison).
</doc>
<reg32 offset="0" name="0">
<bitfield name="ADDR0_LO" low="0" high="31"/>
</reg32>
<reg32 offset="1" name="1">
<bitfield name="ADDR0_HI" low="0" high="31"/>
</reg32>
<reg32 offset="2" name="2">
<bitfield name="ADDR1_LO" low="0" high="31"/>
</reg32>
<reg32 offset="3" name="3">
<bitfield name="ADDR1_HI" low="0" high="31"/>
</reg32>
<reg32 offset="4" name="4">
<bitfield name="REF" low="0" high="31"/>
</reg32>
<reg32 offset="5" name="5">
<bitfield name="DWORDS" low="0" high="31"type="uint"/>
</reg32>
</domain>
<domain name="CP_SET_AMBLE" width="32">
<doc>
Used by the userspace and kernel drivers to set various IB's
which are executed during context save/restore for handling
state that isn't restored by the context switch routine itself.
</doc>
<enum name="amble_type">
<value name="PREAMBLE_AMBLE_TYPE" value="0">
<doc>Executed unconditionally when switching back to the context.</doc>
</value>
<value name="BIN_PREAMBLE_AMBLE_TYPE" value="1">
<doc>
Executed when switching back after switching
away during execution of
a CP_SET_MARKER packet with RM6_BIN_RENDER_END as the
payload *and* skipsaverestore is set. This is
expected to restore static register values not
saved when skipsaverestore is set.
</doc>
</value>
<value name="POSTAMBLE_AMBLE_TYPE" value="2">
<doc>
Executed when switching away from the context,
except for context switches initiated via
CP_YIELD.
</doc>
</value>
<value name="KMD_AMBLE_TYPE" value="3">
<doc>
This can only be set by the RB (i.e. the kernel)
and executes with protected mode off, but
is otherwise similar to POSTAMBLE_AMBLE_TYPE.
</doc>
</value>
</enum>
<reg32 offset="0" name="0">
<bitfield name="ADDR_LO" low="0" high="31"/>
</reg32>
<reg32 offset="1" name="1">
<bitfield name="ADDR_HI" low="0" high="31"/>
</reg32>
<reg32 offset="2" name="2">
<bitfield name="DWORDS" low="0" high="19"type="uint"/>
<bitfield name="TYPE" low="20" high="21"type="amble_type"/>
</reg32>
</domain>
<domain name="CP_REG_WRITE" width="32">
<enum name="reg_tracker">
<doc>
Keep shadow copies of these registers and only set them
when drawing, avoiding redundant writes:
- VPC_CNTL_0
- HLSQ_CONTROL_1_REG
- HLSQ_UNKNOWN_B980
</doc>
<value name="TRACK_CNTL_REG" value="0x1"/>
<doc>
Track RB_RENDER_CNTL, and insert a WFI in the following
situation:
- There is a write that disables binning
- There was a draw with binning left enabled, but in
BYPASS mode
Presumably this is a hang workaround?
</doc>
<value name="TRACK_RENDER_CNTL" value="0x2"/>
<doc>
Do a mysterious CP_EVENT_WRITE 0x3f when the low bit of
the data to write is 0. Used by the Vulkan blob with
PC_MULTIVIEW_CNTL, but this isn't predicated on particular
register(s) like the others.
</doc>
<value name="UNK_EVENT_WRITE" value="0x4"/>
<doc>
Tracks GRAS_LRZ_CNTL::GREATER, GRAS_LRZ_CNTL::DIR, and
GRAS_LRZ_VIEW_INFO with previous values, and if one of
the following is true:
- GRAS_LRZ_CNTL::GREATER has changed
- GRAS_LRZ_CNTL::DIR has changed, the old value is not
CUR_DIR_GE, and the new value is not CUR_DIR_DISABLED
- GRAS_LRZ_VIEW_INFO has changed
then it does a LRZ_FLUSH with GRAS_LRZ_CNTL::ENABLE
forced to 1.
Only exists in a650_sqe.fw.
</doc>
<value name="TRACK_LRZ" value="0x8"/>
</enum>
<reg32 offset="0" name="0">
<bitfield name="TRACKER" low="0" high="3"type="reg_tracker"/>
</reg32>
<reg32 offset="1" name="1"/>
<reg32 offset="2" name="2"/>
</domain>
<domain name="CP_SMMU_TABLE_UPDATE" width="32">
<doc>
Note that the SMMU's definition of TTBRn can take different forms
depending on the pgtable format. But a5xx+ only uses aarch64
format.
</doc>
<reg32 offset="0" name="0">
<bitfield name="TTBR0_LO" low="0" high="31"/>
</reg32>
<reg32 offset="1" name="1">
<bitfield name="TTBR0_HI" low="0" high="15"/>
<bitfield name="ASID" low="16" high="31"/>
</reg32>
<reg32 offset="2" name="2">
<doc>Unused, does not apply to aarch64 pgtable format</doc>
<bitfield name="CONTEXTIDR" low="0" high="31"/>
</reg32>
<reg32 offset="3" name="3">
<bitfield name="CONTEXTBANK" low="0" high="31"/>
</reg32>
</domain>
<domain name="CP_START_BIN" width="32">
<reg32 offset="0" name="BIN_COUNT"type="uint"/>
<reg64 offset="1" name="PREFIX_ADDR"type="address"/>
<reg32 offset="3" name="PREFIX_DWORDS">
<doc>
Size of prefix for each bin. For each bin index i, the
prefix commands at PREFIX_ADDR + i * PREFIX_DWORDS are
executed in an IB2 before the IB1 commands following
this packet.
</doc>
</reg32>
<reg32 offset="4" name="BODY_DWORDS">
<doc>Number of dwords after this packet until CP_END_BIN</doc>
</reg32>
</domain>
<domain name="CP_WAIT_TIMESTAMP" width="32">
<enum name="ts_wait_value_src"> <!-- Wait for value at memory address to be >= SRC_0 (signed comparison) -->
<value value="0" name="TS_WAIT_GE_32B"/> <!-- Wait for value at memory address to be >= SRC_0 (unsigned) -->
<value value="1" name="TS_WAIT_GE_64B"/> <!-- Write (TIMESTAMP_GLOBAL + TIMESTAMP_LOCAL) -->
<value value="2" name="TS_WAIT_GE_TIMESTAMP_SUM"/>
</enum>
<domain name="CP_MEM_TO_SCRATCH_MEM" width="32">
<doc>
Best guess is that it is a faster way to fetch all the VSC_CHANNEL_VISIBILITY registers
and keep them in a local scratch memory instead of fetching every time
when skipping IBs.
</doc>
<reg32 offset="0" name="0">
<bitfield name="CNT" low="0" high="5"type="uint"/>
</reg32>
<reg32 offset="1" name="1">
<doc>Scratch memory size is 48 dwords`</doc>
<bitfield name="OFFSET" low="0" high="5"type="uint"/>
</reg32>
<reg32 offset="2" name="2">
<bitfield name="SRC" low="0" high="31"/>
</reg32>
<reg32 offset="3" name="3">
<bitfield name="SRC_HI" low="0" high="31"/>
</reg32>
</domain>
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