Quelle  ni_dpm.c   Sprache: C

/*
 * Copyright 2012 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include <linux/math64.h>
#include <linux/pci.h>
#include <linux/seq_file.h>

#include "atom.h"
#include "evergreen.h"
#include "ni_dpm.h"
#include "nid.h"
#include "r600_dpm.h"
#include "rv770.h"
#include "radeon.h"
#include "radeon_asic.h"

#define MC_CG_ARB_FREQ_F0           0x0a
#define MC_CG_ARB_FREQ_F1           0x0b
#define MC_CG_ARB_FREQ_F2           0x0c
#define MC_CG_ARB_FREQ_F3           0x0d

#define SMC_RAM_END 0xC000

static const struct ni_cac_weights cac_weights_cayman_xt =
{
 0x15,
 0x2,
 0x19,
 0x2,
 0x8,
 0x14,
 0x2,
 0x16,
 0xE,
 0x17,
 0x13,
 0x2B,
 0x10,
 0x7,
 0x5,
 0x5,
 0x5,
 0x2,
 0x3,
 0x9,
 0x10,
 0x10,
 0x2B,
 0xA,
 0x9,
 0x4,
 0xD,
 0xD,
 0x3E,
 0x18,
 0x14,
 0,
 0x3,
 0x3,
 0x5,
 0,
 0x2,
 0,
 0,
 0,
 0,
 0,
 0,
 0,
 0,
 0,
 0x1CC,
 0,
 0x164,
 1,
 1,
 1,
 1,
 12,
 12,
 12,
 0x12,
 0x1F,
 132,
 5,
 7,
 0,
 { 0, 0, 0, 0, 0, 0, 0, 0 },
 { 0, 0, 0, 0 },
 true
};

static const struct ni_cac_weights cac_weights_cayman_pro =
{
 0x16,
 0x4,
 0x10,
 0x2,
 0xA,
 0x16,
 0x2,
 0x18,
 0x10,
 0x1A,
 0x16,
 0x2D,
 0x12,
 0xA,
 0x6,
 0x6,
 0x6,
 0x2,
 0x4,
 0xB,
 0x11,
 0x11,
 0x2D,
 0xC,
 0xC,
 0x7,
 0x10,
 0x10,
 0x3F,
 0x1A,
 0x16,
 0,
 0x7,
 0x4,
 0x6,
 1,
 0x2,
 0x1,
 0,
 0,
 0,
 0,
 0,
 0,
 0x30,
 0,
 0x1CF,
 0,
 0x166,
 1,
 1,
 1,
 1,
 12,
 12,
 12,
 0x15,
 0x1F,
 132,
 6,
 6,
 0,
 { 0, 0, 0, 0, 0, 0, 0, 0 },
 { 0, 0, 0, 0 },
 true
};

static const struct ni_cac_weights cac_weights_cayman_le =
{
 0x7,
 0xE,
 0x1,
 0xA,
 0x1,
 0x3F,
 0x2,
 0x18,
 0x10,
 0x1A,
 0x1,
 0x3F,
 0x1,
 0xE,
 0x6,
 0x6,
 0x6,
 0x2,
 0x4,
 0x9,
 0x1A,
 0x1A,
 0x2C,
 0xA,
 0x11,
 0x8,
 0x19,
 0x19,
 0x1,
 0x1,
 0x1A,
 0,
 0x8,
 0x5,
 0x8,
 0x1,
 0x3,
 0x1,
 0,
 0,
 0,
 0,
 0,
 0,
 0x38,
 0x38,
 0x239,
 0x3,
 0x18A,
 1,
 1,
 1,
 1,
 12,
 12,
 12,
 0x15,
 0x22,
 132,
 6,
 6,
 0,
 { 0, 0, 0, 0, 0, 0, 0, 0 },
 { 0, 0, 0, 0 },
 true
};

#define NISLANDS_MGCG_SEQUENCE  300

static const u32 cayman_cgcg_cgls_default[] =
{
 0x000008f8, 0x00000010, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000011, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000012, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000013, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000014, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000015, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000016, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000017, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000018, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000019, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x0000001a, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x0000001b, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000020, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000021, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000022, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000023, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000024, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000025, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000026, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000027, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000028, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000029, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x0000002a, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x0000002b, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff
};
#define CAYMAN_CGCG_CGLS_DEFAULT_LENGTH sizeof(cayman_cgcg_cgls_default) / (3 * sizeof(u32))

static const u32 cayman_cgcg_cgls_disable[] =
{
 0x000008f8, 0x00000010, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000011, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000012, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000013, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000014, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000015, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000016, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000017, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000018, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000019, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x0000001a, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x0000001b, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000020, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000021, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000022, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000023, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000024, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000025, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000026, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000027, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000028, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000029, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x0000002a, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x0000002b, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x00000644, 0x000f7902, 0x001f4180,
 0x00000644, 0x000f3802, 0x001f4180
};
#define CAYMAN_CGCG_CGLS_DISABLE_LENGTH sizeof(cayman_cgcg_cgls_disable) / (3 * sizeof(u32))

static const u32 cayman_cgcg_cgls_enable[] =
{
 0x00000644, 0x000f7882, 0x001f4080,
 0x000008f8, 0x00000010, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000011, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000012, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000013, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000014, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000015, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000016, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000017, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000018, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000019, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x0000001a, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x0000001b, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000020, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000021, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000022, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000023, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000024, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000025, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000026, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000027, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000028, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000029, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x0000002a, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x0000002b, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff
};
#define CAYMAN_CGCG_CGLS_ENABLE_LENGTH  sizeof(cayman_cgcg_cgls_enable) / (3 * sizeof(u32))

static const u32 cayman_mgcg_default[] =
{
 0x0000802c, 0xc0000000, 0xffffffff,
 0x00003fc4, 0xc0000000, 0xffffffff,
 0x00005448, 0x00000100, 0xffffffff,
 0x000055e4, 0x00000100, 0xffffffff,
 0x0000160c, 0x00000100, 0xffffffff,
 0x00008984, 0x06000100, 0xffffffff,
 0x0000c164, 0x00000100, 0xffffffff,
 0x00008a18, 0x00000100, 0xffffffff,
 0x0000897c, 0x06000100, 0xffffffff,
 0x00008b28, 0x00000100, 0xffffffff,
 0x00009144, 0x00800200, 0xffffffff,
 0x00009a60, 0x00000100, 0xffffffff,
 0x00009868, 0x00000100, 0xffffffff,
 0x00008d58, 0x00000100, 0xffffffff,
 0x00009510, 0x00000100, 0xffffffff,
 0x0000949c, 0x00000100, 0xffffffff,
 0x00009654, 0x00000100, 0xffffffff,
 0x00009030, 0x00000100, 0xffffffff,
 0x00009034, 0x00000100, 0xffffffff,
 0x00009038, 0x00000100, 0xffffffff,
 0x0000903c, 0x00000100, 0xffffffff,
 0x00009040, 0x00000100, 0xffffffff,
 0x0000a200, 0x00000100, 0xffffffff,
 0x0000a204, 0x00000100, 0xffffffff,
 0x0000a208, 0x00000100, 0xffffffff,
 0x0000a20c, 0x00000100, 0xffffffff,
 0x00009744, 0x00000100, 0xffffffff,
 0x00003f80, 0x00000100, 0xffffffff,
 0x0000a210, 0x00000100, 0xffffffff,
 0x0000a214, 0x00000100, 0xffffffff,
 0x000004d8, 0x00000100, 0xffffffff,
 0x00009664, 0x00000100, 0xffffffff,
 0x00009698, 0x00000100, 0xffffffff,
 0x000004d4, 0x00000200, 0xffffffff,
 0x000004d0, 0x00000000, 0xffffffff,
 0x000030cc, 0x00000104, 0xffffffff,
 0x0000d0c0, 0x00000100, 0xffffffff,
 0x0000d8c0, 0x00000100, 0xffffffff,
 0x0000802c, 0x40000000, 0xffffffff,
 0x00003fc4, 0x40000000, 0xffffffff,
 0x0000915c, 0x00010000, 0xffffffff,
 0x00009160, 0x00030002, 0xffffffff,
 0x00009164, 0x00050004, 0xffffffff,
 0x00009168, 0x00070006, 0xffffffff,
 0x00009178, 0x00070000, 0xffffffff,
 0x0000917c, 0x00030002, 0xffffffff,
 0x00009180, 0x00050004, 0xffffffff,
 0x0000918c, 0x00010006, 0xffffffff,
 0x00009190, 0x00090008, 0xffffffff,
 0x00009194, 0x00070000, 0xffffffff,
 0x00009198, 0x00030002, 0xffffffff,
 0x0000919c, 0x00050004, 0xffffffff,
 0x000091a8, 0x00010006, 0xffffffff,
 0x000091ac, 0x00090008, 0xffffffff,
 0x000091b0, 0x00070000, 0xffffffff,
 0x000091b4, 0x00030002, 0xffffffff,
 0x000091b8, 0x00050004, 0xffffffff,
 0x000091c4, 0x00010006, 0xffffffff,
 0x000091c8, 0x00090008, 0xffffffff,
 0x000091cc, 0x00070000, 0xffffffff,
 0x000091d0, 0x00030002, 0xffffffff,
 0x000091d4, 0x00050004, 0xffffffff,
 0x000091e0, 0x00010006, 0xffffffff,
 0x000091e4, 0x00090008, 0xffffffff,
 0x000091e8, 0x00000000, 0xffffffff,
 0x000091ec, 0x00070000, 0xffffffff,
 0x000091f0, 0x00030002, 0xffffffff,
 0x000091f4, 0x00050004, 0xffffffff,
 0x00009200, 0x00010006, 0xffffffff,
 0x00009204, 0x00090008, 0xffffffff,
 0x00009208, 0x00070000, 0xffffffff,
 0x0000920c, 0x00030002, 0xffffffff,
 0x00009210, 0x00050004, 0xffffffff,
 0x0000921c, 0x00010006, 0xffffffff,
 0x00009220, 0x00090008, 0xffffffff,
 0x00009224, 0x00070000, 0xffffffff,
 0x00009228, 0x00030002, 0xffffffff,
 0x0000922c, 0x00050004, 0xffffffff,
 0x00009238, 0x00010006, 0xffffffff,
 0x0000923c, 0x00090008, 0xffffffff,
 0x00009240, 0x00070000, 0xffffffff,
 0x00009244, 0x00030002, 0xffffffff,
 0x00009248, 0x00050004, 0xffffffff,
 0x00009254, 0x00010006, 0xffffffff,
 0x00009258, 0x00090008, 0xffffffff,
 0x0000925c, 0x00070000, 0xffffffff,
 0x00009260, 0x00030002, 0xffffffff,
 0x00009264, 0x00050004, 0xffffffff,
 0x00009270, 0x00010006, 0xffffffff,
 0x00009274, 0x00090008, 0xffffffff,
 0x00009278, 0x00070000, 0xffffffff,
 0x0000927c, 0x00030002, 0xffffffff,
 0x00009280, 0x00050004, 0xffffffff,
 0x0000928c, 0x00010006, 0xffffffff,
 0x00009290, 0x00090008, 0xffffffff,
 0x000092a8, 0x00070000, 0xffffffff,
 0x000092ac, 0x00030002, 0xffffffff,
 0x000092b0, 0x00050004, 0xffffffff,
 0x000092bc, 0x00010006, 0xffffffff,
 0x000092c0, 0x00090008, 0xffffffff,
 0x000092c4, 0x00070000, 0xffffffff,
 0x000092c8, 0x00030002, 0xffffffff,
 0x000092cc, 0x00050004, 0xffffffff,
 0x000092d8, 0x00010006, 0xffffffff,
 0x000092dc, 0x00090008, 0xffffffff,
 0x00009294, 0x00000000, 0xffffffff,
 0x0000802c, 0x40010000, 0xffffffff,
 0x00003fc4, 0x40010000, 0xffffffff,
 0x0000915c, 0x00010000, 0xffffffff,
 0x00009160, 0x00030002, 0xffffffff,
 0x00009164, 0x00050004, 0xffffffff,
 0x00009168, 0x00070006, 0xffffffff,
 0x00009178, 0x00070000, 0xffffffff,
 0x0000917c, 0x00030002, 0xffffffff,
 0x00009180, 0x00050004, 0xffffffff,
 0x0000918c, 0x00010006, 0xffffffff,
 0x00009190, 0x00090008, 0xffffffff,
 0x00009194, 0x00070000, 0xffffffff,
 0x00009198, 0x00030002, 0xffffffff,
 0x0000919c, 0x00050004, 0xffffffff,
 0x000091a8, 0x00010006, 0xffffffff,
 0x000091ac, 0x00090008, 0xffffffff,
 0x000091b0, 0x00070000, 0xffffffff,
 0x000091b4, 0x00030002, 0xffffffff,
 0x000091b8, 0x00050004, 0xffffffff,
 0x000091c4, 0x00010006, 0xffffffff,
 0x000091c8, 0x00090008, 0xffffffff,
 0x000091cc, 0x00070000, 0xffffffff,
 0x000091d0, 0x00030002, 0xffffffff,
 0x000091d4, 0x00050004, 0xffffffff,
 0x000091e0, 0x00010006, 0xffffffff,
 0x000091e4, 0x00090008, 0xffffffff,
 0x000091e8, 0x00000000, 0xffffffff,
 0x000091ec, 0x00070000, 0xffffffff,
 0x000091f0, 0x00030002, 0xffffffff,
 0x000091f4, 0x00050004, 0xffffffff,
 0x00009200, 0x00010006, 0xffffffff,
 0x00009204, 0x00090008, 0xffffffff,
 0x00009208, 0x00070000, 0xffffffff,
 0x0000920c, 0x00030002, 0xffffffff,
 0x00009210, 0x00050004, 0xffffffff,
 0x0000921c, 0x00010006, 0xffffffff,
 0x00009220, 0x00090008, 0xffffffff,
 0x00009224, 0x00070000, 0xffffffff,
 0x00009228, 0x00030002, 0xffffffff,
 0x0000922c, 0x00050004, 0xffffffff,
 0x00009238, 0x00010006, 0xffffffff,
 0x0000923c, 0x00090008, 0xffffffff,
 0x00009240, 0x00070000, 0xffffffff,
 0x00009244, 0x00030002, 0xffffffff,
 0x00009248, 0x00050004, 0xffffffff,
 0x00009254, 0x00010006, 0xffffffff,
 0x00009258, 0x00090008, 0xffffffff,
 0x0000925c, 0x00070000, 0xffffffff,
 0x00009260, 0x00030002, 0xffffffff,
 0x00009264, 0x00050004, 0xffffffff,
 0x00009270, 0x00010006, 0xffffffff,
 0x00009274, 0x00090008, 0xffffffff,
 0x00009278, 0x00070000, 0xffffffff,
 0x0000927c, 0x00030002, 0xffffffff,
 0x00009280, 0x00050004, 0xffffffff,
 0x0000928c, 0x00010006, 0xffffffff,
 0x00009290, 0x00090008, 0xffffffff,
 0x000092a8, 0x00070000, 0xffffffff,
 0x000092ac, 0x00030002, 0xffffffff,
 0x000092b0, 0x00050004, 0xffffffff,
 0x000092bc, 0x00010006, 0xffffffff,
 0x000092c0, 0x00090008, 0xffffffff,
 0x000092c4, 0x00070000, 0xffffffff,
 0x000092c8, 0x00030002, 0xffffffff,
 0x000092cc, 0x00050004, 0xffffffff,
 0x000092d8, 0x00010006, 0xffffffff,
 0x000092dc, 0x00090008, 0xffffffff,
 0x00009294, 0x00000000, 0xffffffff,
 0x0000802c, 0xc0000000, 0xffffffff,
 0x00003fc4, 0xc0000000, 0xffffffff,
 0x000008f8, 0x00000010, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000011, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000012, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000013, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000014, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000015, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000016, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000017, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000018, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000019, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x0000001a, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x0000001b, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff
};
#define CAYMAN_MGCG_DEFAULT_LENGTH sizeof(cayman_mgcg_default) / (3 * sizeof(u32))

static const u32 cayman_mgcg_disable[] =
{
 0x0000802c, 0xc0000000, 0xffffffff,
 0x000008f8, 0x00000000, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000001, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000002, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x000008f8, 0x00000003, 0xffffffff,
 0x000008fc, 0xffffffff, 0xffffffff,
 0x00009150, 0x00600000, 0xffffffff
};
#define CAYMAN_MGCG_DISABLE_LENGTH   sizeof(cayman_mgcg_disable) / (3 * sizeof(u32))

static const u32 cayman_mgcg_enable[] =
{
 0x0000802c, 0xc0000000, 0xffffffff,
 0x000008f8, 0x00000000, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000001, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x000008f8, 0x00000002, 0xffffffff,
 0x000008fc, 0x00600000, 0xffffffff,
 0x000008f8, 0x00000003, 0xffffffff,
 0x000008fc, 0x00000000, 0xffffffff,
 0x00009150, 0x96944200, 0xffffffff
};

#define CAYMAN_MGCG_ENABLE_LENGTH   sizeof(cayman_mgcg_enable) / (3 * sizeof(u32))

#define NISLANDS_SYSLS_SEQUENCE  100

static const u32 cayman_sysls_default[] =
{
 /* Register,   Value,     Mask bits */
 0x000055e8, 0x00000000, 0xffffffff,
 0x0000d0bc, 0x00000000, 0xffffffff,
 0x0000d8bc, 0x00000000, 0xffffffff,
 0x000015c0, 0x000c1401, 0xffffffff,
 0x0000264c, 0x000c0400, 0xffffffff,
 0x00002648, 0x000c0400, 0xffffffff,
 0x00002650, 0x000c0400, 0xffffffff,
 0x000020b8, 0x000c0400, 0xffffffff,
 0x000020bc, 0x000c0400, 0xffffffff,
 0x000020c0, 0x000c0c80, 0xffffffff,
 0x0000f4a0, 0x000000c0, 0xffffffff,
 0x0000f4a4, 0x00680fff, 0xffffffff,
 0x00002f50, 0x00000404, 0xffffffff,
 0x000004c8, 0x00000001, 0xffffffff,
 0x000064ec, 0x00000000, 0xffffffff,
 0x00000c7c, 0x00000000, 0xffffffff,
 0x00008dfc, 0x00000000, 0xffffffff
};
#define CAYMAN_SYSLS_DEFAULT_LENGTH sizeof(cayman_sysls_default) / (3 * sizeof(u32))

static const u32 cayman_sysls_disable[] =
{
 /* Register,   Value,     Mask bits */
 0x0000d0c0, 0x00000000, 0xffffffff,
 0x0000d8c0, 0x00000000, 0xffffffff,
 0x000055e8, 0x00000000, 0xffffffff,
 0x0000d0bc, 0x00000000, 0xffffffff,
 0x0000d8bc, 0x00000000, 0xffffffff,
 0x000015c0, 0x00041401, 0xffffffff,
 0x0000264c, 0x00040400, 0xffffffff,
 0x00002648, 0x00040400, 0xffffffff,
 0x00002650, 0x00040400, 0xffffffff,
 0x000020b8, 0x00040400, 0xffffffff,
 0x000020bc, 0x00040400, 0xffffffff,
 0x000020c0, 0x00040c80, 0xffffffff,
 0x0000f4a0, 0x000000c0, 0xffffffff,
 0x0000f4a4, 0x00680000, 0xffffffff,
 0x00002f50, 0x00000404, 0xffffffff,
 0x000004c8, 0x00000001, 0xffffffff,
 0x000064ec, 0x00007ffd, 0xffffffff,
 0x00000c7c, 0x0000ff00, 0xffffffff,
 0x00008dfc, 0x0000007f, 0xffffffff
};
#define CAYMAN_SYSLS_DISABLE_LENGTH sizeof(cayman_sysls_disable) / (3 * sizeof(u32))

static const u32 cayman_sysls_enable[] =
{
 /* Register,   Value,     Mask bits */
 0x000055e8, 0x00000001, 0xffffffff,
 0x0000d0bc, 0x00000100, 0xffffffff,
 0x0000d8bc, 0x00000100, 0xffffffff,
 0x000015c0, 0x000c1401, 0xffffffff,
 0x0000264c, 0x000c0400, 0xffffffff,
 0x00002648, 0x000c0400, 0xffffffff,
 0x00002650, 0x000c0400, 0xffffffff,
 0x000020b8, 0x000c0400, 0xffffffff,
 0x000020bc, 0x000c0400, 0xffffffff,
 0x000020c0, 0x000c0c80, 0xffffffff,
 0x0000f4a0, 0x000000c0, 0xffffffff,
 0x0000f4a4, 0x00680fff, 0xffffffff,
 0x00002f50, 0x00000903, 0xffffffff,
 0x000004c8, 0x00000000, 0xffffffff,
 0x000064ec, 0x00000000, 0xffffffff,
 0x00000c7c, 0x00000000, 0xffffffff,
 0x00008dfc, 0x00000000, 0xffffffff
};
#define CAYMAN_SYSLS_ENABLE_LENGTH sizeof(cayman_sysls_enable) / (3 * sizeof(u32))

extern int ni_mc_load_microcode(struct radeon_device *rdev);

struct ni_power_info *ni_get_pi(struct radeon_device *rdev)
{
 struct ni_power_info *pi = rdev->pm.dpm.priv;

 return pi;
}

struct ni_ps *ni_get_ps(struct radeon_ps *rps)
{
 struct ni_ps *ps = rps->ps_priv;

 return ps;
}

static void ni_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
           u16 v, s32 t,
           u32 ileakage,
           u32 *leakage)
{
 s64 kt, kv, leakage_w, i_leakage, vddc, temperature;

 i_leakage = div64_s64(drm_int2fixp(ileakage), 1000);
 vddc = div64_s64(drm_int2fixp(v), 1000);
 temperature = div64_s64(drm_int2fixp(t), 1000);

 kt = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->at), 1000),
     drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bt), 1000), temperature)));
 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 1000),
     drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 1000), vddc)));

 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);

 *leakage = drm_fixp2int(leakage_w * 1000);
}

static void ni_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
          const struct ni_leakage_coeffients *coeff,
          u16 v,
          s32 t,
          u32 i_leakage,
          u32 *leakage)
{
 ni_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
}

bool ni_dpm_vblank_too_short(struct radeon_device *rdev)
{
 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
 /* we never hit the non-gddr5 limit so disable it */
 u32 switch_limit = pi->mem_gddr5 ? 450 : 0;

 if (vblank_time < switch_limit)
  return true;
 else
  return false;

}

static void ni_apply_state_adjust_rules(struct radeon_device *rdev,
     struct radeon_ps *rps)
{
 struct ni_ps *ps = ni_get_ps(rps);
 struct radeon_clock_and_voltage_limits *max_limits;
 bool disable_mclk_switching;
 u32 mclk;
 u16 vddci;
 int i;

 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
     ni_dpm_vblank_too_short(rdev))
  disable_mclk_switching = true;
 else
  disable_mclk_switching = false;

 if (rdev->pm.dpm.ac_power)
  max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
 else
  max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;

 if (rdev->pm.dpm.ac_power == false) {
  for (i = 0; i < ps->performance_level_count; i++) {
   if (ps->performance_levels[i].mclk > max_limits->mclk)
    ps->performance_levels[i].mclk = max_limits->mclk;
   if (ps->performance_levels[i].sclk > max_limits->sclk)
    ps->performance_levels[i].sclk = max_limits->sclk;
   if (ps->performance_levels[i].vddc > max_limits->vddc)
    ps->performance_levels[i].vddc = max_limits->vddc;
   if (ps->performance_levels[i].vddci > max_limits->vddci)
    ps->performance_levels[i].vddci = max_limits->vddci;
  }
 }

 /* XXX validate the min clocks required for display */

 /* adjust low state */
 if (disable_mclk_switching) {
  ps->performance_levels[0].mclk =
   ps->performance_levels[ps->performance_level_count - 1].mclk;
  ps->performance_levels[0].vddci =
   ps->performance_levels[ps->performance_level_count - 1].vddci;
 }

 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
      &ps->performance_levels[0].sclk,
      &ps->performance_levels[0].mclk);

 for (i = 1; i < ps->performance_level_count; i++) {
  if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
   ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
  if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
   ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
 }

 /* adjust remaining states */
 if (disable_mclk_switching) {
  mclk = ps->performance_levels[0].mclk;
  vddci = ps->performance_levels[0].vddci;
  for (i = 1; i < ps->performance_level_count; i++) {
   if (mclk < ps->performance_levels[i].mclk)
    mclk = ps->performance_levels[i].mclk;
   if (vddci < ps->performance_levels[i].vddci)
    vddci = ps->performance_levels[i].vddci;
  }
  for (i = 0; i < ps->performance_level_count; i++) {
   ps->performance_levels[i].mclk = mclk;
   ps->performance_levels[i].vddci = vddci;
  }
 } else {
  for (i = 1; i < ps->performance_level_count; i++) {
   if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
    ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
   if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
    ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
  }
 }

 for (i = 1; i < ps->performance_level_count; i++)
  btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
       &ps->performance_levels[i].sclk,
       &ps->performance_levels[i].mclk);

 for (i = 0; i < ps->performance_level_count; i++)
  btc_adjust_clock_combinations(rdev, max_limits,
           &ps->performance_levels[i]);

 for (i = 0; i < ps->performance_level_count; i++) {
  btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
         ps->performance_levels[i].sclk,
         max_limits->vddc,  &ps->performance_levels[i].vddc);
  btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
         ps->performance_levels[i].mclk,
         max_limits->vddci, &ps->performance_levels[i].vddci);
  btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
         ps->performance_levels[i].mclk,
         max_limits->vddc,  &ps->performance_levels[i].vddc);
  btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
         rdev->clock.current_dispclk,
         max_limits->vddc,  &ps->performance_levels[i].vddc);
 }

 for (i = 0; i < ps->performance_level_count; i++) {
  btc_apply_voltage_delta_rules(rdev,
           max_limits->vddc, max_limits->vddci,
           &ps->performance_levels[i].vddc,
           &ps->performance_levels[i].vddci);
 }

 ps->dc_compatible = true;
 for (i = 0; i < ps->performance_level_count; i++) {
  if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
   ps->dc_compatible = false;

  if (ps->performance_levels[i].vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2)
   ps->performance_levels[i].flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2;
 }
}

static void ni_cg_clockgating_default(struct radeon_device *rdev)
{
 u32 count;
 const u32 *ps = NULL;

 ps = (const u32 *)&cayman_cgcg_cgls_default;
 count = CAYMAN_CGCG_CGLS_DEFAULT_LENGTH;

 btc_program_mgcg_hw_sequence(rdev, ps, count);
}

static void ni_gfx_clockgating_enable(struct radeon_device *rdev,
          bool enable)
{
 u32 count;
 const u32 *ps = NULL;

 if (enable) {
  ps = (const u32 *)&cayman_cgcg_cgls_enable;
  count = CAYMAN_CGCG_CGLS_ENABLE_LENGTH;
 } else {
  ps = (const u32 *)&cayman_cgcg_cgls_disable;
  count = CAYMAN_CGCG_CGLS_DISABLE_LENGTH;
 }

 btc_program_mgcg_hw_sequence(rdev, ps, count);
}

static void ni_mg_clockgating_default(struct radeon_device *rdev)
{
 u32 count;
 const u32 *ps = NULL;

 ps = (const u32 *)&cayman_mgcg_default;
 count = CAYMAN_MGCG_DEFAULT_LENGTH;

 btc_program_mgcg_hw_sequence(rdev, ps, count);
}

static void ni_mg_clockgating_enable(struct radeon_device *rdev,
         bool enable)
{
 u32 count;
 const u32 *ps = NULL;

 if (enable) {
  ps = (const u32 *)&cayman_mgcg_enable;
  count = CAYMAN_MGCG_ENABLE_LENGTH;
 } else {
  ps = (const u32 *)&cayman_mgcg_disable;
  count = CAYMAN_MGCG_DISABLE_LENGTH;
 }

 btc_program_mgcg_hw_sequence(rdev, ps, count);
}

static void ni_ls_clockgating_default(struct radeon_device *rdev)
{
 u32 count;
 const u32 *ps = NULL;

 ps = (const u32 *)&cayman_sysls_default;
 count = CAYMAN_SYSLS_DEFAULT_LENGTH;

 btc_program_mgcg_hw_sequence(rdev, ps, count);
}

static void ni_ls_clockgating_enable(struct radeon_device *rdev,
         bool enable)
{
 u32 count;
 const u32 *ps = NULL;

 if (enable) {
  ps = (const u32 *)&cayman_sysls_enable;
  count = CAYMAN_SYSLS_ENABLE_LENGTH;
 } else {
  ps = (const u32 *)&cayman_sysls_disable;
  count = CAYMAN_SYSLS_DISABLE_LENGTH;
 }

 btc_program_mgcg_hw_sequence(rdev, ps, count);

}

static int ni_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
            struct radeon_clock_voltage_dependency_table *table)
{
 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 u32 i;

 if (table) {
  for (i = 0; i < table->count; i++) {
   if (0xff01 == table->entries[i].v) {
    if (pi->max_vddc == 0)
     return -EINVAL;
    table->entries[i].v = pi->max_vddc;
   }
  }
 }
 return 0;
}

static int ni_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
{
 int ret = 0;

 ret = ni_patch_single_dependency_table_based_on_leakage(rdev,
        &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);

 ret = ni_patch_single_dependency_table_based_on_leakage(rdev,
        &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
 return ret;
}

static void ni_stop_dpm(struct radeon_device *rdev)
{
 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
}

#if 0
static int ni_notify_hw_of_power_source(struct radeon_device *rdev,
     bool ac_power)
{
 if (ac_power)
  return (rv770_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
   0 : -EINVAL;

 return 0;
}
#endif

static PPSMC_Result ni_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
            PPSMC_Msg msg, u32 parameter)
{
 WREG32(SMC_SCRATCH0, parameter);
 return rv770_send_msg_to_smc(rdev, msg);
}

static int ni_restrict_performance_levels_before_switch(struct radeon_device *rdev)
{
 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
  return -EINVAL;

 return (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
  0 : -EINVAL;
}

int ni_dpm_force_performance_level(struct radeon_device *rdev,
       enum radeon_dpm_forced_level level)
{
 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
  if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)
   return -EINVAL;

  if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
   return -EINVAL;
 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
  if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
   return -EINVAL;

  if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
   return -EINVAL;
 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
  if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
   return -EINVAL;

  if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)
   return -EINVAL;
 }

 rdev->pm.dpm.forced_level = level;

 return 0;
}

static void ni_stop_smc(struct radeon_device *rdev)
{
 u32 tmp;
 int i;

 for (i = 0; i < rdev->usec_timeout; i++) {
  tmp = RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK;
  if (tmp != 1)
   break;
  udelay(1);
 }

 udelay(100);

 r7xx_stop_smc(rdev);
}

static int ni_process_firmware_header(struct radeon_device *rdev)
{
 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
 struct ni_power_info *ni_pi = ni_get_pi(rdev);
 u32 tmp;
 int ret;

 ret = rv770_read_smc_sram_dword(rdev,
     NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
     NISLANDS_SMC_FIRMWARE_HEADER_stateTable,
     &tmp, pi->sram_end);

 if (ret)
  return ret;

 pi->state_table_start = (u16)tmp;

 ret = rv770_read_smc_sram_dword(rdev,
     NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
     NISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
     &tmp, pi->sram_end);

 if (ret)
  return ret;

 pi->soft_regs_start = (u16)tmp;

 ret = rv770_read_smc_sram_dword(rdev,
     NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
     NISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
     &tmp, pi->sram_end);

 if (ret)
  return ret;

 eg_pi->mc_reg_table_start = (u16)tmp;

 ret = rv770_read_smc_sram_dword(rdev,
     NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
     NISLANDS_SMC_FIRMWARE_HEADER_fanTable,
     &tmp, pi->sram_end);

 if (ret)
  return ret;

 ni_pi->fan_table_start = (u16)tmp;

 ret = rv770_read_smc_sram_dword(rdev,
     NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
     NISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
     &tmp, pi->sram_end);

 if (ret)
  return ret;

 ni_pi->arb_table_start = (u16)tmp;

 ret = rv770_read_smc_sram_dword(rdev,
     NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
     NISLANDS_SMC_FIRMWARE_HEADER_cacTable,
     &tmp, pi->sram_end);

 if (ret)
  return ret;

 ni_pi->cac_table_start = (u16)tmp;

 ret = rv770_read_smc_sram_dword(rdev,
     NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
     NISLANDS_SMC_FIRMWARE_HEADER_spllTable,
     &tmp, pi->sram_end);

 if (ret)
  return ret;

 ni_pi->spll_table_start = (u16)tmp;


 return ret;
}

static void ni_read_clock_registers(struct radeon_device *rdev)
{
 struct ni_power_info *ni_pi = ni_get_pi(rdev);

 ni_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
 ni_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
 ni_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
 ni_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
 ni_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
 ni_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
 ni_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
 ni_pi->clock_registers.mpll_ad_func_cntl_2 = RREG32(MPLL_AD_FUNC_CNTL_2);
 ni_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
 ni_pi->clock_registers.mpll_dq_func_cntl_2 = RREG32(MPLL_DQ_FUNC_CNTL_2);
 ni_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
 ni_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
 ni_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
 ni_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
}

#if 0
static int ni_enter_ulp_state(struct radeon_device *rdev)
{
 struct rv7xx_power_info *pi = rv770_get_pi(rdev);

 if (pi->gfx_clock_gating) {
  WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
  WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
  WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
  RREG32(GB_ADDR_CONFIG);
 }

 WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
   ~HOST_SMC_MSG_MASK);

 udelay(25000);

 return 0;
}
#endif

static void ni_program_response_times(struct radeon_device *rdev)
{
 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
 u32 vddc_dly, bb_dly, acpi_dly, vbi_dly, mclk_switch_limit;
 u32 reference_clock;

 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);

 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;

 if (voltage_response_time == 0)
  voltage_response_time = 1000;

 if (backbias_response_time == 0)
  backbias_response_time = 1000;

 acpi_delay_time = 15000;
 vbi_time_out = 100000;

 reference_clock = radeon_get_xclk(rdev);

 vddc_dly = (voltage_response_time  * reference_clock) / 1600;
 bb_dly   = (backbias_response_time * reference_clock) / 1600;
 acpi_dly = (acpi_delay_time * reference_clock) / 1600;
 vbi_dly  = (vbi_time_out * reference_clock) / 1600;

 mclk_switch_limit = (460 * reference_clock) / 100;

 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_bbias, bb_dly);
 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mclk_switch_lim, mclk_switch_limit);
}

static void ni_populate_smc_voltage_table(struct radeon_device *rdev,
       struct atom_voltage_table *voltage_table,
       NISLANDS_SMC_STATETABLE *table)
{
 unsigned int i;

 for (i = 0; i < voltage_table->count; i++) {
  table->highSMIO[i] = 0;
  table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
 }
}

static void ni_populate_smc_voltage_tables(struct radeon_device *rdev,
        NISLANDS_SMC_STATETABLE *table)
{
 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
 unsigned char i;

 if (eg_pi->vddc_voltage_table.count) {
  ni_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
  table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDC] = 0;
  table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDC] =
   cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);

  for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
   if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
    table->maxVDDCIndexInPPTable = i;
    break;
   }
  }
 }

 if (eg_pi->vddci_voltage_table.count) {
  ni_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);

  table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] = 0;
  table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] =
   cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
 }
}

static int ni_populate_voltage_value(struct radeon_device *rdev,
         struct atom_voltage_table *table,
         u16 value,
         NISLANDS_SMC_VOLTAGE_VALUE *voltage)
{
 unsigned int i;

 for (i = 0; i < table->count; i++) {
  if (value <= table->entries[i].value) {
   voltage->index = (u8)i;
   voltage->value = cpu_to_be16(table->entries[i].value);
   break;
  }
 }

 if (i >= table->count)
  return -EINVAL;

 return 0;
}

static void ni_populate_mvdd_value(struct radeon_device *rdev,
       u32 mclk,
       NISLANDS_SMC_VOLTAGE_VALUE *voltage)
{
 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);

 if (!pi->mvdd_control) {
  voltage->index = eg_pi->mvdd_high_index;
  voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
  return;
 }

 if (mclk <= pi->mvdd_split_frequency) {
  voltage->index = eg_pi->mvdd_low_index;
  voltage->value = cpu_to_be16(MVDD_LOW_VALUE);
 } else {
  voltage->index = eg_pi->mvdd_high_index;
  voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
 }
}

static int ni_get_std_voltage_value(struct radeon_device *rdev,
        NISLANDS_SMC_VOLTAGE_VALUE *voltage,
        u16 *std_voltage)
{
 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries &&
     ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count))
  *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
 else
  *std_voltage = be16_to_cpu(voltage->value);

 return 0;
}

static void ni_populate_std_voltage_value(struct radeon_device *rdev,
       u16 value, u8 index,
       NISLANDS_SMC_VOLTAGE_VALUE *voltage)
{
 voltage->index = index;
 voltage->value = cpu_to_be16(value);
}

static u32 ni_get_smc_power_scaling_factor(struct radeon_device *rdev)
{
 u32 xclk_period;
 u32 xclk = radeon_get_xclk(rdev);
 u32 tmp = RREG32(CG_CAC_CTRL) & TID_CNT_MASK;

 xclk_period = (1000000000UL / xclk);
 xclk_period /= 10000UL;

 return tmp * xclk_period;
}

static u32 ni_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
{
 return (power_in_watts * scaling_factor) << 2;
}

static u32 ni_calculate_power_boost_limit(struct radeon_device *rdev,
       struct radeon_ps *radeon_state,
       u32 near_tdp_limit)
{
 struct ni_ps *state = ni_get_ps(radeon_state);
 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
 struct ni_power_info *ni_pi = ni_get_pi(rdev);
 u32 power_boost_limit = 0;
 int ret;

 if (ni_pi->enable_power_containment &&
     ni_pi->use_power_boost_limit) {
  NISLANDS_SMC_VOLTAGE_VALUE vddc;
  u16 std_vddc_med;
  u16 std_vddc_high;
  u64 tmp, n, d;

  if (state->performance_level_count < 3)
   return 0;

  ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
      state->performance_levels[state->performance_level_count - 2].vddc,
      &vddc);
  if (ret)
   return 0;

  ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_med);
  if (ret)
   return 0;

  ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
      state->performance_levels[state->performance_level_count - 1].vddc,
      &vddc);
  if (ret)
   return 0;

  ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_high);
  if (ret)
   return 0;

  n = ((u64)near_tdp_limit * ((u64)std_vddc_med * (u64)std_vddc_med) * 90);
  d = ((u64)std_vddc_high * (u64)std_vddc_high * 100);
  tmp = div64_u64(n, d);

  if (tmp >> 32)
   return 0;
  power_boost_limit = (u32)tmp;
 }

 return power_boost_limit;
}

static int ni_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
         bool adjust_polarity,
         u32 tdp_adjustment,
         u32 *tdp_limit,
         u32 *near_tdp_limit)
{
 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
  return -EINVAL;

 if (adjust_polarity) {
  *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
  *near_tdp_limit = rdev->pm.dpm.near_tdp_limit + (*tdp_limit - rdev->pm.dpm.tdp_limit);
 } else {
  *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
  *near_tdp_limit = rdev->pm.dpm.near_tdp_limit - (rdev->pm.dpm.tdp_limit - *tdp_limit);
 }

 return 0;
}

static int ni_populate_smc_tdp_limits(struct radeon_device *rdev,
          struct radeon_ps *radeon_state)
{
 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 struct ni_power_info *ni_pi = ni_get_pi(rdev);

 if (ni_pi->enable_power_containment) {
  NISLANDS_SMC_STATETABLE *smc_table = &ni_pi->smc_statetable;
  u32 scaling_factor = ni_get_smc_power_scaling_factor(rdev);
  u32 tdp_limit;
  u32 near_tdp_limit;
  u32 power_boost_limit;
  int ret;

  if (scaling_factor == 0)
   return -EINVAL;

  memset(smc_table, 0, sizeof(NISLANDS_SMC_STATETABLE));

  ret = ni_calculate_adjusted_tdp_limits(rdev,
             false, /* ??? */
             rdev->pm.dpm.tdp_adjustment,
             &tdp_limit,
             &near_tdp_limit);
  if (ret)
   return ret;

  power_boost_limit = ni_calculate_power_boost_limit(rdev, radeon_state,
           near_tdp_limit);

  smc_table->dpm2Params.TDPLimit =
   cpu_to_be32(ni_scale_power_for_smc(tdp_limit, scaling_factor));
  smc_table->dpm2Params.NearTDPLimit =
   cpu_to_be32(ni_scale_power_for_smc(near_tdp_limit, scaling_factor));
  smc_table->dpm2Params.SafePowerLimit =
   cpu_to_be32(ni_scale_power_for_smc((near_tdp_limit * NISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100,
          scaling_factor));
  smc_table->dpm2Params.PowerBoostLimit =
   cpu_to_be32(ni_scale_power_for_smc(power_boost_limit, scaling_factor));

  ret = rv770_copy_bytes_to_smc(rdev,
           (u16)(pi->state_table_start + offsetof(NISLANDS_SMC_STATETABLE, dpm2Params) +
          offsetof(PP_NIslands_DPM2Parameters, TDPLimit)),
           (u8 *)(&smc_table->dpm2Params.TDPLimit),
           sizeof(u32) * 4, pi->sram_end);
  if (ret)
   return ret;
 }

 return 0;
}

int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
    u32 arb_freq_src, u32 arb_freq_dest)
{
 u32 mc_arb_dram_timing;
 u32 mc_arb_dram_timing2;
 u32 burst_time;
 u32 mc_cg_config;

 switch (arb_freq_src) {
 case MC_CG_ARB_FREQ_F0:
  mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
  mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
  burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
  break;
 case MC_CG_ARB_FREQ_F1:
  mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_1);
  mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
  burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
  break;
 case MC_CG_ARB_FREQ_F2:
  mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_2);
  mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
  burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
  break;
 case MC_CG_ARB_FREQ_F3:
  mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_3);
  mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
  burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
  break;
 default:
  return -EINVAL;
 }

 switch (arb_freq_dest) {
 case MC_CG_ARB_FREQ_F0:
  WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
  WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
  WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
  break;
 case MC_CG_ARB_FREQ_F1:
  WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
  WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
  WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
  break;
 case MC_CG_ARB_FREQ_F2:
  WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
  WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
  WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
  break;
 case MC_CG_ARB_FREQ_F3:
  WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
  WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
  WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
  break;
 default:
  return -EINVAL;
 }

 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
 WREG32(MC_CG_CONFIG, mc_cg_config);
 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);

 return 0;
}

static int ni_init_arb_table_index(struct radeon_device *rdev)
{
 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 struct ni_power_info *ni_pi = ni_get_pi(rdev);
 u32 tmp;
 int ret;

 ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start,
     &tmp, pi->sram_end);
 if (ret)
  return ret;

 tmp &= 0x00FFFFFF;
 tmp |= ((u32)MC_CG_ARB_FREQ_F1) << 24;

 return rv770_write_smc_sram_dword(rdev, ni_pi->arb_table_start,
       tmp, pi->sram_end);
}

static int ni_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
{
 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
}

static int ni_force_switch_to_arb_f0(struct radeon_device *rdev)
{
 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 struct ni_power_info *ni_pi = ni_get_pi(rdev);
 u32 tmp;
 int ret;

 ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start,
     &tmp, pi->sram_end);
 if (ret)
  return ret;

 tmp = (tmp >> 24) & 0xff;

 if (tmp == MC_CG_ARB_FREQ_F0)
  return 0;

 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
}

static int ni_populate_memory_timing_parameters(struct radeon_device *rdev,
      struct rv7xx_pl *pl,
      SMC_NIslands_MCArbDramTimingRegisterSet *arb_regs)
{
 u32 dram_timing;
 u32 dram_timing2;

 arb_regs->mc_arb_rfsh_rate =
  (u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk);


 radeon_atom_set_engine_dram_timings(rdev, pl->sclk, pl->mclk);

 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);

 arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);

 return 0;
}

static int ni_do_program_memory_timing_parameters(struct radeon_device *rdev,
        struct radeon_ps *radeon_state,
        unsigned int first_arb_set)
{
 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 struct ni_power_info *ni_pi = ni_get_pi(rdev);
 struct ni_ps *state = ni_get_ps(radeon_state);
 SMC_NIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
 int i, ret = 0;

 for (i = 0; i < state->performance_level_count; i++) {
  ret = ni_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
  if (ret)
   break;

  ret = rv770_copy_bytes_to_smc(rdev,
           (u16)(ni_pi->arb_table_start +
          offsetof(SMC_NIslands_MCArbDramTimingRegisters, data) +
          sizeof(SMC_NIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i)),
           (u8 *)&arb_regs,
           (u16)sizeof(SMC_NIslands_MCArbDramTimingRegisterSet),
           pi->sram_end);
  if (ret)
   break;
 }
 return ret;
}

static int ni_program_memory_timing_parameters(struct radeon_device *rdev,
            struct radeon_ps *radeon_new_state)
{
 return ni_do_program_memory_timing_parameters(rdev, radeon_new_state,
            NISLANDS_DRIVER_STATE_ARB_INDEX);
}

static void ni_populate_initial_mvdd_value(struct radeon_device *rdev,
        struct NISLANDS_SMC_VOLTAGE_VALUE *voltage)
{
 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);

 voltage->index = eg_pi->mvdd_high_index;
 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
}

static int ni_populate_smc_initial_state(struct radeon_device *rdev,
      struct radeon_ps *radeon_initial_state,
      NISLANDS_SMC_STATETABLE *table)
{
 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
 struct ni_power_info *ni_pi = ni_get_pi(rdev);
 u32 reg;
 int ret;

 table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL =
  cpu_to_be32(ni_pi->clock_registers.mpll_ad_func_cntl);
 table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL_2 =
  cpu_to_be32(ni_pi->clock_registers.mpll_ad_func_cntl_2);
 table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL =
  cpu_to_be32(ni_pi->clock_registers.mpll_dq_func_cntl);
 table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL_2 =
  cpu_to_be32(ni_pi->clock_registers.mpll_dq_func_cntl_2);
 table->initialState.level.mclk.vMCLK_PWRMGT_CNTL =
  cpu_to_be32(ni_pi->clock_registers.mclk_pwrmgt_cntl);
 table->initialState.level.mclk.vDLL_CNTL =
  cpu_to_be32(ni_pi->clock_registers.dll_cntl);
 table->initialState.level.mclk.vMPLL_SS =
  cpu_to_be32(ni_pi->clock_registers.mpll_ss1);
 table->initialState.level.mclk.vMPLL_SS2 =
  cpu_to_be32(ni_pi->clock_registers.mpll_ss2);
 table->initialState.level.mclk.mclk_value =
  cpu_to_be32(initial_state->performance_levels[0].mclk);

 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL =
  cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl);
 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 =
  cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_2);
 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 =
  cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_3);
 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 =
  cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_4);
 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM =
  cpu_to_be32(ni_pi->clock_registers.cg_spll_spread_spectrum);
 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
  cpu_to_be32(ni_pi->clock_registers.cg_spll_spread_spectrum_2);
 table->initialState.level.sclk.sclk_value =
  cpu_to_be32(initial_state->performance_levels[0].sclk);
 table->initialState.level.arbRefreshState =
  NISLANDS_INITIAL_STATE_ARB_INDEX;

 table->initialState.level.ACIndex = 0;

 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
     initial_state->performance_levels[0].vddc,
     &table->initialState.level.vddc);
 if (!ret) {
  u16 std_vddc;

  ret = ni_get_std_voltage_value(rdev,
            &table->initialState.level.vddc,
            &std_vddc);
  if (!ret)
   ni_populate_std_voltage_value(rdev, std_vddc,
            table->initialState.level.vddc.index,
            &table->initialState.level.std_vddc);
 }

 if (eg_pi->vddci_control)
  ni_populate_voltage_value(rdev,
       &eg_pi->vddci_voltage_table,
       initial_state->performance_levels[0].vddci,
       &table->initialState.level.vddci);

 ni_populate_initial_mvdd_value(rdev, &table->initialState.level.mvdd);

 reg = CG_R(0xffff) | CG_L(0);
 table->initialState.level.aT = cpu_to_be32(reg);

 table->initialState.level.bSP = cpu_to_be32(pi->dsp);

 if (pi->boot_in_gen2)
  table->initialState.level.gen2PCIE = 1;
 else
  table->initialState.level.gen2PCIE = 0;

 if (pi->mem_gddr5) {
  table->initialState.level.strobeMode =
   cypress_get_strobe_mode_settings(rdev,
        initial_state->performance_levels[0].mclk);

  if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
   table->initialState.level.mcFlags = NISLANDS_SMC_MC_EDC_RD_FLAG | NISLANDS_SMC_MC_EDC_WR_FLAG;
  else
   table->initialState.level.mcFlags =  0;
 }

 table->initialState.levelCount = 1;

 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;

 table->initialState.level.dpm2.MaxPS = 0;
 table->initialState.level.dpm2.NearTDPDec = 0;
 table->initialState.level.dpm2.AboveSafeInc = 0;
 table->initialState.level.dpm2.BelowSafeInc = 0;

 reg = MIN_POWER_MASK | MAX_POWER_MASK;
 table->initialState.level.SQPowerThrottle = cpu_to_be32(reg);

 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
 table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg);

 return 0;
}

static int ni_populate_smc_acpi_state(struct radeon_device *rdev,
          NISLANDS_SMC_STATETABLE *table)
{
 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
 struct ni_power_info *ni_pi = ni_get_pi(rdev);
 u32 mpll_ad_func_cntl   = ni_pi->clock_registers.mpll_ad_func_cntl;
 u32 mpll_ad_func_cntl_2 = ni_pi->clock_registers.mpll_ad_func_cntl_2;
 u32 mpll_dq_func_cntl   = ni_pi->clock_registers.mpll_dq_func_cntl;
 u32 mpll_dq_func_cntl_2 = ni_pi->clock_registers.mpll_dq_func_cntl_2;
 u32 spll_func_cntl      = ni_pi->clock_registers.cg_spll_func_cntl;
 u32 spll_func_cntl_2    = ni_pi->clock_registers.cg_spll_func_cntl_2;
 u32 spll_func_cntl_3    = ni_pi->clock_registers.cg_spll_func_cntl_3;
 u32 spll_func_cntl_4    = ni_pi->clock_registers.cg_spll_func_cntl_4;
 u32 mclk_pwrmgt_cntl    = ni_pi->clock_registers.mclk_pwrmgt_cntl;
 u32 dll_cntl            = ni_pi->clock_registers.dll_cntl;
 u32 reg;
 int ret;

 table->ACPIState = table->initialState;

 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;

 if (pi->acpi_vddc) {
  ret = ni_populate_voltage_value(rdev,
      &eg_pi->vddc_voltage_table,
      pi->acpi_vddc, &table->ACPIState.level.vddc);
  if (!ret) {
   u16 std_vddc;

   ret = ni_get_std_voltage_value(rdev,
             &table->ACPIState.level.vddc, &std_vddc);
   if (!ret)
    ni_populate_std_voltage_value(rdev, std_vddc,
             table->ACPIState.level.vddc.index,
             &table->ACPIState.level.std_vddc);
  }

  if (pi->pcie_gen2) {
   if (pi->acpi_pcie_gen2)
    table->ACPIState.level.gen2PCIE = 1;
   else
    table->ACPIState.level.gen2PCIE = 0;
  } else {
   table->ACPIState.level.gen2PCIE = 0;
  }
 } else {
  ret = ni_populate_voltage_value(rdev,
      &eg_pi->vddc_voltage_table,
      pi->min_vddc_in_table,
      &table->ACPIState.level.vddc);
  if (!ret) {
   u16 std_vddc;

   ret = ni_get_std_voltage_value(rdev,
             &table->ACPIState.level.vddc,
             &std_vddc);
   if (!ret)
    ni_populate_std_voltage_value(rdev, std_vddc,
             table->ACPIState.level.vddc.index,
             &table->ACPIState.level.std_vddc);
  }
  table->ACPIState.level.gen2PCIE = 0;
 }

 if (eg_pi->acpi_vddci) {
  if (eg_pi->vddci_control)
   ni_populate_voltage_value(rdev,
        &eg_pi->vddci_voltage_table,
        eg_pi->acpi_vddci,
        &table->ACPIState.level.vddci);
 }


 mpll_ad_func_cntl &= ~PDNB;

 mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN;

 if (pi->mem_gddr5)
  mpll_dq_func_cntl &= ~PDNB;
 mpll_dq_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN | BYPASS;


 mclk_pwrmgt_cntl |= (MRDCKA0_RESET |
        MRDCKA1_RESET |
        MRDCKB0_RESET |
        MRDCKB1_RESET |
        MRDCKC0_RESET |
        MRDCKC1_RESET |
        MRDCKD0_RESET |
        MRDCKD1_RESET);

 mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB |
         MRDCKA1_PDNB |
         MRDCKB0_PDNB |
         MRDCKB1_PDNB |
         MRDCKC0_PDNB |
         MRDCKC1_PDNB |
         MRDCKD0_PDNB |
         MRDCKD1_PDNB);

 dll_cntl |= (MRDCKA0_BYPASS |
       MRDCKA1_BYPASS |
       MRDCKB0_BYPASS |
       MRDCKB1_BYPASS |
       MRDCKC0_BYPASS |
       MRDCKC1_BYPASS |
       MRDCKD0_BYPASS |
       MRDCKD1_BYPASS);

 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
 spll_func_cntl_2 |= SCLK_MUX_SEL(4);

 table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
 table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
 table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
 table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
 table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
 table->ACPIState.level.mclk.vDLL_CNTL = cpu_to_be32(dll_cntl);

 table->ACPIState.level.mclk.mclk_value = 0;

 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(spll_func_cntl_4);

 table->ACPIState.level.sclk.sclk_value = 0;

 ni_populate_mvdd_value(rdev, 0, &table->ACPIState.level.mvdd);

 if (eg_pi->dynamic_ac_timing)
  table->ACPIState.level.ACIndex = 1;

 table->ACPIState.level.dpm2.MaxPS = 0;
 table->ACPIState.level.dpm2.NearTDPDec = 0;
 table->ACPIState.level.dpm2.AboveSafeInc = 0;
 table->ACPIState.level.dpm2.BelowSafeInc = 0;

 reg = MIN_POWER_MASK | MAX_POWER_MASK;
 table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg);

 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
 table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg);

 return 0;
}

static int ni_init_smc_table(struct radeon_device *rdev)
{
 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 struct ni_power_info *ni_pi = ni_get_pi(rdev);
 int ret;
 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
 NISLANDS_SMC_STATETABLE *table = &ni_pi->smc_statetable;

 memset(table, 0, sizeof(NISLANDS_SMC_STATETABLE));

 ni_populate_smc_voltage_tables(rdev, table);

 switch (rdev->pm.int_thermal_type) {
 case THERMAL_TYPE_NI:
 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
  table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
  break;
 case THERMAL_TYPE_NONE:
  table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
  break;
 default:
  table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
  break;
 }

 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
  table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;

 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
  table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;

 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
  table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;

 if (pi->mem_gddr5)
  table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;

 ret = ni_populate_smc_initial_state(rdev, radeon_boot_state, table);
 if (ret)
  return ret;

 ret = ni_populate_smc_acpi_state(rdev, table);
 if (ret)
  return ret;

 table->driverState.flags = table->initialState.flags;
 table->driverState.levelCount = table->initialState.levelCount;
 table->driverState.levels[0] = table->initialState.level;

 table->ULVState = table->initialState;

 ret = ni_do_program_memory_timing_parameters(rdev, radeon_boot_state,
           NISLANDS_INITIAL_STATE_ARB_INDEX);
 if (ret)
  return ret;

 return rv770_copy_bytes_to_smc(rdev, pi->state_table_start, (u8 *)table,
           sizeof(NISLANDS_SMC_STATETABLE), pi->sram_end);
}

static int ni_calculate_sclk_params(struct radeon_device *rdev,
        u32 engine_clock,
        NISLANDS_SMC_SCLK_VALUE *sclk)
{
 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 struct ni_power_info *ni_pi = ni_get_pi(rdev);
 struct atom_clock_dividers dividers;
 u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl;
 u32 spll_func_cntl_2 = ni_pi->clock_registers.cg_spll_func_cntl_2;
 u32 spll_func_cntl_3 = ni_pi->clock_registers.cg_spll_func_cntl_3;
 u32 spll_func_cntl_4 = ni_pi->clock_registers.cg_spll_func_cntl_4;
 u32 cg_spll_spread_spectrum = ni_pi->clock_registers.cg_spll_spread_spectrum;
 u32 cg_spll_spread_spectrum_2 = ni_pi->clock_registers.cg_spll_spread_spectrum_2;
 u64 tmp;
 u32 reference_clock = rdev->clock.spll.reference_freq;
 u32 reference_divider;
 u32 fbdiv;
 int ret;

 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
          engine_clock, false, ÷rs);
 if (ret)
  return ret;

 reference_divider = 1 + dividers.ref_div;


 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834;
 do_div(tmp, reference_clock);
 fbdiv = (u32) tmp;

 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);

 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
 spll_func_cntl_2 |= SCLK_MUX_SEL(2);

 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
 spll_func_cntl_3 |= SPLL_DITHEN;

 if (pi->sclk_ss) {
  struct radeon_atom_ss ss;
  u32 vco_freq = engine_clock * dividers.post_div;

  if (radeon_atombios_get_asic_ss_info(rdev, &ss,
           ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
   u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
   u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);

   cg_spll_spread_spectrum &= ~CLK_S_MASK;
   cg_spll_spread_spectrum |= CLK_S(clk_s);
   cg_spll_spread_spectrum |= SSEN;

   cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
   cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
  }
 }

 sclk->sclk_value = engine_clock;
 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;

 return 0;
}

static int ni_populate_sclk_value(struct radeon_device *rdev,
      u32 engine_clock,
      NISLANDS_SMC_SCLK_VALUE *sclk)
{
 NISLANDS_SMC_SCLK_VALUE sclk_tmp;
 int ret;

 ret = ni_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
 if (!ret) {
  sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
  sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
  sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
  sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
  sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
  sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
  sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
 }

 return ret;
}

static int ni_init_smc_spll_table(struct radeon_device *rdev)
{
 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 struct ni_power_info *ni_pi = ni_get_pi(rdev);
 SMC_NISLANDS_SPLL_DIV_TABLE *spll_table;
 NISLANDS_SMC_SCLK_VALUE sclk_params;
 u32 fb_div;
 u32 p_div;
 u32 clk_s;
 u32 clk_v;
 u32 sclk = 0;
 int i, ret;
 u32 tmp;

 if (ni_pi->spll_table_start == 0)
  return -EINVAL;

 spll_table = kzalloc(sizeof(SMC_NISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
 if (spll_table == NULL)
  return -ENOMEM;

 for (i = 0; i < 256; i++) {
  ret = ni_calculate_sclk_params(rdev, sclk, &sclk_params);
  if (ret)
   break;

  p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
  fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
  clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
  clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;

  fb_div &= ~0x00001FFF;
  fb_div >>= 1;
  clk_v >>= 6;

  if (p_div & ~(SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
   ret = -EINVAL;

  if (clk_s & ~(SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
   ret = -EINVAL;

  if (fb_div & ~(SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
   ret = -EINVAL;

  if (clk_v & ~(SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
   ret = -EINVAL;

  if (ret)
   break;

  tmp = ((fb_div << SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
   ((p_div << SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
  spll_table->freq[i] = cpu_to_be32(tmp);

  tmp = ((clk_v << SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
   ((clk_s << SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
  spll_table->ss[i] = cpu_to_be32(tmp);

  sclk += 512;
 }

 if (!ret)
  ret = rv770_copy_bytes_to_smc(rdev, ni_pi->spll_table_start, (u8 *)spll_table,
           sizeof(SMC_NISLANDS_SPLL_DIV_TABLE), pi->sram_end);

 kfree(spll_table);

 return ret;
}

static int ni_populate_mclk_value(struct radeon_device *rdev,
      u32 engine_clock,
      u32 memory_clock,
      NISLANDS_SMC_MCLK_VALUE *mclk,
      bool strobe_mode,
      bool dll_state_on)
{
 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
 struct ni_power_info *ni_pi = ni_get_pi(rdev);
 u32 mpll_ad_func_cntl = ni_pi->clock_registers.mpll_ad_func_cntl;
 u32 mpll_ad_func_cntl_2 = ni_pi->clock_registers.mpll_ad_func_cntl_2;
 u32 mpll_dq_func_cntl = ni_pi->clock_registers.mpll_dq_func_cntl;
 u32 mpll_dq_func_cntl_2 = ni_pi->clock_registers.mpll_dq_func_cntl_2;
 u32 mclk_pwrmgt_cntl = ni_pi->clock_registers.mclk_pwrmgt_cntl;
 u32 dll_cntl = ni_pi->clock_registers.dll_cntl;
 u32 mpll_ss1 = ni_pi->clock_registers.mpll_ss1;
 u32 mpll_ss2 = ni_pi->clock_registers.mpll_ss2;
 struct atom_clock_dividers dividers;
 u32 ibias;
 u32 dll_speed;
 int ret;
 u32 mc_seq_misc7;

 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
          memory_clock, strobe_mode, ÷rs);
 if (ret)
  return ret;

 if (!strobe_mode) {
  mc_seq_misc7 = RREG32(MC_SEQ_MISC7);

  if (mc_seq_misc7 & 0x8000000)
   dividers.post_div = 1;
 }

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