/* * This function is a helper for TCON output muxing. The TCON output * muxing control register in earlier SoCs (without the TCON TOP block) * are located in TCON0. This helper returns a pointer to TCON0's * sun4i_tcon structure, or NULL if not found.
*/ staticstruct sun4i_tcon *sun4i_get_tcon0(struct drm_device *drm)
{ struct sun4i_drv *drv = drm->dev_private; struct sun4i_tcon *tcon;
list_for_each_entry(tcon, &drv->tcon_list, list) if (tcon->id == 0) return tcon;
dev_warn(drm->dev, "TCON0 not found, display output muxing may not work\n");
return NULL;
}
staticvoid sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel, conststruct drm_encoder *encoder)
{ int ret = -ENOTSUPP;
if (tcon->quirks->set_mux)
ret = tcon->quirks->set_mux(tcon, encoder);
/* XXX Would this ever happen? */ if (!connector) return;
/* * FIXME: Undocumented bits * * The whole dithering process and these parameters are not * explained in the vendor documents or BSP kernel code.
*/
regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111);
regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111);
regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111);
regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111);
regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111);
regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111);
regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000);
regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111);
regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555);
regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777);
/* Do dithering if panel only supports 6 bits per color */ if (connector->display_info.bpc == 6)
val |= SUN4I_TCON0_FRM_CTL_EN;
if (connector->display_info.num_bus_formats == 1)
bus_format = connector->display_info.bus_formats[0];
/* Check the connection format */ switch (bus_format) { case MEDIA_BUS_FMT_RGB565_1X16: /* R and B components are only 5 bits deep */
val |= SUN4I_TCON0_FRM_CTL_MODE_R;
val |= SUN4I_TCON0_FRM_CTL_MODE_B;
fallthrough; case MEDIA_BUS_FMT_RGB666_1X18: case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: /* Fall through: enable dithering */
val |= SUN4I_TCON0_FRM_CTL_EN; break;
}
/* * dclk is required to run at 1/4 the DSI per-lane bit rate.
*/
tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;
clk_set_rate(tcon->dclk, mode->crtc_clock * 1000 * (bpp / lanes)
/ SUN6I_DSI_TCON_DIV);
/* Set the resolution */
regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
/* Set dithering if needed */
sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
/* * This looks suspicious, but it works... * * The datasheet says that this should be set higher than 20 * * pixel cycle, but it's not clear what a pixel cycle is.
*/
regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div);
tcon_div &= GENMASK(6, 0);
block_space = mode->htotal * bpp / (tcon_div * lanes);
block_space -= mode->hdisplay + 40;
/* * The Allwinner BSP has a comment that the period should be * the display clock * 15, but uses an hardcoded 3000...
*/
regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG,
SUN4I_TCON_SAFE_PERIOD_NUM(3000) |
SUN4I_TCON_SAFE_PERIOD_MODE(3));
/* Enable the output on the pins */
regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG,
0xe0000000);
}
/* Set the resolution */
regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
/* Set dithering if needed */
sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
/* * This is called a backporch in the register documentation, * but it really is the back porch + hsync
*/
bp = mode->crtc_htotal - mode->crtc_hsync_start;
DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
mode->crtc_htotal, bp);
/* * This is called a backporch in the register documentation, * but it really is the back porch + hsync
*/
bp = mode->crtc_vtotal - mode->crtc_vsync_start;
DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
mode->crtc_vtotal, bp);
/* Set the resolution */
regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
/* Set dithering if needed */
sun4i_tcon0_mode_set_dithering(tcon, connector);
/* * This is called a backporch in the register documentation, * but it really is the back porch + hsync
*/
bp = mode->crtc_htotal - mode->crtc_hsync_start;
DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
mode->crtc_htotal, bp);
/* * This is called a backporch in the register documentation, * but it really is the back porch + hsync
*/
bp = mode->crtc_vtotal - mode->crtc_vsync_start;
DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
mode->crtc_vtotal, bp);
/* Set interlaced mode */ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
val = SUN4I_TCON1_CTL_INTERLACE_ENABLE; else
val = 0;
regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
SUN4I_TCON1_CTL_INTERLACE_ENABLE,
val);
/* Set the input resolution */
regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG,
SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) |
SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay));
/* Set the upscaling resolution */
regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG,
SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) |
SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay));
/* Set the output resolution */
regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG,
SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) |
SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay));
/* Set horizontal display timings */
bp = mode->crtc_htotal - mode->crtc_hsync_start;
DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
mode->htotal, bp);
regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,
SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) |
SUN4I_TCON1_BASIC3_H_BACKPORCH(bp));
bp = mode->crtc_vtotal - mode->crtc_vsync_start;
DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
mode->crtc_vtotal, bp);
/* * The vertical resolution needs to be doubled in all * cases. We could use crtc_vtotal and always multiply by two, * but that leads to a rounding error in interlace when vtotal * is odd. * * This happens with TV's PAL for example, where vtotal will * be 625, crtc_vtotal 312, and thus crtc_vtotal * 2 will be * 624, which apparently confuses the hardware. * * To work around this, we will always use vtotal, and * multiply by two only if we're not in interlace.
*/
vtotal = mode->vtotal; if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
vtotal = vtotal * 2;
/* Setup the polarity of multiple signals */ if (tcon->quirks->polarity_in_ch0) {
val = 0;
if (mode->flags & DRM_MODE_FLAG_PHSYNC)
val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
} else { /* according to vendor driver, this bit must be always set */
val = SUN4I_TCON1_IO_POL_UNKNOWN;
if (mode->flags & DRM_MODE_FLAG_PHSYNC)
val |= SUN4I_TCON1_IO_POL_HSYNC_POSITIVE;
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
val |= SUN4I_TCON1_IO_POL_VSYNC_POSITIVE;
regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(regs)) return PTR_ERR(regs);
tcon->regs = devm_regmap_init_mmio(dev, regs,
&sun4i_tcon_regmap_config); if (IS_ERR(tcon->regs)) {
dev_err(dev, "Couldn't create the TCON regmap\n"); return PTR_ERR(tcon->regs);
}
/* Make sure the TCON is disabled and all IRQs are off */
regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);
regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0);
/* Disable IO lines and set them to tristate */
regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);
regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);
return 0;
}
/* * On SoCs with the old display pipeline design (Display Engine 1.0), * the TCON is always tied to just one backend. Hence we can traverse * the of_graph upwards to find the backend our tcon is connected to, * and take its ID as our own. * * We can either identify backends from their compatible strings, which * means maintaining a large list of them. Or, since the backend is * registered and binded before the TCON, we can just go through the * list of registered backends and compare the device node. * * As the structures now store engines instead of backends, here this * function in fact searches the corresponding engine, and the ID is * requested via the get_id function of the engine.
*/ staticstruct sunxi_engine *
sun4i_tcon_find_engine_traverse(struct sun4i_drv *drv, struct device_node *node,
u32 port_id)
{ struct device_node *port, *ep, *remote; struct sunxi_engine *engine = ERR_PTR(-EINVAL);
u32 reg = 0;
port = of_graph_get_port_by_id(node, port_id); if (!port) return ERR_PTR(-EINVAL);
/* * This only works if there is only one path from the TCON * to any display engine. Otherwise the probe order of the * TCONs and display engines is not guaranteed. They may * either bind to the wrong one, or worse, bind to the same * one if additional checks are not done. * * Bail out if there are multiple input connections.
*/ if (of_get_available_child_count(port) != 1) goto out_put_port;
/* Get the first connection without specifying an ID */
ep = of_get_next_available_child(port, NULL); if (!ep) goto out_put_port;
remote = of_graph_get_remote_port_parent(ep); if (!remote) goto out_put_ep;
/* does this node match any registered engines? */
list_for_each_entry(engine, &drv->engine_list, list) if (remote == engine->node) goto out_put_remote;
/* * According to device tree binding input ports have even id * number and output ports have odd id. Since component with * more than one input and one output (TCON TOP) exits, correct * remote input id has to be calculated by subtracting 1 from * remote output id. If this for some reason can't be done, 0 * is used as input port id.
*/
of_node_put(port);
port = of_graph_get_remote_port(ep); if (!of_property_read_u32(port, "reg", ®) && reg > 0)
reg -= 1;
/* * The device tree binding says that the remote endpoint ID of any * connection between components, up to and including the TCON, of * the display pipeline should be equal to the actual ID of the local * component. Thus we can look at any one of the input connections of * the TCONs, and use that connection's remote endpoint ID as our own. * * Since the user of this function already finds the input port, * the port is passed in directly without further checks.
*/ staticint sun4i_tcon_of_get_id_from_port(struct device_node *port)
{ struct device_node *ep; int ret = -EINVAL;
remote = of_graph_get_remote_endpoint(ep); if (!remote) continue;
ret = of_property_read_u32(remote, "reg", ®); if (ret) continue;
ret = reg;
}
return ret;
}
/* * Once we know the TCON's id, we can look through the list of * engines to find a matching one. We assume all engines have * been probed and added to the list.
*/ staticstruct sunxi_engine *sun4i_tcon_get_engine_by_id(struct sun4i_drv *drv, int id)
{ struct sunxi_engine *engine;
list_for_each_entry(engine, &drv->engine_list, list) if (engine->id == id) return engine;
/* * Because TCON is added to the list at the end of the probe * (after this function is called), index of the current TCON * will be same as current TCON list size.
*/
list_for_each(pos, &drv->tcon_list)
++size;
return size;
}
/* * On SoCs with the old display pipeline design (Display Engine 1.0), * we assumed the TCON was always tied to just one backend. However * this proved not to be the case. On the A31, the TCON can select * either backend as its source. On the A20 (and likely on the A10), * the backend can choose which TCON to output to. * * The device tree binding says that the remote endpoint ID of any * connection between components, up to and including the TCON, of * the display pipeline should be equal to the actual ID of the local * component. Thus we should be able to look at any one of the input * connections of the TCONs, and use that connection's remote endpoint * ID as our own. * * However the connections between the backend and TCON were assumed * to be always singular, and their endpoit IDs were all incorrectly * set to 0. This means for these old device trees, we cannot just look * up the remote endpoint ID of a TCON input endpoint. TCON1 would be * incorrectly identified as TCON0. * * This function first checks if the TCON node has 2 input endpoints. * If so, then the device tree is a corrected version, and it will use * sun4i_tcon_of_get_id() and sun4i_tcon_get_engine_by_id() from above * to fetch the ID and engine directly. If not, then it is likely an * old device trees, where the endpoint IDs were incorrect, but did not * have endpoint connections between the backend and TCON across * different display pipelines. It will fall back to the old method of * traversing the of_graph to try and find a matching engine by device * node. * * In the case of single display pipeline device trees, either method * works.
*/ staticstruct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv, struct device_node *node)
{ struct device_node *port; struct sunxi_engine *engine;
port = of_graph_get_port_by_id(node, 0); if (!port) return ERR_PTR(-EINVAL);
/* * Is this a corrected device tree with cross pipeline * connections between the backend and TCON?
*/ if (of_get_child_count(port) > 1) { int id;
/* * When pipeline has the same number of TCONs and engines which * are represented by frontends/backends (DE1) or mixers (DE2), * we match them by their respective IDs. However, if pipeline * contains TCON TOP, chances are that there are either more * TCONs than engines (R40) or TCONs with non-consecutive ids. * (H6). In that case it's easier just use TCON index in list * as an id. That means that on R40, any 2 TCONs can be enabled * in DT out of 4 (there are 2 mixers). Due to the design of * TCON TOP, remaining 2 TCONs can't be connected to anything * anyway.
*/ if (sun4i_tcon_connected_to_tcon_top(node))
id = sun4i_tcon_get_index(drv); else
id = sun4i_tcon_of_get_id_from_port(port);
/* Get our engine by matching our ID */
engine = sun4i_tcon_get_engine_by_id(drv, id);
of_node_put(port); return engine;
}
/* Fallback to old method by traversing input endpoints */
of_node_put(port); return sun4i_tcon_find_engine_traverse(drv, node, 0);
}
tcon->lcd_rst = devm_reset_control_get(dev, "lcd"); if (IS_ERR(tcon->lcd_rst)) {
dev_err(dev, "Couldn't get our reset line\n"); return PTR_ERR(tcon->lcd_rst);
}
if (tcon->quirks->needs_edp_reset) {
edp_rstc = devm_reset_control_get_shared(dev, "edp"); if (IS_ERR(edp_rstc)) {
dev_err(dev, "Couldn't get edp reset line\n"); return PTR_ERR(edp_rstc);
}
ret = reset_control_deassert(edp_rstc); if (ret) {
dev_err(dev, "Couldn't deassert edp reset line\n"); return ret;
}
}
/* Make sure our TCON is reset */
ret = reset_control_reset(tcon->lcd_rst); if (ret) {
dev_err(dev, "Couldn't deassert our reset line\n"); return ret;
}
if (tcon->quirks->supports_lvds) { /* * This can only be made optional since we've had DT * nodes without the LVDS reset properties. * * If the property is missing, just disable LVDS, and * print a warning.
*/
tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds"); if (IS_ERR(tcon->lvds_rst)) {
dev_err(dev, "Couldn't get our reset line\n"); return PTR_ERR(tcon->lvds_rst);
} elseif (tcon->lvds_rst) {
has_lvds_rst = true;
reset_control_reset(tcon->lvds_rst);
} else {
has_lvds_rst = false;
}
/* * This can only be made optional since we've had DT * nodes without the LVDS reset properties. * * If the property is missing, just disable LVDS, and * print a warning.
*/ if (tcon->quirks->has_lvds_alt) {
tcon->lvds_pll = devm_clk_get(dev, "lvds-alt"); if (IS_ERR(tcon->lvds_pll)) { if (PTR_ERR(tcon->lvds_pll) == -ENOENT) {
has_lvds_alt = false;
} else {
dev_err(dev, "Couldn't get the LVDS PLL\n"); return PTR_ERR(tcon->lvds_pll);
}
} else {
has_lvds_alt = true;
}
}
ret = sun4i_tcon_init_clocks(dev, tcon); if (ret) {
dev_err(dev, "Couldn't init our TCON clocks\n"); goto err_assert_reset;
}
ret = sun4i_tcon_init_regmap(dev, tcon); if (ret) {
dev_err(dev, "Couldn't init our TCON regmap\n"); goto err_assert_reset;
}
if (tcon->quirks->has_channel_0) {
ret = sun4i_dclk_create(dev, tcon); if (ret) {
dev_err(dev, "Couldn't create our TCON dot clock\n"); goto err_assert_reset;
}
}
ret = sun4i_tcon_init_irq(dev, tcon); if (ret) {
dev_err(dev, "Couldn't init our TCON interrupts\n"); goto err_free_dclk;
}
tcon->crtc = sun4i_crtc_init(drm, engine, tcon); if (IS_ERR(tcon->crtc)) {
dev_err(dev, "Couldn't create our CRTC\n");
ret = PTR_ERR(tcon->crtc); goto err_free_dclk;
}
if (tcon->quirks->has_channel_0) { /* * If we have an LVDS panel connected to the TCON, we should * just probe the LVDS connector. Otherwise, just probe RGB as * we used to.
*/
remote = of_graph_get_remote_node(dev->of_node, 1, 0); if (of_device_is_compatible(remote, "panel-lvds")) if (can_lvds)
ret = sun4i_lvds_init(drm, tcon); else
ret = -EINVAL; else
ret = sun4i_rgb_init(drm, tcon);
of_node_put(remote);
if (ret < 0) goto err_free_dclk;
}
if (tcon->quirks->needs_de_be_mux) { /* * We assume there is no dynamic muxing of backends * and TCONs, so we select the backend with same ID. * * While dynamic selection might be interesting, since * the CRTC is tied to the TCON, while the layers are * tied to the backends, this means, we will need to * switch between groups of layers. There might not be * a way to represent this constraint in DRM.
*/
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
SUN4I_TCON0_CTL_SRC_SEL_MASK,
tcon->id);
regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
SUN4I_TCON1_CTL_SRC_SEL_MASK,
tcon->id);
}
list_add_tail(&tcon->list, &drv->tcon_list);
return 0;
err_free_dclk: if (tcon->quirks->has_channel_0)
sun4i_dclk_free(tcon);
err_assert_reset:
reset_control_assert(tcon->lcd_rst); return ret;
}
/* panels and bridges are present only on TCONs with channel 0 */ if (quirks->has_channel_0) {
ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge); if (ret == -EPROBE_DEFER) return ret;
}
switch (encoder->encoder_type) { case DRM_MODE_ENCODER_TMDS: /* HDMI */
shift = 8; break; default: /* TODO A31 has MIPI DSI but A31s does not */ return -EINVAL;
}
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