/* SPDX-License-Identifier: GPL-2.0-only */ /* drivers/media/platform/s5p-cec/regs-cec.h * * Copyright ( c ) 2010 Samsung Electronics * http : //www.samsung.com/ * * register header file for Samsung TVOUT driver #ifndef __EXYNOS_REGS__H#define __EXYNOS_REGS__H/* * Register part #define S5P_CEC_STATUS_0 (0 x0000)#define S5P_CEC_STATUS_1 (0 x0004)#define S5P_CEC_STATUS_2 (0 x0008)#define S5P_CEC_STATUS_3 (0 x000C)#define S5P_CEC_IRQ_MASK (0 x0010)#define S5P_CEC_IRQ_CLEAR (0 x0014)#define S5P_CEC_LOGIC_ADDR (0 x0020)#define S5P_CEC_DIVISOR_0 (0 x0030)#define S5P_CEC_DIVISOR_1 (0 x0034)#define S5P_CEC_DIVISOR_2 (0 x0038)#define S5P_CEC_DIVISOR_3 (0 x003C)#define S5P_CEC_TX_CTRL (0 x0040)#define S5P_CEC_TX_BYTES (0 x0044)#define S5P_CEC_TX_STAT0 (0 x0060)#define S5P_CEC_TX_STAT1 (0 x0064)#define S5P_CEC_TX_BUFF0 (0 x0080)#define S5P_CEC_TX_BUFF1 (0 x0084)#define S5P_CEC_TX_BUFF2 (0 x0088)#define S5P_CEC_TX_BUFF3 (0 x008C)#define S5P_CEC_TX_BUFF4 (0 x0090)#define S5P_CEC_TX_BUFF5 (0 x0094)#define S5P_CEC_TX_BUFF6 (0 x0098)#define S5P_CEC_TX_BUFF7 (0 x009C)#define S5P_CEC_TX_BUFF8 (0 x00A0)#define S5P_CEC_TX_BUFF9 (0 x00A4)#define S5P_CEC_TX_BUFF10 (0 x00A8)#define S5P_CEC_TX_BUFF11 (0 x00AC)#define S5P_CEC_TX_BUFF12 (0 x00B0)#define S5P_CEC_TX_BUFF13 (0 x00B4)#define S5P_CEC_TX_BUFF14 (0 x00B8)#define S5P_CEC_TX_BUFF15 (0 x00BC)#define S5P_CEC_RX_CTRL (0 x00C0)#define S5P_CEC_RX_STAT0 (0 x00E0)#define S5P_CEC_RX_STAT1 (0 x00E4)#define S5P_CEC_RX_BUFF0 (0 x0100)#define S5P_CEC_RX_BUFF1 (0 x0104)#define S5P_CEC_RX_BUFF2 (0 x0108)#define S5P_CEC_RX_BUFF3 (0 x010C)#define S5P_CEC_RX_BUFF4 (0 x0110)#define S5P_CEC_RX_BUFF5 (0 x0114)#define S5P_CEC_RX_BUFF6 (0 x0118)#define S5P_CEC_RX_BUFF7 (0 x011C)#define S5P_CEC_RX_BUFF8 (0 x0120)#define S5P_CEC_RX_BUFF9 (0 x0124)#define S5P_CEC_RX_BUFF10 (0 x0128)#define S5P_CEC_RX_BUFF11 (0 x012C)#define S5P_CEC_RX_BUFF12 (0 x0130)#define S5P_CEC_RX_BUFF13 (0 x0134)#define S5P_CEC_RX_BUFF14 (0 x0138)#define S5P_CEC_RX_BUFF15 (0 x013C)#define S5P_CEC_RX_FILTER_CTRL (0 x0180)#define S5P_CEC_RX_FILTER_TH (0 x0184)/* * Bit definition part #define S5P_CEC_IRQ_TX_DONE (1 <<0 )#define S5P_CEC_IRQ_TX_ERROR (1 <<1 )#define S5P_CEC_IRQ_RX_DONE (1 <<4 )#define S5P_CEC_IRQ_RX_ERROR (1 <<5 )#define S5P_CEC_TX_CTRL_START (1 <<0 )#define S5P_CEC_TX_CTRL_BCAST (1 <<1 )#define S5P_CEC_TX_CTRL_RETRY (0 x04<<4 )#define S5P_CEC_TX_CTRL_RESET (1 <<7 )#define S5P_CEC_RX_CTRL_ENABLE (1 <<0 )#define S5P_CEC_RX_CTRL_RESET (1 <<7 )#define S5P_CEC_LOGIC_ADDR_MASK (0 xF)/* PMU Registers for PHY */ #define EXYNOS_HDMI_PHY_CONTROL 0 x700#endif /* __EXYNOS_REGS__H */
Messung V0.5 in Prozent C=94 H=92 G=92
¤ Dauer der Verarbeitung: 0.3 Sekunden
¤ *© Formatika GbR, Deutschland
