// SPDX-License-Identifier: GPL-2.0-only /* * mt9m114.c onsemi MT9M114 sensor driver * * Copyright (c) 2020-2023 Laurent Pinchart <laurent.pinchart@ideasonboard.com> * Copyright (c) 2012 Analog Devices Inc. * * Almost complete rewrite of work by Scott Jiang <Scott.Jiang.Linux@gmail.com> * itself based on work from Andrew Chew <achew@nvidia.com>. #include <linux/clk.h>#include <linux/delay.h>#include <linux/errno.h>#include <linux/gpio/consumer.h>#include <linux/i2c.h>#include <linux/mod_devicetable.h>#include <linux/module.h>#include <linux/mutex.h>#include <linux/pm_runtime.h>#include <linux/regmap.h>#include <linux/regulator/consumer.h>#include <linux/types.h>#include <linux/videodev2.h>#include <media/v4l2-async.h>#include <media/v4l2-cci.h>#include <media/v4l2-ctrls.h>#include <media/v4l2-device.h>#include <media/v4l2-fwnode.h>#include <media/v4l2-mediabus.h>#include <media/v4l2-subdev.h>/* Sysctl registers */ #define MT9M114_CHIP_ID CCI_REG16(0x0000)#define MT9M114_COMMAND_REGISTER CCI_REG16(0x0080)#define MT9M114_COMMAND_REGISTER_APPLY_PATCH BIT(0)#define MT9M114_COMMAND_REGISTER_SET_STATE BIT(1)#define MT9M114_COMMAND_REGISTER_REFRESH BIT(2)#define MT9M114_COMMAND_REGISTER_WAIT_FOR_EVENT BIT(3)#define MT9M114_COMMAND_REGISTER_OK BIT(15)#define MT9M114_RESET_AND_MISC_CONTROL CCI_REG16(0x001a)#define MT9M114_RESET_SOC BIT(0)#define MT9M114_PAD_SLEW CCI_REG16(0x001e)#define MT9M114_PAD_CONTROL CCI_REG16(0x0032)/* XDMA registers */ #define MT9M114_ACCESS_CTL_STAT CCI_REG16(0x0982)#define MT9M114_PHYSICAL_ADDRESS_ACCESS CCI_REG16(0x098a)#define MT9M114_LOGICAL_ADDRESS_ACCESS CCI_REG16(0x098e)/* Sensor Core registers */ #define MT9M114_COARSE_INTEGRATION_TIME CCI_REG16(0x3012)#define MT9M114_FINE_INTEGRATION_TIME CCI_REG16(0x3014)#define MT9M114_RESET_REGISTER CCI_REG16(0x301a)#define MT9M114_RESET_REGISTER_LOCK_REG BIT(3)#define MT9M114_RESET_REGISTER_MASK_BAD BIT(9)#define MT9M114_FLASH CCI_REG16(0x3046)#define MT9M114_GREEN1_GAIN CCI_REG16(0x3056)#define MT9M114_BLUE_GAIN CCI_REG16(0x3058)#define MT9M114_RED_GAIN CCI_REG16(0x305a)#define MT9M114_GREEN2_GAIN CCI_REG16(0x305c)#define MT9M114_GLOBAL_GAIN CCI_REG16(0x305e)#define MT9M114_GAIN_DIGITAL_GAIN(n) ((n) << 12)#define MT9M114_GAIN_DIGITAL_GAIN_MASK (0xf << 12)#define MT9M114_GAIN_ANALOG_GAIN(n) ((n) << 0)#define MT9M114_GAIN_ANALOG_GAIN_MASK (0xff << 0)#define MT9M114_CUSTOMER_REV CCI_REG16(0x31fe)/* Monitor registers */ #define MT9M114_MON_MAJOR_VERSION CCI_REG16(0x8000)#define MT9M114_MON_MINOR_VERSION CCI_REG16(0x8002)#define MT9M114_MON_RELEASE_VERSION CCI_REG16(0x8004)/* Auto-Exposure Track registers */ #define MT9M114_AE_TRACK_ALGO CCI_REG16(0xa804)#define MT9M114_AE_TRACK_EXEC_AUTOMATIC_EXPOSURE BIT(0)#define MT9M114_AE_TRACK_AE_TRACKING_DAMPENING_SPEED CCI_REG8(0xa80a)/* Color Correction Matrix registers */ #define MT9M114_CCM_ALGO CCI_REG16(0xb404)#define MT9M114_CCM_EXEC_CALC_CCM_MATRIX BIT(4)#define MT9M114_CCM_DELTA_GAIN CCI_REG8(0xb42a)/* Camera Control registers */ #define MT9M114_CAM_SENSOR_CFG_Y_ADDR_START CCI_REG16(0xc800)#define MT9M114_CAM_SENSOR_CFG_X_ADDR_START CCI_REG16(0xc802)#define MT9M114_CAM_SENSOR_CFG_Y_ADDR_END CCI_REG16(0xc804)#define MT9M114_CAM_SENSOR_CFG_X_ADDR_END CCI_REG16(0xc806)#define MT9M114_CAM_SENSOR_CFG_PIXCLK CCI_REG32(0xc808)#define MT9M114_CAM_SENSOR_CFG_ROW_SPEED CCI_REG16(0xc80c)#define MT9M114_CAM_SENSOR_CFG_FINE_INTEG_TIME_MIN CCI_REG16(0xc80e)#define MT9M114_CAM_SENSOR_CFG_FINE_INTEG_TIME_MAX CCI_REG16(0xc810)#define MT9M114_CAM_SENSOR_CFG_FRAME_LENGTH_LINES CCI_REG16(0xc812)#define MT9M114_CAM_SENSOR_CFG_FRAME_LENGTH_LINES_MAX 65535#define MT9M114_CAM_SENSOR_CFG_LINE_LENGTH_PCK CCI_REG16(0xc814)#define MT9M114_CAM_SENSOR_CFG_LINE_LENGTH_PCK_MAX 8191#define MT9M114_CAM_SENSOR_CFG_FINE_CORRECTION CCI_REG16(0xc816)#define MT9M114_CAM_SENSOR_CFG_CPIPE_LAST_ROW CCI_REG16(0xc818)#define MT9M114_CAM_SENSOR_CFG_REG_0_DATA CCI_REG16(0xc826)#define MT9M114_CAM_SENSOR_CONTROL_READ_MODE CCI_REG16(0xc834)#define MT9M114_CAM_SENSOR_CONTROL_HORZ_MIRROR_EN BIT(0)#define MT9M114_CAM_SENSOR_CONTROL_VERT_FLIP_EN BIT(1)#define MT9M114_CAM_SENSOR_CONTROL_X_READ_OUT_NORMAL (0 << 4)#define MT9M114_CAM_SENSOR_CONTROL_X_READ_OUT_SKIPPING (1 << 4)#define MT9M114_CAM_SENSOR_CONTROL_X_READ_OUT_AVERAGE (2 << 4)#define MT9M114_CAM_SENSOR_CONTROL_X_READ_OUT_SUMMING (3 << 4)#define MT9M114_CAM_SENSOR_CONTROL_X_READ_OUT_MASK (3 << 4)#define MT9M114_CAM_SENSOR_CONTROL_Y_READ_OUT_NORMAL (0 << 8)#define MT9M114_CAM_SENSOR_CONTROL_Y_READ_OUT_SKIPPING (1 << 8)#define MT9M114_CAM_SENSOR_CONTROL_Y_READ_OUT_SUMMING (3 << 8)#define MT9M114_CAM_SENSOR_CONTROL_Y_READ_OUT_MASK (3 << 8)#define MT9M114_CAM_SENSOR_CONTROL_ANALOG_GAIN CCI_REG16(0xc836)#define MT9M114_CAM_SENSOR_CONTROL_COARSE_INTEGRATION_TIME CCI_REG16(0xc83c)#define MT9M114_CAM_SENSOR_CONTROL_FINE_INTEGRATION_TIME CCI_REG16(0xc83e)#define MT9M114_CAM_MODE_SELECT CCI_REG8(0xc84c)#define MT9M114_CAM_MODE_SELECT_NORMAL (0 << 0)#define MT9M114_CAM_MODE_SELECT_LENS_CALIBRATION (1 << 0)#define MT9M114_CAM_MODE_SELECT_TEST_PATTERN (2 << 0)#define MT9M114_CAM_MODE_TEST_PATTERN_SELECT CCI_REG8(0xc84d)#define MT9M114_CAM_MODE_TEST_PATTERN_SELECT_SOLID (1 << 0)#define MT9M114_CAM_MODE_TEST_PATTERN_SELECT_SOLID_BARS (4 << 0)#define MT9M114_CAM_MODE_TEST_PATTERN_SELECT_RANDOM (5 << 0)#define MT9M114_CAM_MODE_TEST_PATTERN_SELECT_FADING_BARS (8 << 0)#define MT9M114_CAM_MODE_TEST_PATTERN_SELECT_WALKING_1S_10B (10 << 0)#define MT9M114_CAM_MODE_TEST_PATTERN_SELECT_WALKING_1S_8B (11 << 0)#define MT9M114_CAM_MODE_TEST_PATTERN_RED CCI_REG16(0xc84e)#define MT9M114_CAM_MODE_TEST_PATTERN_GREEN CCI_REG16(0xc850)#define MT9M114_CAM_MODE_TEST_PATTERN_BLUE CCI_REG16(0xc852)#define MT9M114_CAM_CROP_WINDOW_XOFFSET CCI_REG16(0xc854)#define MT9M114_CAM_CROP_WINDOW_YOFFSET CCI_REG16(0xc856)#define MT9M114_CAM_CROP_WINDOW_WIDTH CCI_REG16(0xc858)#define MT9M114_CAM_CROP_WINDOW_HEIGHT CCI_REG16(0xc85a)#define MT9M114_CAM_CROP_CROPMODE CCI_REG8(0xc85c)#define MT9M114_CAM_CROP_MODE_AE_AUTO_CROP_EN BIT(0)#define MT9M114_CAM_CROP_MODE_AWB_AUTO_CROP_EN BIT(1)#define MT9M114_CAM_OUTPUT_WIDTH CCI_REG16(0xc868)#define MT9M114_CAM_OUTPUT_HEIGHT CCI_REG16(0xc86a)#define MT9M114_CAM_OUTPUT_FORMAT CCI_REG16(0xc86c)#define MT9M114_CAM_OUTPUT_FORMAT_SWAP_RED_BLUE BIT(0)#define MT9M114_CAM_OUTPUT_FORMAT_SWAP_BYTES BIT(1)#define MT9M114_CAM_OUTPUT_FORMAT_MONO_ENABLE BIT(2)#define MT9M114_CAM_OUTPUT_FORMAT_BT656_ENABLE BIT(3)#define MT9M114_CAM_OUTPUT_FORMAT_BT656_CROP_SCALE_DISABLE BIT(4)#define MT9M114_CAM_OUTPUT_FORMAT_FVLV_DISABLE BIT(5)#define MT9M114_CAM_OUTPUT_FORMAT_FORMAT_YUV (0 << 8)#define MT9M114_CAM_OUTPUT_FORMAT_FORMAT_RGB (1 << 8)#define MT9M114_CAM_OUTPUT_FORMAT_FORMAT_BAYER (2 << 8)#define MT9M114_CAM_OUTPUT_FORMAT_FORMAT_NONE (3 << 8)#define MT9M114_CAM_OUTPUT_FORMAT_FORMAT_MASK (3 << 8)#define MT9M114_CAM_OUTPUT_FORMAT_BAYER_FORMAT_RAWR10 (0 << 10)#define MT9M114_CAM_OUTPUT_FORMAT_BAYER_FORMAT_PRELSC_8_2 (1 << 10)#define MT9M114_CAM_OUTPUT_FORMAT_BAYER_FORMAT_POSTLSC_8_2 (2 << 10)#define MT9M114_CAM_OUTPUT_FORMAT_BAYER_FORMAT_PROCESSED8 (3 << 10)#define MT9M114_CAM_OUTPUT_FORMAT_BAYER_FORMAT_MASK (3 << 10)#define MT9M114_CAM_OUTPUT_FORMAT_RGB_FORMAT_565RGB (0 << 12)#define MT9M114_CAM_OUTPUT_FORMAT_RGB_FORMAT_555RGB (1 << 12)#define MT9M114_CAM_OUTPUT_FORMAT_RGB_FORMAT_444xRGB (2 << 12)#define MT9M114_CAM_OUTPUT_FORMAT_RGB_FORMAT_444RGBx (3 << 12)#define MT9M114_CAM_OUTPUT_FORMAT_RGB_FORMAT_MASK (3 << 12)#define MT9M114_CAM_OUTPUT_FORMAT_YUV CCI_REG16(0xc86e)#define MT9M114_CAM_OUTPUT_FORMAT_YUV_CLIP BIT(5)#define MT9M114_CAM_OUTPUT_FORMAT_YUV_AUV_OFFSET BIT(4)#define MT9M114_CAM_OUTPUT_FORMAT_YUV_SELECT_601 BIT(3)#define MT9M114_CAM_OUTPUT_FORMAT_YUV_NORMALISE BIT(2)#define MT9M114_CAM_OUTPUT_FORMAT_YUV_SAMPLING_EVEN_UV (0 << 0)#define MT9M114_CAM_OUTPUT_FORMAT_YUV_SAMPLING_ODD_UV (1 << 0)#define MT9M114_CAM_OUTPUT_FORMAT_YUV_SAMPLING_EVENU_ODDV (2 << 0)#define MT9M114_CAM_OUTPUT_Y_OFFSET CCI_REG8(0xc870)#define MT9M114_CAM_AET_AEMODE CCI_REG8(0xc878)#define MT9M114_CAM_AET_EXEC_SET_INDOOR BIT(0)#define MT9M114_CAM_AET_DISCRETE_FRAMERATE BIT(1)#define MT9M114_CAM_AET_ADAPTATIVE_TARGET_LUMA BIT(2)#define MT9M114_CAM_AET_ADAPTATIVE_SKIP_FRAMES BIT(3)#define MT9M114_CAM_AET_SKIP_FRAMES CCI_REG8(0xc879)#define MT9M114_CAM_AET_TARGET_AVERAGE_LUMA CCI_REG8(0xc87a)#define MT9M114_CAM_AET_TARGET_AVERAGE_LUMA_DARK CCI_REG8(0xc87b)#define MT9M114_CAM_AET_BLACK_CLIPPING_TARGET CCI_REG16(0xc87c)#define MT9M114_CAM_AET_AE_MIN_VIRT_INT_TIME_PCLK CCI_REG16(0xc87e)#define MT9M114_CAM_AET_AE_MIN_VIRT_DGAIN CCI_REG16(0xc880)#define MT9M114_CAM_AET_AE_MAX_VIRT_DGAIN CCI_REG16(0xc882)#define MT9M114_CAM_AET_AE_MIN_VIRT_AGAIN CCI_REG16(0xc884)#define MT9M114_CAM_AET_AE_MAX_VIRT_AGAIN CCI_REG16(0xc886)#define MT9M114_CAM_AET_AE_VIRT_GAIN_TH_EG CCI_REG16(0xc888)#define MT9M114_CAM_AET_AE_EG_GATE_PERCENTAGE CCI_REG8(0xc88a)#define MT9M114_CAM_AET_FLICKER_FREQ_HZ CCI_REG8(0xc88b)#define MT9M114_CAM_AET_MAX_FRAME_RATE CCI_REG16(0xc88c)#define MT9M114_CAM_AET_MIN_FRAME_RATE CCI_REG16(0xc88e)#define MT9M114_CAM_AET_TARGET_GAIN CCI_REG16(0xc890)#define MT9M114_CAM_AWB_CCM_L(n) CCI_REG16(0xc892 + (n) * 2)#define MT9M114_CAM_AWB_CCM_M(n) CCI_REG16(0xc8a4 + (n) * 2)#define MT9M114_CAM_AWB_CCM_R(n) CCI_REG16(0xc8b6 + (n) * 2)#define MT9M114_CAM_AWB_CCM_L_RG_GAIN CCI_REG16(0xc8c8)#define MT9M114_CAM_AWB_CCM_L_BG_GAIN CCI_REG16(0xc8ca)#define MT9M114_CAM_AWB_CCM_M_RG_GAIN CCI_REG16(0xc8cc)#define MT9M114_CAM_AWB_CCM_M_BG_GAIN CCI_REG16(0xc8ce)#define MT9M114_CAM_AWB_CCM_R_RG_GAIN CCI_REG16(0xc8d0)#define MT9M114_CAM_AWB_CCM_R_BG_GAIN CCI_REG16(0xc8d2)#define MT9M114_CAM_AWB_CCM_L_CTEMP CCI_REG16(0xc8d4)#define MT9M114_CAM_AWB_CCM_M_CTEMP CCI_REG16(0xc8d6)#define MT9M114_CAM_AWB_CCM_R_CTEMP CCI_REG16(0xc8d8)#define MT9M114_CAM_AWB_AWB_XSCALE CCI_REG8(0xc8f2)#define MT9M114_CAM_AWB_AWB_YSCALE CCI_REG8(0xc8f3)#define MT9M114_CAM_AWB_AWB_WEIGHTS(n) CCI_REG16(0xc8f4 + (n) * 2)#define MT9M114_CAM_AWB_AWB_XSHIFT_PRE_ADJ CCI_REG16(0xc904)#define MT9M114_CAM_AWB_AWB_YSHIFT_PRE_ADJ CCI_REG16(0xc906)#define MT9M114_CAM_AWB_AWBMODE CCI_REG8(0xc909)#define MT9M114_CAM_AWB_MODE_AUTO BIT(1)#define MT9M114_CAM_AWB_MODE_EXCLUSIVE_AE BIT(0)#define MT9M114_CAM_AWB_K_R_L CCI_REG8(0xc90c)#define MT9M114_CAM_AWB_K_G_L CCI_REG8(0xc90d)#define MT9M114_CAM_AWB_K_B_L CCI_REG8(0xc90e)#define MT9M114_CAM_AWB_K_R_R CCI_REG8(0xc90f)#define MT9M114_CAM_AWB_K_G_R CCI_REG8(0xc910)#define MT9M114_CAM_AWB_K_B_R CCI_REG8(0xc911)#define MT9M114_CAM_STAT_AWB_CLIP_WINDOW_XSTART CCI_REG16(0xc914)#define MT9M114_CAM_STAT_AWB_CLIP_WINDOW_YSTART CCI_REG16(0xc916)#define MT9M114_CAM_STAT_AWB_CLIP_WINDOW_XEND CCI_REG16(0xc918)#define MT9M114_CAM_STAT_AWB_CLIP_WINDOW_YEND CCI_REG16(0xc91a)#define MT9M114_CAM_STAT_AE_INITIAL_WINDOW_XSTART CCI_REG16(0xc91c)#define MT9M114_CAM_STAT_AE_INITIAL_WINDOW_YSTART CCI_REG16(0xc91e)#define MT9M114_CAM_STAT_AE_INITIAL_WINDOW_XEND CCI_REG16(0xc920)#define MT9M114_CAM_STAT_AE_INITIAL_WINDOW_YEND CCI_REG16(0xc922)#define MT9M114_CAM_LL_LLMODE CCI_REG16(0xc924)#define MT9M114_CAM_LL_START_BRIGHTNESS CCI_REG16(0xc926)#define MT9M114_CAM_LL_STOP_BRIGHTNESS CCI_REG16(0xc928)#define MT9M114_CAM_LL_START_SATURATION CCI_REG8(0xc92a)#define MT9M114_CAM_LL_END_SATURATION CCI_REG8(0xc92b)#define MT9M114_CAM_LL_START_DESATURATION CCI_REG8(0xc92c)#define MT9M114_CAM_LL_END_DESATURATION CCI_REG8(0xc92d)#define MT9M114_CAM_LL_START_DEMOSAICING CCI_REG8(0xc92e)#define MT9M114_CAM_LL_START_AP_GAIN CCI_REG8(0xc92f)#define MT9M114_CAM_LL_START_AP_THRESH CCI_REG8(0xc930)#define MT9M114_CAM_LL_STOP_DEMOSAICING CCI_REG8(0xc931)#define MT9M114_CAM_LL_STOP_AP_GAIN CCI_REG8(0xc932)#define MT9M114_CAM_LL_STOP_AP_THRESH CCI_REG8(0xc933)#define MT9M114_CAM_LL_START_NR_RED CCI_REG8(0xc934)#define MT9M114_CAM_LL_START_NR_GREEN CCI_REG8(0xc935)#define MT9M114_CAM_LL_START_NR_BLUE CCI_REG8(0xc936)#define MT9M114_CAM_LL_START_NR_THRESH CCI_REG8(0xc937)#define MT9M114_CAM_LL_STOP_NR_RED CCI_REG8(0xc938)#define MT9M114_CAM_LL_STOP_NR_GREEN CCI_REG8(0xc939)#define MT9M114_CAM_LL_STOP_NR_BLUE CCI_REG8(0xc93a)#define MT9M114_CAM_LL_STOP_NR_THRESH CCI_REG8(0xc93b)#define MT9M114_CAM_LL_START_CONTRAST_BM CCI_REG16(0xc93c)#define MT9M114_CAM_LL_STOP_CONTRAST_BM CCI_REG16(0xc93e)#define MT9M114_CAM_LL_GAMMA CCI_REG16(0xc940)#define MT9M114_CAM_LL_START_CONTRAST_GRADIENT CCI_REG8(0xc942)#define MT9M114_CAM_LL_STOP_CONTRAST_GRADIENT CCI_REG8(0xc943)#define MT9M114_CAM_LL_START_CONTRAST_LUMA_PERCENTAGE CCI_REG8(0xc944)#define MT9M114_CAM_LL_STOP_CONTRAST_LUMA_PERCENTAGE CCI_REG8(0xc945)#define MT9M114_CAM_LL_START_GAIN_METRIC CCI_REG16(0xc946)#define MT9M114_CAM_LL_STOP_GAIN_METRIC CCI_REG16(0xc948)#define MT9M114_CAM_LL_START_FADE_TO_BLACK_LUMA CCI_REG16(0xc94a)#define MT9M114_CAM_LL_STOP_FADE_TO_BLACK_LUMA CCI_REG16(0xc94c)#define MT9M114_CAM_LL_CLUSTER_DC_TH_BM CCI_REG16(0xc94e)#define MT9M114_CAM_LL_CLUSTER_DC_GATE_PERCENTAGE CCI_REG8(0xc950)#define MT9M114_CAM_LL_SUMMING_SENSITIVITY_FACTOR CCI_REG8(0xc951)#define MT9M114_CAM_LL_START_TARGET_LUMA_BM CCI_REG16(0xc952)#define MT9M114_CAM_LL_STOP_TARGET_LUMA_BM CCI_REG16(0xc954)#define MT9M114_CAM_PGA_PGA_CONTROL CCI_REG16(0xc95e)#define MT9M114_CAM_SYSCTL_PLL_ENABLE CCI_REG8(0xc97e)#define MT9M114_CAM_SYSCTL_PLL_ENABLE_VALUE BIT(0)#define MT9M114_CAM_SYSCTL_PLL_DISABLE_VALUE 0x00#define MT9M114_CAM_SYSCTL_PLL_DIVIDER_M_N CCI_REG16(0xc980)#define MT9M114_CAM_SYSCTL_PLL_DIVIDER_VALUE(m, n) (((n) << 8) | (m))#define MT9M114_CAM_SYSCTL_PLL_DIVIDER_P CCI_REG16(0xc982)#define MT9M114_CAM_SYSCTL_PLL_DIVIDER_P_VALUE(p) ((p) << 8)#define MT9M114_CAM_PORT_OUTPUT_CONTROL CCI_REG16(0xc984)#define MT9M114_CAM_PORT_PORT_SELECT_PARALLEL (0 << 0)#define MT9M114_CAM_PORT_PORT_SELECT_MIPI (1 << 0)#define MT9M114_CAM_PORT_CLOCK_SLOWDOWN BIT(3)#define MT9M114_CAM_PORT_TRUNCATE_RAW_BAYER BIT(4)#define MT9M114_CAM_PORT_PIXCLK_GATE BIT(5)#define MT9M114_CAM_PORT_CONT_MIPI_CLK BIT(6)#define MT9M114_CAM_PORT_CHAN_NUM(vc) ((vc) << 8)#define MT9M114_CAM_PORT_MIPI_TIMING_T_HS_ZERO CCI_REG16(0xc988)#define MT9M114_CAM_PORT_MIPI_TIMING_T_HS_ZERO_VALUE(n) ((n) << 8)#define MT9M114_CAM_PORT_MIPI_TIMING_T_HS_EXIT_TRAIL CCI_REG16(0xc98a)#define MT9M114_CAM_PORT_MIPI_TIMING_T_HS_EXIT_VALUE(n) ((n) << 8)#define MT9M114_CAM_PORT_MIPI_TIMING_T_HS_TRAIL_VALUE(n) ((n) << 0)#define MT9M114_CAM_PORT_MIPI_TIMING_T_CLK_POST_PRE CCI_REG16(0xc98c)#define MT9M114_CAM_PORT_MIPI_TIMING_T_CLK_POST_VALUE(n) ((n) << 8)#define MT9M114_CAM_PORT_MIPI_TIMING_T_CLK_PRE_VALUE(n) ((n) << 0)#define MT9M114_CAM_PORT_MIPI_TIMING_T_CLK_TRAIL_ZERO CCI_REG16(0xc98e)#define MT9M114_CAM_PORT_MIPI_TIMING_T_CLK_TRAIL_VALUE(n) ((n) << 8)#define MT9M114_CAM_PORT_MIPI_TIMING_T_CLK_ZERO_VALUE(n) ((n) << 0)/* System Manager registers */ #define MT9M114_SYSMGR_NEXT_STATE CCI_REG8(0xdc00)#define MT9M114_SYSMGR_CURRENT_STATE CCI_REG8(0xdc01)#define MT9M114_SYSMGR_CMD_STATUS CCI_REG8(0xdc02)/* Patch Loader registers */ #define MT9M114_PATCHLDR_LOADER_ADDRESS CCI_REG16(0xe000)#define MT9M114_PATCHLDR_PATCH_ID CCI_REG16(0xe002)#define MT9M114_PATCHLDR_FIRMWARE_ID CCI_REG32(0xe004)#define MT9M114_PATCHLDR_APPLY_STATUS CCI_REG8(0xe008)#define MT9M114_PATCHLDR_NUM_PATCHES CCI_REG8(0xe009)#define MT9M114_PATCHLDR_PATCH_ID_0 CCI_REG16(0xe00a)#define MT9M114_PATCHLDR_PATCH_ID_1 CCI_REG16(0xe00c)#define MT9M114_PATCHLDR_PATCH_ID_2 CCI_REG16(0xe00e)#define MT9M114_PATCHLDR_PATCH_ID_3 CCI_REG16(0xe010)#define MT9M114_PATCHLDR_PATCH_ID_4 CCI_REG16(0xe012)#define MT9M114_PATCHLDR_PATCH_ID_5 CCI_REG16(0xe014)#define MT9M114_PATCHLDR_PATCH_ID_6 CCI_REG16(0xe016)#define MT9M114_PATCHLDR_PATCH_ID_7 CCI_REG16(0xe018)/* SYS_STATE values (for SYSMGR_NEXT_STATE and SYSMGR_CURRENT_STATE) */ #define MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE 0x28#define MT9M114_SYS_STATE_STREAMING 0x31#define MT9M114_SYS_STATE_START_STREAMING 0x34#define MT9M114_SYS_STATE_ENTER_SUSPEND 0x40#define MT9M114_SYS_STATE_SUSPENDED 0x41#define MT9M114_SYS_STATE_ENTER_STANDBY 0x50#define MT9M114_SYS_STATE_STANDBY 0x52#define MT9M114_SYS_STATE_LEAVE_STANDBY 0x54/* Result status of last SET_STATE comamnd */ #define MT9M114_SET_STATE_RESULT_ENOERR 0x00#define MT9M114_SET_STATE_RESULT_EINVAL 0x0c#define MT9M114_SET_STATE_RESULT_ENOSPC 0x0d/* * The minimum amount of horizontal and vertical blanking is undocumented. The * minimum values that have been seen in register lists are 303 and 38, use * them. * * Set the default to achieve 1280x960 at 30fps. #define MT9M114_MIN_HBLANK 303#define MT9M114_MIN_VBLANK 38#define MT9M114_DEF_HBLANK 323#define MT9M114_DEF_VBLANK 39#define MT9M114_DEF_FRAME_RATE 30#define MT9M114_MAX_FRAME_RATE 120#define MT9M114_PIXEL_ARRAY_WIDTH 1296U#define MT9M114_PIXEL_ARRAY_HEIGHT 976U/* * These values are not well documented and are semi-arbitrary. The pixel array * minimum output size is 8 pixels larger than the minimum scaler cropped input * width to account for the demosaicing. #define MT9M114_PIXEL_ARRAY_MIN_OUTPUT_WIDTH (32U + 8U)#define MT9M114_PIXEL_ARRAY_MIN_OUTPUT_HEIGHT (32U + 8U)#define MT9M114_SCALER_CROPPED_INPUT_WIDTH 32U#define MT9M114_SCALER_CROPPED_INPUT_HEIGHT 32U/* Indices into the mt9m114.ifp.tpg array. */ #define MT9M114_TPG_PATTERN 0#define MT9M114_TPG_RED 1#define MT9M114_TPG_GREEN 2#define MT9M114_TPG_BLUE 3/* ----------------------------------------------------------------------------- * Data Structures enum mt9m114_format_flag {struct mt9m114_format_info {struct mt9m114 {struct i2c_client *client;struct regmap *regmap;struct clk *clk;struct gpio_desc *reset;struct regulator_bulk_data supplies[3];struct v4l2_fwnode_endpoint bus_cfg;bool bypass_pll;struct {unsigned int m;unsigned int n;unsigned int p;unsigned int pixrate;bool streaming;/* Pixel Array */ struct {struct v4l2_subdev sd;struct media_pad pad;struct v4l2_ctrl_handler hdl;struct v4l2_ctrl *exposure;struct v4l2_ctrl *gain;struct v4l2_ctrl *hblank;struct v4l2_ctrl *vblank;/* Image Flow Processor */ struct {struct v4l2_subdev sd;struct media_pad pads[2];struct v4l2_ctrl_handler hdl;unsigned int frame_rate;struct v4l2_ctrl *tpg[4];/* ----------------------------------------------------------------------------- * Formats static const struct mt9m114_format_info mt9m114_format_infos[] = {/* * The first two entries are used as defaults, for parallel and * CSI-2 buses respectively. Keep them in that order. /* Keep the format compatible with the IFP sink pad last. */ static const struct mt9m114_format_info *struct mt9m114 *sensor)if (sensor->bus_cfg.bus_type == V4L2_MBUS_CSI2_DPHY)return &mt9m114_format_infos[1];else return &mt9m114_format_infos[0];static const struct mt9m114_format_info *struct mt9m114 *sensor, unsigned int pad, u32 code)const unsigned int num_formats = ARRAY_SIZE(mt9m114_format_infos);unsigned int flag;unsigned int i;switch (pad) {case 0:return &mt9m114_format_infos[num_formats - 1];case 1:if (sensor->bus_cfg.bus_type == V4L2_MBUS_CSI2_DPHY)else for (i = 0; i < num_formats; ++i) {const struct mt9m114_format_info *info =if (info->code == code && info->flags & flag)return info;return mt9m114_default_format_info(sensor);default :return NULL;/* ----------------------------------------------------------------------------- * Initialization static const struct cci_reg_sequence mt9m114_init[] = {/* Sensor optimization */ /* APGA */ /* Automatic White balance */ /* Low-Light Image Enhancements */ /* Auto-Exposure */ /* Pixel array timings and integration time */ /* Miscellaneous settings */ /* ----------------------------------------------------------------------------- * Hardware Configuration /* Wait for a command to complete. */ static int mt9m114_poll_command(struct mt9m114 *sensor, u32 command)unsigned int i;int ret;for (i = 0; i < 100; ++i) {if (ret < 0)return ret;if (!(value & command))break ;if (value & command) {"Command %u completion timeout\n" ,return -ETIMEDOUT;if (!(value & MT9M114_COMMAND_REGISTER_OK)) {"Command %u failed\n" , command);return -EIO;return 0;/* Wait for a state to be entered. */ static int mt9m114_poll_state(struct mt9m114 *sensor, u32 state)unsigned int i;int ret;for (i = 0; i < 100; ++i) {if (ret < 0)return ret;if (value == state)return 0;"Timeout waiting for state 0x%02x\n" ,return -ETIMEDOUT;static int mt9m114_set_state(struct mt9m114 *sensor, u8 next_state)int ret = 0;/* Set the next desired state and start the state transition. */ if (ret < 0)return ret;/* Wait for the state transition to complete. */ if (ret < 0)return ret;return 0;static int mt9m114_initialize(struct mt9m114 *sensor)int ret;if (ret < 0) {"Failed to initialize the sensor\n" );return ret;/* Configure the PLL. */ if (sensor->bypass_pll) {else {/* Configure the output mode. */ if (sensor->bus_cfg.bus_type == V4L2_MBUS_CSI2_DPHY) {if (!(sensor->bus_cfg.bus.mipi_csi2.flags &else {if (ret < 0)return ret;if (ret < 0)return ret;if (ret < 0)return ret;return 0;static int mt9m114_configure_pa(struct mt9m114 *sensor,struct v4l2_subdev_state *state)const struct v4l2_mbus_framefmt *format;const struct v4l2_rect *crop;unsigned int hratio, vratio;int ret;if (ret < 0)return ret;/* * Pixel array crop and binning. The CAM_SENSOR_CFG_CPIPE_LAST_ROW * register isn't clearly documented, but is always set to the number * of active rows minus 4 divided by the vertical binning factor in all * example sensor modes. if (hratio > 1)if (vratio > 1)return ret;static int mt9m114_configure_ifp(struct mt9m114 *sensor,struct v4l2_subdev_state *state)const struct mt9m114_format_info *info;const struct v4l2_mbus_framefmt *format;const struct v4l2_rect *crop;const struct v4l2_rect *compose;int ret = 0;if (ret < 0)return ret;/* * Color pipeline (IFP) cropping and scaling. Subtract 4 from the left * and top coordinates to compensate for the lines and columns removed * by demosaicing that are taken into account in the crop rectangle but * not in the hardware. /* AWB and AE windows, use the full frame. */ /* Set the media bus code. */ return ret;static int mt9m114_set_frame_rate(struct mt9m114 *sensor)int ret = 0;return ret;static int mt9m114_start_streaming(struct mt9m114 *sensor,struct v4l2_subdev_state *pa_state,struct v4l2_subdev_state *ifp_state)int ret;if (ret)return ret;if (ret)goto error;if (ret)goto error;if (ret)goto error;if (ret)goto error;if (ret)goto error;/* * The Change-Config state is transient and moves to the streaming * state automatically. if (ret)goto error;true ;return 0;return ret;static int mt9m114_stop_streaming(struct mt9m114 *sensor)int ret;false ;return ret;/* ----------------------------------------------------------------------------- * Common Subdev Operations static const struct media_entity_operations mt9m114_entity_ops = {/* ----------------------------------------------------------------------------- * Pixel Array Control Operations static inline struct mt9m114 *pa_ctrl_to_mt9m114(struct v4l2_ctrl *ctrl)return container_of(ctrl->handler, struct mt9m114, pa.hdl);static int mt9m114_pa_g_ctrl(struct v4l2_ctrl *ctrl)struct mt9m114 *sensor = pa_ctrl_to_mt9m114(ctrl);int ret;if (!pm_runtime_get_if_in_use(&sensor->client->dev))return 0;switch (ctrl->id) {case V4L2_CID_EXPOSURE:if (ret)break ;break ;case V4L2_CID_ANALOGUE_GAIN:if (ret)break ;break ;default :break ;return ret;static int mt9m114_pa_s_ctrl(struct v4l2_ctrl *ctrl)struct mt9m114 *sensor = pa_ctrl_to_mt9m114(ctrl);const struct v4l2_mbus_framefmt *format;struct v4l2_subdev_state *state;int ret = 0;/* V4L2 controls values are applied only when power is up. */ if (!pm_runtime_get_if_in_use(&sensor->client->dev))return 0;switch (ctrl->id) {case V4L2_CID_HBLANK:break ;case V4L2_CID_VBLANK:break ;case V4L2_CID_EXPOSURE:break ;case V4L2_CID_ANALOGUE_GAIN:/* * The CAM_SENSOR_CONTROL_ANALOG_GAIN contains linear analog * gain values that are mapped to the GLOBAL_GAIN register * values by the sensor firmware. break ;case V4L2_CID_HFLIP:break ;case V4L2_CID_VFLIP:break ;default :break ;return ret;static const struct v4l2_ctrl_ops mt9m114_pa_ctrl_ops = {static void mt9m114_pa_ctrl_update_exposure(struct mt9m114 *sensor, bool manual)/* * Update the volatile flag on the manual exposure and gain controls. * If the controls have switched to manual, read their current value * from the hardware to ensure that control read and write operations * will behave correctly if (manual) {else {static void mt9m114_pa_ctrl_update_blanking(struct mt9m114 *sensor,const struct v4l2_mbus_framefmt *format)unsigned int max_blank;/* Update the blanking controls ranges based on the output size. */ /* ----------------------------------------------------------------------------- * Pixel Array Subdev Operations static inline struct mt9m114 *pa_to_mt9m114(struct v4l2_subdev *sd)return container_of(sd, struct mt9m114, pa.sd);static int mt9m114_pa_init_state(struct v4l2_subdev *sd,struct v4l2_subdev_state *state)struct v4l2_mbus_framefmt *format;struct v4l2_rect *crop;return 0;static int mt9m114_pa_enum_mbus_code(struct v4l2_subdev *sd,struct v4l2_subdev_state *state,struct v4l2_subdev_mbus_code_enum *code)if (code->index > 0)return -EINVAL;return 0;static int mt9m114_pa_enum_framesizes(struct v4l2_subdev *sd,struct v4l2_subdev_state *state,struct v4l2_subdev_frame_size_enum *fse)if (fse->index > 1)return -EINVAL;if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)return -EINVAL;/* Report binning capability through frame size enumeration. */ return 0;static int mt9m114_pa_set_fmt(struct v4l2_subdev *sd,struct v4l2_subdev_state *state,struct v4l2_subdev_format *fmt)struct mt9m114 *sensor = pa_to_mt9m114(sd);struct v4l2_mbus_framefmt *format;struct v4l2_rect *crop;unsigned int hscale;unsigned int vscale;/* The sensor can bin horizontally and vertically. */ if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)return 0;static int mt9m114_pa_get_selection(struct v4l2_subdev *sd,struct v4l2_subdev_state *state,struct v4l2_subdev_selection *sel)switch (sel->target) {case V4L2_SEL_TGT_CROP:return 0;case V4L2_SEL_TGT_CROP_DEFAULT:case V4L2_SEL_TGT_CROP_BOUNDS:case V4L2_SEL_TGT_NATIVE_SIZE:return 0;default :return -EINVAL;static int mt9m114_pa_set_selection(struct v4l2_subdev *sd,struct v4l2_subdev_state *state,struct v4l2_subdev_selection *sel)struct mt9m114 *sensor = pa_to_mt9m114(sd);struct v4l2_mbus_framefmt *format;struct v4l2_rect *crop;if (sel->target != V4L2_SEL_TGT_CROP)return -EINVAL;/* * Clamp the crop rectangle. The vertical coordinates must be even, and * the horizontal coordinates must be a multiple of 4. * * FIXME: The horizontal coordinates must be a multiple of 8 when * binning, but binning is configured after setting the selection, so * we can't know tell here if it will be used. unsigned int , ALIGN(sel->r.width, 4),unsigned int , ALIGN(sel->r.height, 2),/* Reset the format. */ if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE)return 0;static const struct v4l2_subdev_pad_ops mt9m114_pa_pad_ops = {static const struct v4l2_subdev_ops mt9m114_pa_ops = {static const struct v4l2_subdev_internal_ops mt9m114_pa_internal_ops = {static int mt9m114_pa_init(struct mt9m114 *sensor)struct v4l2_ctrl_handler *hdl = &sensor->pa.hdl;struct v4l2_subdev *sd = &sensor->pa.sd;struct media_pad *pads = &sensor->pa.pad;const struct v4l2_mbus_framefmt *format;struct v4l2_subdev_state *state;unsigned int max_exposure;int ret;/* Initialize the subdev. */ " pixel array" );/* Initialize the media entity. */ if (ret < 0)return ret;/* Initialize the control handler. */ /* The range of the HBLANK and VBLANK controls will be updated below. */ /* * The maximum coarse integration time is the frame length in lines * minus two. The default is taken directly from the datasheet, but * makes little sense as auto-exposure is enabled by default. if (sensor->pa.exposure)if (sensor->pa.gain)if (hdl->error) {goto error;if (ret)goto error;/* Update the range of the blanking controls based on the format. */ return 0;return ret;static void mt9m114_pa_cleanup(struct mt9m114 *sensor)/* ----------------------------------------------------------------------------- * Image Flow Processor Control Operations static const char * const mt9m114_test_pattern_menu[] = {"Disabled" ,"Solid Color" ,"100% Color Bars" ,"Pseudo-Random" ,"Fade-to-Gray Color Bars" ,"Walking Ones 10-bit" ,"Walking Ones 8-bit" ,/* Keep in sync with mt9m114_test_pattern_menu */ static const unsigned int mt9m114_test_pattern_value[] = {static inline struct mt9m114 *ifp_ctrl_to_mt9m114(struct v4l2_ctrl *ctrl)return container_of(ctrl->handler, struct mt9m114, ifp.hdl);static int mt9m114_ifp_s_ctrl(struct v4l2_ctrl *ctrl)struct mt9m114 *sensor = ifp_ctrl_to_mt9m114(ctrl);int ret = 0;if (ctrl->id == V4L2_CID_EXPOSURE_AUTO)/* V4L2 controls values are applied only when power is up. */ if (!pm_runtime_get_if_in_use(&sensor->client->dev))return 0;switch (ctrl->id) {case V4L2_CID_AUTO_WHITE_BALANCE:/* Control both the AWB mode and the CCM algorithm. */ if (ctrl->val)else if (ctrl->val)else break ;case V4L2_CID_EXPOSURE_AUTO:if (ctrl->val == V4L2_EXPOSURE_AUTO)else if (ret)break ;break ;case V4L2_CID_TEST_PATTERN:case V4L2_CID_TEST_PATTERN_RED:case V4L2_CID_TEST_PATTERN_GREENR:case V4L2_CID_TEST_PATTERN_BLUE: {unsigned int pattern = sensor->ifp.tpg[MT9M114_TPG_PATTERN]->val;if (pattern) {else {/* * A Config-Change needs to be issued for the change to take * effect. If we're not streaming ignore this, the change will * be applied when the stream is started. if (ret || !sensor->streaming)break ;break ;default :break ;return ret;static const struct v4l2_ctrl_ops mt9m114_ifp_ctrl_ops = {/* ----------------------------------------------------------------------------- * Image Flow Processor Subdev Operations static inline struct mt9m114 *ifp_to_mt9m114(struct v4l2_subdev *sd)return container_of(sd, struct mt9m114, ifp.sd);static int mt9m114_ifp_s_stream(struct v4l2_subdev *sd, int enable)struct mt9m114 *sensor = ifp_to_mt9m114(sd);struct v4l2_subdev_state *pa_state;struct v4l2_subdev_state *ifp_state;int ret;if (!enable)return mt9m114_stop_streaming(sensor);return ret;static int mt9m114_ifp_get_frame_interval(struct v4l2_subdev *sd,struct v4l2_subdev_state *sd_state,struct v4l2_subdev_frame_interval *interval)struct v4l2_fract *ival = &interval->interval;struct mt9m114 *sensor = ifp_to_mt9m114(sd);/* * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2 * subdev active state API. if (interval->which != V4L2_SUBDEV_FORMAT_ACTIVE)return -EINVAL;return 0;static int mt9m114_ifp_set_frame_interval(struct v4l2_subdev *sd,struct v4l2_subdev_state *sd_state,struct v4l2_subdev_frame_interval *interval)struct v4l2_fract *ival = &interval->interval;struct mt9m114 *sensor = ifp_to_mt9m114(sd);int ret = 0;/* * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2 * subdev active state API. if (interval->which != V4L2_SUBDEV_FORMAT_ACTIVE)return -EINVAL;if (ival->numerator != 0 && ival->denominator != 0)unsigned int ,else if (sensor->streaming)return ret;static int mt9m114_ifp_init_state(struct v4l2_subdev *sd,struct v4l2_subdev_state *state)struct mt9m114 *sensor = ifp_to_mt9m114(sd);struct v4l2_mbus_framefmt *format;struct v4l2_rect *crop;struct v4l2_rect *compose;return 0;static int mt9m114_ifp_enum_mbus_code(struct v4l2_subdev *sd,struct v4l2_subdev_state *state,struct v4l2_subdev_mbus_code_enum *code)const unsigned int num_formats = ARRAY_SIZE(mt9m114_format_infos);struct mt9m114 *sensor = ifp_to_mt9m114(sd);unsigned int index = 0;unsigned int flag;unsigned int i;switch (code->pad) {case 0:if (code->index != 0)return -EINVAL;return 0;case 1:if (sensor->bus_cfg.bus_type == V4L2_MBUS_CSI2_DPHY)else for (i = 0; i < num_formats; ++i) {const struct mt9m114_format_info *info =if (info->flags & flag) {if (index == code->index) {return 0;return -EINVAL;default :return -EINVAL;static int mt9m114_ifp_enum_framesizes(struct v4l2_subdev *sd,struct v4l2_subdev_state *state,struct v4l2_subdev_frame_size_enum *fse)struct mt9m114 *sensor = ifp_to_mt9m114(sd);const struct mt9m114_format_info *info;if (fse->index > 0)return -EINVAL;if (!info || info->code != fse->code)return -EINVAL;if (fse->pad == 0) {else {const struct v4l2_rect *crop;return 0;static int mt9m114_ifp_enum_frameintervals(struct v4l2_subdev *sd,struct v4l2_subdev_state *state,struct v4l2_subdev_frame_interval_enum *fie)struct mt9m114 *sensor = ifp_to_mt9m114(sd);const struct mt9m114_format_info *info;if (fie->index > 0)return -EINVAL;if (!info || info->code != fie->code)return -EINVAL;return 0;static int mt9m114_ifp_set_fmt(struct v4l2_subdev *sd,struct v4l2_subdev_state *state,struct v4l2_subdev_format *fmt)struct mt9m114 *sensor = ifp_to_mt9m114(sd);struct v4l2_mbus_framefmt *format;if (fmt->pad == 0) {/* Only the size can be changed on the sink pad. */ else {const struct mt9m114_format_info *info;/* Only the media bus code can be changed on the source pad. */ /* If the output format is RAW10, bypass the scaler. */ if (format->code == MEDIA_BUS_FMT_SGRBG10_1X10)return 0;static int mt9m114_ifp_get_selection(struct v4l2_subdev *sd,struct v4l2_subdev_state *state,struct v4l2_subdev_selection *sel)const struct v4l2_mbus_framefmt *format;const struct v4l2_rect *crop;int ret = 0;/* Crop and compose are only supported on the sink pad. */ if (sel->pad != 0)return -EINVAL;switch (sel->target) {case V4L2_SEL_TGT_CROP:break ;case V4L2_SEL_TGT_CROP_DEFAULT:case V4L2_SEL_TGT_CROP_BOUNDS:/* * The crop default and bounds are equal to the sink * format size minus 4 pixels on each side for demosaicing. break ;case V4L2_SEL_TGT_COMPOSE:break ;case V4L2_SEL_TGT_COMPOSE_DEFAULT:case V4L2_SEL_TGT_COMPOSE_BOUNDS:/* * The compose default and bounds sizes are equal to the sink * crop rectangle size. break ;default :break ;return ret;static int mt9m114_ifp_set_selection(struct v4l2_subdev *sd,struct v4l2_subdev_state *state,struct v4l2_subdev_selection *sel)struct v4l2_mbus_framefmt *format;struct v4l2_rect *crop;struct v4l2_rect *compose;if (sel->target != V4L2_SEL_TGT_CROP &&return -EINVAL;/* Crop and compose are only supported on the sink pad. */ if (sel->pad != 0)return -EINVAL;if (sel->target == V4L2_SEL_TGT_CROP) {/* * Clamp the crop rectangle. Demosaicing removes 4 pixels on * each side of the image. unsigned int , ALIGN(sel->r.left, 2), 4,unsigned int , ALIGN(sel->r.top, 2), 4,unsigned int , ALIGN(sel->r.width, 2),unsigned int , ALIGN(sel->r.height, 2),/* Propagate to the compose rectangle. */ else {/* * Clamp the compose rectangle. The scaler can only downscale. unsigned int , ALIGN(sel->r.width, 2),unsigned int , ALIGN(sel->r.height, 2),/* Propagate the compose rectangle to the source format. */ return 0;static void mt9m114_ifp_unregistered(struct v4l2_subdev *sd)struct mt9m114 *sensor = ifp_to_mt9m114(sd);static int mt9m114_ifp_registered(struct v4l2_subdev *sd)struct mt9m114 *sensor = ifp_to_mt9m114(sd);int ret;if (ret < 0) {"Failed to register pixel array subdev\n" );return ret;if (ret < 0) {"Failed to link pixel array to ifp\n" );return ret;return 0;static const struct v4l2_subdev_video_ops mt9m114_ifp_video_ops = {static const struct v4l2_subdev_pad_ops mt9m114_ifp_pad_ops = {static const struct v4l2_subdev_ops mt9m114_ifp_ops = {static const struct v4l2_subdev_internal_ops mt9m114_ifp_internal_ops = {static int mt9m114_ifp_init(struct mt9m114 *sensor)struct v4l2_subdev *sd = &sensor->ifp.sd;struct media_pad *pads = sensor->ifp.pads;struct v4l2_ctrl_handler *hdl = &sensor->ifp.hdl;struct v4l2_ctrl *link_freq;int ret;/* Initialize the subdev. */ " ifp" );/* Initialize the media entity. */ if (ret < 0)return ret;
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