/* Note: this driver was created without any documentation. Based * on sniffing, testing and in some cases mimic of original driver. * As soon as some one with documentation or more experience in SD/MMC, or * reverse engineering then me, please review this driver and question every * thing what I did. 2018 Oleksij Rempel <linux@rempel-privat.de>
*/
var = alcor_read8(priv, addr);
var &= ~clear;
var |= set;
alcor_write8(priv, var, addr);
}
/* As soon as irqs are masked, some status updates may be missed. * Use this with care.
*/ staticinlinevoid alcor_mask_sd_irqs(struct alcor_sdmmc_host *host)
{ struct alcor_pci_priv *priv = host->alcor_pci;
if (data->flags & MMC_DATA_WRITE)
ctrl |= AU6601_DATA_WRITE;
if (data->host_cookie == COOKIE_MAPPED) { /* * For DMA transfers, this function is called just once, * at the start of the operation. The hardware can only * perform DMA I/O on a single page at a time, so here * we kick off the transfer with the first page, and expect * subsequent pages to be transferred upon IRQ events * indicating that the single-page DMA was completed.
*/
alcor_data_set_dma(host);
ctrl |= AU6601_DATA_DMA_MODE;
host->dma_on = 1;
alcor_write32(priv, data->sg_count * 0x1000,
AU6601_REG_BLOCK_SIZE);
} else { /* * For PIO transfers, we break down each operation * into several sector-sized transfers. When one sector has * complete, the IRQ handler will call this function again * to kick off the transfer of the next sector.
*/
alcor_write32(priv, data->blksz, AU6601_REG_BLOCK_SIZE);
}
data = host->data;
host->data = NULL;
host->dma_on = 0;
/* * The specification states that the block count register must * be updated, but it does not specify at what point in the * data flow. That makes the register entirely useless to read * back so we have to assume that nothing made it to the card * in the event of an error.
*/ if (data->error)
data->bytes_xfered = 0; else
data->bytes_xfered = data->blksz * data->blocks;
/* * Need to send CMD12 if - * a) open-ended multiblock transfer (no CMD23) * b) error in multiblock transfer
*/ if (data->stop &&
(data->error ||
!host->mrq->sbc)) {
/* * The controller needs a reset of internal state machines * upon error conditions.
*/ if (data->error)
alcor_reset(host, AU6601_RESET_CMD | AU6601_RESET_DATA);
if (!host->cmd && intmask & AU6601_INT_CMD_END) {
dev_dbg(host->dev, "Got command interrupt 0x%08x even though no command operation was in progress.\n",
intmask);
}
/* Processed actual command. */ if (!host->data)
alcor_request_complete(host, 1); else
alcor_trigger_data_transfer(host);
host->cmd = NULL;
}
if (!host->data) {
dev_dbg(host->dev, "Got data interrupt 0x%08x even though no data operation was in progress.\n",
intmask);
alcor_reset(host, AU6601_RESET_DATA); return;
}
detect = alcor_read8(priv, AU6601_DETECT_STATUS)
& AU6601_DETECT_STATUS_M; /* check if card is present then send command and data */ return (detect == AU6601_SD_DETECTED);
}
/* check if card is present then send command and data */ if (alcor_get_cd(mmc))
alcor_send_cmd(host, mrq->cmd, true); else {
mrq->cmd->error = -ENOMEDIUM;
alcor_request_complete(host, 1);
}
/* FIXME: looks like the DMA engine works only with CMD18 */ if (cmd->opcode != MMC_READ_MULTIPLE_BLOCK
&& cmd->opcode != MMC_WRITE_MULTIPLE_BLOCK) return; /* * We don't do DMA on "complex" transfers, i.e. with * non-word-aligned buffers or lengths. A future improvement * could be made to use temporary DMA bounce-buffers when these * requirements are not met. * * Also, we don't bother with all the DMA setup overhead for * short transfers.
*/ if (data->blocks * data->blksz < AU6601_MAX_DMA_BLOCK_SIZE) return;
if (data->blksz & 3) return;
for_each_sg(data->sg, sg, data->sg_len, i) { if (sg->length != AU6601_MAX_DMA_BLOCK_SIZE) return; if (sg->offset != 0) return;
}
switch (ios->power_mode) { case MMC_POWER_OFF:
alcor_set_clock(host, ios->clock); /* set all pins to input */
alcor_write8(priv, 0, AU6601_OUTPUT_ENABLE); /* turn of VDD */
alcor_write8(priv, 0, AU6601_POWER_CONTROL); break; case MMC_POWER_UP: break; case MMC_POWER_ON: /* This is most trickiest part. The order and timings of * instructions seems to play important role. Any changes may * confuse internal state engine if this HW. * FIXME: If we will ever get access to documentation, then this * part should be reviewed again.
*/
/* enable SD card mode */
alcor_write8(priv, AU6601_SD_CARD,
AU6601_ACTIVE_CTRL); /* set signal voltage to 3.3V */
alcor_write8(priv, 0, AU6601_OPT); /* no documentation about clk delay, for now just try to mimic * original driver.
*/
alcor_write8(priv, 0x20, AU6601_CLK_DELAY); /* set BUS width to 1 bit */
alcor_write8(priv, 0, AU6601_REG_BUS_CTRL); /* set CLK first time */
alcor_set_clock(host, ios->clock); /* power on VDD */
alcor_write8(priv, AU6601_SD_CARD,
AU6601_POWER_CONTROL); /* wait until the CLK will get stable */
mdelay(20); /* set CLK again, mimic original driver. */
alcor_set_clock(host, ios->clock);
/* enable output */
alcor_write8(priv, AU6601_SD_CARD,
AU6601_OUTPUT_ENABLE); /* The clk will not work on au6621. We need to trigger data * transfer.
*/
alcor_write8(priv, AU6601_DATA_WRITE,
AU6601_DATA_XFER_CTRL); /* configure timeout. Not clear what exactly it means. */
alcor_write8(priv, 0x7d, AU6601_TIME_OUT_CTRL);
mdelay(100); break; default:
dev_err(host->dev, "Unknown power parameter\n");
}
}
/* FIXME: This part is a mimics HW init of original driver. * If we will ever get access to documentation, then this part * should be reviewed again.
*/
/* reset command state engine */
alcor_reset(host, AU6601_RESET_CMD);
/* set BUS width to 1 bit */
alcor_write8(priv, 0, AU6601_REG_BUS_CTRL);
/* reset data state engine */
alcor_reset(host, AU6601_RESET_DATA); /* Not sure if a voodoo with AU6601_DMA_BOUNDARY is really needed */
alcor_write8(priv, 0, AU6601_DMA_BOUNDARY);
alcor_write8(priv, 0, AU6601_INTERFACE_MODE_CTRL); /* not clear what we are doing here. */
alcor_write8(priv, 0x44, AU6601_PAD_DRIVE0);
alcor_write8(priv, 0x44, AU6601_PAD_DRIVE1);
alcor_write8(priv, 0x00, AU6601_PAD_DRIVE2);
/* for 6601 - dma_boundary; for 6621 - dma_page_cnt * exact meaning of this register is not clear.
*/
alcor_write8(priv, cfg->dma, AU6601_DMA_BOUNDARY);
/* make sure all pins are set to input and VDD is off */
alcor_write8(priv, 0, AU6601_OUTPUT_ENABLE);
alcor_write8(priv, 0, AU6601_POWER_CONTROL);
alcor_write8(priv, AU6601_DETECT_EN, AU6601_DETECT_STATUS); /* now we should be safe to enable IRQs */
alcor_unmask_sd_irqs(host);
}
/* The hardware does DMA data transfer of 4096 bytes to/from a single * buffer address. Scatterlists are not supported at the hardware * level, however we can work with them at the driver level, * provided that each segment is exactly 4096 bytes in size. * Upon DMA completion of a single segment (signalled via IRQ), we * immediately proceed to transfer the next segment from the * scatterlist. * * The overall request is limited to 240 sectors, matching the * original vendor driver.
*/
mmc->max_segs = AU6601_MAX_DMA_SEGMENTS;
mmc->max_seg_size = AU6601_MAX_DMA_BLOCK_SIZE;
mmc->max_blk_count = 240;
mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
dma_set_max_seg_size(host->dev, mmc->max_seg_size);
}
/* make sure irqs are disabled */
alcor_write32(priv, 0, AU6601_REG_INT_ENABLE);
alcor_write32(priv, 0, AU6601_MS_INT_ENABLE);
ret = devm_request_threaded_irq(&pdev->dev, priv->irq,
alcor_irq, alcor_irq_thread, IRQF_SHARED,
DRV_NAME_ALCOR_PCI_SDMMC, host); if (ret) return dev_err_probe(&pdev->dev, ret, "Failed to get irq for data line\n");
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