/* SPDX-License-Identifier: GPL-2.0-or-later */java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 24
/*
*private 
 *
 * Copyright (C) 2014, Broadcom Corporation
java.lang.StringIndexOutOfBoundsException: Index 64 out of bounds for length 3

#DECLARE_BITMAP(, CFP_NUM_RULES);
#define __BCM_SF2_H

#include<inux/.>
#include <linux/kernel.void _iomem   core;
type;
i<inux/.hjava.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
#include <linux/.h>
i <linux/mii.hjava.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 22
# <inux/.h>
#include <linux/types.h>
#include <linux/bitops java.lang.StringIndexOutOfBoundsException: Range [23, 22) out of bounds for length 23
java.lang.StringIndexOutOfBoundsException: Range [9, 8) out of bounds for length 26
i hjava.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 24

#include <net/dsa.h>

#>
"

struct bcm_sf2_hw_params {
 top_revjava.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 13
  core_rev
 return (riv-name+off)   java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
 u32 num_gphy;
 u8 num_acb_queue;
 u8 num_rgmii;
 u8 num_ports;
 u8 fcb_pause_override:1;
acb_packets_inflight:1;
};

#define BCM_SF2_REGS_NAME {\
","""java.lang.StringIndexOutOfBoundsException: Range [27, 25) out of bounds for length 54
}

#define BCM_SF2_REGS_NUM 6

struct bcm_sf2_port_status {
 phy_interface_t mode;
 unsigned int link;
 bool enabled;
};

struct bcm_sf2_cfp_priv {

 java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
 DECLARE_BITMAP(used, CFP_NUM_RULES);
 (unique, CFP_NUM_RULES);
 reg_writel(priv upper_32_bits(val), REG_DIR_DATA_WRITE); \
  list_head rules_list;
};

#defineSWITCH_INTR_L2(which)      \
/* Base registers, keep those in order with BCM_SF2_REGS_NAME */
 void __iomem   *core;
 void    u32 mask)  \
 void __iomem   *intrl2_0;
 void __iomem   *intrl2_1;which_priv ,java.lang.StringIndexOutOfBoundsException: Range [62, 58) out of bounds for length 62
w(,,java.lang.StringIndexOutOfBoundsException: Range [60, 57) out of bounds for length 61
 void __ void __iomem

 struct

 /* Register offsets indirection tables */
    ;
 const u16   *reg_offsets;
 java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 1
 unsigned (> + >reg_offsetso])java.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 58
 int num_crossbar_int_ports
 unsigned int   num_crossbar_ext_bits;

 /* spinlock protecting access to the indirect registers */
 spinlock_t

    irq0;
 int()java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 23
 java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 0
 u32    irq0_mask;
 u32    irq1_stat;
 u32    irq1_mask;

 /* Backing b53_device */
 struct b53_device  *{

 returnreadl_relaxedpriv- +->eg_offsets[off] + reg);

 structbcm_sf2_port_status port_sts[DSA_MAX_PORTS];

 /* Mask of ports enabled for Wake-on-LAN */
 u32    wol_ports_mask;

 struct java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 struct clk   *clk_mdiv;

 /* MoCA port location */
 int    int bcm_sf2_get_rxnfc(struct dsa_switch *ds, int port,

 /* Bitmask of ports having an integrated PHY */
 unsigned intint bcm_sf2_set_rxnfc(struct dsa_switch *ds, int port,;

 /* Master and slave MDIO bus controller */
unsigned  
 struct bcm_sf2_cfp_resume)
 struct bcm_sf2_cfp_get_stringsdsa_switchds,intport u32stringset,

 /* Bitmask of ports needing BRCM tags */
 unsigned uint8_t **data);

 /* CFP rules context */
  bcm_sf2_cfp_get_ethtool_s(truct dsa_switch *ds, int port,
};

static      uint64_t data);
{
 struct b53_device *dev = ds->priv;

 return dev->priv;
}

static inline u32 bcm_sf2_mangle_addr(struct bcm_sf2_priv *priv, u32 off)
{
 return off << priv->core_reg_align;
}

#define SF2_IO_MACRO(name) \
static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off) \
{         \
 return readl_relaxed(priv->name + off);    \
}         \
static inline void name##_writel(struct bcm_sf2_priv *priv,  \
      u32 val, u32 off)   \
{         \
 writel_relaxed(val, priv->name + off);    \
}         \

/* Accesses to 64-bits register requires us to latch the hi/lo pairs
 * using the REG_DIR_DATA_{READ,WRITE} ancillary registers. The 'indir_lock'
 * spinlock is automatically grabbed and released to provide relative
 * atomiticy with latched reads/writes.
 */
#define SF2_IO64_MACRO(name) \
static inline u64 name##_readq(struct bcm_sf2_priv *priv, u32 off) \
{         \
 u32 indir, dir;       \
 spin_lock(&priv->indir_lock);     \
 dir = name##_readl(priv, off);     \
 indir = reg_readl(priv, REG_DIR_DATA_READ);   \
 spin_unlock(&priv->indir_lock);     \
 return (u64)indir << 32 | dir;     \
}         \
static inline void name##_writeq(struct bcm_sf2_priv *priv, u64 val, \
       u32 off) \
{         \
 spin_lock(&priv->indir_lock);     \
 reg_writel(priv, upper_32_bits(val), REG_DIR_DATA_WRITE); \
 name##_writel(priv, lower_32_bits(val), off);   \
 spin_unlock(&priv->indir_lock);     \
}

#define SWITCH_INTR_L2(which)      \
static inline void intrl2_##which##_mask_clear(struct bcm_sf2_priv *priv, \
      u32 mask)  \
{         \
 priv->irq##which##_mask &= ~(mask);    \
 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \
}         \
static inline void intrl2_##which##_mask_set(struct bcm_sf2_priv *priv, \
      u32 mask)  \
{         \
 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \
 priv->irq##which##_mask |= (mask);    \
}         \

static inline u32 core_readl(struct bcm_sf2_priv *priv, u32 off)
{
 u32 tmp = bcm_sf2_mangle_addr(priv, off);
 return readl_relaxed(priv->core + tmp);
}

static inline void core_writel(struct bcm_sf2_priv *priv, u32 val, u32 off)
{
 u32 tmp = bcm_sf2_mangle_addr(priv, off);
 writel_relaxed(val, priv->core + tmp);
}

static inline u32 reg_readl(struct bcm_sf2_priv *priv, u16 off)
{
 return readl_relaxed(priv->reg + priv->reg_offsets[off]);
}

static inline void reg_writel(struct bcm_sf2_priv *priv, u32 val, u16 off)
{
 writel_relaxed(val, priv->reg + priv->reg_offsets[off]);
}

SF2_IO64_MACRO(core);
SF2_IO_MACRO(intrl2_0);
SF2_IO_MACRO(intrl2_1);
SF2_IO_MACRO(fcb);
SF2_IO_MACRO(acb);

SWITCH_INTR_L2(0);
SWITCH_INTR_L2(1);

static inline u32 reg_led_readl(struct bcm_sf2_priv *priv, u16 off, u16 reg)
{
 return readl_relaxed(priv->reg + priv->reg_offsets[off] + reg);
}

static inline void reg_led_writel(struct bcm_sf2_priv *priv, u32 val, u16 off, u16 reg)
{
 writel_relaxed(val, priv->reg + priv->reg_offsets[off] + reg);
}

/* RXNFC */
int bcm_sf2_get_rxnfc(struct dsa_switch *ds, int port,
        struct ethtool_rxnfc *nfc, u32 *rule_locs);
int bcm_sf2_set_rxnfc(struct dsa_switch *ds, int port,
        struct ethtool_rxnfc *nfc);
int bcm_sf2_cfp_rst(struct bcm_sf2_priv *priv);
void bcm_sf2_cfp_exit(struct dsa_switch *ds);
int bcm_sf2_cfp_resume(struct dsa_switch *ds);
void bcm_sf2_cfp_get_strings(struct dsa_switch *ds, int port, u32 stringset,
        uint8_t **data);
void bcm_sf2_cfp_get_ethtool_stats(struct dsa_switch *ds, int port,
       uint64_t *data);
int bcm_sf2_cfp_get_sset_count(struct dsa_switch *ds, int port, int sset);

#endif /* __BCM_SF2_H */