// SPDX-License-Identifier: GPL-2.0 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch. * * Copyright ( C ) 2021 Alvin Š ipraga < alsi @ bang - olufsen . dk > * Copyright ( C ) 2021 Michael Rasmussen < mir @ bang - olufsen . dk > * * The RTL8365MB - VC is a 4 + 1 port 10 / 100 / 1000 M switch controller . It includes 4 * integrated PHYs for the user facing ports , and an extension interface which * can be connected to the CPU - or another PHY - via either MII , RMII , or * RGMII . The switch is configured via the Realtek Simple Management Interface * ( SMI ) , which uses the MDIO / MDC lines . * * Below is a simplified block diagram of the chip and its relevant interfaces . * * . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - . * | | * UTP < - - - - - - - - - - - - - - - > Giga PHY < - > PCS < - > P0 GMAC | * UTP < - - - - - - - - - - - - - - - > Giga PHY < - > PCS < - > P1 GMAC | * UTP < - - - - - - - - - - - - - - - > Giga PHY < - > PCS < - > P2 GMAC | * UTP < - - - - - - - - - - - - - - - > Giga PHY < - > PCS < - > P3 GMAC | * | | * CPU / PHY < - MII / RMII / RGMII - - - > Extension < - - - > Extension | * | interface 1 GMAC 1 | * | | * SMI driver / < - MDC / SCL - - - > Management ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ | * EEPROM < - MDIO / SDA - - > interface ~ REALTEK ~ ~ ~ ~ ~ | * | ~ RTL8365MB ~ ~ ~ | * | ~ GXXXC TAIWAN ~ | * GPIO < - - - - - - - - - - - - - - > Reset ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ | * | | * Interrupt < - - - - - - - - - - > Link UP / DOWN events | * controller | | * ' - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ' * * The driver uses DSA to integrate the 4 user and 1 extension ports into the * kernel . Netdevices are created for the user ports , as are PHY devices for * their integrated PHYs . The device tree firmware should also specify the link * partner of the extension port - either via a fixed - link or other phy - handle . * See the device tree bindings for more detailed information . Note that the * driver has only been tested with a fixed - link , but in principle it should not * matter . * * NOTE : Currently , only the RGMII interface is implemented in this driver . * * The interrupt line is asserted on link UP / DOWN events . The driver creates a * custom irqchip to handle this interrupt and demultiplex the events by reading * the status registers via SMI . Interrupts are then propagated to the relevant * PHY device . * * The EEPROM contains initial register values which the chip will read over I2C * upon hardware reset . It is also possible to omit the EEPROM . In both cases , * the driver will manually reprogram some registers using jam tables to reach * an initial state defined by the vendor driver . * * This Linux driver is written based on an OS - agnostic vendor driver from * Realtek . The reference GPL - licensed sources can be found in the OpenWrt * source tree under the name rtl8367c . The vendor driver claims to support a * number of similar switch controllers from Realtek , but the only hardware we * have is the RTL8365MB - VC . Moreover , there does not seem to be any chip under * the name RTL8367C . Although one wishes that the ' C ' stood for some kind of * common hardware revision , there exist examples of chips with the suffix - VC * which are explicitly not supported by the rtl8367c driver and which instead * require the rtl8367d vendor driver . With all this uncertainty , the driver has * been modestly named rtl8365mb . Future implementors may wish to rename things * accordingly . * * In the same family of chips , some carry up to 8 user ports and up to 2 * extension ports . Where possible this driver tries to make things generic , but * more work must be done to support these configurations . According to * documentation from Realtek , the family should include the following chips : * * - RTL8363NB * - RTL8363NB - VB * - RTL8363SC * - RTL8363SC - VB * - RTL8364NB * - RTL8364NB - VB * - RTL8365MB - VC * - RTL8366SC * - RTL8367RB - VB * - RTL8367SB * - RTL8367S * - RTL8370MB * - RTL8310SR * * Some of the register logic for these additional chips has been skipped over * while implementing this driver . It is therefore not possible to assume that * things will work out - of - the - box for other chips , and a careful review of the * vendor driver may be needed to expand support . The RTL8365MB - VC seems to be * one of the simpler chips . #include <linux/bitfield.h>#include <linux/bitops.h>#include <linux/interrupt.h>#include <linux/irqdomain.h>#include <linux/mutex.h>#include <linux/of_irq.h>#include <linux/regmap.h>#include <linux/if_bridge.h>#include <linux/if_vlan.h>#include "realtek.h" #include "realtek-smi.h" #include "realtek-mdio.h" #include "rtl83xx.h" /* Family-specific data and limits */ #define RTL8365MB_PHYADDRMAX 7 #define RTL8365MB_NUM_PHYREGS 32 #define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1 )#define RTL8365MB_MAX_NUM_PORTS 11 #define RTL8365MB_MAX_NUM_EXTINTS 3 #define RTL8365MB_LEARN_LIMIT_MAX 2112 /* Chip identification registers */ #define RTL8365MB_CHIP_ID_REG 0 x1300#define RTL8365MB_CHIP_VER_REG 0 x1301#define RTL8365MB_MAGIC_REG 0 x13C2#define RTL8365MB_MAGIC_VALUE 0 x0249/* Chip reset register */ #define RTL8365MB_CHIP_RESET_REG 0 x1322#define RTL8365MB_CHIP_RESET_SW_MASK 0 x0002#define RTL8365MB_CHIP_RESET_HW_MASK 0 x0001/* Interrupt polarity register */ #define RTL8365MB_INTR_POLARITY_REG 0 x1100#define RTL8365MB_INTR_POLARITY_MASK 0 x0001#define RTL8365MB_INTR_POLARITY_HIGH 0 #define RTL8365MB_INTR_POLARITY_LOW 1 /* Interrupt control/status register - enable/check specific interrupt types */ #define RTL8365MB_INTR_CTRL_REG 0 x1101#define RTL8365MB_INTR_STATUS_REG 0 x1102#define RTL8365MB_INTR_SLIENT_START_2_MASK 0 x1000#define RTL8365MB_INTR_SLIENT_START_MASK 0 x0800#define RTL8365MB_INTR_ACL_ACTION_MASK 0 x0200#define RTL8365MB_INTR_CABLE_DIAG_FIN_MASK 0 x0100#define RTL8365MB_INTR_INTERRUPT_8051_MASK 0 x0080#define RTL8365MB_INTR_LOOP_DETECTION_MASK 0 x0040#define RTL8365MB_INTR_GREEN_TIMER_MASK 0 x0020#define RTL8365MB_INTR_SPECIAL_CONGEST_MASK 0 x0010#define RTL8365MB_INTR_SPEED_CHANGE_MASK 0 x0008#define RTL8365MB_INTR_LEARN_OVER_MASK 0 x0004#define RTL8365MB_INTR_METER_EXCEEDED_MASK 0 x0002#define RTL8365MB_INTR_LINK_CHANGE_MASK 0 x0001#define RTL8365MB_INTR_ALL_MASK \/* Per-port interrupt type status registers */ #define RTL8365MB_PORT_LINKDOWN_IND_REG 0 x1106#define RTL8365MB_PORT_LINKDOWN_IND_MASK 0 x07FF#define RTL8365MB_PORT_LINKUP_IND_REG 0 x1107#define RTL8365MB_PORT_LINKUP_IND_MASK 0 x07FF/* PHY indirect access registers */ #define RTL8365MB_INDIRECT_ACCESS_CTRL_REG 0 x1F00#define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK 0 x0002#define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ 0 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE 1 #define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK 0 x0001#define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE 1 #define RTL8365MB_INDIRECT_ACCESS_STATUS_REG 0 x1F01#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG 0 x1F02#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK GENMASK(4 , 0 )#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK GENMASK(7 , 5 )#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK GENMASK(11 , 8 )#define RTL8365MB_PHY_BASE 0 x2000#define RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG 0 x1F03#define RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG 0 x1F04/* PHY OCP address prefix register */ #define RTL8365MB_GPHY_OCP_MSB_0_REG 0 x1D15#define RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK 0 x0FC0#define RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK 0 xFC00/* The PHY OCP addresses of PHY registers 0~31 start here */ #define RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE 0 xA400/* External interface port mode values - used in DIGITAL_INTERFACE_SELECT */ #define RTL8365MB_EXT_PORT_MODE_DISABLE 0 #define RTL8365MB_EXT_PORT_MODE_RGMII 1 #define RTL8365MB_EXT_PORT_MODE_MII_MAC 2 #define RTL8365MB_EXT_PORT_MODE_MII_PHY 3 #define RTL8365MB_EXT_PORT_MODE_TMII_MAC 4 #define RTL8365MB_EXT_PORT_MODE_TMII_PHY 5 #define RTL8365MB_EXT_PORT_MODE_GMII 6 #define RTL8365MB_EXT_PORT_MODE_RMII_MAC 7 #define RTL8365MB_EXT_PORT_MODE_RMII_PHY 8 #define RTL8365MB_EXT_PORT_MODE_SGMII 9 #define RTL8365MB_EXT_PORT_MODE_HSGMII 10 #define RTL8365MB_EXT_PORT_MODE_1000X_100FX 11 #define RTL8365MB_EXT_PORT_MODE_1000X 12 #define RTL8365MB_EXT_PORT_MODE_100FX 13 /* External interface mode configuration registers 0~1 */ #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 0 x1305 /* EXT0,EXT1 */ #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 0 x13C3 /* EXT2 */ #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(_extint) \1 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 : \2 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 : \0 x0)#define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(_extint) \0 xF << (((_extint) % 2 )))#define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extint) \2 ) * 4 )/* External interface RGMII TX/RX delay configuration registers 0~2 */ #define RTL8365MB_EXT_RGMXF_REG0 0 x1306 /* EXT0 */ #define RTL8365MB_EXT_RGMXF_REG1 0 x1307 /* EXT1 */ #define RTL8365MB_EXT_RGMXF_REG2 0 x13C5 /* EXT2 */ #define RTL8365MB_EXT_RGMXF_REG(_extint) \0 ? RTL8365MB_EXT_RGMXF_REG0 : \1 ? RTL8365MB_EXT_RGMXF_REG1 : \2 ? RTL8365MB_EXT_RGMXF_REG2 : \0 x0)#define RTL8365MB_EXT_RGMXF_RXDELAY_MASK 0 x0007#define RTL8365MB_EXT_RGMXF_TXDELAY_MASK 0 x0008/* External interface port speed values - used in DIGITAL_INTERFACE_FORCE */ #define RTL8365MB_PORT_SPEED_10M 0 #define RTL8365MB_PORT_SPEED_100M 1 #define RTL8365MB_PORT_SPEED_1000M 2 /* External interface force configuration registers 0~2 */ #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 0 x1310 /* EXT0 */ #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 0 x1311 /* EXT1 */ #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 0 x13C4 /* EXT2 */ #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(_extint) \0 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 : \1 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 : \2 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 : \0 x0)#define RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK 0 x1000#define RTL8365MB_DIGITAL_INTERFACE_FORCE_NWAY_MASK 0 x0080#define RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK 0 x0040#define RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK 0 x0020#define RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK 0 x0010#define RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK 0 x0004#define RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK 0 x0003/* CPU port mask register - controls which ports are treated as CPU ports */ #define RTL8365MB_CPU_PORT_MASK_REG 0 x1219#define RTL8365MB_CPU_PORT_MASK_MASK 0 x07FF/* CPU control register */ #define RTL8365MB_CPU_CTRL_REG 0 x121A#define RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK 0 x0400#define RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK 0 x0200#define RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK 0 x0080#define RTL8365MB_CPU_CTRL_TAG_POSITION_MASK 0 x0040#define RTL8365MB_CPU_CTRL_TRAP_PORT_MASK 0 x0038#define RTL8365MB_CPU_CTRL_INSERTMODE_MASK 0 x0006#define RTL8365MB_CPU_CTRL_EN_MASK 0 x0001/* Maximum packet length register */ #define RTL8365MB_CFG0_MAX_LEN_REG 0 x088C#define RTL8365MB_CFG0_MAX_LEN_MASK 0 x3FFF#define RTL8365MB_CFG0_MAX_LEN_MAX 0 x3FFF/* Port learning limit registers */ #define RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE 0 x0A20#define RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(_physport) \/* Port isolation (forwarding mask) registers */ #define RTL8365MB_PORT_ISOLATION_REG_BASE 0 x08A2#define RTL8365MB_PORT_ISOLATION_REG(_physport) \#define RTL8365MB_PORT_ISOLATION_MASK 0 x07FF/* MSTP port state registers - indexed by tree instance */ #define RTL8365MB_MSTI_CTRL_BASE 0 x0A00#define RTL8365MB_MSTI_CTRL_REG(_msti, _physport) \1 ) + ((_physport) >> 3 ))#define RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(_physport) ((_physport) << 1 )#define RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(_physport) \0 x3 << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET((_physport)))/* MIB counter value registers */ #define RTL8365MB_MIB_COUNTER_BASE 0 x1000#define RTL8365MB_MIB_COUNTER_REG(_x) (RTL8365MB_MIB_COUNTER_BASE + (_x))/* MIB counter address register */ #define RTL8365MB_MIB_ADDRESS_REG 0 x1004#define RTL8365MB_MIB_ADDRESS_PORT_OFFSET 0 x007C#define RTL8365MB_MIB_ADDRESS(_p, _x) \2 )#define RTL8365MB_MIB_CTRL0_REG 0 x1005#define RTL8365MB_MIB_CTRL0_RESET_MASK 0 x0002#define RTL8365MB_MIB_CTRL0_BUSY_MASK 0 x0001/* The DSA callback .get_stats64 runs in atomic context, so we are not allowed * to block . On the other hand , accessing MIB counters absolutely requires us to * block . The solution is thus to schedule work which polls the MIB counters * asynchronously and updates some private data , which the callback can then * fetch atomically . Three seconds should be a good enough polling interval . #define RTL8365MB_STATS_INTERVAL_JIFFIES (3 * HZ)enum rtl8365mb_mib_counter_index {struct rtl8365mb_mib_counter {const char *name;#define RTL8365MB_MAKE_MIB_COUNTER(_offset, _length, _name) \## _name] = { _offset, _length, #_ name }static struct rtl8365mb_mib_counter rtl8365mb_mib_counters[] = {0 , 4 , ifInOctets),4 , 2 , dot3StatsFCSErrors),6 , 2 , dot3StatsSymbolErrors),8 , 2 , dot3InPauseFrames),10 , 2 , dot3ControlInUnknownOpcodes),12 , 2 , etherStatsFragments),14 , 2 , etherStatsJabbers),16 , 2 , ifInUcastPkts),18 , 2 , etherStatsDropEvents),20 , 2 , ifInMulticastPkts),22 , 2 , ifInBroadcastPkts),24 , 2 , inMldChecksumError),26 , 2 , inIgmpChecksumError),28 , 2 , inMldSpecificQuery),30 , 2 , inMldGeneralQuery),32 , 2 , inIgmpSpecificQuery),34 , 2 , inIgmpGeneralQuery),36 , 2 , inMldLeaves),38 , 2 , inIgmpLeaves),40 , 4 , etherStatsOctets),44 , 2 , etherStatsUnderSizePkts),46 , 2 , etherOversizeStats),48 , 2 , etherStatsPkts64Octets),50 , 2 , etherStatsPkts65to127Octets),52 , 2 , etherStatsPkts128to255Octets),54 , 2 , etherStatsPkts256to511Octets),56 , 2 , etherStatsPkts512to1023Octets),58 , 2 , etherStatsPkts1024to1518Octets),60 , 4 , ifOutOctets),64 , 2 , dot3StatsSingleCollisionFrames),66 , 2 , dot3StatsMultipleCollisionFrames),68 , 2 , dot3StatsDeferredTransmissions),70 , 2 , dot3StatsLateCollisions),72 , 2 , etherStatsCollisions),74 , 2 , dot3StatsExcessiveCollisions),76 , 2 , dot3OutPauseFrames),78 , 2 , ifOutDiscards),80 , 2 , dot1dTpPortInDiscards),82 , 2 , ifOutUcastPkts),84 , 2 , ifOutMulticastPkts),86 , 2 , ifOutBroadcastPkts),88 , 2 , outOampduPkts),90 , 2 , inOampduPkts),92 , 4 , inIgmpJoinsSuccess),96 , 2 , inIgmpJoinsFail),98 , 2 , inMldJoinsSuccess),100 , 2 , inMldJoinsFail),102 , 2 , inReportSuppressionDrop),104 , 2 , inLeaveSuppressionDrop),106 , 2 , outIgmpReports),108 , 2 , outIgmpLeaves),110 , 2 , outIgmpGeneralQuery),112 , 2 , outIgmpSpecificQuery),114 , 2 , outMldReports),116 , 2 , outMldLeaves),118 , 2 , outMldGeneralQuery),120 , 2 , outMldSpecificQuery),122 , 2 , inKnownMulticastPkts),struct rtl8365mb_jam_tbl_entry {/* Lifted from the vendor driver sources */ static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_8365mb_vc[] = {0 x13EB, 0 x15BB }, { 0 x1303, 0 x06D6 }, { 0 x1304, 0 x0700 },0 x13E2, 0 x003F }, { 0 x13F9, 0 x0090 }, { 0 x121E, 0 x03CA },0 x1233, 0 x0352 }, { 0 x1237, 0 x00A0 }, { 0 x123A, 0 x0030 },0 x1239, 0 x0084 }, { 0 x0301, 0 x1000 }, { 0 x1349, 0 x001F },0 x18E0, 0 x4004 }, { 0 x122B, 0 x241C }, { 0 x1305, 0 xC000 },0 x13F0, 0 x0000 },static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_common[] = {0 x1200, 0 x7FCB }, { 0 x0884, 0 x0003 }, { 0 x06EB, 0 x0001 },0 x03Fa, 0 x0007 }, { 0 x08C8, 0 x00C0 }, { 0 x0A30, 0 x020E },0 x0800, 0 x0000 }, { 0 x0802, 0 x0000 }, { 0 x09DA, 0 x0013 },0 x1D32, 0 x0002 },enum rtl8365mb_phy_interface_mode {0 ,0 ),1 ),2 ),3 ),4 ),5 ),6 ),/** * struct rtl8365mb_extint - external interface info * @ port : the port with an external interface * @ id : the external interface ID , which is either 0 , 1 , or 2 * @ supported_interfaces : a bitmask of supported PHY interface modes * * Represents a mapping : port - > { id , supported_interfaces } . To be embedded * in & struct rtl8365mb_chip_info for every port with an external interface . struct rtl8365mb_extint {int port;int id;unsigned int supported_interfaces;/** * struct rtl8365mb_chip_info - static chip - specific info * @ name : human - readable chip name * @ chip_id : chip identifier * @ chip_ver : chip silicon revision * @ extints : available external interfaces * @ jam_table : chip - specific initialization jam table * @ jam_size : size of the chip ' s jam table * * These data are specific to a given chip in the family of switches supported * by this driver . When adding support for another chip in the family , a new * chip info should be added to the rtl8365mb_chip_infos array . struct rtl8365mb_chip_info {const char *name;const struct rtl8365mb_extint extints[RTL8365MB_MAX_NUM_EXTINTS];const struct rtl8365mb_jam_tbl_entry *jam_table;/* Chip info for each supported switch in the family */ #define PHY_INTF(_mode) (RTL8365MB_PHY_INTERFACE_MODE_ ## _mode)static const struct rtl8365mb_chip_info rtl8365mb_chip_infos[] = {"RTL8365MB-VC" ,0 x6367,0 x0040,6 , 1 , PHY_INTF(MII) | PHY_INTF(TMII) |"RTL8367S" ,0 x6367,0 x00A0,6 , 1 , PHY_INTF(SGMII) | PHY_INTF(HSGMII) },7 , 2 , PHY_INTF(MII) | PHY_INTF(TMII) |"RTL8367RB-VB" ,0 x6367,0 x0020,6 , 1 , PHY_INTF(MII) | PHY_INTF(TMII) |7 , 2 , PHY_INTF(MII) | PHY_INTF(TMII) |enum rtl8365mb_stp_state {0 ,1 ,2 ,3 ,enum rtl8365mb_cpu_insert {0 ,1 ,2 ,enum rtl8365mb_cpu_position {0 ,1 ,enum rtl8365mb_cpu_format {0 ,1 ,enum rtl8365mb_cpu_rxlen {0 ,1 ,/** * struct rtl8365mb_cpu - CPU port configuration * @ enable : enable / disable hardware insertion of CPU tag in switch - > CPU frames * @ mask : port mask of ports that parse should parse CPU tags * @ trap_port : forward trapped frames to this port * @ insert : CPU tag insertion mode in switch - > CPU frames * @ position : position of CPU tag in frame * @ rx_length : minimum CPU RX length * @ format : CPU tag format * * Represents the CPU tagging and CPU port configuration of the switch . These * settings are configurable at runtime . struct rtl8365mb_cpu {bool enable;enum rtl8365mb_cpu_insert insert;enum rtl8365mb_cpu_position position;enum rtl8365mb_cpu_rxlen rx_length;enum rtl8365mb_cpu_format format;/** * struct rtl8365mb_port - private per - port data * @ priv : pointer to parent realtek_priv data * @ index : DSA port index , same as dsa_port : : index * @ stats : link statistics populated by rtl8365mb_stats_poll , ready for atomic * access via rtl8365mb_get_stats64 * @ stats_lock : protect the stats structure during read / update * @ mib_work : delayed work for polling MIB counters struct rtl8365mb_port {struct realtek_priv *priv;unsigned int index;struct rtnl_link_stats64 stats;struct delayed_work mib_work;/** * struct rtl8365mb - driver private data * @ priv : pointer to parent realtek_priv data * @ irq : registered IRQ or zero * @ chip_info : chip - specific info about the attached switch * @ cpu : CPU tagging and CPU port configuration for this chip * @ mib_lock : prevent concurrent reads of MIB counters * @ ports : per - port data * * Private data for this driver . struct rtl8365mb {struct realtek_priv *priv;int irq;const struct rtl8365mb_chip_info *chip_info;struct rtl8365mb_cpu cpu;struct mutex mib_lock;struct rtl8365mb_port ports[RTL8365MB_MAX_NUM_PORTS];static int rtl8365mb_phy_poll_busy(struct realtek_priv *priv)return regmap_read_poll_timeout(priv->map_nolock,10 , 100 );static int rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy,int ret;/* Set OCP prefix */ if (ret)return ret;/* Set PHY register address */ 1 );6 );if (ret)return ret;return 0 ;static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy,int ret;if (ret)goto out;if (ret)goto out;/* Execute read operation */ if (ret)goto out;if (ret)goto out;/* Get PHY register data */ if (ret)goto out;0 xFFFF;return ret;static int rtl8365mb_phy_ocp_write(struct realtek_priv *priv, int phy,int ret;if (ret)goto out;if (ret)goto out;/* Set PHY register data */ if (ret)goto out;/* Execute write operation */ if (ret)goto out;if (ret)goto out;return 0 ;static int rtl8365mb_phy_read(struct realtek_priv *priv, int phy, int regnum)int ret;if (phy > RTL8365MB_PHYADDRMAX)return -EINVAL;if (regnum > RTL8365MB_PHYREGMAX)return -EINVAL;2 ;if (ret) {"failed to read PHY%d reg %02x @ %04x, ret %d\n" , phy,return ret;"read PHY%d register 0x%02x @ %04x, val <- %04x\n" ,return val;static int rtl8365mb_phy_write(struct realtek_priv *priv, int phy, int regnum,int ret;if (phy > RTL8365MB_PHYADDRMAX)return -EINVAL;if (regnum > RTL8365MB_PHYREGMAX)return -EINVAL;2 ;if (ret) {"failed to write PHY%d reg %02x @ %04x, ret %d\n" , phy,return ret;"write PHY%d register 0x%02x @ %04x, val -> %04x\n" ,return 0 ;static const struct rtl8365mb_extint *struct realtek_priv *priv, int port)struct rtl8365mb *mb = priv->chip_data;int i;for (i = 0 ; i < RTL8365MB_MAX_NUM_EXTINTS; i++) {const struct rtl8365mb_extint *extint =if (!extint->supported_interfaces)continue ;if (extint->port == port)return extint;return NULL;static enum dsa_tag_protocolstruct dsa_switch *ds, int port,enum dsa_tag_protocol mp)struct realtek_priv *priv = ds->priv;struct rtl8365mb_cpu *cpu;struct rtl8365mb *mb;if (cpu->position == RTL8365MB_CPU_POS_BEFORE_CRC)return DSA_TAG_PROTO_RTL8_4T;return DSA_TAG_PROTO_RTL8_4;static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port,const struct rtl8365mb_extint *extint =struct dsa_switch *ds = &priv->ds;struct device_node *dn;struct dsa_port *dp;int tx_delay = 0 ;int rx_delay = 0 ;int ret;if (!extint)return -ENODEV;/* Set the RGMII TX/RX delay * * The Realtek vendor driver indicates the following possible * configuration settings : * * TX delay : * 0 = no delay , 1 = 2 ns delay * RX delay : * 0 = no delay , 7 = maximum delay * Each step is approximately 0 . 3 ns , so the maximum delay is about * 2 . 1 ns . * * The vendor driver also states that this must be configured * before * * forcing the external interface into a particular mode , which is done * in the rtl8365mb_phylink_mac_link_ { up , down } functions . * * Only configure an RGMII TX ( resp . RX ) delay if the * tx - internal - delay - ps ( resp . rx - internal - delay - ps ) OF property is * specified . We ignore the detail of the RGMII interface mode * ( RGMII_ { RXID , TXID , etc . } ) , as this is considered to be a PHY - only * property . if (!of_property_read_u32(dn, "tx-internal-delay-ps" , &val)) {1000 ; /* convert to ns */ if (val == 0 || val == 2 )2 ;else "RGMII TX delay must be 0 or 2 ns\n" );if (!of_property_read_u32(dn, "rx-internal-delay-ps" , &val)) {300 ); /* convert to 0.3 ns step */ if (val <= 7 )else "RGMII RX delay must be 0 to 2.1 ns\n" );if (ret)return ret;if (ret)return ret;return 0 ;static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port,bool link, int speed, int duplex,bool tx_pause, bool rx_pause)const struct rtl8365mb_extint *extint =int val;int ret;if (!extint)return -ENODEV;if (link) {/* Force the link up with the desired configuration */ 1 ;1 : 0 ;1 : 0 ;if (speed == SPEED_1000) {else if (speed == SPEED_100) {else if (speed == SPEED_10) {else {"unsupported port speed %s\n" ,return -EINVAL;if (duplex == DUPLEX_FULL) {1 ;else if (duplex == DUPLEX_HALF) {0 ;else {"unsupported duplex %s\n" ,return -EINVAL;else {/* Force the link down and reset any programmed configuration */ 0 ;0 ;0 ;0 ;0 ;1 ) |if (ret)return ret;return 0 ;static void rtl8365mb_phylink_get_caps(struct dsa_switch *ds, int port,struct phylink_config *config)const struct rtl8365mb_extint *extint =if (!extint) {/* GMII is the default interface mode for phylib, so * we have to support it for ports with integrated PHY . return ;/* Populate according to the modes supported by _this driver_, * not necessarily the modes supported by the hardware , some of * which remain unimplemented . if (extint->supported_interfaces & RTL8365MB_PHY_INTERFACE_MODE_RGMII)static void rtl8365mb_phylink_mac_config(struct phylink_config *config,unsigned int mode,const struct phylink_link_state *state)struct dsa_port *dp = dsa_phylink_to_port(config);struct realtek_priv *priv = dp->ds->priv;int ret;if (mode != MLO_AN_PHY && mode != MLO_AN_FIXED) {"port %d supports only conventional PHY or fixed-link\n" ,return ;if (phy_interface_mode_is_rgmii(state->interface)) {if (ret)"failed to configure RGMII mode on port %d: %d\n" ,return ;/* TODO: Implement MII and RMII modes, which the RTL8365MB-VC also * supports static void rtl8365mb_phylink_mac_link_down(struct phylink_config *config,unsigned int mode,struct dsa_port *dp = dsa_phylink_to_port(config);struct realtek_priv *priv = dp->ds->priv;struct rtl8365mb_port *p;struct rtl8365mb *mb;int ret;if (phy_interface_mode_is_rgmii(interface)) {false , 0 , 0 ,false , false );if (ret)"failed to reset forced mode on port %d: %d\n" ,return ;static void rtl8365mb_phylink_mac_link_up(struct phylink_config *config,struct phy_device *phydev,unsigned int mode,int speed, int duplex, bool tx_pause,bool rx_pause)struct dsa_port *dp = dsa_phylink_to_port(config);struct realtek_priv *priv = dp->ds->priv;struct rtl8365mb_port *p;struct rtl8365mb *mb;int ret;0 );if (phy_interface_mode_is_rgmii(interface)) {true , speed,if (ret)"failed to force mode on port %d: %d\n" , port,return ;static int rtl8365mb_port_change_mtu(struct dsa_switch *ds, int port,int new_mtu)struct realtek_priv *priv = ds->priv;int frame_size;/* When a new MTU is set, DSA always sets the CPU port's MTU to the * largest MTU of the user ports . Because the switch only has a global * RX length register , only allowing CPU port here is enough . if (!dsa_is_cpu_port(ds, port))return 0 ;"changing mtu to %d (frame size: %d)\n" ,return regmap_update_bits(priv->map, RTL8365MB_CFG0_MAX_LEN_REG,static int rtl8365mb_port_max_mtu(struct dsa_switch *ds, int port)return RTL8365MB_CFG0_MAX_LEN_MAX - VLAN_ETH_HLEN - ETH_FCS_LEN;static void rtl8365mb_port_stp_state_set(struct dsa_switch *ds, int port,struct realtek_priv *priv = ds->priv;enum rtl8365mb_stp_state val;int msti = 0 ;switch (state) {case BR_STATE_DISABLED:break ;case BR_STATE_BLOCKING:case BR_STATE_LISTENING:break ;case BR_STATE_LEARNING:break ;case BR_STATE_FORWARDING:break ;default :"invalid STP state: %u\n" , state);return ;static int rtl8365mb_port_set_learning(struct realtek_priv *priv, int port,bool enable)/* Enable/disable learning by limiting the number of L2 addresses the * port can learn . Realtek documentation states that a limit of zero * disables learning . When enabling learning , set it to the chip ' s * maximum . return regmap_write(priv->map, RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(port),0 );static int rtl8365mb_port_set_isolation(struct realtek_priv *priv, int port,return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), mask);static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port,0 ;int ret;int i;/* The MIB address is an SRAM address. We request a particular address * and then poll the control register before reading the value from some * counter registers . if (ret)return ret;/* Poll for completion */ 10 , 100 );if (ret)return ret;/* Presumably this indicates a MIB counter read failure */ if (val & RTL8365MB_MIB_CTRL0_RESET_MASK)return -EIO;/* There are four MIB counter registers each holding a 16 bit word of a * MIB counter . Depending on the offset , we should read from the upper * two or lower two registers . In case the MIB counter is 4 words , we * read from all four registers . if (length == 4 )3 ;else 1 ) % 4 ;/* Read the MIB counter 16 bits at a time */ for (i = 0 ; i < length; i++) {if (ret)return ret;16 ) | (val & 0 xFFFF);/* Only commit the result if no error occurred */ return 0 ;static void rtl8365mb_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data)struct realtek_priv *priv = ds->priv;struct rtl8365mb *mb;int ret;int i;for (i = 0 ; i < RTL8365MB_MIB_END; i++) {struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i];if (ret) {"failed to read port %d counters: %d\n" , port,break ;static void rtl8365mb_get_strings(struct dsa_switch *ds, int port, u32 stringset, u8 *data)int i;if (stringset != ETH_SS_STATS)return ;for (i = 0 ; i < RTL8365MB_MIB_END; i++) {struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i];static int rtl8365mb_get_sset_count(struct dsa_switch *ds, int port, int sset)if (sset != ETH_SS_STATS)return -EOPNOTSUPP;return RTL8365MB_MIB_END;static void rtl8365mb_get_phy_stats(struct dsa_switch *ds, int port,struct ethtool_eth_phy_stats *phy_stats)struct realtek_priv *priv = ds->priv;struct rtl8365mb_mib_counter *mib;struct rtl8365mb *mb;static void rtl8365mb_get_mac_stats(struct dsa_switch *ds, int port,struct ethtool_eth_mac_stats *mac_stats)1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,struct realtek_priv *priv = ds->priv;struct rtl8365mb *mb;int ret;int i;for (i = 0 ; i < RTL8365MB_MIB_END; i++) {struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i];/* Only fetch required MIB counters (marked = 1 above) */ if (!cnt[i])continue ;if (ret)break ;/* The RTL8365MB-VC exposes MIB objects, which we have to translate into * IEEE 802 . 3 Managed Objects . This is not always completely faithful , * but we try out best . See RFC 3635 for a detailed treatment of the * subject . 18 * mac_stats->FramesTransmittedOK;18 * mac_stats->FramesReceivedOK;static void rtl8365mb_get_ctrl_stats(struct dsa_switch *ds, int port,struct ethtool_eth_ctrl_stats *ctrl_stats)struct realtek_priv *priv = ds->priv;struct rtl8365mb_mib_counter *mib;struct rtl8365mb *mb;static void rtl8365mb_stats_update(struct realtek_priv *priv, int port)1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,1 ,struct rtl8365mb *mb = priv->chip_data;struct rtnl_link_stats64 *stats;int ret;int i;for (i = 0 ; i < RTL8365MB_MIB_END; i++) {struct rtl8365mb_mib_counter *c = &rtl8365mb_mib_counters[i];/* Only fetch required MIB counters (marked = 1 above) */ if (!cnt[i])continue ;if (ret)break ;/* Don't update statistics if there was an error reading the counters */ if (ret)return ;/* if{In,Out}Octets includes FCS - remove it */ 4 * stats->rx_packets;4 * stats->tx_packets;static void rtl8365mb_stats_poll(struct work_struct *work)struct rtl8365mb_port *p = container_of(to_delayed_work(work),struct rtl8365mb_port,struct realtek_priv *priv = p->priv;static void rtl8365mb_get_stats64(struct dsa_switch *ds, int port,struct rtnl_link_stats64 *s)struct realtek_priv *priv = ds->priv;struct rtl8365mb_port *p;struct rtl8365mb *mb;sizeof (*s));static void rtl8365mb_stats_setup(struct realtek_priv *priv)struct rtl8365mb *mb = priv->chip_data;struct dsa_switch *ds = &priv->ds;int i;/* Per-chip global mutex to protect MIB counter access, since doing * so requires accessing a series of registers in a particular order . for (i = 0 ; i < priv->num_ports; i++) {struct rtl8365mb_port *p = &mb->ports[i];if (dsa_is_unused_port(ds, i))continue ;/* Per-port spinlock to protect the stats64 data */ /* This work polls the MIB counters and keeps the stats64 data * up - to - date . static void rtl8365mb_stats_teardown(struct realtek_priv *priv)struct rtl8365mb *mb = priv->chip_data;struct dsa_switch *ds = &priv->ds;int i;for (i = 0 ; i < priv->num_ports; i++) {struct rtl8365mb_port *p = &mb->ports[i];if (dsa_is_unused_port(ds, i))continue ;static int rtl8365mb_get_and_clear_status_reg(struct realtek_priv *priv, u32 reg,int ret;if (ret)return ret;return regmap_write(priv->map, reg, *val);static irqreturn_t rtl8365mb_irq(int irq, void *data)struct realtek_priv *priv = data;unsigned long line_changes = 0 ;int line;int ret;if (ret)goto out_error;if (stat & RTL8365MB_INTR_LINK_CHANGE_MASK) {if (ret)goto out_error;if (ret)goto out_error;if (!line_changes)goto out_none;int child_irq = irq_find_mapping(priv->irqdomain, line);return IRQ_HANDLED;"failed to read interrupt status: %d\n" , ret);return IRQ_NONE;static struct irq_chip rtl8365mb_irq_chip = {"rtl8365mb" ,/* The hardware doesn't support masking IRQs on a per-port basis */ static int rtl8365mb_irq_map(struct irq_domain *domain, unsigned int irq,1 );return 0 ;static void rtl8365mb_irq_unmap(struct irq_domain *d, unsigned int irq)0 );static const struct irq_domain_ops rtl8365mb_irqdomain_ops = {static int rtl8365mb_set_irq_enable(struct realtek_priv *priv, bool enable)return regmap_update_bits(priv->map, RTL8365MB_INTR_CTRL_REG,1 : 0 ));static int rtl8365mb_irq_enable(struct realtek_priv *priv)return rtl8365mb_set_irq_enable(priv, true );static int rtl8365mb_irq_disable(struct realtek_priv *priv)return rtl8365mb_set_irq_enable(priv, false );static int rtl8365mb_irq_setup(struct realtek_priv *priv)struct rtl8365mb *mb = priv->chip_data;struct device_node *intc;int virq;int irq;int ret;int i;"interrupt-controller" );if (!intc) {"missing child interrupt-controller node\n" );return -EINVAL;/* rtl8365mb IRQs cascade off this one */ 0 );if (irq <= 0 ) {if (irq != -EPROBE_DEFER)"failed to get parent irq: %d\n" ,goto out_put_node;if (!priv->irqdomain) {"failed to add irq domain\n" );goto out_put_node;for (i = 0 ; i < priv->num_ports; i++) {if (!virq) {"failed to create irq domain mapping\n" );goto out_remove_irqdomain;/* Configure chip interrupt signal polarity */ switch (irq_trig) {case IRQF_TRIGGER_RISING:case IRQF_TRIGGER_HIGH:break ;case IRQF_TRIGGER_FALLING:case IRQF_TRIGGER_LOW:break ;default :"unsupported irq trigger type %u\n" ,goto out_remove_irqdomain;if (ret)goto out_remove_irqdomain;/* Disable the interrupt in case the chip has it enabled on reset */ if (ret)goto out_remove_irqdomain;/* Clear the interrupt status register */ if (ret)goto out_remove_irqdomain;"rtl8365mb" , priv);if (ret) {"failed to request irq: %d\n" , ret);goto out_remove_irqdomain;/* Store the irq so that we know to free it during teardown */ if (ret)goto out_free_irq;return 0 ;0 ;for (i = 0 ; i < priv->num_ports; i++) {return ret;static void rtl8365mb_irq_teardown(struct realtek_priv *priv)struct rtl8365mb *mb = priv->chip_data;int virq;int i;if (mb->irq) {0 ;if (priv->irqdomain) {for (i = 0 ; i < priv->num_ports; i++) {static int rtl8365mb_cpu_config(struct realtek_priv *priv)struct rtl8365mb *mb = priv->chip_data;struct rtl8365mb_cpu *cpu = &mb->cpu;int ret;if (ret)return ret;1 : 0 ) |0 x7) |3 & 0 x1);if (ret)return ret;return 0 ;static int rtl8365mb_change_tag_protocol(struct dsa_switch *ds,enum dsa_tag_protocol proto)struct realtek_priv *priv = ds->priv;struct rtl8365mb_cpu *cpu;struct rtl8365mb *mb;switch (proto) {case DSA_TAG_PROTO_RTL8_4:break ;case DSA_TAG_PROTO_RTL8_4T:break ;/* The switch also supports a 4-byte format, similar to rtl4a but with * the same 0 x04 8 - bit version and probably 8 - bit port source / dest . * There is no public doc about it . Not supported yet and it will probably * never be . default :return -EPROTONOSUPPORT;return rtl8365mb_cpu_config(priv);static int rtl8365mb_switch_init(struct realtek_priv *priv)struct rtl8365mb *mb = priv->chip_data;const struct rtl8365mb_chip_info *ci;int ret;int i;/* Do any chip-specific init jam before getting to the common stuff */ if (ci->jam_table) {for (i = 0 ; i < ci->jam_size; i++) {if (ret)return ret;/* Common init jam */ for (i = 0 ; i < ARRAY_SIZE(rtl8365mb_init_jam_common); i++) {if (ret)return ret;return 0 ;static int rtl8365mb_reset_chip(struct realtek_priv *priv)1 ));/* Realtek documentation says the chip needs 1 second to reset. Sleep * for 100 ms before accessing any registers to prevent ACK timeouts . 100 );return regmap_read_poll_timeout(priv->map, RTL8365MB_CHIP_RESET_REG, val,20000 , 1 e6);static int rtl8365mb_setup(struct dsa_switch *ds)struct realtek_priv *priv = ds->priv;struct rtl8365mb_cpu *cpu;struct dsa_port *cpu_dp;struct rtl8365mb *mb;int ret;int i;if (ret) {"failed to reset chip: %d\n" , ret);goto out_error;/* Configure switch to vendor-defined initial state */ if (ret) {"failed to initialize switch: %d\n" , ret);goto out_error;/* Set up cascading IRQs */ if (ret == -EPROBE_DEFER)return ret;else if (ret)"no interrupt support\n" );/* Configure CPU tagging */ if (cpu->trap_port == RTL8365MB_MAX_NUM_PORTS)0 ;if (ret)goto out_teardown_irq;/* Configure ports */ for (i = 0 ; i < priv->num_ports; i++) {struct rtl8365mb_port *p = &mb->ports[i];if (dsa_is_unused_port(ds, i))continue ;/* Forward only to the CPU */ if (ret)goto out_teardown_irq;/* Disable learning */ false );if (ret)goto out_teardown_irq;/* Set the initial STP state of all ports to DISABLED, otherwise * ports will still forward frames to the CPU despite being * administratively down by default . /* Set up per-port private data */ if (ret)goto out_teardown_irq;if (ret) {"could not set up MDIO bus\n" );goto out_teardown_irq;/* Start statistics counter polling */ return 0 ;return ret;static void rtl8365mb_teardown(struct dsa_switch *ds)struct realtek_priv *priv = ds->priv;static int rtl8365mb_get_chip_id_and_ver(struct regmap *map, u32 *id, u32 *ver)int ret;/* For some reason we have to write a magic value to an arbitrary * register whenever accessing the chip ID / version registers . if (ret)return ret;if (ret)return ret;if (ret)return ret;/* Reset magic register */ 0 );if (ret)return ret;return 0 ;static int rtl8365mb_detect(struct realtek_priv *priv)struct rtl8365mb *mb = priv->chip_data;int ret;int i;if (ret) {"failed to read chip id and version: %d\n" ,return ret;for (i = 0 ; i < ARRAY_SIZE(rtl8365mb_chip_infos); i++) {const struct rtl8365mb_chip_info *ci = &rtl8365mb_chip_infos[i];if (ci->chip_id == chip_id && ci->chip_ver == chip_ver) {break ;if (!mb->chip_info) {"unrecognized switch (id=0x%04x, ver=0x%04x)" , chip_id,return -ENODEV;"found an %s switch\n" , mb->chip_info->name);return 0 ;static const struct phylink_mac_ops rtl8365mb_phylink_mac_ops = {static const struct dsa_switch_ops rtl8365mb_switch_ops = {static const struct realtek_ops rtl8365mb_ops = {const struct realtek_variant rtl8365mb_variant = {10 ,0 xb9,0 xb8,sizeof (struct rtl8365mb),static const struct of_device_id rtl8365mb_of_match[] = {"realtek,rtl8365mb" , .data = &rtl8365mb_variant, },/* sentinel */ }, static struct platform_driver rtl8365mb_smi_driver = {"rtl8365mb-smi" ,static struct mdio_driver rtl8365mb_mdio_driver = {"rtl8365mb-mdio" ,static int rtl8365mb_init(void )int ret;if (ret)return ret;if (ret) {return ret;return 0 ;static void __exit rtl8365mb_exit(void )"Alvin Šipraga <alsi@bang-olufsen.dk>" );"Driver for RTL8365MB-VC ethernet switch" );"GPL" );"REALTEK_DSA" );
Messung V0.5 in Prozent C=96 H=88 G=91
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(vorverarbeitet am 2026-10-11)
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