/* bnx2x_main.c: QLogic Everest network driver. * * Copyright (c) 2007-2013 Broadcom Corporation * Copyright (c) 2014 QLogic Corporation * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation. * * Maintained by: Ariel Elior <ariel.elior@qlogic.com> * Written by: Eliezer Tamir * Based on code from Michael Chan's bnx2 driver * UDP CSUM errata workaround by Arik Gendelman * Slowpath and fastpath rework by Vladislav Zolotarov * Statistics and Link management by Yitchak Gertner *
*/
int bnx2x_num_queues;
module_param_named(num_queues, bnx2x_num_queues, int, 0444);
MODULE_PARM_DESC(num_queues, " Set number of queues (default is as a number of CPUs)");
/**************************************************************************** * General service functions
****************************************************************************/
for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
i, *(((u32 *)dmae) + i));
}
/* copy command into DMAE command memory and set DMAE command go */ void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
{
u32 cmd_offset; int i;
/* set the opcode */
dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, true, DMAE_COMP_PCI);
/* fill in the completion parameters */
dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
dmae->comp_val = DMAE_COMP_VAL;
}
/* issue a dmae command over the init-channel and wait for completion */ int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
u32 *comp)
{ int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; int rc = 0;
bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
/* Lock the dmae channel. Disable BHs to prevent a dead-lock * as long as this code is called both from syscall context and * from ndo_set_rx_mode() flow that may be called from BH.
*/
spin_lock_bh(&bp->dmae_lock);
/* reset completion */
*comp = 0;
/* post the command on the channel used for initializations */
bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
/* wait for completion */
udelay(5); while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
if (!bp->dmae_ready) {
u32 *data = bnx2x_sp(bp, wb_data[0]); int i;
if (CHIP_IS_E1(bp)) for (i = 0; i < len32; i++)
data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); else for (i = 0; i < len32; i++)
data[i] = REG_RD(bp, src_addr + i*4);
return;
}
/* set opcode and fixed command fields */
bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
/* fill in addresses and len */
dmae.src_addr_lo = src_addr >> 2;
dmae.src_addr_hi = 0;
dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
dmae.len = len32;
/* issue the command and wait for completion */
rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); if (rc) {
BNX2X_ERR("DMAE returned failure %d\n", rc); #ifdef BNX2X_STOP_ON_ERROR
bnx2x_panic(); #endif
}
}
staticvoid bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
u32 addr, u32 len)
{ int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); int offset = 0;
if (pci_channel_offline(bp->pdev)) {
BNX2X_ERR("Cannot dump MCP info while in PCI error\n"); return;
}
val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
BNX2X_ERR("%s""MCP PC at 0x%x\n", lvl, val);
staticvoid bnx2x_hc_int_disable(struct bnx2x *bp)
{ int port = BP_PORT(bp);
u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
u32 val = REG_RD(bp, addr);
/* in E1 we must use only PCI configuration space to disable * MSI/MSIX capability * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
*/ if (CHIP_IS_E1(bp)) { /* Since IGU_PF_CONF_MSI_MSIX_EN still always on * Use mask register to prevent from HC sending interrupts * after we exit the function
*/
REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
HC_CONFIG_0_REG_INT_LINE_EN_0 |
HC_CONFIG_0_REG_ATTN_BIT_EN_0);
} else
val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
HC_CONFIG_0_REG_INT_LINE_EN_0 |
HC_CONFIG_0_REG_ATTN_BIT_EN_0);
DP(NETIF_MSG_IFDOWN, "write %x to HC %d (addr 0x%x)\n",
val, port, addr);
REG_WR(bp, addr, val); if (REG_RD(bp, addr) != val)
BNX2X_ERR("BUG! Proper val not read from IGU!\n");
}
staticvoid bnx2x_igu_int_disable(struct bnx2x *bp)
{
u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
IGU_PF_CONF_INT_LINE_EN |
IGU_PF_CONF_ATTN_BIT_EN);
DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
BNX2X_ERR("BUG! Proper val not read from IGU!\n");
}
/* * FLR Support for E2 * * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW * initialization.
*/ #define FLR_WAIT_USEC 10000 /* 10 milliseconds */ #define FLR_WAIT_INTERVAL 50 /* usec */ #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
/* Verify the command queues are flushed P0, P1, P4 */ for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
/* Verify the transmission buffers are flushed P0, P1, P4 */ for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
}
/* Zero the igu 'trailing edge' and 'leading edge' */
/* Send the FW cleanup command */ if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) return -EBUSY;
/* ATC cleanup */
/* Verify TX hw is flushed */
bnx2x_tx_hw_flushed(bp, poll_cnt);
/* Wait 100ms (not adjusted according to platform) */
msleep(100);
/* Verify no pending pci transactions */ if (bnx2x_is_pcie_pending(bp->pdev))
BNX2X_ERR("PCIE Transactions still pending\n");
/* Debug */
bnx2x_hw_enable_status(bp);
/* * Master enable - Due to WB DMAE writes performed before this * register is re-initialized as part of the regular function init
*/
REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
if (msix) {
val &= ~(IGU_PF_CONF_INT_LINE_EN |
IGU_PF_CONF_SINGLE_ISR_EN);
val |= (IGU_PF_CONF_MSI_MSIX_EN |
IGU_PF_CONF_ATTN_BIT_EN);
if (single_msix)
val |= IGU_PF_CONF_SINGLE_ISR_EN;
} elseif (msi) {
val &= ~IGU_PF_CONF_INT_LINE_EN;
val |= (IGU_PF_CONF_MSI_MSIX_EN |
IGU_PF_CONF_ATTN_BIT_EN |
IGU_PF_CONF_SINGLE_ISR_EN);
} else {
val &= ~IGU_PF_CONF_MSI_MSIX_EN;
val |= (IGU_PF_CONF_INT_LINE_EN |
IGU_PF_CONF_ATTN_BIT_EN |
IGU_PF_CONF_SINGLE_ISR_EN);
}
/* Clean previous status - need to configure igu prior to ack*/ if ((!msix) || single_msix) {
REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
bnx2x_ack_int(bp);
}
void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
{ int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; int i, offset;
if (disable_hw) /* prevent the HW from sending interrupts */
bnx2x_int_disable(bp);
/* make sure all ISRs are done */ if (msix) {
synchronize_irq(bp->msix_table[0].vector);
offset = 1; if (CNIC_SUPPORT(bp))
offset++;
for_each_eth_queue(bp, i)
synchronize_irq(bp->msix_table[offset++].vector);
} else
synchronize_irq(bp->pdev->irq);
/* make sure sp_task is not running */
cancel_delayed_work(&bp->sp_task);
cancel_delayed_work(&bp->period_task);
flush_workqueue(bnx2x_wq);
}
/* fast path */
/* * General service functions
*/
/* Return true if succeeded to acquire the lock */ staticbool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
{
u32 lock_status;
u32 resource_bit = (1 << resource); int func = BP_FUNC(bp);
u32 hw_lock_control_reg;
DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Trying to take a lock on resource %d\n", resource);
/* Validating that the resource is within range */ if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
resource, HW_LOCK_MAX_RESOURCE_VALUE); returnfalse;
}
/* Try to acquire the lock */
REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
lock_status = REG_RD(bp, hw_lock_control_reg); if (lock_status & resource_bit) returntrue;
DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Failed to get a lock on resource %d\n", resource); returnfalse;
}
/** * bnx2x_get_leader_lock_resource - get the recovery leader resource id * * @bp: driver handle * * Returns the recovery leader resource id according to the engine this function * belongs to. Currently only 2 engines is supported.
*/ staticint bnx2x_get_leader_lock_resource(struct bnx2x *bp)
{ if (BP_PATH(bp)) return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; else return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
}
/** * bnx2x_trylock_leader_lock- try to acquire a leader lock. * * @bp: driver handle * * Tries to acquire a leader lock for current engine.
*/ staticbool bnx2x_trylock_leader_lock(struct bnx2x *bp)
{ return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
}
staticvoid bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
/* schedule the sp task and mark that interrupt occurred (runs from ISR) */ staticint bnx2x_schedule_sp_task(struct bnx2x *bp)
{ /* Set the interrupt occurred bit for the sp-task to recognize it * must ack the interrupt and transition according to the IGU * state machine.
*/
atomic_set(&bp->interrupt_occurred, 1);
/* The sp_task must execute only after this bit * is set, otherwise we will get out of sync and miss all * further interrupts. Hence, the barrier.
*/
smp_wmb();
DP(BNX2X_MSG_SP, "fp %d cid %d got ramrod #%d state is %x type is %d\n",
fp->index, cid, command, bp->state,
rr_cqe->ramrod_cqe.ramrod_type);
/* If cid is within VF range, replace the slowpath object with the * one corresponding to this VF
*/ if (cid >= BNX2X_FIRST_VF_CID &&
cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
default:
BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
command, fp->index); return;
}
if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
q_obj->complete_cmd(bp, q_obj, drv_cmd)) /* q_obj->complete_cmd() failure means that this was * an unexpected completion. * * In this case we don't want to increase the bp->spq_left * because apparently we haven't sent this command the first * place.
*/ #ifdef BNX2X_STOP_ON_ERROR
bnx2x_panic(); #else return; #endif
smp_mb__before_atomic();
atomic_inc(&bp->cq_spq_left); /* push the change in bp->spq_left and towards the memory */
smp_mb__after_atomic();
if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
(!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { /* if Q update ramrod is completed for last Q in AFEX vif set * flow, then ACK MCP at the end * * mark pending ACK to MCP bit. * prevent case that both bits are cleared. * At the end of load/unload driver checks that * sp_state is cleared, and this order prevents * races
*/
smp_mb__before_atomic();
set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
wmb();
clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
smp_mb__after_atomic();
/* schedule the sp task as mcp ack is required */
bnx2x_schedule_sp_task(bp);
}
/* Return here if interrupt is shared and it's not for us */ if (unlikely(status == 0)) {
DP(NETIF_MSG_INTR, "not our interrupt!\n"); return IRQ_NONE;
}
DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
#ifdef BNX2X_STOP_ON_ERROR if (unlikely(bp->panic)) return IRQ_HANDLED; #endif
/* schedule sp task to perform default status block work, ack * attentions and enable interrupts.
*/
bnx2x_schedule_sp_task(bp);
status &= ~0x1; if (!status) return IRQ_HANDLED;
}
if (unlikely(status))
DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
status);
return IRQ_HANDLED;
}
/* Link */
/* * General service functions
*/
int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
{
u32 lock_status;
u32 resource_bit = (1 << resource); int func = BP_FUNC(bp);
u32 hw_lock_control_reg; int cnt;
/* Validating that the resource is within range */ if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
resource, HW_LOCK_MAX_RESOURCE_VALUE); return -EINVAL;
}
/* Validating that the resource is not already taken */
lock_status = REG_RD(bp, hw_lock_control_reg); if (lock_status & resource_bit) {
BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
lock_status, resource_bit); return -EEXIST;
}
/* Try for 5 second every 5ms */ for (cnt = 0; cnt < 1000; cnt++) { /* Try to acquire the lock */
REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
lock_status = REG_RD(bp, hw_lock_control_reg); if (lock_status & resource_bit) return 0;
/* Validating that the resource is within range */ if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
resource, HW_LOCK_MAX_RESOURCE_VALUE); return -EINVAL;
}
/* Validating that the resource is currently taken */
lock_status = REG_RD(bp, hw_lock_control_reg); if (!(lock_status & resource_bit)) {
BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
lock_status, resource_bit); return -EFAULT;
}
int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
{ /* The GPIO should be swapped if swap register is set and active */ int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; int gpio_shift = gpio_num +
(gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
u32 gpio_mask = (1 << gpio_shift);
u32 gpio_reg; int value;
/* read GPIO value */
gpio_reg = REG_RD(bp, MISC_REG_GPIO);
/* get the requested pin value */ if ((gpio_reg & gpio_mask) == gpio_mask)
value = 1; else
value = 0;
return value;
}
int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
{ /* The GPIO should be swapped if swap register is set and active */ int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; int gpio_shift = gpio_num +
(gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
u32 gpio_mask = (1 << gpio_shift);
u32 gpio_reg;
int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
{ /* The GPIO should be swapped if swap register is set and active */ int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; int gpio_shift = gpio_num +
(gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
u32 gpio_mask = (1 << gpio_shift);
u32 gpio_reg;
case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; break;
default: break;
}
}
staticvoid bnx2x_set_requested_fc(struct bnx2x *bp)
{ /* Initialize link parameters structure variables * It is recommended to turn off RX FC for jumbo frames * for better performance
*/ if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; else
bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
}
if (!BP_NOMCP(bp)) {
bnx2x_acquire_phy_lock(bp);
rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
is_serdes);
bnx2x_release_phy_lock(bp);
} else
BNX2X_ERR("Bootcode is missing - can not test link\n");
return rc;
}
/* Calculates the sum of vn_min_rates. It's needed for further normalizing of the min_rates. Returns: sum of vn_min_rates. or 0 - if all the min_rates are 0. In the later case fairness algorithm should be deactivated. If not all min_rates are zero then those that are zeroes will be set to 1.
*/ staticvoid bnx2x_calc_vn_min(struct bnx2x *bp, struct cmng_init_input *input)
{ int all_zero = 1; int vn;
/* Skip hidden vns */ if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
vn_min_rate = 0; /* If min rate is zero - set it to 1 */ elseif (!vn_min_rate)
vn_min_rate = DEF_MIN_RATE; else
all_zero = 0;
input->vnic_min_rate[vn] = vn_min_rate;
}
/* if ETS or all min rates are zeros - disable fairness */ if (BNX2X_IS_ETS_ENABLED(bp)) {
input->flags.cmng_enables &=
~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
} elseif (all_zero) {
input->flags.cmng_enables &=
~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
DP(NETIF_MSG_IFUP, "All MIN values are zeroes fairness will be disabled\n");
} else
input->flags.cmng_enables |=
CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
}
staticint bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
{ if (CHIP_REV_IS_SLOW(bp)) return CMNG_FNS_NONE; if (IS_MF(bp)) return CMNG_FNS_MINMAX;
return CMNG_FNS_NONE;
}
void bnx2x_read_mf_cfg(struct bnx2x *bp)
{ int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
if (BP_NOMCP(bp)) return; /* what should be the default value in this case */
/* For 2 port configuration the absolute function number formula * is: * abs_func = 2 * vn + BP_PORT + BP_PATH * * and there are 4 functions per port * * For 4 port configuration it is * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH * * and there are 2 functions per port
*/ for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { int/*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
if (func >= E1H_FUNC_MAX) break;
bp->mf_config[vn] =
MF_CFG_RD(bp, func_mf_config[func].config);
} if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
bp->flags |= MF_FUNC_DIS;
} else {
DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
bp->flags &= ~MF_FUNC_DIS;
}
}
/* init cmng mode in HW according to local configuration */ void bnx2x_set_local_cmng(struct bnx2x *bp)
{ int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
if (cmng_fns != CMNG_FNS_NONE) {
bnx2x_cmng_fns_init(bp, false, cmng_fns);
storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
} else { /* rate shaping and fairness are disabled */
DP(NETIF_MSG_IFUP, "single function mode without fairness\n");
}
}
/* This function is called upon link interrupt */ staticvoid bnx2x_link_attn(struct bnx2x *bp)
{ /* Make sure that we are synced with the current statistics */
bnx2x_stats_handle(bp, STATS_EVENT_STOP);
/* if bulletin board did not have an update for link status * __bnx2x_link_report will report current status * but it will NOT duplicate report in case of already reported * during sampling bulletin board.
*/
bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
}
}
/* if ramrod can not be sent, response to MCP immediately */ if (bnx2x_func_state_change(bp, &func_params) < 0)
bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
/* validate only LIST_SET and LIST_GET are received from switch */ if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
cmd_type);
/* if ramrod can not be sent, respond to MCP immediately for * SET and GET requests (other are not triggered from MCP)
*/
rc = bnx2x_func_state_change(bp, &func_params); if (rc < 0)
bnx2x_fw_command(bp, drv_msg_code, 0);
/* write response to scratchpad, for MCP */ for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
REG_WR(bp, addr_to_write + i*sizeof(u32),
*(((u32 *)(&afex_stats))+i));
/* Prepare parameters for function state transitions */
__set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
__set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
if (IS_MF_UFP(bp) || IS_MF_BD(bp)) { int func = BP_ABS_FUNC(bp);
u32 val;
/* Re-learn the S-tag from shmem */
val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
FUNC_MF_CFG_E1HOV_TAG_MASK; if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
bp->mf_ov = val;
} else {
BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n"); goto fail;
}
/* Configure new S-tag in LLH */
REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
bp->mf_ov);
/* Send Ramrod to update FW of change */
__set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
&switch_update_params->changes);
switch_update_params->vlan = bp->mf_ov;
if (bnx2x_func_state_change(bp, &func_params) < 0) {
BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
bp->mf_ov); goto fail;
} else {
DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
bp->mf_ov);
}
} else { goto fail;
}
/** * bnx2x_get_common_flags - Return common flags * * @bp: device handle * @fp: queue handle * @zero_stats: TRUE if statistics zeroing is needed * * Return the flags that are common for the Tx-only and not normal connections.
*/ staticunsignedlong bnx2x_get_common_flags(struct bnx2x *bp, struct bnx2x_fastpath *fp, bool zero_stats)
{ unsignedlong flags = 0;
/* PF driver will always initialize the Queue to an ACTIVE state */
__set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
/* tx only connections collect statistics (on the same index as the * parent connection). The statistics are zeroed when the parent * connection is initialized.
*/
__set_bit(BNX2X_Q_FLG_STATS, &flags); if (zero_stats)
__set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
if (bp->flags & TX_SWITCHING)
__set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
/* calculate other queue flags */ if (IS_MF_SD(bp))
__set_bit(BNX2X_Q_FLG_OV, &flags);
if (IS_FCOE_FP(fp)) {
__set_bit(BNX2X_Q_FLG_FCOE, &flags); /* For FCoE - force usage of default priority (for afex) */
__set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
}
if (fp->mode != TPA_MODE_DISABLED) {
__set_bit(BNX2X_Q_FLG_TPA, &flags);
__set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); if (fp->mode == TPA_MODE_GRO)
__set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
}
if (leading) {
__set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
__set_bit(BNX2X_Q_FLG_MCAST, &flags);
}
/* Always set HW VLAN stripping */
__set_bit(BNX2X_Q_FLG_VLAN, &flags);
/* configure silent vlan removal */ if (IS_MF_AFEX(bp))
__set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
/* validate SGE ring has enough to cross high threshold */
WARN_ON(bp->dropless_fc &&
pause->sge_th_hi + FW_PREFETCH_CNT >
MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
/* This should be a maximum number of data bytes that may be * placed on the BD (not including paddings).
*/
rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
/* Maximum number or simultaneous TPA aggregation for this Queue. * * For PF Clients it should be the maximum available number. * VF driver(s) may want to define it to a smaller value.
*/
rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
/* * Congestion management values depend on the link rate * There is no active link so initial link rate is set to 10 Gbps. * When the link comes up The congestion management values are * re-calculated according to the actual link rate.
*/
bp->link_vars.line_speed = SPEED_10000;
bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
/* Only the PMF sets the HW */ if (bp->port.pmf)
storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
/* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the * mac_local field in ether_stat struct. The base address is offset by 2 * bytes to account for the field being 8 bytes but a mac address is * only 6 bytes. Likewise, the stride for the get_n_elements function is * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes * allocated by the ether_stat struct, so the macs will land in their * proper positions.
*/ for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
memset(ether_stat->mac_local + i, 0, sizeof(ether_stat->mac_local[0]));
mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
ether_stat->mac_local + MAC_PAD, MAC_PAD,
ETH_ALEN);
ether_stat->mtu_size = bp->dev->mtu; if (bp->dev->features & NETIF_F_RXCSUM)
ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; if (bp->dev->features & NETIF_F_TSO)
ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
ether_stat->feature_flags |= bp->common.boot_mode;
/* ask L5 driver to add data to the struct */
bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
}
/* called due to MCP event (on pmf): * reread new bandwidth configuration * configure FW * notify others function about the change
*/ staticvoid bnx2x_config_mf_bw(struct bnx2x *bp)
{ /* Workaround for MFW bug. * MFW is not supposed to generate BW attention in * single function mode.
*/ if (!IS_MF(bp)) {
DP(BNX2X_MSG_MCP, "Ignoring MF BW config in single function mode\n"); return;
}
/* if drv_info version supported by MFW doesn't match - send NACK */ if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); return;
}
switch (op_code) { case ETH_STATS_OPCODE:
bnx2x_drv_info_ether_stat(bp); break; case FCOE_STATS_OPCODE:
bnx2x_drv_info_fcoe_stat(bp); break; case ISCSI_STATS_OPCODE:
bnx2x_drv_info_iscsi_stat(bp); break; default: /* if op code isn't supported - send NACK */
bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); goto out;
}
/* if we got drv_info attn from MFW then these fields are defined in * shmem2 for sure
*/
SHMEM2_WR(bp, drv_info_host_addr_lo,
U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
SHMEM2_WR(bp, drv_info_host_addr_hi,
U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
/* Since possible management wants both this and get_driver_version * need to wait until management notifies us it finished utilizing * the buffer.
*/ if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
DP(BNX2X_MSG_MCP, "Management does not support indication\n");
} elseif (!bp->drv_info_mng_owner) {
u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
DRV_STATUS_OEM_DISABLE_ENABLE_PF)) { /* This is the only place besides the function initialization * where the bp->flags can change so it is done without any * locks
*/ if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
bp->flags |= MF_FUNC_DIS;
/* must be called under the spq lock */ staticvoid bnx2x_sp_prod_update(struct bnx2x *bp)
{ int func = BP_FUNC(bp);
/* * Make sure that BD data is updated before writing the producer: * BD data is written to the memory, the producer is read from the * memory, thus we need a full memory barrier to ensure the ordering.
*/
mb();
/** * bnx2x_is_contextless_ramrod - check if the current command ends on EQ * * @cmd: command to check * @cmd_type: command type
*/ staticbool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
{ if ((cmd_type == NONE_CONNECTION_TYPE) ||
(cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
(cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
(cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
(cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
(cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
(cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) returntrue; else returnfalse;
}
/** * bnx2x_sp_post - place a single command on an SP ring * * @bp: driver handle * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) * @cid: SW CID the command is related to * @data_hi: command private data address (high 32 bits) * @data_lo: command private data address (low 32 bits) * @cmd_type: command type (e.g. NONE, ETH) * * SP data is handled as if it's always an address pair, thus data fields are * not swapped to little endian in upper functions. Instead this function swaps * data as if it's two u32 fields.
*/ int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
u32 data_hi, u32 data_lo, int cmd_type)
{ struct eth_spe *spe;
u16 type; bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
#ifdef BNX2X_STOP_ON_ERROR if (unlikely(bp->panic)) {
BNX2X_ERR("Can't post SP when there is panic\n"); return -EIO;
} #endif
spin_lock_bh(&bp->spq_lock);
if (common) { if (!atomic_read(&bp->eq_spq_left)) {
BNX2X_ERR("BUG! EQ ring full!\n");
spin_unlock_bh(&bp->spq_lock);
bnx2x_panic(); return -EBUSY;
}
} elseif (!atomic_read(&bp->cq_spq_left)) {
BNX2X_ERR("BUG! SPQ ring full!\n");
spin_unlock_bh(&bp->spq_lock);
bnx2x_panic(); return -EBUSY;
}
spe = bnx2x_sp_get_next(bp);
/* CID needs port number to be encoded int it */
spe->hdr.conn_and_cmd_data =
cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
HW_CID(bp, cid));
/* In some cases, type may already contain the func-id * mainly in SRIOV related use cases, so we add it here only * if it's not already set.
*/ if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
SPE_HDR_CONN_TYPE;
type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
SPE_HDR_FUNCTION_ID);
} else {
type = cmd_type;
}
/* * It's ok if the actual decrement is issued towards the memory * somewhere between the spin_lock and spin_unlock. Thus no * more explicit memory barrier is needed.
*/ if (common)
atomic_dec(&bp->eq_spq_left); else
atomic_dec(&bp->cq_spq_left);
barrier(); /* status block is written to by the chip */ if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
rc |= BNX2X_DEF_SB_ATT_IDX;
}
/* now set back the mask */ if (asserted & ATTN_NIG_FOR_FUNC) { /* Verify that IGU ack through BAR was written before restoring * NIG mask. This loop should exit after 2-3 iterations max.
*/ if (bp->common.int_block != INT_BLOCK_HC) {
u32 cnt = 0, igu_acked; do {
igu_acked = REG_RD(bp,
IGU_REG_ATTENTION_ACK_BITS);
} while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
(++cnt < MAX_IGU_ATTN_ACK_TO)); if (!igu_acked)
DP(NETIF_MSG_HW, "Failed to verify IGU ack on time\n");
barrier();
}
REG_WR(bp, nig_int_mask_addr, nig_mask);
bnx2x_release_phy_lock(bp);
}
}
staticvoid bnx2x_fan_failure(struct bnx2x *bp)
{ int port = BP_PORT(bp);
u32 ext_phy_config; /* mark the failure */
ext_phy_config =
SHMEM_RD(bp,
dev_info.port_hw_config[port].external_phy_config);
/* log the failure */
netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" "Please contact OEM Support for assistance\n");
/* Schedule device reset (unload) * This is due to some boards consuming sufficient power when driver is * up to overheat if fan fails.
*/
bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
}
staticvoid bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
{ int port = BP_PORT(bp); int reg_offset;
u32 val;
/* * Bits map: * 0-7 - Engine0 load counter. * 8-15 - Engine1 load counter. * 16 - Engine0 RESET_IN_PROGRESS bit. * 17 - Engine1 RESET_IN_PROGRESS bit. * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function * on the engine * 19 - Engine1 ONE_IS_LOADED. * 20 - Chip reset flow bit. When set none-leader must wait for both engines * leader to complete (check for both RESET_IN_PROGRESS bits and not for * just the one belonging to its engine). *
*/ #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
/* * Set the GLOBAL_RESET bit. * * Should be run under rtnl lock
*/ void bnx2x_set_reset_global(struct bnx2x *bp)
{
u32 val;
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
}
/* * Clear the GLOBAL_RESET bit. * * Should be run under rtnl lock
*/ staticvoid bnx2x_clear_reset_global(struct bnx2x *bp)
{
u32 val;
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
}
/* * Checks the GLOBAL_RESET bit. * * should be run under rtnl lock
*/ staticbool bnx2x_reset_is_global(struct bnx2x *bp)
{
u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
/* * Clear RESET_IN_PROGRESS bit for the current engine. * * Should be run under rtnl lock
*/ staticvoid bnx2x_set_reset_done(struct bnx2x *bp)
{
u32 val;
u32 bit = BP_PATH(bp) ?
BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
/* Clear the bit */
val &= ~bit;
REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
/* * Set RESET_IN_PROGRESS for the current engine. * * should be run under rtnl lock
*/ void bnx2x_set_reset_in_progress(struct bnx2x *bp)
{
u32 val;
u32 bit = BP_PATH(bp) ?
BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
/* Set the bit */
val |= bit;
REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
}
/* * Checks the RESET_IN_PROGRESS bit for the given engine. * should be run under rtnl lock
*/ bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
{
u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
u32 bit = engine ?
BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
/* return false if bit is set */ return (val & bit) ? false : true;
}
/* * set pf load for the current pf. * * should be run under rtnl lock
*/ void bnx2x_set_pf_load(struct bnx2x *bp)
{
u32 val1, val;
u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
BNX2X_PATH0_LOAD_CNT_MASK;
u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
BNX2X_PATH0_LOAD_CNT_SHIFT;
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
/* * Read the load status for the current engine. * * should be run under rtnl lock
*/ staticbool bnx2x_get_load_status(struct bnx2x *bp, int engine)
{
u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
BNX2X_PATH0_LOAD_CNT_MASK);
u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
BNX2X_PATH0_LOAD_CNT_SHIFT);
u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
staticbool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig, int *par_num, bool print)
{
u32 cur_bit; bool res; int i;
res = false;
for (i = 0; sig; i++) {
cur_bit = (0x1UL << i); if (sig & cur_bit) {
res |= true; /* Each bit is real error! */
if (print) { switch (cur_bit) { case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
_print_next_block((*par_num)++, "BRB");
_print_parity(bp,
BRB1_REG_BRB1_PRTY_STS); break; case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
_print_next_block((*par_num)++, "PARSER");
_print_parity(bp, PRS_REG_PRS_PRTY_STS); break; case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
_print_next_block((*par_num)++, "TSDM");
_print_parity(bp,
TSDM_REG_TSDM_PRTY_STS); break; case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
_print_next_block((*par_num)++, "SEARCHER");
_print_parity(bp, SRC_REG_SRC_PRTY_STS); break; case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
_print_next_block((*par_num)++, "TCM");
_print_parity(bp, TCM_REG_TCM_PRTY_STS); break; case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
_print_next_block((*par_num)++, "TSEMI");
_print_parity(bp,
TSEM_REG_TSEM_PRTY_STS_0);
_print_parity(bp,
TSEM_REG_TSEM_PRTY_STS_1); break; case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
_print_next_block((*par_num)++, "XPB");
_print_parity(bp, GRCBASE_XPB +
PB_REG_PB_PRTY_STS); break;
}
}
/* Clear the bit */
sig &= ~cur_bit;
}
}
return res;
}
staticbool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig, int *par_num, bool *global, bool print)
{
u32 cur_bit; bool res; int i;
res = false;
for (i = 0; sig; i++) {
cur_bit = (0x1UL << i); if (sig & cur_bit) {
res |= true; /* Each bit is real error! */ switch (cur_bit) { case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: if (print) {
_print_next_block((*par_num)++, "PBF");
_print_parity(bp, PBF_REG_PBF_PRTY_STS);
} break; case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: if (print) {
_print_next_block((*par_num)++, "QM");
_print_parity(bp, QM_REG_QM_PRTY_STS);
} break; case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: if (print) {
_print_next_block((*par_num)++, "TM");
_print_parity(bp, TM_REG_TM_PRTY_STS);
} break; case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: if (print) {
_print_next_block((*par_num)++, "XSDM");
_print_parity(bp,
XSDM_REG_XSDM_PRTY_STS);
} break; case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: if (print) {
_print_next_block((*par_num)++, "XCM");
_print_parity(bp, XCM_REG_XCM_PRTY_STS);
} break; case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: if (print) {
_print_next_block((*par_num)++, "XSEMI");
_print_parity(bp,
XSEM_REG_XSEM_PRTY_STS_0);
_print_parity(bp,
XSEM_REG_XSEM_PRTY_STS_1);
} break; case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: if (print) {
_print_next_block((*par_num)++, "DOORBELLQ");
_print_parity(bp,
DORQ_REG_DORQ_PRTY_STS);
} break; case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: if (print) {
_print_next_block((*par_num)++, "NIG"); if (CHIP_IS_E1x(bp)) {
_print_parity(bp,
NIG_REG_NIG_PRTY_STS);
} else {
_print_parity(bp,
NIG_REG_NIG_PRTY_STS_0);
_print_parity(bp,
NIG_REG_NIG_PRTY_STS_1);
}
} break; case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: if (print)
_print_next_block((*par_num)++, "VAUX PCI CORE");
*global = true; break; case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: if (print) {
_print_next_block((*par_num)++, "DEBUG");
_print_parity(bp, DBG_REG_DBG_PRTY_STS);
} break; case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: if (print) {
_print_next_block((*par_num)++, "USDM");
_print_parity(bp,
USDM_REG_USDM_PRTY_STS);
} break; case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: if (print) {
_print_next_block((*par_num)++, "UCM");
_print_parity(bp, UCM_REG_UCM_PRTY_STS);
} break; case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: if (print) {
_print_next_block((*par_num)++, "USEMI");
_print_parity(bp,
USEM_REG_USEM_PRTY_STS_0);
_print_parity(bp,
USEM_REG_USEM_PRTY_STS_1);
} break; case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: if (print) {
_print_next_block((*par_num)++, "UPB");
_print_parity(bp, GRCBASE_UPB +
PB_REG_PB_PRTY_STS);
} break; case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: if (print) {
_print_next_block((*par_num)++, "CSDM");
_print_parity(bp,
CSDM_REG_CSDM_PRTY_STS);
} break; case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: if (print) {
_print_next_block((*par_num)++, "CCM");
_print_parity(bp, CCM_REG_CCM_PRTY_STS);
} break;
}
/* Clear the bit */
sig &= ~cur_bit;
}
}
return res;
}
staticbool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig, int *par_num, bool print)
{
u32 cur_bit; bool res; int i;
res = false;
for (i = 0; sig; i++) {
cur_bit = (0x1UL << i); if (sig & cur_bit) {
res = true; /* Each bit is real error! */ if (print) { switch (cur_bit) { case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
_print_next_block((*par_num)++, "CSEMI");
_print_parity(bp,
CSEM_REG_CSEM_PRTY_STS_0);
_print_parity(bp,
CSEM_REG_CSEM_PRTY_STS_1); break; case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
_print_next_block((*par_num)++, "PXP");
_print_parity(bp, PXP_REG_PXP_PRTY_STS);
_print_parity(bp,
PXP2_REG_PXP2_PRTY_STS_0);
_print_parity(bp,
PXP2_REG_PXP2_PRTY_STS_1); break; case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
_print_next_block((*par_num)++, "PXPPCICLOCKCLIENT"); break; case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
_print_next_block((*par_num)++, "CFC");
_print_parity(bp,
CFC_REG_CFC_PRTY_STS); break; case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
_print_next_block((*par_num)++, "CDU");
_print_parity(bp, CDU_REG_CDU_PRTY_STS); break; case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
_print_next_block((*par_num)++, "DMAE");
_print_parity(bp,
DMAE_REG_DMAE_PRTY_STS); break; case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
_print_next_block((*par_num)++, "IGU"); if (CHIP_IS_E1x(bp))
_print_parity(bp,
HC_REG_HC_PRTY_STS); else
_print_parity(bp,
IGU_REG_IGU_PRTY_STS); break; case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
_print_next_block((*par_num)++, "MISC");
_print_parity(bp,
MISC_REG_MISC_PRTY_STS); break;
}
}
/* Clear the bit */
sig &= ~cur_bit;
}
}
return res;
}
staticbool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig, int *par_num, bool *global, bool print)
{ bool res = false;
u32 cur_bit; int i;
for (i = 0; sig; i++) {
cur_bit = (0x1UL << i); if (sig & cur_bit) { switch (cur_bit) { case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: if (print)
_print_next_block((*par_num)++, "MCP ROM");
*global = true;
res = true; break; case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: if (print)
_print_next_block((*par_num)++, "MCP UMP RX");
*global = true;
res = true; break; case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: if (print)
_print_next_block((*par_num)++, "MCP UMP TX");
*global = true;
res = true; break; case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
(*par_num)++; /* clear latched SCPAD PATIRY from MCP */
REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
1UL << 10); break;
}
/* Clear the bit */
sig &= ~cur_bit;
}
}
return res;
}
staticbool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig, int *par_num, bool print)
{
u32 cur_bit; bool res; int i;
res = false;
for (i = 0; sig; i++) {
cur_bit = (0x1UL << i); if (sig & cur_bit) {
res = true; /* Each bit is real error! */ if (print) { switch (cur_bit) { case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
_print_next_block((*par_num)++, "PGLUE_B");
_print_parity(bp,
PGLUE_B_REG_PGLUE_B_PRTY_STS); break; case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
_print_next_block((*par_num)++, "ATC");
_print_parity(bp,
ATC_REG_ATC_PRTY_STS); break;
}
} /* Clear the bit */
sig &= ~cur_bit;
}
}
/** * bnx2x_chk_parity_attn - checks for parity attentions. * * @bp: driver handle * @global: true if there was a global attention * @print: show parity attention in syslog
*/ bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
{ struct attn_route attn = { {0} }; int port = BP_PORT(bp);
attn.sig[0] = REG_RD(bp,
MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
port*4);
attn.sig[1] = REG_RD(bp,
MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
port*4);
attn.sig[2] = REG_RD(bp,
MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
port*4);
attn.sig[3] = REG_RD(bp,
MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
port*4); /* Since MCP attentions can't be disabled inside the block, we need to * read AEU registers to see whether they're currently disabled
*/
attn.sig[3] &= ((REG_RD(bp,
!port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
: MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
MISC_AEU_ENABLE_MCP_PRTY_BITS) |
~MISC_AEU_ENABLE_MCP_PRTY_BITS);
if (!CHIP_IS_E1x(bp))
attn.sig[4] = REG_RD(bp,
MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
port*4);
staticvoid bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
{ struct attn_route attn, *group_mask; int port = BP_PORT(bp); int index;
u32 reg_addr;
u32 val;
u32 aeu_mask; bool global = false;
/* need to take HW lock because MCP or other port might also
try to handle this event */
bnx2x_acquire_alr(bp);
if (bnx2x_chk_parity_attn(bp, &global, true)) { #ifndef BNX2X_STOP_ON_ERROR
bp->recovery_state = BNX2X_RECOVERY_INIT;
schedule_delayed_work(&bp->sp_rtnl_task, 0); /* Disable HW interrupts */
bnx2x_int_disable(bp); /* In case of parity errors don't handle attentions so that * other function would "see" parity errors.
*/ #else
bnx2x_panic(); #endif
bnx2x_release_alr(bp); return;
}
DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
if (unlikely(err)) {
BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
cid);
bnx2x_panic_dump(bp, false);
}
bnx2x_cnic_cfc_comp(bp, cid, err); return 0;
}
staticvoid bnx2x_handle_mcast_eqe(struct bnx2x *bp)
{ struct bnx2x_mcast_ramrod_params rparam; int rc;
memset(&rparam, 0, sizeof(rparam));
rparam.mcast_obj = &bp->mcast_obj;
netif_addr_lock_bh(bp->dev);
/* Clear pending state for the last command */
bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
/* If there are pending mcast commands - send them */ if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); if (rc < 0)
BNX2X_ERR("Failed to send pending mcast commands: %d\n",
rc);
}
break; case BNX2X_FILTER_VLAN_PENDING:
DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n");
vlan_mac_obj = &bp->sp_objs[cid].vlan_obj; break; case BNX2X_FILTER_MCAST_PENDING:
DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); /* This is only relevant for 57710 where multicast MACs are * configured as unicast MACs using the same ramrod.
*/
bnx2x_handle_mcast_eqe(bp); return; default:
BNX2X_ERR("Unsupported classification command: 0x%x\n", echo); return;
}
/* called with rtnl_lock */ staticvoid bnx2x_after_function_update(struct bnx2x *bp)
{ int q, rc; struct bnx2x_fastpath *fp; struct bnx2x_queue_state_params queue_params = {NULL}; struct bnx2x_queue_update_params *q_update_params =
&queue_params.params.update;
/* Send Q update command with afex vlan removal values for all Qs */
queue_params.cmd = BNX2X_Q_CMD_UPDATE;
/* set silent vlan removal values according to vlan mode */
__set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
&q_update_params->update_flags);
__set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
&q_update_params->update_flags);
__set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
/* in access mode mark mask and value are 0 to strip all vlans */ if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
q_update_params->silent_removal_value = 0;
q_update_params->silent_removal_mask = 0;
} else {
q_update_params->silent_removal_value =
(bp->afex_def_vlan_tag & VLAN_VID_MASK);
q_update_params->silent_removal_mask = VLAN_VID_MASK;
}
for_each_eth_queue(bp, q) { /* Set the appropriate Queue object */
fp = &bp->fp[q];
queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
/* send the ramrod */
rc = bnx2x_queue_state_change(bp, &queue_params); if (rc < 0)
BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
q);
}
/* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. * when we get the next-page we need to adjust so the loop * condition below will be met. The next element is the size of a * regular element and hence incrementing by 1
*/ if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
hw_cons++;
/* This function may never run in parallel with itself for a * specific bp, thus there is no need in "paired" read memory * barrier here.
*/
sw_cons = bp->eq_cons;
sw_prod = bp->eq_prod;
/* We will perform the Queues update from * sp_rtnl task as all Queue SP operations * should run under rtnl_lock.
*/
bnx2x_schedule_sp_rtnl(bp, cmd, 0);
}
goto next_spqe;
case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
f_obj->complete_cmd(bp, f_obj,
BNX2X_F_CMD_AFEX_VIFLISTS);
bnx2x_after_afex_vif_lists(bp, elem); goto next_spqe; case EVENT_RING_OPCODE_FUNCTION_START:
DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, "got FUNC_START ramrod\n"); if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) break;
goto next_spqe;
case EVENT_RING_OPCODE_FUNCTION_STOP:
DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, "got FUNC_STOP ramrod\n"); if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) break;
goto next_spqe;
case EVENT_RING_OPCODE_SET_TIMESYNC:
DP(BNX2X_MSG_SP | BNX2X_MSG_PTP, "got set_timesync ramrod completion\n"); if (f_obj->complete_cmd(bp, f_obj,
BNX2X_F_CMD_SET_TIMESYNC)) break; goto next_spqe;
}
switch (opcode | bp->state) { case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
BNX2X_STATE_OPEN): case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
BNX2X_STATE_OPENING_WAIT4_PORT): case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
BNX2X_STATE_CLOSING_WAIT4_HALT):
DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
SW_CID(elem->message.data.eth_event.echo));
rss_raw->clear_pending(rss_raw); break;
case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): case (EVENT_RING_OPCODE_SET_MAC |
BNX2X_STATE_CLOSING_WAIT4_HALT): case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
BNX2X_STATE_OPEN): case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
BNX2X_STATE_DIAG): case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
BNX2X_STATE_CLOSING_WAIT4_HALT):
DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n");
bnx2x_handle_classification_eqe(bp, elem); break;
case (EVENT_RING_OPCODE_MULTICAST_RULES |
BNX2X_STATE_OPEN): case (EVENT_RING_OPCODE_MULTICAST_RULES |
BNX2X_STATE_DIAG): case (EVENT_RING_OPCODE_MULTICAST_RULES |
BNX2X_STATE_CLOSING_WAIT4_HALT):
DP(BNX2X_MSG_SP, "got mcast ramrod\n");
bnx2x_handle_mcast_eqe(bp); break;
case (EVENT_RING_OPCODE_FILTERS_RULES |
BNX2X_STATE_OPEN): case (EVENT_RING_OPCODE_FILTERS_RULES |
BNX2X_STATE_DIAG): case (EVENT_RING_OPCODE_FILTERS_RULES |
BNX2X_STATE_CLOSING_WAIT4_HALT):
DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
bnx2x_handle_rx_mode_eqe(bp); break; default: /* unknown event log error and continue */
BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
elem->message.opcode, bp->state);
}
next_spqe:
spqe_cnt++;
} /* for */
/* HW attentions */ if (status & BNX2X_DEF_SB_ATT_IDX) {
bnx2x_attn_int(bp);
status &= ~BNX2X_DEF_SB_ATT_IDX;
}
/* SP events: STAT_QUERY and others */ if (status & BNX2X_DEF_SB_IDX) { struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
if (FCOE_INIT(bp) &&
(bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { /* Prevent local bottom-halves from running as * we are going to change the local NAPI list.
*/
local_bh_disable();
napi_schedule(&bnx2x_fcoe(bp, napi));
local_bh_enable();
}
/* if status is non zero then perhaps something went wrong */ if (unlikely(status))
DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n", status);
/* ack status block only if something was actually handled */
bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
}
/* afex - poll to check if VIFSET_ACK should be sent to MFW */ if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
&bp->sp_state)) {
bnx2x_link_report(bp);
bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
}
}
mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
MCP_PULSE_SEQ_MASK); /* The delta between driver pulse and mcp response * should not get too big. If the MFW is more than 5 pulses * behind, we should worry about it enough to generate an error * log.
*/ if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
drv_pulse, mcp_pulse);
}
if (bp->state == BNX2X_STATE_OPEN)
bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
/* sample pf vf bulletin board for new posts from pf */ if (IS_VF(bp))
bnx2x_timer_sriov(bp);
staticvoid bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
{
u32 i; if (!(len%4) && !(addr%4)) for (i = 0; i < len; i += 4)
REG_WR(bp, addr + i, fill); else for (i = 0; i < len; i++)
REG_WR8(bp, addr + i, fill);
}
/* helper: writes FP SP data to FW - data_size in dwords */ staticvoid bnx2x_wr_fp_sb_data(struct bnx2x *bp, int fw_sb_id,
u32 *sb_data_p,
u32 data_size)
{ int index; for (index = 0; index < data_size; index++)
REG_WR(bp, BAR_CSTRORM_INTMEM +
CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + sizeof(u32)*index,
*(sb_data_p + index));
}
/* allocates state machine ids. */ staticvoid bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
{ /* zero out state machine indices */ /* rx indices */
index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { int sindex; /* take care of sig[0]..sig[4] */ for (sindex = 0; sindex < 4; sindex++)
bp->attn_group[index].sig[sindex] =
REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
if (!CHIP_IS_E1x(bp)) /* * enable5 is separate from the rest of the registers, * and therefore the address skip is 4 * and not 16 between the different groups
*/
bp->attn_group[index].sig[4] = REG_RD(bp,
reg_offset_en5 + 0x4*index); else
bp->attn_group[index].sig[4] = 0;
}
staticvoid bnx2x_init_eq_ring(struct bnx2x *bp)
{ int i; for (i = 1; i <= NUM_EQ_PAGES; i++) { union event_ring_elem *elem =
&bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
elem->next_page.addr.hi =
cpu_to_le32(U64_HI(bp->eq_mapping +
BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
elem->next_page.addr.lo =
cpu_to_le32(U64_LO(bp->eq_mapping +
BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
}
bp->eq_cons = 0;
bp->eq_prod = NUM_EQ_DESC;
bp->eq_cons_sb = BNX2X_EQ_INDEX; /* we want a warning message before it gets wrought... */
atomic_set(&bp->eq_spq_left,
min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
}
/* called with netif_addr_lock_bh() */ staticint bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, unsignedlong rx_mode_flags, unsignedlong rx_accept_flags, unsignedlong tx_accept_flags, unsignedlong ramrod_flags)
{ struct bnx2x_rx_mode_ramrod_params ramrod_param; int rc;
switch (rx_mode) { case BNX2X_RX_MODE_NONE: /* * 'drop all' supersedes any accept flags that may have been * passed to the function.
*/ break; case BNX2X_RX_MODE_NORMAL:
__set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
__set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
__set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
if (bp->accept_any_vlan) {
__set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
__set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
}
break; case BNX2X_RX_MODE_PROMISC: /* According to definition of SI mode, iface in promisc mode * should receive matched and unmatched (in resolution of port) * unicast packets.
*/
__set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
__set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
__set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
__set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
staticvoid bnx2x_init_internal_common(struct bnx2x *bp)
{ int i;
/* Zero this manually as its initialization is
currently missing in the initTool */ for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
REG_WR(bp, BAR_USTRORM_INTMEM +
USTORM_AGG_DATA_OFFSET + i * 4, 0); if (!CHIP_IS_E1x(bp)) {
REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
CHIP_INT_MODE_IS_BC(bp) ?
HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
}
}
staticvoid bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
{ switch (load_code) { case FW_MSG_CODE_DRV_LOAD_COMMON: case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
bnx2x_init_internal_common(bp);
fallthrough;
case FW_MSG_CODE_DRV_LOAD_PORT: /* nothing to do */
fallthrough;
case FW_MSG_CODE_DRV_LOAD_FUNCTION: /* internal memory per function is
initialized inside bnx2x_pf_init */ break;
default:
BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); break;
}
}
static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
{ if (CHIP_IS_E1x(fp->bp)) return BP_L_ID(fp->bp) + fp->index; else/* We want Client ID to be the same as IGU SB ID for 57712 */ return bnx2x_fp_igu_sb_id(fp);
}
/* initialize the default status block and sp ring */
bnx2x_init_def_sb(bp);
bnx2x_update_dsb_idx(bp);
bnx2x_init_sp_ring(bp);
} else {
bnx2x_memset_stats(bp);
}
}
/* some of the internal memories * are not directly readable from the driver * to test them we send debug packets
*/ staticint bnx2x_int_mem_test(struct bnx2x *bp)
{ int factor; int count, i;
u32 val = 0;
staticvoid bnx2x_init_pxp(struct bnx2x *bp)
{
u16 devctl; int r_order, w_order;
pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); if (bp->mrrs == -1)
r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); else {
DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
r_order = bp->mrrs;
}
bnx2x_init_pxp_arb(bp, r_order, w_order);
}
staticvoid bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
{ int is_required;
u32 val; int port;
if (BP_NOMCP(bp)) return;
is_required = 0;
val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
SHARED_HW_CFG_FAN_FAILURE_MASK;
if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
is_required = 1;
/* * The fan failure mechanism is usually related to the PHY type since * the power consumption of the board is affected by the PHY. Currently, * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
*/ elseif (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) for (port = PORT_0; port < PORT_MAX; port++) {
is_required |=
bnx2x_fan_failure_det_req(
bp,
bp->common.shmem_base,
bp->common.shmem2_base,
port);
}
/* Fan failure is indicated by SPIO 5 */
bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
/* set to active low mode */
val = REG_RD(bp, MISC_REG_SPIO_INT);
val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
REG_WR(bp, MISC_REG_SPIO_INT, val);
/* enable interrupt to signal the IGU */
val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
val |= MISC_SPIO_SPIO5;
REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
}
void bnx2x_pf_disable(struct bnx2x *bp)
{
u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
val &= ~IGU_PF_CONF_FUNC_EN;
/** * bnx2x_init_hw_common - initialize the HW at the COMMON phase. * * @bp: driver handle
*/ staticint bnx2x_init_hw_common(struct bnx2x *bp)
{
u32 val;
DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
/* * take the RESET lock to protect undi_unload flow from accessing * registers while we're resetting the chip
*/
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
val = 0xfffc; if (CHIP_IS_E3(bp)) {
val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
}
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
/** * 4-port mode or 2-port mode we need to turn of master-enable * for everyone, after that, turn it back on for self. * so, we disregard multi-function or not, and always disable * for all functions on the given path, this means 0,2,4,6 for * path 0 and 1,3,5,7 for path 1
*/ for (abs_func_id = BP_PATH(bp);
abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { if (abs_func_id == BP_ABS_FUNC(bp)) {
REG_WR(bp,
PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
1); continue;
}
bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); if (CHIP_IS_E1(bp)) { /* enable HW interrupt from PXP on USDM overflow
bit 16 on INT_MASK_0 */
REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
}
if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
/* let the HW do it's magic ... */
msleep(100); /* finish PXP init */
val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); if (val != 1) {
BNX2X_ERR("PXP2 CFG failed\n"); return -EBUSY;
}
val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); if (val != 1) {
BNX2X_ERR("PXP2 RD_INIT failed\n"); return -EBUSY;
}
/* Timers bug workaround E2 only. We need to set the entire ILT to * have entries with value "0" and valid bit on. * This needs to be done by the first PF that is loaded in a path * (i.e. common phase)
*/ if (!CHIP_IS_E1x(bp)) { /* In E2 there is a bug in the timers block that can cause function 6 / 7 * (i.e. vnic3) to start even if it is marked as "scan-off". * This occurs when a different function (func2,3) is being marked * as "scan-off". Real-life scenario for example: if a driver is being * load-unloaded while func6,7 are down. This will cause the timer to access * the ilt, translate to a logical address and send a request to read/write. * Since the ilt for the function that is down is not valid, this will cause * a translation error which is unrecoverable. * The Workaround is intended to make sure that when this happens nothing fatal * will occur. The workaround: * 1. First PF driver which loads on a path will: * a. After taking the chip out of reset, by using pretend, * it will write "0" to the following registers of * the other vnics. * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); * And for itself it will write '1' to * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable * dmae-operations (writing to pram for example.) * note: can be done for only function 6,7 but cleaner this * way. * b. Write zero+valid to the entire ILT. * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of * VNIC3 (of that port). The range allocated will be the * entire ILT. This is needed to prevent ILT range error. * 2. Any PF driver load flow: * a. ILT update with the physical addresses of the allocated * logical pages. * b. Wait 20msec. - note that this timeout is needed to make * sure there are no requests in one of the PXP internal * queues with "old" ILT addresses. * c. PF enable in the PGLC. * d. Clear the was_error of the PF in the PGLC. (could have * occurred while driver was down) * e. PF enable in the CFC (WEAK + STRONG) * f. Timers scan enable * 3. PF driver unload flow: * a. Clear the Timers scan_en. * b. Polling for scan_on=0 for that PF. * c. Clear the PF enable bit in the PXP. * d. Clear the PF enable in the CFC (WEAK + STRONG) * e. Write zero+valid to all ILT entries (The valid bit must * stay set) * f. If this is VNIC 3 of a port then also init * first_timers_ilt_entry to zero and last_timers_ilt_entry * to the last entry in the ILT. * * Notes: * Currently the PF error in the PGLC is non recoverable. * In the future the there will be a recovery routine for this error. * Currently attention is masked. * Having an MCP lock on the load/unload process does not guarantee that * there is no Timer disable during Func6/7 enable. This is because the * Timers scan is currently being cleared by the MCP on FLR. * Step 2.d can be done only for PF6/7 and the driver can also check if * there is error before clearing it. But the flow above is simpler and * more general. * All ILT entries are written by zero+valid and not just PF6/7 * ILT entries since in the future the ILT entries allocation for * PF-s might be dynamic.
*/ struct ilt_client_info ilt_cli; struct bnx2x_ilt ilt;
memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
memset(&ilt, 0, sizeof(struct bnx2x_ilt));
/* Step 1: set zeroes to all ilt page entries with valid bit on * Step 2: set the timers first/last ilt entry to point * to the entire range to prevent ILT range error for 3rd/4th * vnic (this code assumes existence of the vnic) * * both steps performed by call to bnx2x_ilt_client_init_op() * with dummy TM client * * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT * and his brother are split registers
*/
bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
if (sizeof(union cdu_context) != 1024) /* we currently assume that a context is 1024 bytes */
dev_alert(&bp->pdev->dev, "please adjust the size of cdu_context(%ld)\n",
(long)sizeof(union cdu_context));
bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); if (!CHIP_IS_E1(bp)) { /* in E3 this done in per-port section */ if (!CHIP_IS_E3(bp))
REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
} if (CHIP_IS_E1H(bp)) /* not applicable for E2 (and above ...) */
REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
if (CHIP_IS_E1(bp)) { /* read NIG statistic
to see if this is our first up since powerup */
bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
val = *bnx2x_sp(bp, wb_data[0]);
/* do internal memory self test */ if ((val == 0) && bnx2x_int_mem_test(bp)) {
BNX2X_ERR("internal mem self test failed\n"); return -EBUSY;
}
}
/* Timers bug workaround: disables the pf_master bit in pglue at * common phase, we need to enable it here before any dmae access are * attempted. Therefore we manually added the enable-master to the * port phase (it also happens in the function phase)
*/ if (!CHIP_IS_E1x(bp))
REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); /* init aeu_mask_attn_func_0/1: * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
* bits 4-7 are used for "per vn group attention" */
val = IS_MF(bp) ? 0xF7 : 0x7; /* Enable DCBX attention for all but E1 */
val |= CHIP_IS_E1(bp) ? 0 : 0x10;
REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
/* SCPAD_PARITY should NOT trigger close the gates */
reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
REG_WR(bp, reg,
REG_RD(bp, reg) &
~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
if (!CHIP_IS_E1x(bp)) {
val = 0; switch (bp->mf_mode) { case MULTI_FUNCTION_SD:
val = 1; break; case MULTI_FUNCTION_SI: case MULTI_FUNCTION_AFEX:
val = 2; break;
}
/* If SPIO5 is set to generate interrupts, enable it for this port */
val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); if (val & MISC_SPIO_SPIO5) {
u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
val = REG_RD(bp, reg_addr);
val |= AEU_INPUTS_ATTN_BITS_SPIO5;
REG_WR(bp, reg_addr, val);
}
staticvoid bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
{
u32 i, base = FUNC_ILT_BASE(func); for (i = base; i < base + ILT_PER_FUNC; i++)
bnx2x_ilt_wr(bp, i, 0);
}
staticvoid bnx2x_init_searcher(struct bnx2x *bp)
{ int port = BP_PORT(bp);
bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); /* T1 hash bits value determines the T1 number of entries */
REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
}
staticinlineint bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
{ int rc; struct bnx2x_func_state_params func_params = {NULL}; struct bnx2x_func_switch_update_params *switch_update_params =
&func_params.params.switch_update;
/* Prepare parameters for function state transitions */
__set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
__set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
/* Function parameters */
__set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
&switch_update_params->changes); if (suspend)
__set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
&switch_update_params->changes);
rc = bnx2x_func_state_change(bp, &func_params);
return rc;
}
staticint bnx2x_reset_nic_mode(struct bnx2x *bp)
{ int rc, i, port = BP_PORT(bp); int vlan_en = 0, mac_en[NUM_MACS];
/* Close input from network */ if (bp->mf_mode == SINGLE_FUNCTION) {
bnx2x_set_rx_filter(&bp->link_params, 0);
} else {
vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
NIG_REG_LLH0_FUNC_EN);
REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
NIG_REG_LLH0_FUNC_EN, 0); for (i = 0; i < NUM_MACS; i++) {
mac_en[i] = REG_RD(bp, port ?
(NIG_REG_LLH1_FUNC_MEM_ENABLE +
4 * i) :
(NIG_REG_LLH0_FUNC_MEM_ENABLE +
4 * i));
REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
4 * i) :
(NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
}
}
/* Close BMC to host */
REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
/* Suspend Tx switching to the PF. Completion of this ramrod * further guarantees that all the packets of that PF / child * VFs in BRB were processed by the Parser, so it is safe to * change the NIC_MODE register.
*/
rc = bnx2x_func_switch_update(bp, 1); if (rc) {
BNX2X_ERR("Can't suspend tx-switching!\n"); return rc;
}
int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
{ int rc;
bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
if (CONFIGURE_NIC_MODE(bp)) { /* Configure searcher as part of function hw init */
bnx2x_init_searcher(bp);
/* Reset NIC mode */
rc = bnx2x_reset_nic_mode(bp); if (rc)
BNX2X_ERR("Can't change NIC mode!\n"); return rc;
}
return 0;
}
/* previous driver DMAE transaction may have occurred when pre-boot stage ended * and boot began, or when kdump kernel was loaded. Either case would invalidate * the addresses of the transaction, resulting in was-error bit set in the pci * causing all hw-to-host pcie transactions to timeout. If this happened we want * to clear the interrupt which detected this from the pglueb and the was done * bit
*/ staticvoid bnx2x_clean_pglue_errors(struct bnx2x *bp)
{ if (!CHIP_IS_E1x(bp))
REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
1 << BP_ABS_FUNC(bp));
}
staticint bnx2x_init_hw_func(struct bnx2x *bp)
{ int port = BP_PORT(bp); int func = BP_FUNC(bp); int init_phase = PHASE_PF0 + func; struct bnx2x_ilt *ilt = BP_ILT(bp);
u16 cdu_ilt_start;
u32 addr, val;
u32 main_mem_base, main_mem_size, main_mem_prty_clr; int i, main_mem_width, rc;
if (IS_SRIOV(bp))
cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
/* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes * those of the VFs, so start line should be reset
*/
cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; for (i = 0; i < L2_ILT_LINES(bp); i++) {
ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
ilt->lines[cdu_ilt_start + i].page_mapping =
bp->context[i].cxt_mapping;
ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
}
bnx2x_ilt_init_op(bp, INITOP_SET);
if (!CONFIGURE_NIC_MODE(bp)) {
bnx2x_init_searcher(bp);
REG_WR(bp, PRS_REG_NIC_MODE, 0);
DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
} else { /* Set NIC mode */
REG_WR(bp, PRS_REG_NIC_MODE, 1);
DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
}
if (!CHIP_IS_E1x(bp)) {
u32 pf_conf = IGU_PF_CONF_FUNC_EN;
/* Turn on a single ISR mode in IGU if driver is going to use * INT#x or MSI
*/ if (!(bp->flags & USING_MSIX_FLAG))
pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; /* * Timers workaround bug: function init part. * Need to wait 20msec after initializing ILT, * needed to make sure there are no requests in * one of the PXP internal queues with "old" ILT addresses
*/
msleep(20); /* * Master enable - Due to WB DMAE writes performed before this * register is re-initialized as part of the regular function * init
*/
REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); /* Enable the function in IGU */
REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
}
if (!CHIP_IS_E1x(bp)) {
REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
}
bnx2x_init_block(bp, BLOCK_IGU, init_phase);
if (!CHIP_IS_E1x(bp)) { int dsb_idx = 0; /** * Producer memory: * E2 mode: address 0-135 match to the mapping memory; * 136 - PF0 default prod; 137 - PF1 default prod; * 138 - PF2 default prod; 139 - PF3 default prod; * 140 - PF0 attn prod; 141 - PF1 attn prod; * 142 - PF2 attn prod; 143 - PF3 attn prod; * 144-147 reserved. * * E1.5 mode - In backward compatible mode; * for non default SB; each even line in the memory * holds the U producer and each odd line hold * the C producer. The first 128 producers are for * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 * producers are for the DSB for each PF. * Each PF has five segments: (the order inside each * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; * 132-135 C prods; 136-139 X prods; 140-143 T prods; * 144-147 attn prods;
*/ /* non-default-status-blocks */
num_segs = CHIP_INT_MODE_IS_BC(bp) ?
IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
prod_offset = (bp->igu_base_sb + sb_idx) *
num_segs;
for (i = 0; i < num_segs; i++) {
addr = IGU_REG_PROD_CONS_MEMORY +
(prod_offset + i) * 4;
REG_WR(bp, addr, 0);
} /* send consumer update with value 0 */
bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
USTORM_ID, 0, IGU_INT_NOP, 1);
bnx2x_igu_clear_sb(bp,
bp->igu_base_sb + sb_idx);
}
for (i = 0; i < L2_ILT_LINES(bp); i++)
BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
bp->context[i].size);
bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
{ if (!CHIP_IS_E1x(bp)) { /* size = the status block + ramrod buffers */
bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, sizeof(struct host_hc_status_block_e2)); if (!bp->cnic_sb.e2_sb) goto alloc_mem_err;
} else {
bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, sizeof(struct host_hc_status_block_e1x)); if (!bp->cnic_sb.e1x_sb) goto alloc_mem_err;
}
if (CONFIGURE_NIC_MODE(bp) && !bp->t2) { /* allocate searcher T2 table, as it wasn't allocated before */
bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); if (!bp->t2) goto alloc_mem_err;
}
/* write address to which L5 should insert its values */
bp->cnic_eth_dev.addr_drv_info_to_mcp =
&bp->slowpath->drv_info_to_mcp;
if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC)) goto alloc_mem_err;
int bnx2x_alloc_mem(struct bnx2x *bp)
{ int i, allocated, context_size;
if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) { /* allocate searcher T2 table */
bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); if (!bp->t2) goto alloc_mem_err;
}
bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping, sizeof(struct host_sp_status_block)); if (!bp->def_status_blk) goto alloc_mem_err;
bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping, sizeof(struct bnx2x_slowpath)); if (!bp->slowpath) goto alloc_mem_err;
/* Allocate memory for CDU context: * This memory is allocated separately and not in the generic ILT * functions because CDU differs in few aspects: * 1. There are multiple entities allocating memory for context - * 'regular' driver, CNIC and SRIOV driver. Each separately controls * its own ILT lines. * 2. Since CDU page-size is not a single 4KB page (which is the case * for the other ILT clients), to be efficient we want to support * allocation of sub-page-size in the last entry. * 3. Context pointers are used by the driver to pass to FW / update * the context (for the other ILT clients the pointers are used just to * free the memory during unload).
*/
context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
for (i = 0, allocated = 0; allocated < context_size; i++) {
bp->context[i].size = min(CDU_ILT_PAGE_SZ,
(context_size - allocated));
bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
bp->context[i].size); if (!bp->context[i].vcxt) goto alloc_mem_err;
allocated += bp->context[i].size;
}
bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
GFP_KERNEL); if (!bp->ilt->lines) goto alloc_mem_err;
if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) goto alloc_mem_err;
if (bnx2x_iov_alloc_mem(bp)) goto alloc_mem_err;
/* Slow path ring */
bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE); if (!bp->spq) goto alloc_mem_err;
/* Set the command: ADD or DEL */ if (set)
ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; else
ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
}
rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
if (rc == -EEXIST) {
DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); /* do not treat adding same MAC as error */
rc = 0;
} elseif (rc < 0)
BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
return rc;
}
int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan, struct bnx2x_vlan_mac_obj *obj, bool set, unsignedlong *ramrod_flags)
{ int rc; struct bnx2x_vlan_mac_ramrod_params ramrod_param;
memset(&ramrod_param, 0, sizeof(ramrod_param));
/* Fill general parameters */
ramrod_param.vlan_mac_obj = obj;
ramrod_param.ramrod_flags = *ramrod_flags;
/* Fill a user request section if needed */ if (!test_bit(RAMROD_CONT, ramrod_flags)) {
ramrod_param.user_req.u.vlan.vlan = vlan;
__set_bit(BNX2X_VLAN, &ramrod_param.user_req.vlan_mac_flags); /* Set the command: ADD or DEL */ if (set)
ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; else
ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
}
rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
if (rc == -EEXIST) { /* Do not treat adding same vlan as error. */
DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
rc = 0;
} elseif (rc < 0) {
BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del"));
}
int bnx2x_setup_leading(struct bnx2x *bp)
{ if (IS_PF(bp)) return bnx2x_setup_queue(bp, &bp->fp[0], true); else/* VF */ return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
}
/** * bnx2x_set_int_mode - configure interrupt mode * * @bp: driver handle * * In case of MSI-X it will also try to enable MSI-X.
*/ int bnx2x_set_int_mode(struct bnx2x *bp)
{ int rc = 0;
if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
BNX2X_ERR("VF not loaded since interrupt mode not msix\n"); return -EINVAL;
}
switch (int_mode) { case BNX2X_INT_MODE_MSIX: /* attempt to enable msix */
rc = bnx2x_enable_msix(bp);
/* msix attained */ if (!rc) return 0;
/* vfs use only msix */ if (rc && IS_VF(bp)) return rc;
/* failed to enable multiple MSI-X */
BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
bp->num_queues,
1 + bp->num_cnic_queues);
fallthrough; case BNX2X_INT_MODE_MSI:
bnx2x_enable_msi(bp);
fallthrough; case BNX2X_INT_MODE_INTX:
bp->num_ethernet_queues = 1;
bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
BNX2X_DEV_INFO("set number of queues to 1\n"); break; default:
BNX2X_DEV_INFO("unknown value in int_mode module parameter\n"); return -EINVAL;
} return 0;
}
/* must be called prior to any HW initializations */ staticinline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
{ if (IS_SRIOV(bp)) return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS; return L2_ILT_LINES(bp);
}
/* FCoE Queue uses Default SB, thus has no HC capabilities */ if (!IS_FCOE_FP(fp)) {
__set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
__set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
/* If HC is supported, enable host coalescing in the transition * to INIT state.
*/
__set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
__set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
/* Set the command */
q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
/* Set tx-only QUEUE flags: don't zero statistics */
tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
/* choose the index of the cid to send the slow path on */
tx_only_params->cid_index = tx_index;
/* Set general TX_ONLY_SETUP parameters */
bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
/* Set Tx TX_ONLY_SETUP parameters */
bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
DP(NETIF_MSG_IFUP, "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
tx_only_params->gen_params.spcl_id, tx_only_params->flags);
/* send the ramrod */ return bnx2x_queue_state_change(bp, q_params);
}
/** * bnx2x_setup_queue - setup queue * * @bp: driver handle * @fp: pointer to fastpath * @leading: is leading * * This function performs 2 steps in a Queue state machine * actually: 1) RESET->INIT 2) INIT->SETUP
*/
DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
/* reset IGU state skip FCoE L2 queue */ if (!IS_FCOE_FP(fp))
bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
IGU_INT_ENABLE, 0);
q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; /* We want to wait for completion in this context */
__set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
/* Prepare the INIT parameters */
bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
/* Set the command */
q_params.cmd = BNX2X_Q_CMD_INIT;
/* Change the state to INIT */
rc = bnx2x_queue_state_change(bp, &q_params); if (rc) {
BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); return rc;
}
DP(NETIF_MSG_IFUP, "init complete\n");
/* Now move the Queue to the SETUP state... */
memset(setup_params, 0, sizeof(*setup_params));
/* Set QUEUE flags */
setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
/* Set general SETUP parameters */
bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
FIRST_TX_COS_INDEX);
q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; /* We want to wait for completion in this context */
__set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
/* close tx-only connections */ for (tx_index = FIRST_TX_ONLY_COS_INDEX;
tx_index < fp->max_cos;
tx_index++){
/* ascertain this is a normal queue*/
txdata = fp->txdata_ptr[tx_index];
if (CNIC_LOADED(bp)) { /* Disable Timer scan */
REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); /* * Wait for at least 10ms and up to 2 second for the timers * scan to complete
*/ for (i = 0; i < 200; i++) {
usleep_range(10000, 20000); if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) break;
}
} /* Clear ILT */
bnx2x_clear_func_ilt(bp, func);
/* Timers workaround bug for E2: if this is vnic-3, * we need to set the entire ilt range for this timers.
*/ if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { struct ilt_client_info ilt_cli; /* use dummy TM client */
memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
ilt_cli.start = 0;
ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
ilt_cli.client_num = ILT_CLIENT_TM;
/* Do not rcv packets to BRB */
REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); /* Do not direct rcv packets that are not for MCP to the BRB */
REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
msleep(100); /* Check for BRB port occupancy */
val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); if (val)
DP(NETIF_MSG_IFDOWN, "BRB1 is not empty %d blocks are occupied\n", val);
/* Prepare parameters for function state transitions */
__set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
func_params.f_obj = &bp->func_obj;
func_params.cmd = BNX2X_F_CMD_STOP;
/* * Try to stop the function the 'good way'. If fails (in case * of a parity error during bnx2x_chip_cleanup()) and we are * not in a debug mode, perform a state transaction in order to * enable further HW_RESET transaction.
*/
rc = bnx2x_func_state_change(bp, &func_params); if (rc) { #ifdef BNX2X_STOP_ON_ERROR return rc; #else
BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
__set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); return bnx2x_func_state_change(bp, &func_params); #endif
}
return 0;
}
/** * bnx2x_send_unload_req - request unload mode from the MCP. * * @bp: driver handle * @unload_mode: requested function's unload mode * * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
*/
u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
{
u32 reset_code = 0; int port = BP_PORT(bp);
/* Select the UNLOAD request mode */ if (unload_mode == UNLOAD_NORMAL)
reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
/** * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. * * @bp: driver handle * @keep_link: true iff link should be kept up
*/ void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
{
u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
/* Report UNLOAD_DONE to MCP */ if (!BP_NOMCP(bp))
bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
}
staticint bnx2x_func_wait_started(struct bnx2x *bp)
{ int tout = 50; int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
if (!bp->port.pmf) return 0;
/* * (assumption: No Attention from MCP at this stage) * PMF probably in the middle of TX disable/enable transaction * 1. Sync IRS for default SB * 2. Sync SP queue - this guarantees us that attention handling started * 3. Wait, that TX disable/enable transaction completes * * 1+2 guarantee that if DCBx attention was scheduled it already changed * pending bit of transaction from STARTED-->TX_STOPPED, if we already * received completion for the transaction the state is TX_STOPPED. * State will return to STARTED after completion of TX_STOPPED-->STARTED * transaction.
*/
/* make sure default SB ISR is done */ if (msix)
synchronize_irq(bp->msix_table[0].vector); else
synchronize_irq(bp->pdev->irq);
while (bnx2x_func_get_state(bp, &bp->func_obj) !=
BNX2X_F_STATE_STARTED && tout--)
msleep(20);
if (bnx2x_func_get_state(bp, &bp->func_obj) !=
BNX2X_F_STATE_STARTED) { #ifdef BNX2X_STOP_ON_ERROR
BNX2X_ERR("Wrong function state\n"); return -EBUSY; #else /* * Failed to complete the transaction in a "good way" * Force both transactions with CLR bit
*/ struct bnx2x_func_state_params func_params = {NULL};
DP(NETIF_MSG_IFDOWN, "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
staticvoid bnx2x_disable_ptp(struct bnx2x *bp)
{ int port = BP_PORT(bp);
/* Disable sending PTP packets to host */
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
/* Reset PTP event detection rules */
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
/* Disable the PTP feature */
REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
NIG_REG_P0_PTP_EN, 0x0);
}
/* Called during unload, to stop PTP-related stuff */ staticvoid bnx2x_stop_ptp(struct bnx2x *bp)
{ /* Cancel PTP work queue. Should be done after the Tx queues are * drained to prevent additional scheduling.
*/
cancel_work_sync(&bp->ptp_task);
if (bp->ptp_tx_skb) {
dev_kfree_skb_any(bp->ptp_tx_skb);
bp->ptp_tx_skb = NULL;
}
/* Give HW time to discard old tx messages */
usleep_range(1000, 2000);
/* Clean all ETH MACs */
rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, false); if (rc < 0)
BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
/* Clean up UC list */
rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, true); if (rc < 0)
BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
rc);
/* The whole *vlan_obj structure may be not initialized if VLAN * filtering offload is not supported by hardware. Currently this is * true for all hardware covered by CHIP_IS_E1x().
*/ if (!CHIP_IS_E1x(bp)) { /* Remove all currently configured VLANs */
rc = bnx2x_del_all_vlans(bp); if (rc < 0)
BNX2X_ERR("Failed to delete all VLANs\n");
}
/* Set "drop all" (stop Rx). * We need to take a netif_addr_lock() here in order to prevent * a race between the completion code and this code.
*/
netif_addr_lock_bh(bp->dev); /* Schedule the rx_mode command */ if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); elseif (bp->slowpath)
bnx2x_set_storm_rx_mode(bp);
/* Cleanup multicast configuration */
rparam.mcast_obj = &bp->mcast_obj;
rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); if (rc < 0)
BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
netif_addr_unlock_bh(bp->dev);
bnx2x_iov_chip_cleanup(bp);
/* * Send the UNLOAD_REQUEST to the MCP. This will return if * this function should perform FUNC, PORT or COMMON HW * reset.
*/
reset_code = bnx2x_send_unload_req(bp, unload_mode);
/* * (assumption: No Attention from MCP at this stage) * PMF probably in the middle of TX disable/enable transaction
*/
rc = bnx2x_func_wait_started(bp); if (rc) {
BNX2X_ERR("bnx2x_func_wait_started failed\n"); #ifdef BNX2X_STOP_ON_ERROR return; #endif
}
/* Close multi and leading connections * Completions for ramrods are collected in a synchronous way
*/
for_each_eth_queue(bp, i) if (bnx2x_stop_queue(bp, i)) #ifdef BNX2X_STOP_ON_ERROR return; #else goto unload_error; #endif
if (CNIC_LOADED(bp)) {
for_each_cnic_queue(bp, i) if (bnx2x_stop_queue(bp, i)) #ifdef BNX2X_STOP_ON_ERROR return; #else goto unload_error; #endif
}
/* If SP settings didn't get completed so far - something * very wrong has happen.
*/ if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
/* stop_ptp should be after the Tx queues are drained to prevent * scheduling to the cancelled PTP work queue. It should also be after * function stop ramrod is sent, since as part of this ramrod FW access * PTP registers.
*/ if (bp->flags & PTP_SUPPORTED) {
bnx2x_stop_ptp(bp); if (bp->ptp_clock) {
ptp_clock_unregister(bp->ptp_clock);
bp->ptp_clock = NULL;
}
}
if (!bp->nic_stopped) { /* Disable HW interrupts, NAPI */
bnx2x_netif_stop(bp, 1); /* Delete all NAPI objects */
bnx2x_del_all_napi(bp); if (CNIC_LOADED(bp))
bnx2x_del_all_napi_cnic(bp);
/* Reset the chip, unless PCI function is offline. If we reach this * point following a PCI error handling, it means device is really * in a bad state and we're about to remove it, so reset the chip * is not a good idea.
*/ if (!pci_channel_offline(bp->pdev)) {
rc = bnx2x_reset_hw(bp, reset_code); if (rc)
BNX2X_ERR("HW_RESET failed\n");
}
/* Report UNLOAD_DONE to MCP */
bnx2x_send_unload_done(bp, keep_link);
}
DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
if (CHIP_IS_E1(bp)) { int port = BP_PORT(bp);
u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
MISC_REG_AEU_MASK_ATTN_FUNC_0;
val = REG_RD(bp, addr);
val &= ~(0x300);
REG_WR(bp, addr, val);
} else {
val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
}
}
/* Close gates #2, #3 and #4: */ staticvoid bnx2x_set_234_gates(struct bnx2x *bp, bool close)
{
u32 val;
/* Gates #2 and #4a are closed/opened for "not E1" only */ if (!CHIP_IS_E1(bp)) { /* #4 */
REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); /* #2 */
REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
}
/* #3 */ if (CHIP_IS_E1x(bp)) { /* Prevent interrupts from HC on both ports */
val = REG_RD(bp, HC_REG_CONFIG_1);
REG_WR(bp, HC_REG_CONFIG_1,
(!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
(val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
val = REG_RD(bp, HC_REG_CONFIG_0);
REG_WR(bp, HC_REG_CONFIG_0,
(!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
(val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
} else { /* Prevent incoming interrupts in IGU */
val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
close ? "closing" : "opening");
}
#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
staticvoid bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
{ /* Do some magic... */
u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
*magic_val = val & SHARED_MF_CLP_MAGIC;
MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
}
/** * bnx2x_clp_reset_done - restore the value of the `magic' bit. * * @bp: driver handle * @magic_val: old value of the `magic' bit.
*/ staticvoid bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
{ /* Restore the `magic' bit value... */
u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
MF_CFG_WR(bp, shared_mf_config.clp_mb,
(val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
}
/** * bnx2x_reset_mcp_prep - prepare for MCP reset. * * @bp: driver handle * @magic_val: old value of 'magic' bit. * * Takes care of CLP configurations.
*/ staticvoid bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
{
u32 shmem;
u32 validity_offset;
DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
/* Set `magic' bit in order to save MF config */ if (!CHIP_IS_E1(bp))
bnx2x_clp_reset_prep(bp, magic_val);
#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ #define MCP_ONE_TIMEOUT 100 /* 100 ms */
/** * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT * * @bp: driver handle
*/ staticvoid bnx2x_mcp_wait_one(struct bnx2x *bp)
{ /* special handling for emulation and FPGA,
wait 10 times longer */ if (CHIP_REV_IS_SLOW(bp))
msleep(MCP_ONE_TIMEOUT*10); else
msleep(MCP_ONE_TIMEOUT);
}
/* * initializes bp->common.shmem_base and waits for validity signature to appear
*/ staticint bnx2x_init_shmem(struct bnx2x *bp)
{ int cnt = 0;
u32 val = 0;
do {
bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
/* If we read all 0xFFs, means we are in PCI error state and * should bail out to avoid crashes on adapter's FW reads.
*/ if (bp->common.shmem_base == 0xFFFFFFFF) {
bp->flags |= NO_MCP_FLAG; return -ENODEV;
}
if (bp->common.shmem_base) {
val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); if (val & SHR_MEM_VALIDITY_MB) return 0;
}
bnx2x_mcp_wait_one(bp);
} while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
/* * Bits that have to be set in reset_mask2 if we want to reset 'global' * (per chip) blocks.
*/
global_bits2 =
MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
/* Don't reset the following blocks. * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be * reset, as in 4 port device they might still be owned * by the MCP (there is only one leader per path).
*/
not_reset_mask1 =
MISC_REGISTERS_RESET_REG_1_RST_HC |
MISC_REGISTERS_RESET_REG_1_RST_PXPV |
MISC_REGISTERS_RESET_REG_1_RST_PXP;
/* * Keep the following blocks in reset: * - all xxMACs are handled by the bnx2x_link code.
*/
stay_reset2 =
MISC_REGISTERS_RESET_REG_2_XMAC |
MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
/* Full reset masks according to the chip */
reset_mask1 = 0xffffffff;
/* Don't reset global blocks unless we need to */ if (!global)
reset_mask2 &= ~global_bits2;
/* * In case of attention in the QM, we need to reset PXP * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM * because otherwise QM reset would release 'close the gates' shortly * before resetting the PXP, then the PSWRQ would send a write * request to PGLUE. Then when PXP is reset, PGLUE would try to * read the payload data from PSWWR, but PSWWR would not * respond. The write queue in PGLUE would stuck, dmae commands * would not return. Therefore it's important to reset the second * reset register (containing the * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM * bit).
*/
REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
reset_mask2 & (~not_reset_mask2));
/** * bnx2x_er_poll_igu_vq - poll for pending writes bit. * It should get cleared in no more than 1s. * * @bp: driver handle * * It should get cleared in no more than 1s. Returns 0 if * pending writes bit gets cleared.
*/ staticint bnx2x_er_poll_igu_vq(struct bnx2x *bp)
{
u32 cnt = 1000;
u32 pend_bits = 0;
do {
pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
if (cnt <= 0) {
BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
pgl_exp_rom2); return -EAGAIN;
}
barrier();
/* Close gates #2, #3 and #4 */
bnx2x_set_234_gates(bp, true);
/* Poll for IGU VQs for 57712 and newer chips */ if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) return -EAGAIN;
/* TBD: Indicate that "process kill" is in progress to MCP */
/* Clear "unprepared" bit */
REG_WR(bp, MISC_REG_UNPREPARED, 0);
barrier();
/* Wait for 1ms to empty GLUE and PCI-E core queues, * PSWHST, GRC and PSWRD Tetris buffer.
*/
usleep_range(1000, 2000);
/* Prepare to chip reset: */ /* MCP */ if (global)
bnx2x_reset_mcp_prep(bp, &val);
/* PXP */
bnx2x_pxp_prep(bp);
barrier();
/* reset the chip */
bnx2x_process_kill_chip_reset(bp, global);
barrier();
/* clear errors in PGB */ if (!CHIP_IS_E1x(bp))
REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
/* Recover after reset: */ /* MCP */ if (global && bnx2x_reset_mcp_comp(bp, val)) return -EAGAIN;
/* TBD: Add resetting the NO_MCP mode DB here */
/* Open the gates #2, #3 and #4 */
bnx2x_set_234_gates(bp, false);
/* TBD: IGU/AEU preparation bring back the AEU/IGU to a
* reset state, re-enable attentions. */
return 0;
}
staticint bnx2x_leader_reset(struct bnx2x *bp)
{ int rc = 0; bool global = bnx2x_reset_is_global(bp);
u32 load_code;
/* if not going to reset MCP - load "fake" driver to reset HW while * driver is owner of the HW
*/ if (!global && !BP_NOMCP(bp)) {
load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
DRV_MSG_CODE_LOAD_REQ_WITH_LFA); if (!load_code) {
BNX2X_ERR("MCP response failure, aborting\n");
rc = -EAGAIN; goto exit_leader_reset;
} if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
(load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
BNX2X_ERR("MCP unexpected resp, aborting\n");
rc = -EAGAIN; goto exit_leader_reset2;
}
load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); if (!load_code) {
BNX2X_ERR("MCP response failure, aborting\n");
rc = -EAGAIN; goto exit_leader_reset2;
}
}
/* Try to recover after the failure */ if (bnx2x_process_kill(bp, global)) {
BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
BP_PATH(bp));
rc = -EAGAIN; goto exit_leader_reset2;
}
/* * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver * state.
*/
bnx2x_set_reset_done(bp); if (global)
bnx2x_clear_reset_global(bp);
exit_leader_reset2: /* unload "fake driver" if it was loaded */ if (!global && !BP_NOMCP(bp)) {
bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
}
exit_leader_reset:
bp->is_leader = 0;
bnx2x_release_leader_lock(bp);
smp_mb(); return rc;
}
staticvoid bnx2x_recovery_failed(struct bnx2x *bp)
{
netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
/* Disconnect this device */
netif_device_detach(bp->dev);
/* * Block ifup for all function on this engine until "process kill" * or power cycle.
*/
bnx2x_set_reset_in_progress(bp);
/* Shut down the power */
bnx2x_set_power_state(bp, PCI_D3hot);
bp->recovery_state = BNX2X_RECOVERY_FAILED;
smp_mb();
}
/* * Assumption: runs under rtnl lock. This together with the fact * that it's called only from bnx2x_sp_rtnl() ensure that it * will never be called when netif_running(bp->dev) is false.
*/ staticvoid bnx2x_parity_recover(struct bnx2x *bp)
{
u32 error_recovered, error_unrecovered; bool is_parity, global = false; #ifdef CONFIG_BNX2X_SRIOV int vf_idx;
if (vf)
vf->state = VF_LOST;
} #endif
DP(NETIF_MSG_HW, "Handling parity\n"); while (1) { switch (bp->recovery_state) { case BNX2X_RECOVERY_INIT:
DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
is_parity = bnx2x_chk_parity_attn(bp, &global, false);
WARN_ON(!is_parity);
/* Try to get a LEADER_LOCK HW lock */ if (bnx2x_trylock_leader_lock(bp)) {
bnx2x_set_reset_in_progress(bp); /* * Check if there is a global attention and if * there was a global attention, set the global * reset bit.
*/
if (global)
bnx2x_set_reset_global(bp);
bp->is_leader = 1;
}
/* Stop the driver */ /* If interface has been removed - break */ if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false)) return;
bp->recovery_state = BNX2X_RECOVERY_WAIT;
/* Ensure "is_leader", MCP command sequence and * "recovery_state" update values are seen on other * CPUs.
*/
smp_mb(); break;
case BNX2X_RECOVERY_WAIT:
DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); if (bp->is_leader) { int other_engine = BP_PATH(bp) ? 0 : 1; bool other_load_status =
bnx2x_get_load_status(bp, other_engine); bool load_status =
bnx2x_get_load_status(bp, BP_PATH(bp));
global = bnx2x_reset_is_global(bp);
/* * In case of a parity in a global block, let * the first leader that performs a * leader_reset() reset the global blocks in * order to clear global attentions. Otherwise * the gates will remain closed for that * engine.
*/ if (load_status ||
(global && other_load_status)) { /* Wait until all other functions get * down.
*/
schedule_delayed_work(&bp->sp_rtnl_task,
HZ/10); return;
} else { /* If all other functions got down - * try to bring the chip back to * normal. In any case it's an exit * point for a leader.
*/ if (bnx2x_leader_reset(bp)) {
bnx2x_recovery_failed(bp); return;
}
/* If we are here, means that the * leader has succeeded and doesn't * want to be a leader any more. Try * to continue as a none-leader.
*/ break;
}
} else { /* non-leader */ if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { /* Try to get a LEADER_LOCK HW lock as * long as a former leader may have * been unloaded by the user or * released a leadership by another * reason.
*/ if (bnx2x_trylock_leader_lock(bp)) { /* I'm a leader now! Restart a * switch case.
*/
bp->is_leader = 1; break;
}
} else { /* * If there was a global attention, wait * for it to be cleared.
*/ if (bnx2x_reset_is_global(bp)) {
schedule_delayed_work(
&bp->sp_rtnl_task,
HZ/10); return;
}
error_recovered =
bp->eth_stats.recoverable_error;
error_unrecovered =
bp->eth_stats.unrecoverable_error;
bp->recovery_state =
BNX2X_RECOVERY_NIC_LOADING; if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
error_unrecovered++;
netdev_err(bp->dev, "Recovery failed. Power cycle needed\n"); /* Disconnect this device */
netif_device_detach(bp->dev); /* Shut down the power */
bnx2x_set_power_state(
bp, PCI_D3hot);
smp_mb();
} else {
bp->recovery_state =
BNX2X_RECOVERY_DONE;
error_recovered++;
smp_mb();
}
bp->eth_stats.recoverable_error =
error_recovered;
bp->eth_stats.unrecoverable_error =
error_unrecovered;
/* Prepare parameters for function state transitions */
__set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
__set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is * scheduled on a general queue in order to prevent a dead lock.
*/ staticvoid bnx2x_sp_rtnl_task(struct work_struct *work)
{ struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
rtnl_lock();
if (!netif_running(bp->dev)) {
rtnl_unlock(); return;
}
if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { #ifdef BNX2X_STOP_ON_ERROR
BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" "you will need to reboot when done\n"); goto sp_rtnl_not_reset; #endif /* * Clear all pending SP commands as we are going to reset the * function anyway.
*/
bp->sp_rtnl_state = 0;
smp_mb();
bnx2x_parity_recover(bp);
rtnl_unlock(); return;
}
if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { #ifdef BNX2X_STOP_ON_ERROR
BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" "you will need to reboot when done\n"); goto sp_rtnl_not_reset; #endif
/* * Clear all pending SP commands as we are going to reset the * function anyway.
*/
bp->sp_rtnl_state = 0;
smp_mb();
/* Immediately indicate link as down */
bp->link_vars.link_up = 0;
bp->force_link_down = true;
netif_carrier_off(bp->dev);
BNX2X_ERR("Indicating link is down due to Tx-timeout\n");
bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); /* When ret value shows failure of allocation failure, * the nic is rebooted again. If open still fails, a error * message to notify the user.
*/ if (bnx2x_nic_load(bp, LOAD_NORMAL) == -ENOMEM) {
bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); if (bnx2x_nic_load(bp, LOAD_NORMAL))
BNX2X_ERR("Open the NIC fails again!\n");
}
rtnl_unlock(); return;
} #ifdef BNX2X_STOP_ON_ERROR
sp_rtnl_not_reset: #endif if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
bnx2x_after_function_update(bp); /* * in case of fan failure we need to reset id if the "stop on error" * debug flag is set, since we trying to prevent permanent overheating * damage
*/ if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
netif_device_detach(bp->dev);
bnx2x_close(bp->dev);
rtnl_unlock(); return;
}
if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
DP(BNX2X_MSG_SP, "sending set mcast vf pf channel message from rtnl sp-task\n");
bnx2x_vfpf_set_mcast(bp->dev);
} if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
&bp->sp_rtnl_state)){ if (netif_carrier_ok(bp->dev)) {
bnx2x_tx_disable(bp);
BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
}
}
if (!netif_running(bp->dev)) goto period_task_exit;
if (CHIP_REV_IS_SLOW(bp)) {
BNX2X_ERR("period task called on emulation, ignoring\n"); goto period_task_exit;
}
bnx2x_acquire_phy_lock(bp); /* * The barrier is needed to ensure the ordering between the writing to * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and * the reading here.
*/
smp_mb(); if (bp->port.pmf) {
bnx2x_period_func(&bp->link_params, &bp->link_vars);
staticbool bnx2x_prev_is_after_undi(struct bnx2x *bp)
{ /* UNDI marks its presence in DORQ - * it initializes CID offset for normal bell to 0x7
*/ if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
MISC_REGISTERS_RESET_REG_1_RST_DORQ)) returnfalse;
staticint bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
{ struct bnx2x_prev_path_list *tmp_list; int rc;
rc = down_interruptible(&bnx2x_prev_sem); if (rc) {
BNX2X_ERR("Received %d when tried to take lock\n", rc); return rc;
}
tmp_list = bnx2x_prev_path_get_entry(bp); if (tmp_list) {
tmp_list->aer = 1;
rc = 0;
} else {
BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
BP_PATH(bp));
}
rc = down_interruptible(&bnx2x_prev_sem); if (rc) {
BNX2X_ERR("Received %d when tried to take lock\n", rc); return rc;
}
/* Check whether the entry for this path already exists */
tmp_list = bnx2x_prev_path_get_entry(bp); if (tmp_list) { if (!tmp_list->aer) {
BNX2X_ERR("Re-Marking the path.\n");
} else {
DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
BP_PATH(bp));
tmp_list->aer = 0;
}
up(&bnx2x_prev_sem); return 0;
}
up(&bnx2x_prev_sem);
/* Create an entry for this path and add it */
tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); if (!tmp_list) {
BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); return -ENOMEM;
}
if (CHIP_IS_E1x(bp)) {
BNX2X_DEV_INFO("FLR not supported in E1/E1H\n"); return -EINVAL;
}
/* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */ if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
bp->common.bc_ver); return -EINVAL;
}
if (!pci_wait_for_pending_transaction(dev))
dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
staticint bnx2x_prev_unload_uncommon(struct bnx2x *bp)
{ int rc;
BNX2X_DEV_INFO("Uncommon unload Flow\n");
/* Test if previous unload process was already finished for this path */ if (bnx2x_prev_is_path_marked(bp)) return bnx2x_prev_mcp_done(bp);
BNX2X_DEV_INFO("Path is unmarked\n");
/* Cannot proceed with FLR if UNDI is loaded, since FW does not match */ if (bnx2x_prev_is_after_undi(bp)) goto out;
/* If function has FLR capabilities, and existing FW version matches * the one required, then FLR will be sufficient to clean any residue * left by previous driver
*/
rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
if (!rc) { /* fw version is good */
BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
rc = bnx2x_do_flr(bp);
}
if (!rc) { /* FLR was performed */
BNX2X_DEV_INFO("FLR successful\n"); return 0;
}
BNX2X_DEV_INFO("Could not FLR\n");
out: /* Close the MCP request, return failure*/
rc = bnx2x_prev_mcp_done(bp); if (!rc)
rc = BNX2X_PREV_WAIT_NEEDED;
/* It is possible a previous function received 'common' answer, * but hasn't loaded yet, therefore creating a scenario of * multiple functions receiving 'common' on the same path.
*/
BNX2X_DEV_INFO("Common unload Flow\n");
memset(&mac_vals, 0, sizeof(mac_vals));
if (bnx2x_prev_is_path_marked(bp)) return bnx2x_prev_mcp_done(bp);
reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
/* Reset should be performed after BRB is emptied */ if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
u32 timer_count = 1000;
/* Close the MAC Rx to prevent BRB from filling up */
bnx2x_prev_unload_close_mac(bp, &mac_vals);
/* close LLH filters for both ports towards the BRB */
bnx2x_set_rx_filter(&bp->link_params, 0);
bp->link_params.port ^= 1;
bnx2x_set_rx_filter(&bp->link_params, 0);
bp->link_params.port ^= 1;
/* Check if the UNDI driver was previously loaded */ if (bnx2x_prev_is_after_undi(bp)) {
prev_undi = true; /* clear the UNDI indication */
REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); /* clear possible idle check errors */
REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
} if (!CHIP_IS_E1x(bp)) /* block FW from writing to host */
REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
/* wait until BRB is empty */
tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); while (timer_count) {
u32 prev_brb = tmp_reg;
tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); if (!tmp_reg) break;
BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
/* reset timer as long as BRB actually gets emptied */ if (prev_brb > tmp_reg)
timer_count = 1000; else
timer_count--;
/* If UNDI resides in memory, manually increment it */ if (prev_undi)
bnx2x_prev_unload_undi_inc(bp, 1);
udelay(10);
}
if (!timer_count)
BNX2X_ERR("Failed to empty BRB, hope for the best\n");
}
/* No packets are in the pipeline, path is ready for reset */
bnx2x_reset_common(bp);
if (mac_vals.xmac_addr)
REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val); if (mac_vals.umac_addr[0])
REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]); if (mac_vals.umac_addr[1])
REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]); if (mac_vals.emac_addr)
REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val); if (mac_vals.bmac_addr) {
REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
}
hw_lock_val = REG_RD(bp, hw_lock_reg); if (hw_lock_val) { if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
(MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
}
BNX2X_DEV_INFO("Release Previously held hw lock\n");
REG_WR(bp, hw_lock_reg, 0xffffffff);
} else
BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
BNX2X_DEV_INFO("Release previously held alr\n");
bnx2x_release_alr(bp);
}
do { int aer = 0; /* Lock MCP using an unload request */
fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); if (!fw) {
BNX2X_ERR("MCP response failure, aborting\n");
rc = -EBUSY; break;
}
rc = down_interruptible(&bnx2x_prev_sem); if (rc) {
BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
rc);
} else { /* If Path is marked by EEH, ignore unload status */
aer = !!(bnx2x_prev_path_get_entry(bp) &&
bnx2x_prev_path_get_entry(bp)->aer);
up(&bnx2x_prev_sem);
}
/* non-common reply from MCP might require looping */
rc = bnx2x_prev_unload_uncommon(bp); if (rc != BNX2X_PREV_WAIT_NEEDED) break;
msleep(20);
} while (--time_counter);
if (!time_counter || rc) {
BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
rc = -EPROBE_DEFER;
}
/* Mark function if its port was used to boot from SAN */ if (bnx2x_port_after_undi(bp))
bp->link_params.feature_config_flags |=
FEATURE_CONFIG_BOOT_FROM_SAN;
/* Get the chip revision id and number. */ /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
val = REG_RD(bp, MISC_REG_CHIP_NUM);
id = ((val & 0xffff) << 16);
val = REG_RD(bp, MISC_REG_CHIP_REV);
id |= ((val & 0xf) << 12);
/* Metal is read from PCI regs, but we can't access >=0x400 from * the configuration space (so we need to reg_rd)
*/
val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
id |= (((val >> 24) & 0xf) << 4);
val = REG_RD(bp, MISC_REG_BOND_ID);
id |= (val & 0xf);
bp->common.chip_id = id;
/* force 57811 according to MISC register */ if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { if (CHIP_IS_57810(bp))
bp->common.chip_id = (CHIP_NUM_57811 << 16) |
(bp->common.chip_id & 0x0000FFFF); elseif (CHIP_IS_57810_MF(bp))
bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
(bp->common.chip_id & 0x0000FFFF);
bp->common.chip_id |= 0x1;
}
/* Set doorbell size */
bp->db_size = (1 << BNX2X_DB_SHIFT);
if (!CHIP_IS_E1x(bp)) {
val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); if ((val & 1) == 0)
val = REG_RD(bp, MISC_REG_PORT4MODE_EN); else
val = (val >> 1) & 1;
BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : "2_PORT_MODE");
bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
CHIP_2_PORT_MODE;
bp->link_params.feature_config_flags = 0;
val = SHMEM_RD(bp, dev_info.shared_feature_config.config); if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
bp->link_params.feature_config_flags |=
FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; else
bp->link_params.feature_config_flags &=
~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
bp->common.bc_ver = val;
BNX2X_DEV_INFO("bc_ver %X\n", val); if (val < BNX2X_BC_VER) { /* for now only warn
* later we might need to enforce this */
BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
BNX2X_BC_VER, val);
}
bp->link_params.feature_config_flags |=
(val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
/* IGU in normal mode - read CAM */ for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
igu_sb_id++) {
val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) continue;
fid = IGU_FID(val); if ((fid & IGU_FID_ENCODE_IS_PF)) { if ((fid & IGU_FID_PF_NUM_MASK) != pfid) continue; if (IGU_VEC(val) == 0) /* default status block */
bp->igu_dsb_id = igu_sb_id; else { if (bp->igu_base_sb == 0xff)
bp->igu_base_sb = igu_sb_id;
igu_sb_cnt++;
}
}
}
#ifdef CONFIG_PCI_MSI /* Due to new PF resource allocation by MFW T7.4 and above, it's * optional that number of CAM entries will not be equal to the value * advertised in PCI. * Driver should use the minimal value of both as the actual status * block count
*/
bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt); #endif
bp->link_params.multi_phy_config =
SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); /* If the device is capable of WoL, set the default state according * to the HW
*/
config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
(config & PORT_FEATURE_WOL_ENABLED));
/* * If connected directly, work with the internal PHY, otherwise, work * with the external PHY
*/
ext_phy_config =
SHMEM_RD(bp,
dev_info.port_hw_config[port].external_phy_config);
ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
bp->mdio.prtad = bp->port.phy_addr;
/* Configure link feature according to nvram value */
eee_mode = (((SHMEM_RD(bp, dev_info.
port_feature_config[port].eee_power_mode)) &
PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
EEE_MODE_ENABLE_LPI |
EEE_MODE_OUTPUT_TIME;
} else {
bp->link_params.eee_mode = 0;
}
}
void bnx2x_get_iscsi_info(struct bnx2x *bp)
{
u32 no_flags = NO_ISCSI_FLAG; int port = BP_PORT(bp);
u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
drv_lic_key[port].max_iscsi_conn);
if (!CNIC_SUPPORT(bp)) {
bp->flags |= no_flags; return;
}
/* Get the number of maximum allowed iSCSI connections */
bp->cnic_eth_dev.max_iscsi_conn =
(max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
(cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
count++;
}
}
} else { /* SF */ int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
for (port = 0; port < port_cnt; port++) {
u32 lic = SHMEM_RD(bp,
drv_lic_key[port].max_fcoe_conn) ^
FW_ENCODE_32BIT_PATTERN; if (lic)
count++;
}
}
return count;
}
staticvoid bnx2x_get_fcoe_info(struct bnx2x *bp)
{ int port = BP_PORT(bp); int func = BP_ABS_FUNC(bp);
u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
drv_lic_key[port].max_fcoe_conn);
u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
if (!CNIC_SUPPORT(bp)) {
bp->flags |= NO_FCOE_FLAG; return;
}
/* Get the number of maximum allowed FCoE connections */
bp->cnic_eth_dev.max_fcoe_conn =
(max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
/* Calculate the number of maximum allowed FCoE tasks */
bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
/* check if FCoE resources must be shared between different functions */ if (num_fcoe_func)
bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
/* Read the WWN: */ if (!IS_MF(bp)) { /* Port info */
bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
SHMEM_RD(bp,
dev_info.port_hw_config[port].
fcoe_wwn_port_name_upper);
bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
SHMEM_RD(bp,
dev_info.port_hw_config[port].
fcoe_wwn_port_name_lower);
/* Node info */
bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
SHMEM_RD(bp,
dev_info.port_hw_config[port].
fcoe_wwn_node_name_upper);
bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
SHMEM_RD(bp,
dev_info.port_hw_config[port].
fcoe_wwn_node_name_lower);
} elseif (!IS_MF_SD(bp)) { /* Read the WWN info only if the FCoE feature is enabled for * this function.
*/ if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
bnx2x_get_ext_wwn_info(bp, func);
} else { if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
bnx2x_get_ext_wwn_info(bp, func);
}
/* * If maximum allowed number of connections is zero - * disable the feature.
*/ if (!bp->cnic_eth_dev.max_fcoe_conn) {
bp->flags |= NO_FCOE_FLAG;
eth_zero_addr(bp->fip_mac);
}
}
staticvoid bnx2x_get_cnic_info(struct bnx2x *bp)
{ /* * iSCSI may be dynamically disabled but reading * info here we will decrease memory usage by driver * if the feature is disabled for good
*/
bnx2x_get_iscsi_info(bp);
bnx2x_get_fcoe_info(bp);
}
staticvoid bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
{
u32 val, val2; int func = BP_ABS_FUNC(bp); int port = BP_PORT(bp);
u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
u8 *fip_mac = bp->fip_mac;
if (IS_MF(bp)) { /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or * FCoE MAC then the appropriate feature should be disabled. * In non SD mode features configuration comes from struct * func_ext_config.
*/ if (!IS_MF_SD(bp)) {
u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
val2 = MF_CFG_RD(bp, func_ext_config[func].
iscsi_mac_addr_upper);
val = MF_CFG_RD(bp, func_ext_config[func].
iscsi_mac_addr_lower);
bnx2x_set_mac_buf(iscsi_mac, val, val2);
BNX2X_DEV_INFO
("Read iSCSI MAC: %pM\n", iscsi_mac);
} else {
bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
}
} else { /* SD MODE */ if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { /* use primary mac as iscsi mac */
memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
BNX2X_DEV_INFO("SD ISCSI MODE\n");
BNX2X_DEV_INFO
("Read iSCSI MAC: %pM\n", iscsi_mac);
} elseif (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) { /* use primary mac as fip mac */
memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
BNX2X_DEV_INFO("SD FCoE MODE\n");
BNX2X_DEV_INFO
("Read FIP MAC: %pM\n", fip_mac);
}
}
/* If this is a storage-only interface, use SAN mac as * primary MAC. Notice that for SD this is already the case, * as the SAN mac was copied from the primary MAC.
*/ if (IS_MF_FCOE_AFEX(bp))
eth_hw_addr_set(bp->dev, fip_mac);
} else {
val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
iscsi_mac_upper);
val = SHMEM_RD(bp, dev_info.port_hw_config[port].
iscsi_mac_lower);
bnx2x_set_mac_buf(iscsi_mac, val, val2);
/* Disable iSCSI OOO if MAC configuration is invalid. */ if (!is_valid_ether_addr(iscsi_mac)) {
bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
eth_zero_addr(iscsi_mac);
}
/* Disable FCoE if MAC configuration is invalid. */ if (!is_valid_ether_addr(fip_mac)) {
bp->flags |= NO_FCOE_FLAG;
eth_zero_addr(bp->fip_mac);
}
}
staticvoid bnx2x_get_mac_hwinfo(struct bnx2x *bp)
{
u32 val, val2; int func = BP_ABS_FUNC(bp); int port = BP_PORT(bp);
u8 addr[ETH_ALEN] = {};
/* Zero primary MAC configuration */
eth_hw_addr_set(bp->dev, addr);
if (BP_NOMCP(bp)) {
BNX2X_ERROR("warning: random MAC workaround active\n");
eth_hw_addr_random(bp->dev);
} elseif (IS_MF(bp)) {
val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
(val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) {
bnx2x_set_mac_buf(addr, val, val2);
eth_hw_addr_set(bp->dev, addr);
}
if (CNIC_SUPPORT(bp))
bnx2x_get_cnic_mac_hwinfo(bp);
} else { /* in SF read MACs from port configuration */
val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
bnx2x_set_mac_buf(addr, val, val2);
eth_hw_addr_set(bp->dev, addr);
if (CNIC_SUPPORT(bp))
bnx2x_get_cnic_mac_hwinfo(bp);
}
if (!BP_NOMCP(bp)) { /* Read physical port identifier from shmem */
val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
bp->flags |= HAS_PHYS_PORT_ID;
}
if (!is_valid_ether_addr(bp->dev->dev_addr))
dev_err(&bp->pdev->dev, "bad Ethernet MAC address configuration: %pM\n" "change it manually before bringing up the appropriate network interface\n",
bp->dev->dev_addr);
}
staticbool bnx2x_get_dropless_info(struct bnx2x *bp)
{ int tmp;
u32 cfg;
/* do not allow device reset during IGU info processing */
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { int tout = 5000;
BNX2X_DEV_INFO("FORCING Normal Mode\n");
val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
tout--;
usleep_range(1000, 2000);
}
if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
dev_err(&bp->pdev->dev, "FORCING Normal Mode failed!!!\n");
bnx2x_release_hw_lock(bp,
HW_LOCK_RESOURCE_RESET); return -EPERM;
}
}
if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
} else
BNX2X_DEV_INFO("IGU Normal Mode\n");
rc = bnx2x_get_igu_cam_info(bp);
bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); if (rc) return rc;
}
/* * set base FW non-default (fast path) status block id, this value is * used to initialize the fw_sb_id saved on the fp/queue structure to * determine the id used by the FW.
*/ if (CHIP_IS_E1x(bp))
bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); else/* * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of * the same queue are indicated on the same IGU SB). So we prefer * FW and IGU SBs to be the same value.
*/
bp->base_fw_ndsb = bp->igu_base_sb;
if (SHMEM2_HAS(bp, mf_cfg_addr))
bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); else
bp->common.mf_cfg_base = bp->common.shmem_base +
offsetof(struct shmem_region, func_mb) +
E1H_FUNC_MAX * sizeof(struct drv_func_mb); /* * get mf configuration: * 1. Existence of MF configuration * 2. MAC address must be legal (check only upper bytes) * for Switch-Independent mode; * OVLAN must be legal for Switch-Dependent mode * 3. SF_MODE configures specific MF mode
*/ if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { /* get mf configuration */
val = SHMEM_RD(bp,
dev_info.shared_feature_config.config);
val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
switch (val) { case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
validate_set_si_mode(bp); break; case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: if ((!CHIP_IS_E1x(bp)) &&
(MF_CFG_RD(bp, func_mf_config[func].
mac_upper) != 0xffff) &&
(SHMEM2_HAS(bp,
afex_driver_support))) {
bp->mf_mode = MULTI_FUNCTION_AFEX;
bp->mf_config[vn] = MF_CFG_RD(bp,
func_mf_config[func].config);
} else {
BNX2X_DEV_INFO("can not configure afex mode\n");
} break; case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: /* get OV configuration */
val = MF_CFG_RD(bp,
func_mf_config[FUNC_0].e1hov_tag);
val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
bp->mf_mode = MULTI_FUNCTION_SD;
bp->mf_config[vn] = MF_CFG_RD(bp,
func_mf_config[func].config);
} else
BNX2X_DEV_INFO("illegal OV for SD\n"); break; case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE:
bp->mf_mode = MULTI_FUNCTION_SD;
bp->mf_sub_mode = SUB_MF_MODE_BD;
bp->mf_config[vn] =
MF_CFG_RD(bp,
func_mf_config[func].config);
if (SHMEM2_HAS(bp, mtu_size)) { int mtu_idx = BP_FW_MB_IDX(bp);
u16 mtu_size;
u32 mtu;
mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);
mtu_size = (u16)mtu;
DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n",
mtu_size, mtu);
BNX2X_DEV_INFO("%s function mode\n",
IS_MF(bp) ? "multi" : "single");
switch (bp->mf_mode) { case MULTI_FUNCTION_SD:
val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
FUNC_MF_CFG_E1HOV_TAG_MASK; if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
bp->mf_ov = val;
bp->path_has_ovlan = true;
BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
func, bp->mf_ov, bp->mf_ov);
} elseif ((bp->mf_sub_mode == SUB_MF_MODE_UFP) ||
(bp->mf_sub_mode == SUB_MF_MODE_BD)) {
dev_err(&bp->pdev->dev, "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
func);
bp->path_has_ovlan = true;
} else {
dev_err(&bp->pdev->dev, "No valid MF OV for func %d, aborting\n",
func); return -EPERM;
} break; case MULTI_FUNCTION_AFEX:
BNX2X_DEV_INFO("func %d is in MF afex mode\n", func); break; case MULTI_FUNCTION_SI:
BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
func); break; default: if (vn) {
dev_err(&bp->pdev->dev, "VN %d is in a single function mode, aborting\n",
vn); return -EPERM;
} break;
}
/* check if other port on the path needs ovlan: * Since MF configuration is shared between ports * Possible mixed modes are only * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
*/ if (CHIP_MODE_IS_4_PORT(bp) &&
!bp->path_has_ovlan &&
!IS_MF(bp) &&
bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
u8 other_port = !BP_PORT(bp);
u8 other_func = BP_PATH(bp) + 2*other_port;
val = MF_CFG_RD(bp,
func_mf_config[other_func].e1hov_tag); if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
bp->path_has_ovlan = true;
}
}
/* adjust igu_sb_cnt to MF for E1H */ if (CHIP_IS_E1H(bp) && IS_MF(bp))
bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
/* need to reset chip if undi was active */ if (IS_PF(bp) && !BP_NOMCP(bp)) { /* init fw_seq */
bp->fw_seq =
SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
DRV_MSG_SEQ_NUMBER_MASK;
BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
/* make sure that the numbers are in the right granularity */
bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
/* We need at least one default status block for slow-path events, * second status block for the L2 queue, and a third status block for * CNIC if supported.
*/ if (IS_VF(bp))
bp->min_msix_vec_cnt = 1; elseif (CNIC_SUPPORT(bp))
bp->min_msix_vec_cnt = 3; else/* PF w/o cnic */
bp->min_msix_vec_cnt = 2;
BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
bp->dump_preset_idx = 1;
return rc;
}
/**************************************************************************** * General service functions
****************************************************************************/
/* * net_device service functions
*/
/* called with rtnl_lock */ staticint bnx2x_open(struct net_device *dev)
{ struct bnx2x *bp = netdev_priv(dev); int rc;
bp->stats_init = true;
netif_carrier_off(dev);
bnx2x_set_power_state(bp, PCI_D0);
/* If parity had happen during the unload, then attentions * and/or RECOVERY_IN_PROGRES may still be set. In this case we * want the first function loaded on the current engine to * complete the recovery. * Parity recovery is only relevant for PF driver.
*/ if (IS_PF(bp)) { int other_engine = BP_PATH(bp) ? 0 : 1; bool other_load_status, load_status; bool global = false;
other_load_status = bnx2x_get_load_status(bp, other_engine);
load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
bnx2x_chk_parity_attn(bp, &global, true)) { do { /* If there are attentions and they are in a * global blocks, set the GLOBAL_RESET bit * regardless whether it will be this function * that will complete the recovery or not.
*/ if (global)
bnx2x_set_reset_global(bp);
/* Only the first function on the current * engine should try to recover in open. In case * of attentions in global blocks only the first * in the chip should try to recover.
*/ if ((!load_status &&
(!global || !other_load_status)) &&
bnx2x_trylock_leader_lock(bp) &&
!bnx2x_leader_reset(bp)) {
netdev_info(bp->dev, "Recovered in open\n"); break;
}
/* recovery has failed... */
bnx2x_set_power_state(bp, PCI_D3hot);
bp->recovery_state = BNX2X_RECOVERY_FAILED;
BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" "If you still see this message after a few retries then power cycle is required.\n");
INIT_LIST_HEAD(&p->mcast_list);
netdev_for_each_mc_addr(ha, bp->dev) { if (!offset) {
current_mcast_group =
(struct bnx2x_mcast_list_elem_group *)
__get_free_page(GFP_ATOMIC); if (!current_mcast_group) {
bnx2x_free_mcast_macs_list(mcast_group_list);
BNX2X_ERR("Failed to allocate mc MAC list\n"); return -ENOMEM;
}
list_add(¤t_mcast_group->mcast_group_link,
mcast_group_list);
}
mc_mac = ¤t_mcast_group->mcast_elems[offset];
mc_mac->mac = bnx2x_mc_addr(ha);
list_add_tail(&mc_mac->link, &p->mcast_list);
offset++; if (offset == MCAST_ELEMS_PER_PG)
offset = 0;
}
p->mcast_list_len = mc_count; return 0;
}
/** * bnx2x_set_uc_list - configure a new unicast MACs list. * * @bp: driver handle * * We will use zero (0) as a MAC type for these MACs.
*/ staticint bnx2x_set_uc_list(struct bnx2x *bp)
{ int rc; struct net_device *dev = bp->dev; struct netdev_hw_addr *ha; struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; unsignedlong ramrod_flags = 0;
/* First schedule a cleanup up of old configuration */
rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); if (rc < 0) {
BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); return rc;
}
netdev_for_each_uc_addr(ha, dev) {
rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
BNX2X_UC_LIST_MAC, &ramrod_flags); if (rc == -EEXIST) {
DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); /* do not treat adding same MAC as error */
rc = 0;
/* first, clear all configured multicast MACs */
rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); if (rc < 0) {
BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); return rc;
}
/* then, configure a new MACs list */ if (netdev_mc_count(dev)) {
rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list); if (rc) return rc;
/* Now add the new MACs */
rc = bnx2x_config_mcast(bp, &rparam,
BNX2X_MCAST_CMD_ADD); if (rc < 0)
BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
rc);
/* On older adapters, we need to flush and re-add filters */ if (CHIP_IS_E1x(bp)) return bnx2x_set_mc_list_e1x(bp);
rparam.mcast_obj = &bp->mcast_obj;
if (netdev_mc_count(dev)) {
rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list); if (rc) return rc;
/* Override the curently configured set of mc filters */
rc = bnx2x_config_mcast(bp, &rparam,
BNX2X_MCAST_CMD_SET); if (rc < 0)
BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
rc);
bnx2x_free_mcast_macs_list(&mcast_group_list);
} else { /* If no mc addresses are required, flush the configuration */
rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); if (rc < 0)
BNX2X_ERR("Failed to clear multicast configuration %d\n",
rc);
}
return rc;
}
/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ staticvoid bnx2x_set_rx_mode(struct net_device *dev)
{ struct bnx2x *bp = netdev_priv(dev);
if (bp->state != BNX2X_STATE_OPEN) {
DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); return;
} else { /* Schedule an SP task to handle rest of change */
bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
NETIF_MSG_IFUP);
}
}
/* Schedule the rx_mode command */ if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
netif_addr_unlock_bh(bp->dev); return;
}
if (IS_PF(bp)) {
bnx2x_set_storm_rx_mode(bp);
netif_addr_unlock_bh(bp->dev);
} else { /* VF will need to request the PF to make this change, and so * the VF needs to release the bottom-half lock prior to the * request (as it will likely require sleep on the VF side)
*/
netif_addr_unlock_bh(bp->dev);
bnx2x_vfpf_storm_rx_mode(bp);
}
}
/* called with rtnl_lock */ staticint bnx2x_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
{ struct bnx2x *bp = netdev_priv(netdev);
u16 value; int rc;
/* called with rtnl_lock */ staticint bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
u16 addr, u16 value)
{ struct bnx2x *bp = netdev_priv(netdev); int rc;
static netdev_features_t bnx2x_features_check(struct sk_buff *skb, struct net_device *dev,
netdev_features_t features)
{ /* * A skb with gso_size + header length > 9700 will cause a * firmware panic. Drop GSO support. * * Eventually the upper layer should not pass these packets down. * * For speed, if the gso_size is <= 9000, assume there will * not be 700 bytes of headers and pass it through. Only do a * full (slow) validation if the gso_size is > 9000. * * (Due to the way SKB_BY_FRAGS works this will also do a full * validation in that case.)
*/ if (unlikely(skb_is_gso(skb) &&
(skb_shinfo(skb)->gso_size > 9000) &&
!skb_gso_validate_mac_len(skb, 9700)))
features &= ~NETIF_F_GSO_MASK;
features = vlan_features_check(skb, features); return vxlan_features_check(skb, features);
}
rc = dma_set_mask_and_coherent(&bp->pdev->dev, DMA_BIT_MASK(64)); if (rc) {
dev_err(&bp->pdev->dev, "System does not support DMA, aborting\n"); goto err_out_release;
}
/* In E1/E1H use pci device function given by kernel. * In E2/E3 read physical function from ME register since these chips * support Physical Device Assignment where kernel BDF maybe arbitrary * (depending on hypervisor).
*/ if (chip_is_e1x) {
bp->pf_num = PCI_FUNC(pdev->devfn);
} else { /* chip is E2/3*/
pci_read_config_dword(bp->pdev,
PCICFG_ME_REGISTER, &pci_cfg_dword);
bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
ME_REG_ABS_PF_NUM_SHIFT);
}
BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
/* Set PCIe reset type to fundamental for EEH recovery */
pdev->needs_freset = 1;
/* * Clean the following indirect addresses for all functions since it * is not used by the driver.
*/ if (IS_PF(bp)) {
REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
/* Enable internal target-read (in case we are probed after PF * FLR). Must be done prior to any BAR read access. Only for * 57712 and up
*/ if (!chip_is_e1x)
REG_WR(bp,
PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
}
if (IS_PF(bp)) { if (chip_is_e1x)
bp->accept_any_vlan = true; else
dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
} /* For VF we'll know whether to enable VLAN filtering after * getting a response to CHANNEL_TLV_ACQUIRE from PF.
*/
/* Make sure none of the offsets and sizes make us read beyond
* the end of the firmware data */ for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
offset = be32_to_cpu(sections[i].offset);
len = be32_to_cpu(sections[i].len); if (offset + len > firmware->size) {
BNX2X_ERR("Section %d length is out of bounds\n", i); return -EINVAL;
}
}
for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { if (be16_to_cpu(ops_offsets[i]) > num_ops) {
BNX2X_ERR("Section offset %d is out of bounds\n", i); return -EINVAL;
}
}
/* must be called after sriov-enable */ staticint bnx2x_set_qm_cid_count(struct bnx2x *bp)
{ int cid_count = BNX2X_L2_MAX_CID(bp);
if (IS_SRIOV(bp))
cid_count += BNX2X_VF_CIDS;
if (CNIC_SUPPORT(bp))
cid_count += CNIC_CID_MAX;
return roundup(cid_count, QM_CID_ROUND);
}
/** * bnx2x_get_num_non_def_sbs - return the number of none default SBs * @pdev: pci device * @cnic_cnt: count *
*/ staticint bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
{ int index;
u16 control = 0;
/* * If MSI-X is not supported - return number of SBs needed to support * one fast path queue: one FP queue + SB for CNIC
*/ if (!pdev->msix_cap) {
dev_info(&pdev->dev, "no msix capability found\n"); return 1 + cnic_cnt;
}
dev_info(&pdev->dev, "msix capability found\n");
/* * The value in the PCI configuration space is the index of the last * entry, namely one less than the actual size of the table, which is * exactly what we want to return from this function: number of all SBs * without the default SB. * For VFs there is no default SB, then we return (index+1).
*/
pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
index = control & PCI_MSIX_FLAGS_QSIZE;
return index;
}
staticint set_max_cos_est(int chip_id)
{ switch (chip_id) { case BCM57710: case BCM57711: case BCM57711E: return BNX2X_MULTI_TX_COS_E1X; case BCM57712: case BCM57712_MF: return BNX2X_MULTI_TX_COS_E2_E3A0; case BCM57800: case BCM57800_MF: case BCM57810: case BCM57810_MF: case BCM57840_4_10: case BCM57840_2_20: case BCM57840_O: case BCM57840_MFO: case BCM57840_MF: case BCM57811: case BCM57811_MF: return BNX2X_MULTI_TX_COS_E3B0; case BCM57712_VF: case BCM57800_VF: case BCM57810_VF: case BCM57840_VF: case BCM57811_VF: return 1; default:
pr_err("Unknown board_type (%d), aborting\n", chip_id); return -ENODEV;
}
}
staticint set_is_vf(int chip_id)
{ switch (chip_id) { case BCM57712_VF: case BCM57800_VF: case BCM57810_VF: case BCM57840_VF: case BCM57811_VF: returntrue; default: returnfalse;
}
}
/* FW workaround for setting drift */ staticint bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir, int best_val, int best_period)
{ struct bnx2x_func_state_params func_params = {NULL}; struct bnx2x_func_set_timesync_params *set_timesync_params =
&func_params.params.set_timesync;
/* Prepare parameters for function state transitions */
__set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
__set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
staticint bnx2x_init_one(struct pci_dev *pdev, conststruct pci_device_id *ent)
{ struct net_device *dev = NULL; struct bnx2x *bp; int rc, max_non_def_sbs; int rx_count, tx_count, rss_count, doorbell_size; int max_cos_est; bool is_vf; int cnic_cnt;
/* Management FW 'remembers' living interfaces. Allow it some time * to forget previously living interfaces, allowing a proper re-load.
*/ if (is_kdump_kernel()) {
ktime_t now = ktime_get_boottime();
ktime_t fw_ready_time = ktime_set(5, 0);
if (ktime_before(now, fw_ready_time))
msleep(ktime_ms_delta(fw_ready_time, now));
}
/* An estimated maximum supported CoS number according to the chip * version. * We will try to roughly estimate the maximum number of CoSes this chip * may support in order to minimize the memory allocated for Tx * netdev_queue's. This number will be accurately calculated during the * initialization of bp->max_cos based on the chip versions AND chip * revision in the bnx2x_init_bp().
*/
max_cos_est = set_max_cos_est(ent->driver_data); if (max_cos_est < 0) return max_cos_est;
is_vf = set_is_vf(ent->driver_data);
cnic_cnt = is_vf ? 0 : 1;
/* add another SB for VF as it has no default SB */
max_non_def_sbs += is_vf ? 1 : 0;
/* Maximum number of RSS queues: one IGU SB goes to CNIC */
rss_count = max_non_def_sbs - cnic_cnt;
if (rss_count < 1) return -EINVAL;
/* Maximum number of netdev Rx queues: RSS + FCoE L2 */
rx_count = rss_count + cnic_cnt;
/* Maximum number of netdev Tx queues: * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
*/
tx_count = rss_count * max_cos_est + cnic_cnt;
/* dev zeroed in init_etherdev */
dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); if (!dev) return -ENOMEM;
bp = netdev_priv(dev);
bp->flags = 0; if (is_vf)
bp->flags |= IS_VF_FLAG;
BNX2X_DEV_INFO("This is a %s function\n",
IS_PF(bp) ? "physical" : "virtual");
BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
tx_count, rx_count);
rc = bnx2x_init_bp(bp); if (rc) goto init_one_exit;
/* Map doorbells here as we need the real value of bp->max_cos which * is initialized in bnx2x_init_bp() to determine the number of * l2 connections.
*/ if (IS_VF(bp)) {
bp->doorbells = bnx2x_vf_doorbells(bp);
rc = bnx2x_vf_pci_alloc(bp); if (rc) goto init_one_freemem;
} else {
doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT); if (doorbell_size > pci_resource_len(pdev, 2)) {
dev_err(&bp->pdev->dev, "Cannot map doorbells, bar size too small, aborting\n");
rc = -ENOMEM; goto init_one_freemem;
}
bp->doorbells = ioremap(pci_resource_start(pdev, 2),
doorbell_size);
} if (!bp->doorbells) {
dev_err(&bp->pdev->dev, "Cannot map doorbell space, aborting\n");
rc = -ENOMEM; goto init_one_freemem;
}
if (IS_VF(bp)) {
rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count); if (rc) goto init_one_freemem;
#ifdef CONFIG_BNX2X_SRIOV /* VF with OLD Hypervisor or old PF do not support filtering */ if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) {
dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
} #endif
}
/* Enable SRIOV if capability found in configuration space */
rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS); if (rc) goto init_one_freemem;
/* disable FCOE L2 queue for E1x*/ if (CHIP_IS_E1x(bp))
bp->flags |= NO_FCOE_FLAG;
/* Set bp->num_queues for MSI-X mode*/
bnx2x_set_num_queues(bp);
/* Configure interrupt mode: try to enable MSI-X/MSI if * needed.
*/
rc = bnx2x_set_int_mode(bp); if (rc) {
dev_err(&pdev->dev, "Cannot set interrupts\n"); goto init_one_freemem;
}
BNX2X_DEV_INFO("set interrupts successfully\n");
/* register the net device */
rc = register_netdev(dev); if (rc) {
dev_err(&pdev->dev, "Cannot register net device\n"); goto init_one_freemem;
}
BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
if (!NO_FCOE(bp)) { /* Add storage MAC address */
rtnl_lock();
dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
rtnl_unlock();
}
BNX2X_DEV_INFO( "%s (%c%d) PCI-E found at mem %lx, IRQ %d, node addr %pM\n",
board_info[ent->driver_data].name,
(CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
dev->base_addr, bp->pdev->irq, dev->dev_addr);
pcie_print_link_status(bp->pdev);
if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
return 0;
init_one_freemem:
bnx2x_free_mem_bp(bp);
init_one_exit: if (bp->regview)
iounmap(bp->regview);
if (IS_PF(bp) && bp->doorbells)
iounmap(bp->doorbells);
free_netdev(dev);
if (atomic_read(&pdev->enable_cnt) == 1)
pci_release_regions(pdev);
/* Close the interface - either directly or implicitly */ if (remove_netdev) {
unregister_netdev(dev);
} else {
rtnl_lock();
dev_close(dev);
rtnl_unlock();
}
bnx2x_iov_remove_one(bp);
/* Power on: we can't let PCI layer write to us while we are in D3 */ if (IS_PF(bp)) {
bnx2x_set_power_state(bp, PCI_D0);
bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED);
/* Set endianity registers to reset values in case next driver * boots in different endianty environment.
*/
bnx2x_reset_endianity(bp);
}
/* Disable MSI/MSI-X */
bnx2x_disable_msi(bp);
/* Power off */ if (IS_PF(bp))
bnx2x_set_power_state(bp, PCI_D3hot);
/* Make sure RESET task is not scheduled before continuing */
cancel_delayed_work_sync(&bp->sp_rtnl_task);
/* send message via vfpf channel to release the resources of this vf */ if (IS_VF(bp))
bnx2x_vfpf_release(bp);
/* Assumes no further PCIe PM changes will occur */ if (system_state == SYSTEM_POWER_OFF) {
pci_wake_from_d3(pdev, bp->wol);
pci_set_power_state(pdev, PCI_D3hot);
}
if (remove_netdev) { if (bp->regview)
iounmap(bp->regview);
/* For vfs, doorbells are part of the regview and were unmapped * along with it. FW is only loaded by PF.
*/ if (IS_PF(bp)) { if (bp->doorbells)
iounmap(bp->doorbells);
/** * bnx2x_io_error_detected - called when PCI error is detected * @pdev: Pointer to PCI device * @state: The current pci connection state * * This function is called after a PCI bus error affecting * this device has been detected.
*/ static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
pci_channel_state_t state)
{ struct net_device *dev = pci_get_drvdata(pdev); struct bnx2x *bp = netdev_priv(dev);
rtnl_lock();
BNX2X_ERR("IO error detected\n");
netif_device_detach(dev);
if (state == pci_channel_io_perm_failure) {
rtnl_unlock(); return PCI_ERS_RESULT_DISCONNECT;
}
if (netif_running(dev))
bnx2x_eeh_nic_unload(bp);
bnx2x_prev_path_mark_eeh(bp);
pci_disable_device(pdev);
rtnl_unlock();
/* Request a slot reset */ return PCI_ERS_RESULT_NEED_RESET;
}
/** * bnx2x_io_slot_reset - called after the PCI bus has been reset * @pdev: Pointer to PCI device * * Restart the card from scratch, as if from a cold-boot.
*/ static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
{ struct net_device *dev = pci_get_drvdata(pdev); struct bnx2x *bp = netdev_priv(dev); int i;
rtnl_lock();
BNX2X_ERR("IO slot reset initializing...\n"); if (pci_enable_device(pdev)) {
dev_err(&pdev->dev, "Cannot re-enable PCI device after reset\n");
rtnl_unlock(); return PCI_ERS_RESULT_DISCONNECT;
}
if (netif_running(dev))
bnx2x_set_power_state(bp, PCI_D0);
if (netif_running(dev)) {
BNX2X_ERR("IO slot reset --> driver unload\n");
/* MCP should have been reset; Need to wait for validity */ if (bnx2x_init_shmem(bp)) {
rtnl_unlock(); return PCI_ERS_RESULT_DISCONNECT;
}
if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
u32 v;
v = SHMEM2_RD(bp,
drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
}
bnx2x_drain_tx_queues(bp);
bnx2x_send_unload_req(bp, UNLOAD_RECOVERY); if (!bp->nic_stopped) {
bnx2x_netif_stop(bp, 1);
bnx2x_del_all_napi(bp);
if (CNIC_LOADED(bp))
bnx2x_del_all_napi_cnic(bp);
bnx2x_free_irq(bp);
bp->nic_stopped = true;
}
/* Report UNLOAD_DONE to MCP */
bnx2x_send_unload_done(bp, true);
bp->sp_state = 0;
bp->port.pmf = 0;
bnx2x_prev_unload(bp);
/* We should have reseted the engine, so It's fair to * assume the FW will no longer write to the bnx2x driver.
*/
bnx2x_squeeze_objects(bp);
bnx2x_free_skbs(bp);
for_each_rx_queue(bp, i)
bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
bnx2x_free_fp_mem(bp);
bnx2x_free_mem(bp);
bp->state = BNX2X_STATE_CLOSED;
}
rtnl_unlock();
return PCI_ERS_RESULT_RECOVERED;
}
/** * bnx2x_io_resume - called when traffic can start flowing again * @pdev: Pointer to PCI device * * This callback is called when the error recovery driver tells us that * its OK to resume normal operation.
*/ staticvoid bnx2x_io_resume(struct pci_dev *pdev)
{ struct net_device *dev = pci_get_drvdata(pdev); struct bnx2x *bp = netdev_priv(dev);
if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); return;
}
if (netif_running(dev)) { if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
netdev_err(bp->dev, "Error during driver initialization, try unloading/reloading the driver\n"); goto done;
}
}
/* Don't remove the netdevice, as there are scenarios which will cause * the kernel to hang, e.g., when trying to remove bnx2i while the * rootfs is mounted from SAN.
*/
__bnx2x_remove(pdev, dev, bp, false);
}
/* count denotes the number of new completions we have seen */ staticvoid bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
{ struct eth_spe *spe; int cxt_index, cxt_offset;
#ifdef BNX2X_STOP_ON_ERROR if (unlikely(bp->panic)) return; #endif
/* Set validation for iSCSI L2 client before sending SETUP * ramrod
*/ if (type == ETH_CONNECTION_TYPE) { if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
ILT_PAGE_CIDS;
cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
(cxt_index * ILT_PAGE_CIDS);
bnx2x_set_ctx_validation(bp,
&bp->context[cxt_index].
vcxt[cxt_offset].eth,
BNX2X_ISCSI_ETH_CID(bp));
}
}
/* * There may be not more than 8 L2, not more than 8 L5 SPEs * and in the air. We also check that number of outstanding * COMMON ramrods is not more than the EQ and SPQ can * accommodate.
*/ if (type == ETH_CONNECTION_TYPE) { if (!atomic_read(&bp->cq_spq_left)) break; else
atomic_dec(&bp->cq_spq_left);
} elseif (type == NONE_CONNECTION_TYPE) { if (!atomic_read(&bp->eq_spq_left)) break; else
atomic_dec(&bp->eq_spq_left);
} elseif ((type == ISCSI_CONNECTION_TYPE) ||
(type == FCOE_CONNECTION_TYPE)) { if (bp->cnic_spq_pending >=
bp->cnic_eth_dev.max_kwqe_pending) break; else
bp->cnic_spq_pending++;
} else {
BNX2X_ERR("Unknown SPE type: %d\n", type);
bnx2x_panic(); break;
}
/* first we tell CNIC and only then we count this as a completion */
ctl.cmd = CNIC_CTL_COMPLETION_CMD;
ctl.data.comp.cid = cid;
ctl.data.comp.error = err;
/* Called with netif_addr_lock_bh() taken. * Sets an rx_mode config for an iSCSI ETH client. * Doesn't block. * Completion should be checked outside.
*/ staticvoid bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
{ unsignedlong accept_flags = 0, ramrod_flags = 0;
u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
if (start) { /* Start accepting on iSCSI L2 ring. Accept all multicasts * because it's the only way for UIO Queue to accept * multicasts (in non-promiscuous mode only one Queue per * function will receive multicast packets (leading in our * case).
*/
__set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
__set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
__set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
__set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
/* Clear STOP_PENDING bit if START is requested */
clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
} else /* Clear START_PENDING bit if STOP is requested */
clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
/* bits to wait on */
__set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
__set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
if (!bnx2x_wait_sp_comp(bp, sp_bits))
BNX2X_ERR("rx_mode completion timed out!\n");
break;
}
/* rtnl_lock is held. */ case DRV_CTL_STOP_L2_CMD: { unsignedlong sp_bits = 0;
/* Stop accepting on iSCSI L2 ring */
netif_addr_lock_bh(dev);
bnx2x_set_iscsi_eth_rx_mode(bp, false);
netif_addr_unlock_bh(dev);
/* bits to wait on */
__set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
__set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
if (!bnx2x_wait_sp_comp(bp, sp_bits))
BNX2X_ERR("rx_mode completion timed out!\n");
barrier();
/* Unset iSCSI L2 MAC */
rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
BNX2X_ISCSI_ETH_MAC, true); break;
} case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { int count = ctl->data.credit.credit_count;
smp_mb__before_atomic();
atomic_add(count, &bp->cq_spq_left);
smp_mb__after_atomic(); break;
} case DRV_CTL_ULP_REGISTER_CMD: { int ulp_type = ctl->data.register_data.ulp_type;
if (CHIP_IS_E3(bp)) { int idx = BP_FW_MB_IDX(bp);
u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); int path = BP_PATH(bp); int port = BP_PORT(bp); int i;
u32 scratch_offset;
u32 *host_addr;
/* first write capability to shmem2 */ if (ulp_type == CNIC_ULP_ISCSI)
cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; elseif (ulp_type == CNIC_ULP_FCOE)
cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0])) goto out;
DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n");
tbl = kmalloc(sizeof(*tbl), GFP_KERNEL); if (!tbl) {
BNX2X_ERR("Failed to allocate fc_npiv table\n"); goto out;
}
offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]); if (!offset) {
DP(BNX2X_MSG_MCP, "No FC-NPIV in NVRAM\n"); goto out;
}
DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset);
/* Read the table contents from nvram */ if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) {
BNX2X_ERR("Failed to read FC-NPIV table\n"); goto out;
}
/* Since bnx2x_nvram_read() returns data in be32, we need to convert * the number of entries back to cpu endianness.
*/
entries = tbl->fc_npiv_cfg.num_of_npiv;
entries = (__force u32)be32_to_cpu((__force __be32)entries);
tbl->fc_npiv_cfg.num_of_npiv = entries;
if (!tbl->fc_npiv_cfg.num_of_npiv) {
DP(BNX2X_MSG_MCP, "No FC-NPIV table [valid, simply not present]\n"); goto out;
} elseif (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) {
BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n",
tbl->fc_npiv_cfg.num_of_npiv); goto out;
} else {
DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n",
tbl->fc_npiv_cfg.num_of_npiv);
}
/* Copy the data into cnic-provided struct */
cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv; for (i = 0; i < cnic_tbl->count; i++) {
memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8);
memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8);
}
/* If both iSCSI and FCoE are disabled - return NULL in * order to indicate CNIC that it should not try to work * with this device.
*/ if (NO_ISCSI(bp) && NO_FCOE(bp)) return NULL;
/* called only on E1H or E2. * When pretending to be PF, the pretend value is the function number 0...7 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID * combination
*/ int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
{
u32 pretend_reg;
if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX) return -1;
/* get my own pretend register */
pretend_reg = bnx2x_get_pretend_reg(bp);
REG_WR(bp, pretend_reg, pretend_func_val);
REG_RD(bp, pretend_reg); return 0;
}
/* FW may take a while to complete timestamping; try a bit and if it's * still not complete, may indicate an error state - bail out then.
*/ for (i = 0; i < 10; i++) { /* Read Tx timestamp registers */
val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
NIG_REG_P0_TLLH_PTP_BUF_SEQID); if (val_seq & 0x10000) {
bail = false; break;
}
msleep(1 << i);
}
if (!bail) { /* There is a valid timestamp value */
timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
timestamp <<= 32;
timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
NIG_REG_P0_TLLH_PTP_BUF_TS_LSB); /* Reset timestamp register to allow new timestamp */
REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
ns = timecounter_cyc2time(&bp->timecounter, timestamp);
/* Prepare parameters for function state transitions */
__set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
__set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
/* Reset drift register (offset register is not reset) */
rc = bnx2x_send_reset_timesync_ramrod(bp); if (rc) {
BNX2X_ERR("Failed to reset PHC drift register\n"); return -EFAULT;
}
/* Reset possibly old timestamps */
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
return 0;
}
/* Called during load, to initialize PTP-related stuff */ void bnx2x_init_ptp(struct bnx2x *bp)
{ int rc;
/* Configure PTP in HW */
rc = bnx2x_configure_ptp(bp); if (rc) {
BNX2X_ERR("Stopping PTP initialization\n"); return;
}
/* Init work queue for Tx timestamping */
INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
/* Init cyclecounter and timecounter. This is done only in the first * load. If done in every load, PTP application will fail when doing * unload / load (e.g. MTU change) while it is running.
*/ if (!bp->timecounter_init_done) {
bnx2x_init_cyclecounter(bp);
timecounter_init(&bp->timecounter, &bp->cyclecounter,
ktime_to_ns(ktime_get_real()));
bp->timecounter_init_done = true;
}
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