/* * tg3.c: Broadcom Tigon3 ethernet driver. * * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) * Copyright (C) 2004 Sun Microsystems Inc. * Copyright (C) 2005-2016 Broadcom Corporation. * Copyright (C) 2016-2017 Broadcom Limited. * Copyright (C) 2018 Broadcom. All Rights Reserved. The term "Broadcom" * refers to Broadcom Inc. and/or its subsidiaries. * * Firmware is: * Derived from proprietary unpublished source code, * Copyright (C) 2000-2016 Broadcom Corporation. * Copyright (C) 2016-2017 Broadcom Ltd. * Copyright (C) 2018 Broadcom. All Rights Reserved. The term "Broadcom" * refers to Broadcom Inc. and/or its subsidiaries. * * Permission is hereby granted for the distribution of this firmware * data in hexadecimal or equivalent format, provided this copyright * notice is accompanying it.
*/
/* length of time before we decide the hardware is borked, * and dev->tx_timeout() should be called to fix the problem
*/
#define TG3_TX_TIMEOUT (5 * HZ)
/* hardware minimum and maximum for a single frame's data payload */ #define TG3_MIN_MTU ETH_ZLEN #define TG3_MAX_MTU(tp) \
(tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
/* These numbers seem to be hard coded in the NIC firmware somehow. * You can't change the ring sizes, but you can change where you place * them in the NIC onboard memory.
*/ #define TG3_RX_STD_RING_SIZE(tp) \
(tg3_flag(tp, LRG_PROD_RING_CAP) ? \
TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700) #define TG3_DEF_RX_RING_PENDING 200 #define TG3_RX_JMB_RING_SIZE(tp) \
(tg3_flag(tp, LRG_PROD_RING_CAP) ? \
TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700) #define TG3_DEF_RX_JUMBO_RING_PENDING 100
/* Do not place this n-ring entries value into the tp struct itself, * we really want to expose these constants to GCC so that modulo et * al. operations are done with shifts and masks instead of with * hw multiply/modulo instructions. Another solution would be to * replace things like '% foo' with '& (foo - 1)'.
*/
/* Due to a hardware bug, the 5701 can only DMA to memory addresses * that are at least dword aligned when used in PCIX mode. The driver * works around this bug by double copying the packet. This workaround * is built into the normal double copy length check for efficiency. * * However, the double copy is only necessary on those architectures * where unaligned memory accesses are inefficient. For those architectures * where unaligned memory accesses incur little penalty, we can reintegrate * the 5701 in the normal rx path. Doing so saves a device structure * dereference by hardcoding the double copy threshold in place.
*/ #define TG3_RX_COPY_THRESHOLD 256 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD #else #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) #endif
/* minimum number of free TX descriptors required to wake up TX process */ #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) #define TG3_TX_BD_DMA_MAX_2K 2048 #define TG3_TX_BD_DMA_MAX_4K 4096
MODULE_AUTHOR("David S. Miller <davem@redhat.com> and Jeff Garzik <jgarzik@pobox.com>");
MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
MODULE_LICENSE("GPL");
MODULE_FIRMWARE(FIRMWARE_TG3);
MODULE_FIRMWARE(FIRMWARE_TG357766);
MODULE_FIRMWARE(FIRMWARE_TG3TSO);
MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
staticint tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
module_param(tg3_debug, int, 0);
MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
/* In indirect mode when disabling interrupts, we also need * to clear the interrupt bit in the GRC local ctrl register.
*/ if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
(val == 0x1)) {
pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
}
}
/* usec_wait specifies the wait time in usec when writing to certain registers * where it is unsafe to read back the register without some delay. * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
*/ staticvoid _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
{ if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND)) /* Non-posted methods */
tp->write32(tp, off, val); else { /* Posted method */
tg3_write32(tp, off, val); if (usec_wait)
udelay(usec_wait);
tp->read32(tp, off);
} /* Wait again after the read for the posted method to guarantee that * the wait time is met.
*/ if (usec_wait)
udelay(usec_wait);
}
/* Make sure the driver hasn't any stale locks. */ for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) { switch (i) { case TG3_APE_LOCK_PHY0: case TG3_APE_LOCK_PHY1: case TG3_APE_LOCK_PHY2: case TG3_APE_LOCK_PHY3:
bit = APE_LOCK_GRANT_DRIVER; break; default: if (!tp->pci_fn)
bit = APE_LOCK_GRANT_DRIVER; else
bit = 1 << tp->pci_fn;
}
tg3_ape_write32(tp, regbase + 4 * i, bit);
}
}
staticint tg3_ape_lock(struct tg3 *tp, int locknum)
{ int i, off; int ret = 0;
u32 status, req, gnt, bit;
if (!tg3_flag(tp, ENABLE_APE)) return 0;
switch (locknum) { case TG3_APE_LOCK_GPIO: if (tg3_asic_rev(tp) == ASIC_REV_5761) return 0;
fallthrough; case TG3_APE_LOCK_GRC: case TG3_APE_LOCK_MEM: if (!tp->pci_fn)
bit = APE_LOCK_REQ_DRIVER; else
bit = 1 << tp->pci_fn; break; case TG3_APE_LOCK_PHY0: case TG3_APE_LOCK_PHY1: case TG3_APE_LOCK_PHY2: case TG3_APE_LOCK_PHY3:
bit = APE_LOCK_REQ_DRIVER; break; default: return -EINVAL;
}
/* Wait for up to 1 millisecond to acquire lock. */ for (i = 0; i < 100; i++) {
status = tg3_ape_read32(tp, gnt + off); if (status == bit) break; if (pci_channel_offline(tp->pdev)) break;
udelay(10);
}
if (status != bit) { /* Revoke the lock request. */
tg3_ape_write32(tp, gnt + off, bit);
ret = -EBUSY;
}
return ret;
}
staticvoid tg3_ape_unlock(struct tg3 *tp, int locknum)
{
u32 gnt, bit;
if (!tg3_flag(tp, ENABLE_APE)) return;
switch (locknum) { case TG3_APE_LOCK_GPIO: if (tg3_asic_rev(tp) == ASIC_REV_5761) return;
fallthrough; case TG3_APE_LOCK_GRC: case TG3_APE_LOCK_MEM: if (!tp->pci_fn)
bit = APE_LOCK_GRANT_DRIVER; else
bit = 1 << tp->pci_fn; break; case TG3_APE_LOCK_PHY0: case TG3_APE_LOCK_PHY1: case TG3_APE_LOCK_PHY2: case TG3_APE_LOCK_PHY3:
bit = APE_LOCK_GRANT_DRIVER; break; default: return;
}
staticvoid tg3_disable_ints(struct tg3 *tp)
{ int i;
tw32(TG3PCI_MISC_HOST_CTRL,
(tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); for (i = 0; i < tp->irq_max; i++)
tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
}
staticvoid tg3_enable_ints(struct tg3 *tp)
{ int i;
/* check for phy events */ if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { if (sblk->status & SD_STATUS_LINK_CHG)
work_exists = 1;
}
/* check for TX work to do */ if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
work_exists = 1;
/* check for RX work to do */ if (tnapi->rx_rcb_prod_idx &&
*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
work_exists = 1;
return work_exists;
}
/* tg3_int_reenable * similar to tg3_enable_ints, but it accurately determines whether there * is new work pending and can return without flushing the PIO write * which reenables interrupts
*/ staticvoid tg3_int_reenable(struct tg3_napi *tnapi)
{ struct tg3 *tp = tnapi->tp;
/* When doing tagged status, this work check is unnecessary. * The last_tag we write above tells the chip which piece of * work we've completed.
*/ if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
tw32(HOSTCC_MODE, tp->coalesce_mode |
HOSTCC_MODE_ENABLE | tnapi->coal_now);
}
if (enable)
val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA; else
val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
val | MII_TG3_AUXCTL_ACTL_TX_6DB);
return err;
}
staticint tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
{ return tg3_writephy(tp, MII_TG3_MISC_SHDW,
reg | val | MII_TG3_MISC_SHDW_WREN);
}
staticint tg3_bmcr_reset(struct tg3 *tp)
{
u32 phy_control; int limit, err;
/* OK, reset it, and poll the BMCR_RESET bit until it * clears or we time out.
*/
phy_control = BMCR_RESET;
err = tg3_writephy(tp, MII_BMCR, phy_control); if (err != 0) return -EBUSY;
limit = 5000; while (limit--) {
err = tg3_readphy(tp, MII_BMCR, &phy_control); if (err != 0) return -EBUSY;
if ((phy_control & BMCR_RESET) == 0) {
udelay(40); break;
}
udelay(10);
} if (limit < 0) return -EBUSY;
return 0;
}
staticint tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
{ struct tg3 *tp = bp->priv;
u32 val;
spin_lock_bh(&tp->lock);
if (__tg3_readphy(tp, mii_id, reg, &val))
val = -EIO;
spin_unlock_bh(&tp->lock);
return val;
}
staticint tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
{ struct tg3 *tp = bp->priv;
u32 ret = 0;
spin_lock_bh(&tp->lock);
if (__tg3_writephy(tp, mii_id, reg, val))
ret = -EIO;
phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { case PHY_ID_BCM50610: case PHY_ID_BCM50610M:
val = MAC_PHYCFG2_50610_LED_MODES; break; case PHY_ID_BCMAC131:
val = MAC_PHYCFG2_AC131_LED_MODES; break; case PHY_ID_RTL8211C:
val = MAC_PHYCFG2_RTL8211C_LED_MODES; break; case PHY_ID_RTL8201E:
val = MAC_PHYCFG2_RTL8201E_LED_MODES; break; default: return;
}
if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
tw32(MAC_PHYCFG2, val);
val = tr32(MAC_PHYCFG1);
val &= ~(MAC_PHYCFG1_RGMII_INT |
MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
tw32(MAC_PHYCFG1, val);
return;
}
if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
val |= MAC_PHYCFG2_EMODE_MASK_MASK |
MAC_PHYCFG2_FMODE_MASK_MASK |
MAC_PHYCFG2_GMODE_MASK_MASK |
MAC_PHYCFG2_ACT_MASK_MASK |
MAC_PHYCFG2_QUAL_MASK_MASK |
MAC_PHYCFG2_INBAND_ENABLE;
tw32(MAC_PHYCFG2, val);
val = tr32(MAC_PHYCFG1);
val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN); if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
}
val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
tw32(MAC_PHYCFG1, val);
val = tr32(MAC_EXT_RGMII_MODE);
val &= ~(MAC_RGMII_MODE_RX_INT_B |
MAC_RGMII_MODE_RX_QUALITY |
MAC_RGMII_MODE_RX_ACTIVITY |
MAC_RGMII_MODE_RX_ENG_DET |
MAC_RGMII_MODE_TX_ENABLE |
MAC_RGMII_MODE_TX_LOWPWR |
MAC_RGMII_MODE_TX_RESET); if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
val |= MAC_RGMII_MODE_RX_INT_B |
MAC_RGMII_MODE_RX_QUALITY |
MAC_RGMII_MODE_RX_ACTIVITY |
MAC_RGMII_MODE_RX_ENG_DET; if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
val |= MAC_RGMII_MODE_TX_ENABLE |
MAC_RGMII_MODE_TX_LOWPWR |
MAC_RGMII_MODE_TX_RESET;
}
tw32(MAC_EXT_RGMII_MODE, val);
}
/* The bus registration will look for all the PHYs on the mdio bus. * Unfortunately, it does not ensure the PHY is powered up before * accessing the PHY ID registers. A chip reset is the * quickest way to bring the device back to an operational state..
*/ if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
tg3_bmcr_reset(tp);
i = mdiobus_register(tp->mdio_bus); if (i) {
dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
mdiobus_free(tp->mdio_bus); return i;
}
val = tr32(GRC_RX_CPU_EVENT);
val |= GRC_RX_CPU_DRIVER_EVENT;
tw32_f(GRC_RX_CPU_EVENT, val);
tp->last_event_jiffies = jiffies;
}
#define TG3_FW_EVENT_TIMEOUT_USEC 2500
/* tp->lock is held. */ staticvoid tg3_wait_for_event_ack(struct tg3 *tp)
{ int i; unsignedint delay_cnt; long time_remain;
/* If enough time has passed, no wait is necessary. */
time_remain = (long)(tp->last_event_jiffies + 1 +
usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
(long)jiffies; if (time_remain < 0) return;
/* Check if we can shorten the wait time. */
delay_cnt = jiffies_to_usecs(time_remain); if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
delay_cnt = (delay_cnt >> 3) + 1;
for (i = 0; i < delay_cnt; i++) { if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) break; if (pci_channel_offline(tp->pdev)) break;
val = 0; if (!tg3_readphy(tp, MII_BMCR, ®))
val = reg << 16; if (!tg3_readphy(tp, MII_BMSR, ®))
val |= (reg & 0xffff);
*data++ = val;
val = 0; if (!tg3_readphy(tp, MII_ADVERTISE, ®))
val = reg << 16; if (!tg3_readphy(tp, MII_LPA, ®))
val |= (reg & 0xffff);
*data++ = val;
val = 0; if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { if (!tg3_readphy(tp, MII_CTRL1000, ®))
val = reg << 16; if (!tg3_readphy(tp, MII_STAT1000, ®))
val |= (reg & 0xffff);
}
*data++ = val;
if (!tg3_readphy(tp, MII_PHYADDR, ®))
val = reg << 16; else
val = 0;
*data++ = val;
}
/* tp->lock is held. */ staticvoid tg3_stop_fw(struct tg3 *tp)
{ if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { /* Wait for RX cpu to ACK the previous event. */
tg3_wait_for_event_ack(tp);
/* Wait for RX cpu to ACK this event. */
tg3_wait_for_event_ack(tp);
}
}
/* tp->lock is held. */ staticvoid tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
{
tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { switch (kind) { case RESET_KIND_INIT:
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
DRV_STATE_START); break;
case RESET_KIND_SHUTDOWN:
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
DRV_STATE_UNLOAD); break;
case RESET_KIND_SUSPEND:
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
DRV_STATE_SUSPEND); break;
default: break;
}
}
}
/* tp->lock is held. */ staticvoid tg3_write_sig_post_reset(struct tg3 *tp, int kind)
{ if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { switch (kind) { case RESET_KIND_INIT:
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
DRV_STATE_START_DONE); break;
case RESET_KIND_SHUTDOWN:
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
DRV_STATE_UNLOAD_DONE); break;
default: break;
}
}
}
/* tp->lock is held. */ staticvoid tg3_write_sig_legacy(struct tg3 *tp, int kind)
{ if (tg3_flag(tp, ENABLE_ASF)) { switch (kind) { case RESET_KIND_INIT:
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
DRV_STATE_START); break;
case RESET_KIND_SHUTDOWN:
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
DRV_STATE_UNLOAD); break;
case RESET_KIND_SUSPEND:
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
DRV_STATE_SUSPEND); break;
default: break;
}
}
}
staticint tg3_poll_fw(struct tg3 *tp)
{ int i;
u32 val;
if (tg3_flag(tp, NO_FWARE_REPORTED)) return 0;
if (tg3_flag(tp, IS_SSB_CORE)) { /* We don't use firmware. */ return 0;
}
if (tg3_asic_rev(tp) == ASIC_REV_5906) { /* Wait up to 20ms for init done. */ for (i = 0; i < 200; i++) { if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) return 0; if (pci_channel_offline(tp->pdev)) return -ENODEV;
udelay(100);
} return -ENODEV;
}
/* Wait for firmware initialization to complete. */ for (i = 0; i < 100000; i++) {
tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) break; if (pci_channel_offline(tp->pdev)) { if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
tg3_flag_set(tp, NO_FWARE_REPORTED);
netdev_info(tp->dev, "No firmware running\n");
}
break;
}
udelay(10);
}
/* Chip might not be fitted with firmware. Some Sun onboard * parts are configured like that. So don't signal the timeout * of the above loop as an error, but do report the lack of * running firmware once.
*/ if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
tg3_flag_set(tp, NO_FWARE_REPORTED);
netdev_info(tp->dev, "No firmware running\n");
}
if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) { /* The 57765 A0 needs a little more * time to do some important work.
*/
mdelay(10);
}
return 0;
}
staticvoid tg3_link_report(struct tg3 *tp)
{ if (!netif_carrier_ok(tp->dev)) {
netif_info(tp, link, tp->dev, "Link is down\n");
tg3_ump_link_report(tp);
} elseif (netif_msg_link(tp)) {
netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
(tp->link_config.active_speed == SPEED_1000 ?
1000 :
(tp->link_config.active_speed == SPEED_100 ?
100 : 10)),
(tp->link_config.active_duplex == DUPLEX_FULL ? "full" : "half"));
netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
(tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? "on" : "off",
(tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? "on" : "off");
if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
netdev_info(tp->dev, "EEE is %s\n",
tp->setlpicnt ? "enabled" : "disabled");
/* Attach the MAC to the PHY. */
phydev = phy_connect(tp->dev, phydev_name(phydev),
tg3_adjust_link, phydev->interface); if (IS_ERR(phydev)) {
dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); return PTR_ERR(phydev);
}
/* Mask with MAC supported features. */ switch (phydev->interface) { case PHY_INTERFACE_MODE_GMII: case PHY_INTERFACE_MODE_RGMII: if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
phy_set_max_speed(phydev, SPEED_1000);
phy_support_asym_pause(phydev); break;
}
fallthrough; case PHY_INTERFACE_MODE_MII:
phy_set_max_speed(phydev, SPEED_100);
phy_support_asym_pause(phydev); break; default:
phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); return -EINVAL;
}
ret = tg3_phy_auxctl_read(tp,
MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); if (!ret) { if (enable)
phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; else
phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
tg3_phy_auxctl_write(tp,
MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
}
}
}
staticvoid tg3_phy_set_wirespeed(struct tg3 *tp)
{ int ret;
u32 val;
if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) return;
ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); if (!ret)
tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
}
staticvoid tg3_warn_mgmt_link_flap(struct tg3 *tp)
{ if (tg3_flag(tp, ENABLE_ASF))
netdev_warn(tp->dev, "Management side-band traffic will be interrupted during phy settings change\n");
}
/* This will reset the tigon3 PHY if there is no valid * link unless the FORCE argument is non-zero.
*/ staticint tg3_phy_reset(struct tg3 *tp)
{
u32 val, cpmuctrl; int err;
if (tg3_asic_rev(tp) == ASIC_REV_5906) {
val = tr32(GRC_MISC_CFG);
tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
udelay(40);
}
err = tg3_readphy(tp, MII_BMSR, &val);
err |= tg3_readphy(tp, MII_BMSR, &val); if (err != 0) return -EBUSY;
if (netif_running(tp->dev) && tp->link_up) {
netif_carrier_off(tp->dev);
tg3_link_report(tp);
}
/* Set Extended packet length bit (bit 14) on all chips that */ /* support jumbo frames */ if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { /* Cannot do read-modify-write on 5401 */
tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
} elseif (tg3_flag(tp, JUMBO_CAPABLE)) { /* Set bit 14 with read-modify-write to preserve other bits */
err = tg3_phy_auxctl_read(tp,
MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); if (!err)
tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
}
/* Set phy register 0x10 bit 0 to high fifo elasticity to support * jumbo frames transmission.
*/ if (tg3_flag(tp, JUMBO_CAPABLE)) { if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
tg3_writephy(tp, MII_TG3_EXT_CTRL,
val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
}
if (tg3_asic_rev(tp) == ASIC_REV_5906) { /* adjust output voltage */
tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
}
if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
tg3_phydsp_write(tp, 0xffb, 0x4000);
staticbool tg3_phy_power_bug(struct tg3 *tp)
{ switch (tg3_asic_rev(tp)) { case ASIC_REV_5700: case ASIC_REV_5704: returntrue; case ASIC_REV_5780: if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) returntrue; returnfalse; case ASIC_REV_5717: if (!tp->pci_fn) returntrue; returnfalse; case ASIC_REV_5719: case ASIC_REV_5720: if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
!tp->pci_fn) returntrue; returnfalse;
}
returnfalse;
}
staticbool tg3_phy_led_bug(struct tg3 *tp)
{ switch (tg3_asic_rev(tp)) { case ASIC_REV_5719: case ASIC_REV_5720: if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
!tp->pci_fn) returntrue; returnfalse;
}
/* NOTE: Data read in from NVRAM is byteswapped according to * the byteswapping settings for all other register accesses. * tg3 devices are BE devices, so on a BE machine, the data * returned will be exactly as it is seen in NVRAM. On a LE * machine, the 32-bit value will be byteswapped.
*/ staticint tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
{ int ret;
if (!tg3_flag(tp, NVRAM)) return tg3_nvram_read_using_eeprom(tp, offset, val);
/* Ensures NVRAM data is in bytestream format. */ staticint tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
{
u32 v; int res = tg3_nvram_read(tp, offset, &v); if (!res)
*val = cpu_to_be32(v); return res;
}
staticint tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
u32 offset, u32 len, u8 *buf)
{ int i, j, rc = 0;
u32 val;
for (i = 0; i < len; i += 4) {
u32 addr;
__be32 data;
addr = offset + i;
memcpy(&data, buf + i, 4);
/* * The SEEPROM interface expects the data to always be opposite * the native endian format. We accomplish this by reversing * all the operations that would have been performed on the * data from a call to tg3_nvram_read_be32().
*/
tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
val = tr32(GRC_EEPROM_ADDR);
tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
/* * Before we can erase the flash page, we need * to issue a special "write enable" command.
*/
nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
if (tg3_nvram_exec_cmd(tp, nvram_cmd)) break;
/* Erase the target page */
tw32(NVRAM_ADDR, phy_addr);
cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
ret = tg3_nvram_exec_cmd(tp, cmd); if (ret) break;
} if (!tg3_flag(tp, FLASH)) { /* We always do complete word writes to eeprom. */
nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
}
ret = tg3_nvram_exec_cmd(tp, nvram_cmd); if (ret) break;
} return ret;
}
/* offset and length are dword aligned */ staticint tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
{ int ret;
if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
~GRC_LCLCTRL_GPIO_OUTPUT1);
udelay(40);
}
if (!tg3_flag(tp, NVRAM)) {
ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
} else {
u32 grc_mode;
ret = tg3_nvram_lock(tp); if (ret) return ret;
tg3_enable_nvram_access(tp); if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
tw32(NVRAM_WRITE1, 0x406);
if (tg3_asic_rev(tp) == ASIC_REV_5906) {
u32 val = tr32(GRC_VCPU_EXT_CTRL);
tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); return 0;
} if (cpu_base == RX_CPU_BASE) {
rc = tg3_rxcpu_pause(tp);
} else { /* * There is only an Rx CPU for the 5750 derivative in the * BCM4785.
*/ if (tg3_flag(tp, IS_SSB_CORE)) return 0;
staticint tg3_fw_data_len(struct tg3 *tp, conststruct tg3_firmware_hdr *fw_hdr)
{ int fw_len;
/* Non fragmented firmware have one firmware header followed by a * contiguous chunk of data to be written. The length field in that * header is not the length of data to be written but the complete * length of the bss. The data length is determined based on * tp->fw->size minus headers. * * Fragmented firmware have a main header followed by multiple * fragments. Each fragment is identical to non fragmented firmware * with a firmware header followed by a contiguous chunk of data. In * the main header, the length field is unused and set to 0xffffffff. * In each fragment header the length is the entire size of that * fragment i.e. fragment data + header length. Data length is * therefore length field in the header minus TG3_FW_HDR_LEN.
*/ if (tp->fw_len == 0xffffffff)
fw_len = be32_to_cpu(fw_hdr->len); else
fw_len = tp->fw->size;
return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
}
/* tp->lock is held. */ staticint tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
u32 cpu_scratch_base, int cpu_scratch_size, conststruct tg3_firmware_hdr *fw_hdr)
{ int err, i; void (*write_op)(struct tg3 *, u32, u32); int total_len = tp->fw->size;
if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
netdev_err(tp->dev, "%s: Trying to load TX cpu firmware which is 5705\n",
__func__); return -EINVAL;
}
if (tg3_asic_rev(tp) != ASIC_REV_57766) { /* It is possible that bootcode is still loading at this point. * Get the nvram lock first before halting the cpu.
*/ int lock_err = tg3_nvram_lock(tp);
err = tg3_halt_cpu(tp, cpu_base); if (!lock_err)
tg3_nvram_unlock(tp); if (err) goto out;
for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
write_op(tp, cpu_scratch_base + i, 0);
tw32(cpu_base + CPU_STATE, 0xffffffff);
tw32(cpu_base + CPU_MODE,
tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
} else { /* Subtract additional main header for fragmented firmware and * advance to the first fragment
*/
total_len -= TG3_FW_HDR_LEN;
fw_hdr++;
}
do {
__be32 *fw_data = (__be32 *)(fw_hdr + 1); for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
write_op(tp, cpu_scratch_base +
(be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
(i * sizeof(u32)),
be32_to_cpu(fw_data[i]));
total_len -= be32_to_cpu(fw_hdr->len);
/* Advance to next fragment */
fw_hdr = (struct tg3_firmware_hdr *)
((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
} while (total_len > 0);
err = 0;
out: return err;
}
/* tp->lock is held. */ staticint tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
{ int i; constint iters = 5;
for (i = 0; i < iters; i++) { if (tr32(cpu_base + CPU_PC) == pc) break;
tw32(cpu_base + CPU_STATE, 0xffffffff);
tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
tw32_f(cpu_base + CPU_PC, pc);
udelay(1000);
}
return (i == iters) ? -EBUSY : 0;
}
/* tp->lock is held. */ staticint tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
{ conststruct tg3_firmware_hdr *fw_hdr; int err;
fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
/* Firmware blob starts with version numbers, followed by start address and length. We are setting complete length. length = end_address_of_bss - start_address_of_text. Remainder is the blob to be loaded contiguously
from start address. */
/* Now startup only the RX cpu. */
err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
be32_to_cpu(fw_hdr->base_addr)); if (err) {
netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " "should be %08x\n", __func__,
tr32(RX_CPU_BASE + CPU_PC),
be32_to_cpu(fw_hdr->base_addr)); return -ENODEV;
}
/* Wait for boot code to complete initialization and enter service * loop. It is then safe to download service patches
*/ for (i = 0; i < iters; i++) { if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP) break;
udelay(10);
}
if (i == iters) {
netdev_err(tp->dev, "Boot code not ready for service patches\n"); return -EBUSY;
}
val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE); if (val & 0xff) {
netdev_warn(tp->dev, "Other patches exist. Not downloading EEE patch\n"); return -EEXIST;
}
/* This firmware blob has a different format than older firmware * releases as given below. The main difference is we have fragmented * data to be written to non-contiguous locations. * * In the beginning we have a firmware header identical to other * firmware which consists of version, base addr and length. The length * here is unused and set to 0xffffffff. * * This is followed by a series of firmware fragments which are * individually identical to previous firmware. i.e. they have the * firmware header and followed by data for that fragment. The version * field of the individual fragment header is unused.
*/
fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR) return;
if (tg3_rxcpu_pause(tp)) return;
/* tg3_load_firmware_cpu() will always succeed for the 57766 */
tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
tg3_rxcpu_resume(tp);
}
/* tp->lock is held. */ staticint tg3_load_tso_firmware(struct tg3 *tp)
{ conststruct tg3_firmware_hdr *fw_hdr; unsignedlong cpu_base, cpu_scratch_base, cpu_scratch_size; int err;
if (!tg3_flag(tp, FW_TSO)) return 0;
fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
/* Firmware blob starts with version numbers, followed by start address and length. We are setting complete length. length = end_address_of_bss - start_address_of_text. Remainder is the blob to be loaded contiguously
from start address. */
/* Now startup the cpu. */
err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
be32_to_cpu(fw_hdr->base_addr)); if (err) {
netdev_err(tp->dev, "%s fails to set CPU PC, is %08x should be %08x\n",
__func__, tr32(cpu_base + CPU_PC),
be32_to_cpu(fw_hdr->base_addr)); return -ENODEV;
}
tg3_resume_cpu(tp, cpu_base); return 0;
}
/* tp->lock is held. */ staticvoid __tg3_set_one_mac_addr(struct tg3 *tp, const u8 *mac_addr, int index)
{
u32 addr_high, addr_low;
staticvoid tg3_enable_register_access(struct tg3 *tp)
{ /* * Make sure register accesses (indirect or otherwise) will function * correctly.
*/
pci_write_config_dword(tp->pdev,
TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
}
staticint tg3_power_up(struct tg3 *tp)
{ int err;
tg3_enable_register_access(tp);
err = pci_set_power_state(tp->pdev, PCI_D0); if (!err) { /* Switch out of Vaux if it is a NIC */
tg3_pwrsrc_switch_to_vmain(tp);
} else {
netdev_err(tp->dev, "Transition to D0 failed\n");
}
err = tg3_phy_toggle_auxctl_smdsp(tp, true); if (!err) {
u32 err2;
if (!tp->eee.eee_enabled)
val = 0; else
val = ethtool_adv_to_mmd_eee_adv_t(advertise);
mii_eee_cap1_mod_linkmode_t(tp->eee.advertised, val);
err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); if (err)
val = 0;
switch (tg3_asic_rev(tp)) { case ASIC_REV_5717: case ASIC_REV_57765: case ASIC_REV_57766: case ASIC_REV_5719: /* If we advertised any eee advertisements above... */ if (val)
val = MII_TG3_DSP_TAP26_ALNOKO |
MII_TG3_DSP_TAP26_RMRXSTO |
MII_TG3_DSP_TAP26_OPCSINPT;
tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
fallthrough; case ASIC_REV_5720: case ASIC_REV_5762: if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
MII_TG3_DSP_CH34TP2_HIBW01);
}
err2 = tg3_phy_toggle_auxctl_smdsp(tp, false); if (!err)
err = err2;
}
if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
adv = ADVERTISED_10baseT_Half |
ADVERTISED_10baseT_Full; if (tg3_flag(tp, WOL_SPEED_100MB))
adv |= ADVERTISED_100baseT_Half |
ADVERTISED_100baseT_Full; if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) { if (!(tp->phy_flags &
TG3_PHYFLG_DISABLE_1G_HD_ADV))
adv |= ADVERTISED_1000baseT_Half;
adv |= ADVERTISED_1000baseT_Full;
}
fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
} else {
adv = tp->link_config.advertising; if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
adv &= ~(ADVERTISED_1000baseT_Half |
ADVERTISED_1000baseT_Full);
fc = tp->link_config.flowctrl;
}
tg3_phy_autoneg_cfg(tp, adv, fc);
if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { /* Normally during power down we want to autonegotiate * the lowest possible speed for WOL. However, to avoid * link flap, we leave it untouched.
*/ return;
}
if (tg3_asic_rev(tp) == ASIC_REV_5714) { /* With autoneg disabled, 5715 only links up when the * advertisement register has the configured speed * enabled.
*/
tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
}
bmcr = 0; switch (tp->link_config.speed) { default: case SPEED_10: break;
case SPEED_100:
bmcr |= BMCR_SPEED100; break;
case SPEED_1000:
bmcr |= BMCR_SPEED1000; break;
}
if (tp->link_config.duplex == DUPLEX_FULL)
bmcr |= BMCR_FULLDPLX;
if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
(bmcr != orig_bmcr)) {
tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); for (i = 0; i < 1500; i++) {
u32 tmp;
val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
TG3_CPMU_EEE_LNKIDL_UART_IDL; if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
/* EEE settings changes take effect only after a phy * reset. If we have skipped a reset due to Link Flap * Avoidance being enabled, do it now.
*/ if (!eee_config_ok &&
(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
!force_reset) {
tg3_setup_eee(tp);
tg3_phy_reset(tp);
}
} else { if (!(bmcr & BMCR_ANENABLE) &&
tp->link_config.speed == current_speed &&
tp->link_config.duplex == current_duplex) {
current_link_up = true;
}
}
if (current_link_up &&
tp->link_config.active_duplex == DUPLEX_FULL) {
u32 reg, bit;
if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
reg = MII_TG3_FET_GEN_STAT;
bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
} else {
reg = MII_TG3_EXT_STAT;
bit = MII_TG3_EXT_STAT_MDIX;
}
/* In order for the 5750 core in BCM4785 chip to work properly * in RGMII mode, the Led Control Register must be set up.
*/ if (tg3_flag(tp, RGMII_MODE)) {
u32 led_ctrl = tr32(MAC_LED_CTRL);
led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
(tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { /* do nothing, just check for link up at the end */
} elseif (tp->link_config.autoneg == AUTONEG_ENABLE) {
u32 adv, newadv;
val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
tw32(GRC_MISC_CFG, val);
}
val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
(6 << TX_LENGTHS_IPG_SHIFT); if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
tg3_asic_rev(tp) == ASIC_REV_5762)
val |= tr32(MAC_TX_LENGTHS) &
(TX_LENGTHS_JMB_FRM_LEN_MSK |
TX_LENGTHS_CNT_DWN_VAL_MSK);
if (tp->link_config.active_speed == SPEED_1000 &&
tp->link_config.active_duplex == DUPLEX_HALF)
tw32(MAC_TX_LENGTHS, val |
(0xff << TX_LENGTHS_SLOT_TIME_SHIFT)); else
tw32(MAC_TX_LENGTHS, val |
(32 << TX_LENGTHS_SLOT_TIME_SHIFT));
if (!tg3_flag(tp, 5705_PLUS)) { if (tp->link_up) {
tw32(HOSTCC_STAT_COAL_TICKS,
tp->coal.stats_block_coalesce_usecs);
} else {
tw32(HOSTCC_STAT_COAL_TICKS, 0);
}
}
if (tg3_flag(tp, ASPM_WORKAROUND)) {
val = tr32(PCIE_PWR_MGMT_THRESH); if (!tp->link_up)
val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
tp->pwrmgmt_thresh; else
val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
tw32(PCIE_PWR_MGMT_THRESH, val);
}
return err;
}
/* tp->lock must be held */ static u64 tg3_refclk_read(struct tg3 *tp, struct ptp_system_timestamp *sts)
{
u64 stamp;
/* Frequency adjustment is performed using hardware with a 24 bit * accumulator and a programmable correction value. On each clk, the * correction value gets added to the accumulator and when it * overflows, the time counter is incremented/decremented.
*/
neg_adj = diff_by_scaled_ppm(1 << 24, scaled_ppm, &correction);
if (rq->perout.period.sec || rq->perout.period.nsec) {
netdev_warn(tp->dev, "Device supports only a one-shot timesync output, period must be 0\n");
rval = -EINVAL; goto err_out;
}
if (nsec & (1ULL << 63)) {
netdev_warn(tp->dev, "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
rval = -EINVAL; goto err_out;
}
/* tp->lock must be held */ staticvoid tg3_ptp_init(struct tg3 *tp)
{ if (!tg3_flag(tp, PTP_CAPABLE)) return;
/* Initialize the hardware clock to the system time. */
tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
tp->ptp_adjust = 0;
tp->ptp_info = tg3_ptp_caps;
}
/* tp->lock must be held */ staticvoid tg3_ptp_resume(struct tg3 *tp)
{ if (!tg3_flag(tp, PTP_CAPABLE)) return;
if (tg3_flag(tp, NVRAM))
tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
}
staticvoid tg3_dump_state(struct tg3 *tp)
{ int i;
u32 *regs;
/* If it is a PCI error, all registers will be 0xffff, * we don't dump them out, just report the error and return
*/ if (tp->pdev->error_state != pci_channel_io_normal) {
netdev_err(tp->dev, "PCI channel ERROR!\n"); return;
}
regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC); if (!regs) return;
if (tg3_flag(tp, PCI_EXPRESS)) { /* Read up to but not including private PCI registers */ for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
regs[i / sizeof(u32)] = tr32(i);
} else
tg3_dump_legacy_regs(tp, regs);
for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) { if (!regs[i + 0] && !regs[i + 1] &&
!regs[i + 2] && !regs[i + 3]) continue;
for (i = 0; i < tp->irq_cnt; i++) { struct tg3_napi *tnapi = &tp->napi[i];
/* SW status block */
netdev_err(tp->dev, "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
i,
tnapi->hw_status->status,
tnapi->hw_status->status_tag,
tnapi->hw_status->rx_jumbo_consumer,
tnapi->hw_status->rx_consumer,
tnapi->hw_status->rx_mini_consumer,
tnapi->hw_status->idx[0].rx_producer,
tnapi->hw_status->idx[0].tx_consumer);
netdev_err(tp->dev, "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
i,
tnapi->last_tag, tnapi->last_irq_tag,
tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
tnapi->rx_rcb_ptr,
tnapi->prodring.rx_std_prod_idx,
tnapi->prodring.rx_std_cons_idx,
tnapi->prodring.rx_jmb_prod_idx,
tnapi->prodring.rx_jmb_cons_idx);
}
}
/* This is called whenever we suspect that the system chipset is re- * ordering the sequence of MMIO to the tx send mailbox. The symptom * is bogus tx completions. We try to recover by setting the * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later * in the workqueue.
*/ staticvoid tg3_tx_recover(struct tg3 *tp)
{
BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
tp->write32_tx_mbox == tg3_write_indirect_mbox);
netdev_warn(tp->dev, "The system may be re-ordering memory-mapped I/O " "cycles to the network device, attempting to recover. " "Please report the problem to the driver maintainer " "and include system chipset information.\n");
tg3_flag_set(tp, TX_RECOVERY_PENDING);
}
staticinline u32 tg3_tx_avail(struct tg3_napi *tnapi)
{ /* Tell compiler to fetch tx indices from memory. */
barrier(); return tnapi->tx_pending -
((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
}
/* Tigon3 never reports partial packet sends. So we do not * need special logic to handle SKBs that have not had all * of their frags sent yet, like SunGEM does.
*/ staticvoid tg3_tx(struct tg3_napi *tnapi)
{ struct tg3 *tp = tnapi->tp;
u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
u32 sw_idx = tnapi->tx_cons; struct netdev_queue *txq; int index = tnapi - tp->napi; unsignedint pkts_compl = 0, bytes_compl = 0;
if (tg3_flag(tp, ENABLE_TSS))
index--;
txq = netdev_get_tx_queue(tp->dev, index);
while (sw_idx != hw_idx) { struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx]; bool complete_skb_later = false; struct sk_buff *skb = ri->skb; int i, tx_bug = 0;
if (unlikely(skb == NULL)) {
tg3_tx_recover(tp); return;
}
if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) { struct skb_shared_hwtstamps timestamp;
u64 hwclock;
/* Need to make the tx_cons update visible to __tg3_start_xmit() * before checking for netif_queue_stopped(). Without the * memory barrier, there is a small possibility that __tg3_start_xmit() * will miss it and cause the queue to be stopped forever.
*/
smp_mb();
if (unlikely(netif_tx_queue_stopped(txq) &&
(tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
__netif_tx_lock(txq, smp_processor_id()); if (netif_tx_queue_stopped(txq) &&
(tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
netif_tx_wake_queue(txq);
__netif_tx_unlock(txq);
}
}
/* Returns size of skb allocated or < 0 on error. * * We only need to fill in the address because the other members * of the RX descriptor are invariant, see tg3_init_rings. * * Note the purposeful asymmetry of cpu vs. chip accesses. For * posting buffers we only dirty the first cache line of the RX * descriptor (containing the address). Whereas for the RX status * buffers the cpu only reads the last cacheline of the RX descriptor * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
*/ staticint tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
u32 opaque_key, u32 dest_idx_unmasked, unsignedint *frag_size)
{ struct tg3_rx_buffer_desc *desc; struct ring_info *map;
u8 *data;
dma_addr_t mapping; int skb_size, data_size, dest_idx;
/* Do not overwrite any of the map or rp information * until we are sure we can commit to a new buffer. * * Callers depend upon this behavior and assume that * we leave everything unchanged if we fail.
*/
skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); if (skb_size <= PAGE_SIZE) {
data = napi_alloc_frag(skb_size);
*frag_size = skb_size;
} else {
data = kmalloc(skb_size, GFP_ATOMIC);
*frag_size = 0;
} if (!data) return -ENOMEM;
mapping = dma_map_single(&tp->pdev->dev, data + TG3_RX_OFFSET(tp),
data_size, DMA_FROM_DEVICE); if (unlikely(dma_mapping_error(&tp->pdev->dev, mapping))) {
tg3_frag_free(skb_size <= PAGE_SIZE, data); return -EIO;
}
/* We only need to move over in the address because the other * members of the RX descriptor are invariant. See notes above * tg3_alloc_rx_data for full details.
*/ staticvoid tg3_recycle_rx(struct tg3_napi *tnapi, struct tg3_rx_prodring_set *dpr,
u32 opaque_key, int src_idx,
u32 dest_idx_unmasked)
{ struct tg3 *tp = tnapi->tp; struct tg3_rx_buffer_desc *src_desc, *dest_desc; struct ring_info *src_map, *dest_map; struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; int dest_idx;
/* Ensure that the update to the skb happens after the physical * addresses have been transferred to the new BD location.
*/
smp_wmb();
src_map->data = NULL;
}
/* The RX ring scheme is composed of multiple rings which post fresh * buffers to the chip, and one special ring the chip uses to report * status back to the host. * * The special ring reports the status of received packets to the * host. The chip does not write into the original descriptor the * RX buffer was obtained from. The chip simply takes the original * descriptor as provided by the host, updates the status and length * field, then writes this into the next status ring entry. * * Each ring the host uses to post buffers to the chip is described * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, * it is first placed into the on-chip ram. When the packet's length * is known, it walks down the TG3_BDINFO entries to select the ring. * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO * which is within the range of the new packet's length is chosen. * * The "separate ring for rx status" scheme may sound queer, but it makes * sense from a cache coherency perspective. If only the host writes * to the buffer post rings, and only the chip writes to the rx status * rings, then cache lines never move beyond shared-modified state. * If both the host and chip were to write into the same ring, cache line * eviction could occur since both entities want it in an exclusive state.
*/ staticint tg3_rx(struct tg3_napi *tnapi, int budget)
{ struct tg3 *tp = tnapi->tp;
u32 work_mask, rx_std_posted = 0;
u32 std_prod_idx, jmb_prod_idx;
u32 sw_idx = tnapi->rx_rcb_ptr;
u16 hw_idx; int received; struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
hw_idx = *(tnapi->rx_rcb_prod_idx); /* * We need to order the read of hw_idx and the read of * the opaque cookie.
*/
rmb();
work_mask = 0;
received = 0;
std_prod_idx = tpr->rx_std_prod_idx;
jmb_prod_idx = tpr->rx_jmb_prod_idx; while (sw_idx != hw_idx && budget > 0) { struct ring_info *ri; struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; unsignedint len; struct sk_buff *skb;
dma_addr_t dma_addr;
u32 opaque_key, desc_idx, *post_ptr;
u8 *data;
u64 tstamp = 0;
/* Refresh hw_idx to see if there is new work */ if (sw_idx == hw_idx) {
hw_idx = *(tnapi->rx_rcb_prod_idx);
rmb();
}
}
/* ACK the status ring. */
tnapi->rx_rcb_ptr = sw_idx;
tw32_rx_mbox(tnapi->consmbox, sw_idx);
/* Refill RX ring(s). */ if (!tg3_flag(tp, ENABLE_RSS)) { /* Sync BD data before updating mailbox */
wmb();
if (work_mask & RXD_OPAQUE_RING_STD) {
tpr->rx_std_prod_idx = std_prod_idx &
tp->rx_std_ring_mask;
tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
tpr->rx_std_prod_idx);
} if (work_mask & RXD_OPAQUE_RING_JUMBO) {
tpr->rx_jmb_prod_idx = jmb_prod_idx &
tp->rx_jmb_ring_mask;
tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
tpr->rx_jmb_prod_idx);
}
} elseif (work_mask) { /* rx_std_buffers[] and rx_jmb_buffers[] entries must be * updated before the producer indices can be updated.
*/
smp_wmb();
si = spr->rx_std_cons_idx;
di = dpr->rx_std_prod_idx;
for (i = di; i < di + cpycnt; i++) { if (dpr->rx_std_buffers[i].data) {
cpycnt = i - di;
err = -ENOSPC; break;
}
}
if (!cpycnt) break;
/* Ensure that updates to the rx_std_buffers ring and the * shadowed hardware producer ring from tg3_recycle_skb() are * ordered correctly WRT the skb check above.
*/
smp_rmb();
si = spr->rx_jmb_cons_idx;
di = dpr->rx_jmb_prod_idx;
for (i = di; i < di + cpycnt; i++) { if (dpr->rx_jmb_buffers[i].data) {
cpycnt = i - di;
err = -ENOSPC; break;
}
}
if (!cpycnt) break;
/* Ensure that updates to the rx_jmb_buffers ring and the * shadowed hardware producer ring from tg3_recycle_skb() are * ordered correctly WRT the skb check above.
*/
smp_rmb();
staticint tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
{ struct tg3 *tp = tnapi->tp;
/* run TX completion thread */ if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
tg3_tx(tnapi); if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) return work_done;
}
if (!tnapi->rx_rcb_prod_idx) return work_done;
/* run RX thread, within the bounds set by NAPI. * All RX "locking" is done by ensuring outside * code synchronizes with tg3->napi.poll()
*/ if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
work_done += tg3_rx(tnapi, budget - work_done);
if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; int i, err = 0;
u32 std_prod_idx = dpr->rx_std_prod_idx;
u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
tp->rx_refill = false; for (i = 1; i <= tp->rxq_cnt; i++)
err |= tg3_rx_prodring_xfer(tp, dpr,
&tp->napi[i].prodring);
wmb();
if (std_prod_idx != dpr->rx_std_prod_idx)
tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
dpr->rx_std_prod_idx);
if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
dpr->rx_jmb_prod_idx);
if (err)
tw32_f(HOSTCC_MODE, tp->coal_now);
}
return work_done;
}
staticinlinevoid tg3_reset_task_schedule(struct tg3 *tp)
{ if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
schedule_work(&tp->reset_task);
}
while (1) {
work_done = tg3_poll_work(tnapi, work_done, budget);
if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) goto tx_recovery;
if (unlikely(work_done >= budget)) break;
/* tp->last_tag is used in tg3_int_reenable() below * to tell the hw how much work has been processed, * so we must read it before checking for more work.
*/
tnapi->last_tag = sblk->status_tag;
tnapi->last_irq_tag = tnapi->last_tag;
rmb();
/* check for RX/TX work to do */ if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
*(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
/* This test here is not race free, but will reduce * the number of interrupts by looping again.
*/ if (tnapi == &tp->napi[1] && tp->rx_refill) continue;
/* This test here is synchronized by napi_schedule() * and napi_complete() to close the race condition.
*/ if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
tw32(HOSTCC_MODE, tp->coalesce_mode |
HOSTCC_MODE_ENABLE |
tnapi->coal_now);
} break;
}
}
if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) goto tx_recovery;
if (unlikely(work_done >= budget)) break;
if (tg3_flag(tp, TAGGED_STATUS)) { /* tp->last_tag is used in tg3_int_reenable() below * to tell the hw how much work has been processed, * so we must read it before checking for more work.
*/
tnapi->last_tag = sblk->status_tag;
tnapi->last_irq_tag = tnapi->last_tag;
rmb();
} else
sblk->status &= ~SD_STATUS_UPDATED;
if (likely(!tg3_has_work(tnapi))) {
napi_complete_done(napi, work_done);
tg3_int_reenable(tnapi); break;
}
}
tx_recovery: /* work_done is guaranteed to be less than budget. */
napi_complete(napi);
tg3_reset_task_schedule(tp); return work_done;
}
staticvoid tg3_napi_disable(struct tg3 *tp)
{ int txq_idx = tp->txq_cnt - 1; int rxq_idx = tp->rxq_cnt - 1; struct tg3_napi *tnapi; int i;
for (i = tp->irq_cnt - 1; i >= 0; i--) {
tnapi = &tp->napi[i]; if (tnapi->tx_buffers) {
netif_queue_set_napi(tp->dev, txq_idx,
NETDEV_QUEUE_TYPE_TX, NULL);
txq_idx--;
} if (tnapi->rx_rcb) {
netif_queue_set_napi(tp->dev, rxq_idx,
NETDEV_QUEUE_TYPE_RX, NULL);
rxq_idx--;
}
napi_disable(&tnapi->napi);
}
}
staticvoid tg3_napi_enable(struct tg3 *tp)
{ int txq_idx = 0, rxq_idx = 0; struct tg3_napi *tnapi; int i;
for (i = 0; i < tp->irq_cnt; i++) {
tnapi = &tp->napi[i];
napi_enable_locked(&tnapi->napi); if (tnapi->tx_buffers) {
netif_queue_set_napi(tp->dev, txq_idx,
NETDEV_QUEUE_TYPE_TX,
&tnapi->napi);
txq_idx++;
} if (tnapi->rx_rcb) {
netif_queue_set_napi(tp->dev, rxq_idx,
NETDEV_QUEUE_TYPE_RX,
&tnapi->napi);
rxq_idx++;
}
}
}
staticvoid tg3_napi_init(struct tg3 *tp)
{ int i;
for (i = 0; i < tp->irq_cnt; i++) {
netif_napi_add_locked(tp->dev, &tp->napi[i].napi,
i ? tg3_poll_msix : tg3_poll);
netif_napi_set_irq_locked(&tp->napi[i].napi,
tp->napi[i].irq_vec);
}
}
staticvoid tg3_napi_fini(struct tg3 *tp)
{ int i;
for (i = 0; i < tp->irq_cnt; i++)
netif_napi_del(&tp->napi[i].napi);
}
/* tp->lock must be held */ staticinlinevoid tg3_netif_start(struct tg3 *tp)
{
tg3_ptp_resume(tp);
/* NOTE: unconditional netif_tx_wake_all_queues is only * appropriate so long as all callers are assured to * have free tx slots (such as after tg3_init_hw)
*/
netif_tx_wake_all_queues(tp->dev);
staticvoid tg3_irq_quiesce(struct tg3 *tp)
__releases(tp->lock)
__acquires(tp->lock)
{ int i;
BUG_ON(tp->irq_sync);
tp->irq_sync = 1;
smp_mb();
spin_unlock_bh(&tp->lock);
for (i = 0; i < tp->irq_cnt; i++)
synchronize_irq(tp->napi[i].irq_vec);
spin_lock_bh(&tp->lock);
}
/* Fully shutdown all tg3 driver activity elsewhere in the system. * If irq_sync is non-zero, then the IRQ handler must be synchronized * with as well. Most of the time, this is not necessary except when * shutting down the device.
*/ staticinlinevoid tg3_full_lock(struct tg3 *tp, int irq_sync)
{
spin_lock_bh(&tp->lock); if (irq_sync)
tg3_irq_quiesce(tp);
}
/* One-shot MSI handler - Chip automatically disables interrupt * after sending MSI so driver doesn't have to do it.
*/ static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
{ struct tg3_napi *tnapi = dev_id; struct tg3 *tp = tnapi->tp;
prefetch(tnapi->hw_status); if (tnapi->rx_rcb)
prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
if (likely(!tg3_irq_sync(tp)))
napi_schedule(&tnapi->napi);
return IRQ_HANDLED;
}
/* MSI ISR - No need to check for interrupt sharing and no need to * flush status block and interrupt mailbox. PCI ordering rules * guarantee that MSI will arrive after the status block.
*/ static irqreturn_t tg3_msi(int irq, void *dev_id)
{ struct tg3_napi *tnapi = dev_id; struct tg3 *tp = tnapi->tp;
prefetch(tnapi->hw_status); if (tnapi->rx_rcb)
prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); /* * Writing any value to intr-mbox-0 clears PCI INTA# and * chip-internal interrupt pending events. * Writing non-zero to intr-mbox-0 additional tells the * NIC to stop sending us irqs, engaging "in-intr-handler" * event coalescing.
*/
tw32_mailbox(tnapi->int_mbox, 0x00000001); if (likely(!tg3_irq_sync(tp)))
napi_schedule(&tnapi->napi);
/* In INTx mode, it is possible for the interrupt to arrive at * the CPU before the status block posted prior to the interrupt. * Reading the PCI State register will confirm whether the * interrupt is ours and will flush the status block.
*/ if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { if (tg3_flag(tp, CHIP_RESETTING) ||
(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
handled = 0; goto out;
}
}
/* * Writing any value to intr-mbox-0 clears PCI INTA# and * chip-internal interrupt pending events. * Writing non-zero to intr-mbox-0 additional tells the * NIC to stop sending us irqs, engaging "in-intr-handler" * event coalescing. * * Flush the mailbox to de-assert the IRQ immediately to prevent * spurious interrupts. The flush impacts performance but * excessive spurious interrupts can be worse in some cases.
*/
tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); if (tg3_irq_sync(tp)) goto out;
sblk->status &= ~SD_STATUS_UPDATED; if (likely(tg3_has_work(tnapi))) {
prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
napi_schedule(&tnapi->napi);
} else { /* No work, shared interrupt perhaps? re-enable * interrupts, and flush that PCI write
*/
tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
0x00000000);
}
out: return IRQ_RETVAL(handled);
}
/* In INTx mode, it is possible for the interrupt to arrive at * the CPU before the status block posted prior to the interrupt. * Reading the PCI State register will confirm whether the * interrupt is ours and will flush the status block.
*/ if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { if (tg3_flag(tp, CHIP_RESETTING) ||
(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
handled = 0; goto out;
}
}
/* * writing any value to intr-mbox-0 clears PCI INTA# and * chip-internal interrupt pending events. * writing non-zero to intr-mbox-0 additional tells the * NIC to stop sending us irqs, engaging "in-intr-handler" * event coalescing. * * Flush the mailbox to de-assert the IRQ immediately to prevent * spurious interrupts. The flush impacts performance but * excessive spurious interrupts can be worse in some cases.
*/
tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
/* * In a shared interrupt configuration, sometimes other devices' * interrupts will scream. We record the current status tag here * so that the above check can report that the screaming interrupts * are unhandled. Eventually they will be silenced.
*/
tnapi->last_irq_tag = sblk->status_tag;
if (netif_msg_tx_err(tp)) {
netdev_err(dev, "transmit timed out, resetting\n");
tg3_dump_state(tp);
}
tg3_reset_task_schedule(tp);
}
/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ staticinlineint tg3_4g_overflow_test(dma_addr_t mapping, int len)
{
u32 base = (u32) mapping & 0xffffffff;
return base + len + 8 < base;
}
/* Test for TSO DMA buffers that cross into regions which are within MSS bytes * of any 4GB boundaries: 4G, 8G, etc
*/ staticinlineint tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
u32 len, u32 mss)
{ if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
u32 base = (u32) mapping & 0xffffffff;
if (!new_skb) {
ret = -1;
} else { /* New SKB is guaranteed to be linear. */
new_addr = dma_map_single(&tp->pdev->dev, new_skb->data,
new_skb->len, DMA_TO_DEVICE); /* Make sure the mapping succeeded */ if (dma_mapping_error(&tp->pdev->dev, new_addr)) {
dev_kfree_skb_any(new_skb);
ret = -1;
} else {
u32 save_entry = *entry;
staticbool tg3_tso_bug_gso_check(struct tg3_napi *tnapi, struct sk_buff *skb)
{ /* Check if we will never have enough descriptors, * as gso_segs can be more than current ring size
*/ return skb_shinfo(skb)->gso_segs < tnapi->tx_pending / 3;
}
/* Use GSO to workaround all TSO packets that meet HW bug conditions * indicated in tg3_tx_frag_set()
*/ staticint tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi, struct netdev_queue *txq, struct sk_buff *skb)
{
u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; struct sk_buff *segs, *seg, *next;
/* Estimate the number of fragments in the worst case */ if (unlikely(tg3_tx_avail(tnapi) <= frag_cnt_est)) {
netif_tx_stop_queue(txq);
/* netif_tx_stop_queue() must be done before checking * checking tx index in tg3_tx_avail() below, because in * tg3_tx(), we update tx index before checking for * netif_tx_queue_stopped().
*/
smp_mb(); if (tg3_tx_avail(tnapi) <= frag_cnt_est) return NETDEV_TX_BUSY;
/* We are running in BH disabled context with netif_tx_lock * and TX reclaim runs via tp->napi.poll inside of a software * interrupt. Furthermore, IRQ processing runs lockless so we have * no IRQ context deadlocks to worry about either. Rejoice!
*/ if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) { if (!netif_tx_queue_stopped(txq)) {
netif_tx_stop_queue(txq);
/* This is a hard error, log it. */
netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
} return NETDEV_TX_BUSY;
}
entry = tnapi->tx_prod;
base_flags = 0;
mss = skb_shinfo(skb)->gso_size; if (mss) {
u32 tcp_opt_len, hdr_len;
if (skb_cow_head(skb, 0)) goto drop;
iph = ip_hdr(skb);
tcp_opt_len = tcp_optlen(skb);
hdr_len = skb_tcp_all_headers(skb) - ETH_HLEN;
/* HW/FW can not correctly segment packets that have been * vlan encapsulated.
*/ if (skb->protocol == htons(ETH_P_8021Q) ||
skb->protocol == htons(ETH_P_8021AD)) { if (tg3_tso_bug_gso_check(tnapi, skb)) return tg3_tso_bug(tp, tnapi, txq, skb); goto drop;
}
/* Now loop through additional data * fragments, and queue them.
*/
last = skb_shinfo(skb)->nr_frags - 1; for (i = 0; i <= last; i++) {
skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
len = skb_frag_size(frag);
mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
len, DMA_TO_DEVICE);
if (would_hit_hwbug) {
tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
if (mss && tg3_tso_bug_gso_check(tnapi, skb)) { /* If it's a TSO packet, do GSO instead of * allocating and copying to a large linear SKB
*/ if (ip_tot_len) {
iph->check = ip_csum;
iph->tot_len = ip_tot_len;
}
tcph->check = tcp_csum; return tg3_tso_bug(tp, tnapi, txq, skb);
}
/* If the workaround fails due to memory/mapping * failure, silently drop this packet.
*/
entry = tnapi->tx_prod;
budget = tg3_tx_avail(tnapi); if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
base_flags, mss, vlan)) goto drop_nofree;
}
/* netif_tx_stop_queue() must be done before checking * checking tx index in tg3_tx_avail() below, because in * tg3_tx(), we update tx index before checking for * netif_tx_queue_stopped().
*/
smp_mb(); if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
netif_tx_wake_queue(txq);
}
/* Notify the hardware that packets are ready by updating the TX ring * tail pointer. We respect netdev_xmit_more() thus avoiding poking * the hardware for every packet. To guarantee forward progress the TX * ring must be drained when it is full as indicated by * netif_xmit_stopped(). This needs to happen even when the current * skb was dropped or rejected with NETDEV_TX_BUSY. Otherwise packets * queued by previous __tg3_start_xmit() calls might get stuck in * the queue forever.
*/ if (!netdev_xmit_more() || netif_xmit_stopped(txq)) { struct tg3_napi *tnapi; struct tg3 *tp;
if (features & NETIF_F_LOOPBACK) { if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) return;
spin_lock_bh(&tp->lock);
tg3_mac_loopback(tp, true);
netif_carrier_on(tp->dev);
spin_unlock_bh(&tp->lock);
netdev_info(dev, "Internal MAC loopback mode enabled.\n");
} else { if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) return;
spin_lock_bh(&tp->lock);
tg3_mac_loopback(tp, false); /* Force link status check */
tg3_setup_phy(tp, true);
spin_unlock_bh(&tp->lock);
netdev_info(dev, "Internal MAC loopback mode disabled.\n");
}
}
if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
tg3_set_loopback(dev, features);
return 0;
}
staticvoid tg3_rx_prodring_free(struct tg3 *tp, struct tg3_rx_prodring_set *tpr)
{ int i;
if (tpr != &tp->napi[0].prodring) { for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
i = (i + 1) & tp->rx_std_ring_mask)
tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
tp->rx_pkt_map_sz);
if (tg3_flag(tp, JUMBO_CAPABLE)) { for (i = tpr->rx_jmb_cons_idx;
i != tpr->rx_jmb_prod_idx;
i = (i + 1) & tp->rx_jmb_ring_mask) {
tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
TG3_RX_JMB_MAP_SZ);
}
}
return;
}
for (i = 0; i <= tp->rx_std_ring_mask; i++)
tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
tp->rx_pkt_map_sz);
if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
TG3_RX_JMB_MAP_SZ);
}
}
/* Initialize rx rings for packet processing. * * The chip has been shut down and the driver detached from * the networking, so no interrupts or new tx packets will * end up in the driver. tp->{tx,}lock are held and thus * we may not sleep.
*/ staticint tg3_rx_prodring_alloc(struct tg3 *tp, struct tg3_rx_prodring_set *tpr)
{
u32 i, rx_pkt_dma_sz;
/* Initialize invariants of the rings, we only set this * stuff once. This works because the card does not * write into the rx buffer posting rings.
*/ for (i = 0; i <= tp->rx_std_ring_mask; i++) { struct tg3_rx_buffer_desc *rxd;
/* Now allocate fresh SKBs for each rx ring. */ for (i = 0; i < tp->rx_pending; i++) { unsignedint frag_size;
if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
&frag_size) < 0) {
netdev_warn(tp->dev, "Using a smaller RX standard ring. Only " "%d out of %d buffers were allocated " "successfully\n", i, tp->rx_pending); if (i == 0) goto initfail;
tp->rx_pending = i; break;
}
}
if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) goto done;
for (i = 0; i < tp->rx_jumbo_pending; i++) { unsignedint frag_size;
if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
&frag_size) < 0) {
netdev_warn(tp->dev, "Using a smaller RX jumbo ring. Only %d " "out of %d buffers were allocated " "successfully\n", i, tp->rx_jumbo_pending); if (i == 0) goto initfail;
tp->rx_jumbo_pending = i; break;
}
}
/* Free up pending packets in all rx/tx rings. * * The chip has been shut down and the driver detached from * the networking, so no interrupts or new tx packets will * end up in the driver. tp->{tx,}lock is not held and we are not * in an interrupt context and thus may sleep.
*/ staticvoid tg3_free_rings(struct tg3 *tp)
{ int i, j;
/* Initialize tx/rx rings for packet processing. * * The chip has been shut down and the driver detached from * the networking, so no interrupts or new tx packets will * end up in the driver. tp->{tx,}lock are held and thus * we may not sleep.
*/ staticint tg3_init_rings(struct tg3 *tp)
{ int i;
/* Free up all the SKBs. */
tg3_free_rings(tp);
for (i = 0; i < tp->irq_cnt; i++) { struct tg3_napi *tnapi = &tp->napi[i];
/* If multivector TSS is enabled, vector 0 does not handle * tx interrupts. Don't allocate any resources for it.
*/ if (tg3_flag(tp, ENABLE_TSS))
tnapi++;
for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
tnapi->tx_buffers = kcalloc(TG3_TX_RING_SIZE, sizeof(struct tg3_tx_ring_info),
GFP_KERNEL); if (!tnapi->tx_buffers) goto err_out;
staticint tg3_mem_rx_acquire(struct tg3 *tp)
{ unsignedint i, limit;
limit = tp->rxq_cnt;
/* If RSS is enabled, we need a (dummy) producer ring * set on vector zero. This is the true hw prodring.
*/ if (tg3_flag(tp, ENABLE_RSS))
limit++;
for (i = 0; i < limit; i++) { struct tg3_napi *tnapi = &tp->napi[i];
if (tg3_rx_prodring_init(tp, &tnapi->prodring)) goto err_out;
/* If multivector RSS is enabled, vector 0 * does not handle rx or tx interrupts. * Don't allocate any resources for it.
*/ if (!i && tg3_flag(tp, ENABLE_RSS)) continue;
/* tp->hw_stats can be referenced safely: * 1. under rtnl_lock * 2. or under tp->lock if TG3_FLAG_INIT_COMPLETE is set.
*/ if (tp->hw_stats) {
dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
tp->hw_stats, tp->stats_mapping);
tp->hw_stats = NULL;
}
}
/* * Must not be invoked with interrupt sources disabled and * the hardware shutdown down. Can sleep.
*/ staticint tg3_alloc_consistent(struct tg3 *tp)
{ int i;
for (i = 0; i < tp->irq_cnt; i++) { struct tg3_napi *tnapi = &tp->napi[i]; struct tg3_hw_status *sblk;
tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
TG3_HW_STATUS_SIZE,
&tnapi->status_mapping,
GFP_KERNEL); if (!tnapi->hw_status) goto err_out;
sblk = tnapi->hw_status;
if (tg3_flag(tp, ENABLE_RSS)) {
u16 *prodptr = NULL;
/* * When RSS is enabled, the status block format changes * slightly. The "rx_jumbo_consumer", "reserved", * and "rx_mini_consumer" members get mapped to the * other three rx return ring producer indexes.
*/ switch (i) { case 1:
prodptr = &sblk->idx[0].rx_producer; break; case 2:
prodptr = &sblk->rx_jumbo_consumer; break; case 3:
prodptr = &sblk->reserved; break; case 4:
prodptr = &sblk->rx_mini_consumer; break;
}
tnapi->rx_rcb_prod_idx = prodptr;
} else {
tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
}
}
if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp)) goto err_out;
/* To stop a block, clear the enable bit and poll till it * clears. tp->lock is held.
*/ staticint tg3_stop_block(struct tg3 *tp, unsignedlong ofs, u32 enable_bit, bool silent)
{ unsignedint i;
u32 val;
if (tg3_flag(tp, 5705_PLUS)) { switch (ofs) { case RCVLSC_MODE: case DMAC_MODE: case MBFREE_MODE: case BUFMGR_MODE: case MEMARB_MODE: /* We can't enable/disable these bits of the * 5705/5750, just say success.
*/ return 0;
default: break;
}
}
val = tr32(ofs);
val &= ~enable_bit;
tw32_f(ofs, val);
for (i = 0; i < MAX_WAIT_CNT; i++) { if (pci_channel_offline(tp->pdev)) {
dev_err(&tp->pdev->dev, "tg3_stop_block device offline, " "ofs=%lx enable_bit=%x\n",
ofs, enable_bit); return -ENODEV;
}
udelay(100);
val = tr32(ofs); if ((val & enable_bit) == 0) break;
}
if (i == MAX_WAIT_CNT && !silent) {
dev_err(&tp->pdev->dev, "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
ofs, enable_bit); return -ENODEV;
}
return 0;
}
/* tp->lock is held. */ staticint tg3_abort_hw(struct tg3 *tp, bool silent)
{ int i, err;
for (i = 0; i < MAX_WAIT_CNT; i++) {
udelay(100); if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) break;
} if (i >= MAX_WAIT_CNT) {
dev_err(&tp->pdev->dev, "%s timed out, TX_MODE_ENABLE will not clear " "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
err |= -ENODEV;
}
/* Set MAX PCI retry to zero. */
val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
tg3_flag(tp, PCIX_MODE))
val |= PCISTATE_RETRY_SAME_DMA; /* Allow reads and writes to the APE register and memory space. */ if (tg3_flag(tp, ENABLE_APE))
val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
PCISTATE_ALLOW_APE_SHMEM_WR |
PCISTATE_ALLOW_APE_PSPACE_WR;
pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
switch (tg3_asic_rev(tp)) { case ASIC_REV_5717:
val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
TG3_CPMU_MAC_ORIDE_ENABLE); break;
case ASIC_REV_5719: case ASIC_REV_5720:
tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN); break;
switch (tg3_asic_rev(tp)) { case ASIC_REV_5717:
val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
val & ~TG3_CPMU_MAC_ORIDE_ENABLE); break;
case ASIC_REV_5719: case ASIC_REV_5720:
val = tr32(TG3_CPMU_CLCK_ORIDE);
tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN); break;
default: return;
}
}
/* tp->lock is held. */ staticint tg3_chip_reset(struct tg3 *tp)
__releases(tp->lock)
__acquires(tp->lock)
{
u32 val; void (*write_op)(struct tg3 *, u32, u32); int i, err;
if (!pci_device_is_present(tp->pdev)) return -ENODEV;
tg3_nvram_lock(tp);
tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
/* No matching tg3_nvram_unlock() after this because * chip reset below will undo the nvram lock.
*/
tp->nvram_lock_cnt = 0;
/* GRC_MISC_CFG core clock reset will clear the memory * enable bit in PCI register 4 and the MSI enable bit * on some chips, so we save relevant registers here.
*/
tg3_save_pci_state(tp);
if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
tg3_flag(tp, 5755_PLUS))
tw32(GRC_FASTBOOT_PC, 0);
/* * We must avoid the readl() that normally takes place. * It locks machines, causes machine checks, and other * fun things. So, temporarily disable the 5701 * hardware workaround, while we do the reset.
*/
write_op = tp->write32; if (write_op == tg3_write_flush_reg32)
tp->write32 = tg3_write32;
/* Prevent the irq handler from reading or writing PCI registers * during chip reset when the memory enable bit in the PCI command * register may be cleared. The chip does not generate interrupt * at this time, but the irq handler may still be called due to irq * sharing or irqpoll.
*/
tg3_flag_set(tp, CHIP_RESETTING); for (i = 0; i < tp->irq_cnt; i++) { struct tg3_napi *tnapi = &tp->napi[i]; if (tnapi->hw_status) {
tnapi->hw_status->status = 0;
tnapi->hw_status->status_tag = 0;
}
tnapi->last_tag = 0;
tnapi->last_irq_tag = 0;
}
smp_mb();
tg3_full_unlock(tp);
for (i = 0; i < tp->irq_cnt; i++)
synchronize_irq(tp->napi[i].irq_vec);
tg3_full_lock(tp, 0);
if (tg3_asic_rev(tp) == ASIC_REV_57780) {
val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
}
/* do the reset */
val = GRC_MISC_CFG_CORECLK_RESET;
if (tg3_flag(tp, PCI_EXPRESS)) { /* Force PCIe 1.0a mode */ if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
!tg3_flag(tp, 57765_PLUS) &&
tr32(TG3_PCIE_PHY_TSTCTL) ==
(TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
tw32(GRC_MISC_CFG, (1 << 29));
val |= (1 << 29);
}
}
/* Set the clock to the highest frequency to avoid timeouts. With link * aware mode, the clock speed could be slow and bootcode does not * complete within the expected time. Override the clock to allow the * bootcode to finish sooner and then restore it.
*/
tg3_override_clk(tp);
/* Manage gphy power for all CPMU absent PCIe devices. */ if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
/* Unfortunately, we have to delay before the PCI read back. * Some 575X chips even will not respond to a PCI cfg access * when the reset command is given to the chip. * * How do these hardware designers expect things to work * properly if the PCI write is posted for a long period * of time? It is always necessary to have some method by * which a register read back can occur to push the write * out which does the reset. * * For most tg3 variants the trick below was working. * Ho hum...
*/
udelay(120);
/* Flush PCI posted writes. The normal MMIO registers * are inaccessible at this time so this is the only * way to make this reliably (actually, this is no longer * the case, see above). I tried to use indirect * register read/write but this upset some 5701 variants.
*/
pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
udelay(120);
if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
u16 val16;
if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) { int j;
u32 cfg_val;
/* Wait for link training to complete. */ for (j = 0; j < 5000; j++)
udelay(100);
val = 0; if (tg3_flag(tp, 5780_CLASS))
val = tr32(MEMARB_MODE);
tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
tg3_stop_fw(tp);
tw32(0x5000, 0x400);
}
if (tg3_flag(tp, IS_SSB_CORE)) { /* * BCM4785: In order to avoid repercussions from using * potentially defective internal ROM, stop the Rx RISC CPU, * which is not required.
*/
tg3_stop_fw(tp);
tg3_halt_cpu(tp, RX_CPU_BASE);
}
err = tg3_poll_fw(tp); if (err) return err;
tw32(GRC_MODE, tp->grc_mode);
if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
val = tr32(0xc4);
if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
val = tp->mac_mode;
} elseif (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
val = tp->mac_mode;
} else
val = 0;
tw32_f(MAC_MODE, val);
udelay(40);
tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
tg3_mdio_start(tp);
if (tg3_flag(tp, PCI_EXPRESS) &&
tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
tg3_asic_rev(tp) != ASIC_REV_5785 &&
!tg3_flag(tp, 57765_PLUS)) {
val = tr32(0x7c00);
tw32(0x7c00, val | (1 << 25));
}
tg3_restore_clk(tp);
/* Increase the core clock speed to fix tx timeout issue for 5762 * with 100Mbps link speed.
*/ if (tg3_asic_rev(tp) == ASIC_REV_5762) {
val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
TG3_CPMU_MAC_ORIDE_ENABLE);
}
/* Zero mailbox registers. */ if (tg3_flag(tp, SUPPORT_MSIX)) { for (i = 1; i < tp->irq_max; i++) {
tp->napi[i].tx_prod = 0;
tp->napi[i].tx_cons = 0; if (tg3_flag(tp, ENABLE_TSS))
tw32_mailbox(tp->napi[i].prodmbox, 0);
tw32_rx_mbox(tp->napi[i].consmbox, 0);
tw32_mailbox_f(tp->napi[i].int_mbox, 1);
tp->napi[i].chk_msi_cnt = 0;
tp->napi[i].last_rx_cons = 0;
tp->napi[i].last_tx_cons = 0;
} if (!tg3_flag(tp, ENABLE_TSS))
tw32_mailbox(tp->napi[0].prodmbox, 0);
} else {
tp->napi[0].tx_prod = 0;
tp->napi[0].tx_cons = 0;
tw32_mailbox(tp->napi[0].prodmbox, 0);
tw32_rx_mbox(tp->napi[0].consmbox, 0);
}
/* Make sure the NIC-based send BD rings are disabled. */ if (!tg3_flag(tp, 5705_PLUS)) {
u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; for (i = 0; i < 16; i++)
tw32_tx_mbox(mbox + i * 8, 0);
}
/* Clear status block in ram. */
memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
#if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE) /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG * flag clear.
*/ if (!tg3_flag(tp, ENABLE_ASF))
rx_mode |= RX_MODE_KEEP_VLAN_TAG; #endif
if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
rx_mode |= RX_MODE_PROMISC;
} elseif (!(dev->flags & IFF_PROMISC)) { /* Add all entries into to the mac addr filter list */ int i = 0; struct netdev_hw_addr *ha;
staticvoid tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
{ int i;
for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
}
staticvoid tg3_rss_check_indir_tbl(struct tg3 *tp)
{ int i;
if (!tg3_flag(tp, SUPPORT_MSIX)) return;
if (tp->rxq_cnt == 1) {
memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl)); return;
}
/* Validate table against current IRQ count */ for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) { if (tp->rss_ind_tbl[i] >= tp->rxq_cnt) break;
}
if (i != TG3_RSS_INDIR_TBL_SIZE)
tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
}
staticvoid tg3_rss_write_indir_tbl(struct tg3 *tp)
{ int i = 0;
u32 reg = MAC_RSS_INDIR_TBL_0;
while (i < TG3_RSS_INDIR_TBL_SIZE) {
u32 val = tp->rss_ind_tbl[i];
i++; for (; i % 8; i++) {
val <<= 4;
val |= tp->rss_ind_tbl[i];
}
tw32(reg, val);
reg += 4;
}
}
/* Enable MAC control of LPI */ if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
tg3_setup_eee(tp);
if (reset_phy)
tg3_phy_reset(tp);
err = tg3_chip_reset(tp); if (err) return err;
tg3_write_sig_legacy(tp, RESET_KIND_INIT);
if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
val = tr32(TG3_CPMU_CTRL);
val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
tw32(TG3_CPMU_CTRL, val);
val = tr32(TG3_CPMU_LSPD_10MB_CLK);
val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
val |= CPMU_LSPD_10MB_MACCLK_6_25;
tw32(TG3_CPMU_LSPD_10MB_CLK, val);
val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
val |= CPMU_LNK_AWARE_MACCLK_6_25;
tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
val = tr32(TG3_CPMU_HST_ACC);
val &= ~CPMU_HST_ACC_MACCLK_MASK;
val |= CPMU_HST_ACC_MACCLK_6_25;
tw32(TG3_CPMU_HST_ACC, val);
}
if (tg3_asic_rev(tp) == ASIC_REV_57780) {
val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
PCIE_PWR_MGMT_L1_THRESH_4MS;
tw32(PCIE_PWR_MGMT_THRESH, val);
val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
}
if (tg3_flag(tp, L1PLLPD_EN)) {
u32 grc_mode = tr32(GRC_MODE);
/* Access the lower 1K of PL PCIE block registers. */
val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
tw32(GRC_MODE, grc_mode);
}
if (tg3_flag(tp, 57765_CLASS)) { if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
u32 grc_mode = tr32(GRC_MODE);
/* Access the lower 1K of PL PCIE block registers. */
val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
val = tr32(TG3_PCIE_TLDLPL_PORT +
TG3_PCIE_PL_LO_PHYCTL5);
tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
tw32(GRC_MODE, grc_mode);
}
if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
u32 grc_mode;
/* Fix transmit hangs */
val = tr32(TG3_CPMU_PADRNG_CTL);
val |= TG3_CPMU_PADRNG_CTL_RDIV2;
tw32(TG3_CPMU_PADRNG_CTL, val);
grc_mode = tr32(GRC_MODE);
/* Access the lower 1K of DL PCIE block registers. */
val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
val = tr32(TG3_PCIE_TLDLPL_PORT +
TG3_PCIE_DL_LO_FTSMAX);
val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
val | TG3_PCIE_DL_LO_FTSMAX_VAL);
tw32(GRC_MODE, grc_mode);
}
val = tr32(TG3_CPMU_LSPD_10MB_CLK);
val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
val |= CPMU_LSPD_10MB_MACCLK_6_25;
tw32(TG3_CPMU_LSPD_10MB_CLK, val);
}
/* This works around an issue with Athlon chipsets on * B3 tigon3 silicon. This bit has no effect on any * other revision. But do not set this on PCI Express * chips and don't even touch the clocks if the CPMU is present.
*/ if (!tg3_flag(tp, CPMU_PRESENT)) { if (!tg3_flag(tp, PCI_EXPRESS))
tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
}
if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
tg3_flag(tp, PCIX_MODE)) {
val = tr32(TG3PCI_PCISTATE);
val |= PCISTATE_RETRY_SAME_DMA;
tw32(TG3PCI_PCISTATE, val);
}
if (tg3_flag(tp, ENABLE_APE)) { /* Allow reads and writes to the * APE register and memory space.
*/
val = tr32(TG3PCI_PCISTATE);
val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
PCISTATE_ALLOW_APE_SHMEM_WR |
PCISTATE_ALLOW_APE_PSPACE_WR;
tw32(TG3PCI_PCISTATE, val);
}
if (tg3_chip_rev(tp) == CHIPREV_5704_BX) { /* Enable some hw fixes. */
val = tr32(TG3PCI_MSI_DATA);
val |= (1 << 26) | (1 << 28) | (1 << 29);
tw32(TG3PCI_MSI_DATA, val);
}
/* Descriptor ring init may make accesses to the * NIC SRAM area to setup the TX descriptors, so we * can only do this after the hardware has been * successfully reset.
*/
err = tg3_init_rings(tp); if (err) return err;
if (tg3_flag(tp, 57765_PLUS)) {
val = tr32(TG3PCI_DMA_RW_CTRL) &
~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; if (!tg3_flag(tp, 57765_CLASS) &&
tg3_asic_rev(tp) != ASIC_REV_5717 &&
tg3_asic_rev(tp) != ASIC_REV_5762)
val |= DMA_RWCTRL_TAGGED_STAT_WA;
tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
} elseif (tg3_asic_rev(tp) != ASIC_REV_5784 &&
tg3_asic_rev(tp) != ASIC_REV_5761) { /* This value is determined during the probe time DMA * engine test, tg3_test_dma.
*/
tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
}
/* Pseudo-header checksum is done by hardware logic and not * the offload processors, so make the chip do the pseudo- * header checksums on receive. For transmit it is more * convenient to do the pseudo-header checksum in software * as Linux does that on transmit for us in all cases.
*/
tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP; if (tp->rxptpctl)
tw32(TG3_RX_PTP_CTL,
tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
if (tg3_flag(tp, PTP_CAPABLE))
val |= GRC_MODE_TIME_SYNC_ENABLE;
tw32(GRC_MODE, tp->grc_mode | val);
/* On one of the AMD platform, MRRS is restricted to 4000 because of * south bridge limitation. As a workaround, Driver is setting MRRS * to 2048 instead of default 4096.
*/ if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) {
val = tr32(TG3PCI_DEV_STATUS_CTRL) & ~MAX_READ_REQ_MASK;
tw32(TG3PCI_DEV_STATUS_CTRL, val | MAX_READ_REQ_SIZE_2048);
}
/* Setup the timer prescalar register. Clock is always 66Mhz. */
val = tr32(GRC_MISC_CFG);
val &= ~0xff;
val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
tw32(GRC_MISC_CFG, val);
/* Initialize MBUF/DESC pool. */ if (tg3_flag(tp, 5750_PLUS)) { /* Do nothing. */
} elseif (tg3_asic_rev(tp) != ASIC_REV_5705) {
tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); if (tg3_asic_rev(tp) == ASIC_REV_5704)
tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); else
tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
} elseif (tg3_flag(tp, TSO_CAPABLE)) { int fw_len;
val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; if (tg3_asic_rev(tp) == ASIC_REV_5719)
val |= BUFMGR_MODE_NO_TX_UNDERRUN; if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
tg3_asic_rev(tp) == ASIC_REV_5762 ||
tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
tw32(BUFMGR_MODE, val); for (i = 0; i < 2000; i++) { if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) break;
udelay(10);
} if (i >= 2000) {
netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); return -ENODEV;
}
if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
tg3_setup_rxbd_thresholds(tp);
/* Initialize TG3_BDINFO's at: * RCVDBDI_STD_BD: standard eth size rx ring * RCVDBDI_JUMBO_BD: jumbo frame rx ring * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) * * like so: * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | * ring attribute flags * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM * * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. * * The size of each ring is fixed in the firmware, but the location is * configurable.
*/
tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
((u64) tpr->rx_std_mapping >> 32));
tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
((u64) tpr->rx_std_mapping & 0xffffffff)); if (!tg3_flag(tp, 5717_PLUS))
tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
NIC_SRAM_RX_BUFFER_DESC);
/* Disable the mini ring */ if (!tg3_flag(tp, 5705_PLUS))
tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
BDINFO_FLAGS_DISABLED);
/* Program the jumbo buffer descriptor ring control * blocks on those devices that have them.
*/ if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
(tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
if (tg3_flag(tp, 57765_PLUS)) {
val = TG3_RX_STD_RING_SIZE(tp);
val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
val |= (TG3_RX_STD_DMA_SZ << 2);
} else
val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
} else
val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
/* Initialize MAC address and backoff seed. */
__tg3_set_mac_addr(tp, false);
/* MTU + ethernet header + FCS + optional VLAN tag */
tw32(MAC_RX_MTU_SIZE,
tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
/* The slot time is changed by tg3_setup_phy if we * run at gigabit with half duplex.
*/
val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
(6 << TX_LENGTHS_IPG_SHIFT) |
(32 << TX_LENGTHS_SLOT_TIME_SHIFT);
if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
tg3_asic_rev(tp) == ASIC_REV_5762)
val |= tr32(MAC_TX_LENGTHS) &
(TX_LENGTHS_JMB_FRM_LEN_MSK |
TX_LENGTHS_CNT_DWN_VAL_MSK);
val = tr32(tgtreg);
tw32(tgtreg, val |
TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
}
/* Receive/send statistics. */ if (tg3_flag(tp, 5750_PLUS)) {
val = tr32(RCVLPC_STATS_ENABLE);
val &= ~RCVLPC_STATSENAB_DACK_FIX;
tw32(RCVLPC_STATS_ENABLE, val);
} elseif ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
tg3_flag(tp, TSO_CAPABLE)) {
val = tr32(RCVLPC_STATS_ENABLE);
val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
tw32(RCVLPC_STATS_ENABLE, val);
} else {
tw32(RCVLPC_STATS_ENABLE, 0xffffff);
}
tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
tw32(SNDDATAI_STATSENAB, 0xffffff);
tw32(SNDDATAI_STATSCTRL,
(SNDDATAI_SCTRL_ENABLE |
SNDDATAI_SCTRL_FASTUPD));
/* Setup host coalescing engine. */
tw32(HOSTCC_MODE, 0); for (i = 0; i < 2000; i++) { if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) break;
udelay(10);
}
__tg3_set_coalesce(tp, &tp->coal);
if (!tg3_flag(tp, 5705_PLUS)) { /* Status/statistics block address. See tg3_timer, * the tg3_periodic_fetch_stats call there, and * tg3_get_stats to see how this works for 5705/5750 chips.
*/
tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
((u64) tp->stats_mapping >> 32));
tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
((u64) tp->stats_mapping & 0xffffffff));
tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
/* Clear statistics and status block memory areas */ for (i = NIC_SRAM_STATS_BLK;
i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
i += sizeof(u32)) {
tg3_write_mem(tp, i, 0);
udelay(40);
}
}
/* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). * If TG3_FLAG_IS_NIC is zero, we should read the * register to preserve the GPIO settings for LOMs. The GPIOs, * whether used as inputs or outputs, are set by boot code after * reset.
*/ if (!tg3_flag(tp, IS_NIC)) {
u32 gpio_mask;
/* GPIO1 must be driven high for eeprom write protect */ if (tg3_flag(tp, EEPROM_WRITE_PROT))
tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
GRC_LCLCTRL_GPIO_OUTPUT1);
}
tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
udelay(100);
if (tg3_flag(tp, USING_MSIX)) {
val = tr32(MSGINT_MODE);
val |= MSGINT_MODE_ENABLE; if (tp->irq_cnt > 1)
val |= MSGINT_MODE_MULTIVEC_EN; if (!tg3_flag(tp, 1SHOT_MSI))
val |= MSGINT_MODE_ONE_SHOT_DISABLE;
tw32(MSGINT_MODE, val);
}
if (!tg3_flag(tp, 5705_PLUS)) {
tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
udelay(40);
}
if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
tg3_asic_rev(tp) == ASIC_REV_5720) { for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) { if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp)) break;
} if (i < TG3_NUM_RDMA_CHANNELS) {
val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
val |= tg3_lso_rd_dma_workaround_bit(tp);
tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
tg3_flag_set(tp, 5719_5720_RDMA_BUG);
}
}
tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); if (!tg3_flag(tp, 5705_PLUS))
tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ; if (tg3_flag(tp, LRG_PROD_RING_CAP))
val |= RCVDBDI_MODE_LRG_RING_SZ;
tw32(RCVDBDI_MODE, val);
tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); if (tg3_flag(tp, HW_TSO_1) ||
tg3_flag(tp, HW_TSO_2) ||
tg3_flag(tp, HW_TSO_3))
tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; if (tg3_flag(tp, ENABLE_TSS))
val |= SNDBDI_MODE_MULTI_TXQ_EN;
tw32(SNDBDI_MODE, val);
tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
err = tg3_load_5701_a0_firmware_fix(tp); if (err) return err;
}
if (tg3_asic_rev(tp) == ASIC_REV_57766) { /* Ignore any errors for the firmware download. If download * fails, the device will operate with EEE disabled
*/
tg3_load_57766_firmware(tp);
}
if (tg3_flag(tp, TSO_CAPABLE)) {
err = tg3_load_tso_firmware(tp); if (err) return err;
}
tp->tx_mode = TX_MODE_ENABLE;
if (tg3_flag(tp, 5755_PLUS) ||
tg3_asic_rev(tp) == ASIC_REV_5906)
tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
!(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { /* Set drive transmission level to 1.2V */ /* only if the signal pre-emphasis bit is not set */
val = tr32(MAC_SERDES_CFG);
val &= 0xfffff000;
val |= 0x880;
tw32(MAC_SERDES_CFG, val);
} if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
tw32(MAC_SERDES_CFG, 0x616000);
}
/* Prevent chip from dropping frames when flow control * is enabled.
*/ if (tg3_flag(tp, 57765_CLASS))
val = 1; else
val = 2;
tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { /* Use hardware link auto-negotiation */
tg3_flag_set(tp, HW_AUTONEG);
}
if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
limit = 8; else
limit = 16; if (tg3_flag(tp, ENABLE_ASF))
limit -= 4; switch (limit) { case 16:
tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
fallthrough; case 15:
tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
fallthrough; case 14:
tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
fallthrough; case 13:
tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
fallthrough; case 12:
tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
fallthrough; case 11:
tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
fallthrough; case 10:
tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
fallthrough; case 9:
tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
fallthrough; case 8:
tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
fallthrough; case 7:
tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
fallthrough; case 6:
tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
fallthrough; case 5:
tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
fallthrough; case 4: /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ case 3: /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ case 2: case 1:
default: break;
}
if (tg3_flag(tp, ENABLE_APE)) /* Write our heartbeat update interval to APE. */
tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
APE_HOST_HEARTBEAT_INT_5SEC);
tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
return 0;
}
/* Called at device open time to get the chip ready for * packet processing. Invoked with tp->lock held.
*/ staticint tg3_init_hw(struct tg3 *tp, bool reset_phy)
{ /* Chip may have been just powered on. If so, the boot code may still * be running initialization. Wait for it to finish to avoid races in * accessing the hardware.
*/
tg3_enable_register_access(tp);
tg3_poll_fw(tp);
tg3_switch_clocks(tp);
tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
return tg3_reset_hw(tp, reset_phy);
}
#ifdef CONFIG_TIGON3_HWMON staticvoid tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
{
u32 off, len = TG3_OCIR_LEN; int i;
for (i = 0, off = 0; i < TG3_SD_NUM_RECS; i++, ocir++, off += len) {
tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) {
spin_unlock(&tp->lock); goto restart_timer;
}
if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
tg3_flag(tp, 57765_CLASS))
tg3_chk_missed_msi(tp);
if (tg3_flag(tp, FLUSH_POSTED_WRITES)) { /* BCM4785: Flush posted writes from GbE to host memory. */
tr32(HOSTCC_MODE);
}
if (!tg3_flag(tp, TAGGED_STATUS)) { /* All of this garbage is because when using non-tagged * IRQ status the mailbox/status_block protocol the chip * uses with the cpu is race prone.
*/ if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
tw32(GRC_LOCAL_CTRL,
tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
} else {
tw32(HOSTCC_MODE, tp->coalesce_mode |
HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
}
if (link_up != tp->link_up)
tg3_setup_phy(tp, false);
}
tp->timer_counter = tp->timer_multiplier;
}
/* Heartbeat is only sent once every 2 seconds. * * The heartbeat is to tell the ASF firmware that the host * driver is still alive. In the event that the OS crashes, * ASF needs to reset the hardware to free up the FIFO space * that may be filled with rx packets destined for the host. * If the FIFO is full, ASF will no longer function properly. * * Unintended resets have been reported on real time kernels * where the timer doesn't run on time. Netpoll will also have * same problem. * * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware * to check the ring condition when the heartbeat is expiring * before doing the reset. This will prevent most unintended * resets.
*/ if (!--tp->asf_counter) { if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
tg3_wait_for_event_ack(tp);
tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
err = tg3_init_hw(tp, true); if (err) {
tg3_full_unlock(tp);
tp->irq_sync = 0;
tg3_napi_enable(tp); /* Clear this flag so that tg3_reset_task_cancel() will not * call cancel_work_sync() and wait forever.
*/
tg3_flag_clear(tp, RESET_TASK_PENDING);
netdev_unlock(tp->dev);
dev_close(tp->dev); goto out;
}
/* * Turn off MSI one shot mode. Otherwise this test has no * observable way to know whether the interrupt was delivered.
*/ if (tg3_flag(tp, 57765_PLUS)) {
val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
tw32(MSGINT_MODE, val);
}
if (intr_ok) { /* Reenable MSI one shot mode. */ if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
tw32(MSGINT_MODE, val);
} return 0;
}
return -EIO;
}
/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is * successfully restored
*/ staticint tg3_test_msi(struct tg3 *tp)
{ int err;
u16 pci_cmd;
if (!tg3_flag(tp, USING_MSI)) return 0;
/* Turn off SERR reporting in case MSI terminates with Master * Abort.
*/
pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
pci_write_config_word(tp->pdev, PCI_COMMAND,
pci_cmd & ~PCI_COMMAND_SERR);
/* MSI test failed, go back to INTx mode */
netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " "to INTx mode. Please report this failure to the PCI " "maintainer and include system chipset information\n");
if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
tp->fw_needed); return -ENOENT;
}
fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
/* Firmware blob starts with version numbers, followed by * start address and _full_ length including BSS sections * (which must be longer than the actual data, of course
*/
tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */ if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
tp->fw_len, tp->fw_needed);
release_firmware(tp->fw);
tp->fw = NULL; return -EINVAL;
}
/* We no longer need firmware; we have it. */
tp->fw_needed = NULL; return 0;
}
if (irq_cnt > 1) { /* We want as many rx rings enabled as there are cpus. * In multiqueue MSI-X mode, the first MSI-X vector * only deals with link interrupts, etc, so we add * one to the number of vectors we are requesting.
*/
irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
}
return irq_cnt;
}
staticbool tg3_enable_msix(struct tg3 *tp)
{ int i, rc; struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
tp->txq_cnt = tp->txq_req;
tp->rxq_cnt = tp->rxq_req; if (!tp->rxq_cnt)
tp->rxq_cnt = netif_get_num_default_rss_queues(); if (tp->rxq_cnt > tp->rxq_max)
tp->rxq_cnt = tp->rxq_max;
/* Disable multiple TX rings by default. Simple round-robin hardware * scheduling of the TX rings can cause starvation of rings with * small packets when other rings have TSO or jumbo packets.
*/ if (!tp->txq_req)
tp->txq_cnt = 1;
tp->irq_cnt = tg3_irq_count(tp);
for (i = 0; i < tp->irq_max; i++) {
msix_ent[i].entry = i;
msix_ent[i].vector = 0;
}
staticvoid tg3_ints_init(struct tg3 *tp)
{ if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
!tg3_flag(tp, TAGGED_STATUS)) { /* All MSI supporting chips should support tagged * status. Assert that this is the case.
*/
netdev_warn(tp->dev, "MSI without TAGGED_STATUS? Not using MSI\n"); goto defcfg;
}
/* * Reset loopback feature if it was turned on while the device was down * make sure that it's installed properly now.
*/ if (dev->features & NETIF_F_LOOPBACK)
tg3_set_loopback(dev, dev->features);
return 0;
out_free_irq: for (i = tp->irq_cnt - 1; i >= 0; i--) { struct tg3_napi *tnapi = &tp->napi[i];
free_irq(tnapi->irq_vec, tnapi);
}
/* Aggregate per-queue counters. The per-queue counters are updated * by a single writer, race-free. The result computed by this loop * might not be 100% accurate (counters can be updated in the middle of * the loop) but the next tg3_get_nstats() will recompute the current * value so it is acceptable. * * Note that these counters wrap around at 4G on 32bit machines.
*/
rx_dropped = (unsignedlong)(old_stats->rx_dropped);
tx_dropped = (unsignedlong)(old_stats->tx_dropped);
for (i = 0; i < tp->irq_cnt; i++) { struct tg3_napi *tnapi = &tp->napi[i];
offset = eeprom->offset;
len = eeprom->len;
eeprom->len = 0;
eeprom->magic = TG3_EEPROM_MAGIC;
/* Override clock, link aware and link idle modes */ if (tg3_flag(tp, CPMU_PRESENT)) {
cpmu_val = tr32(TG3_CPMU_CTRL); if (cpmu_val & (CPMU_CTRL_LINK_AWARE_MODE |
CPMU_CTRL_LINK_IDLE_MODE)) {
tw32(TG3_CPMU_CTRL, cpmu_val &
~(CPMU_CTRL_LINK_AWARE_MODE |
CPMU_CTRL_LINK_IDLE_MODE));
cpmu_restore = 1;
}
}
tg3_override_clk(tp);
if (offset & 3) { /* adjustments to start on required 4 byte boundary */
b_offset = offset & 3;
b_count = 4 - b_offset; if (b_count > len) { /* i.e. offset=1 len=2 */
b_count = len;
}
ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); if (ret) goto eeprom_done;
memcpy(data, ((char *)&val) + b_offset, b_count);
len -= b_count;
offset += b_count;
eeprom->len += b_count;
}
/* read bytes up to the last 4 byte boundary */
pd = &data[eeprom->len]; for (i = 0; i < (len - (len & 3)); i += 4) {
ret = tg3_nvram_read_be32(tp, offset + i, &val); if (ret) { if (i)
i -= 4;
eeprom->len += i; goto eeprom_done;
}
memcpy(pd + i, &val, 4); if (need_resched()) { if (signal_pending(current)) {
eeprom->len += i;
ret = -EINTR; goto eeprom_done;
}
cond_resched();
}
}
eeprom->len += i;
if (len & 3) { /* read last bytes not ending on 4 byte boundary */
pd = &data[eeprom->len];
b_count = len & 3;
b_offset = offset + len - b_count;
ret = tg3_nvram_read_be32(tp, b_offset, &val); if (ret) goto eeprom_done;
memcpy(pd, &val, b_count);
eeprom->len += b_count;
}
ret = 0;
eeprom_done: /* Restore clock, link aware and link idle modes */
tg3_restore_clk(tp); if (cpmu_restore)
tw32(TG3_CPMU_CTRL, cpmu_val);
if (tg3_flag(tp, NO_NVRAM) ||
eeprom->magic != TG3_EEPROM_MAGIC) return -EINVAL;
offset = eeprom->offset;
len = eeprom->len;
if ((b_offset = (offset & 3))) { /* adjustments to start on required 4 byte boundary */
ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); if (ret) return ret;
len += b_offset;
offset &= ~3; if (len < 4)
len = 4;
}
odd_len = 0; if (len & 3) { /* adjustments to end on required 4 byte boundary */
odd_len = 1;
len = (len + 3) & ~3;
ret = tg3_nvram_read_be32(tp, offset+len-4, &end); if (ret) return ret;
}
buf = data; if (b_offset || odd_len) {
buf = kmalloc(len, GFP_KERNEL); if (!buf) return -ENOMEM; if (b_offset)
memcpy(buf, &start, 4); if (odd_len)
memcpy(buf+len-4, &end, 4);
memcpy(buf + b_offset, data, eeprom->len);
}
ret = tg3_nvram_write_block(tp, offset, len, buf);
if (epause->autoneg)
tg3_flag_set(tp, PAUSE_AUTONEG); else
tg3_flag_clear(tp, PAUSE_AUTONEG);
if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { if (phydev->autoneg) { /* phy_set_asym_pause() will * renegotiate the link to inform our * link partner of our flow control * settings, even if the flow control * is forced. Let tg3_adjust_link() * do the final flow control setup.
*/ return 0;
}
if (!epause->autoneg)
tg3_setup_flow_control(tp, 0, 0);
}
} else { int irq_sync = 0;
if (netif_running(dev)) {
tg3_netif_stop(tp);
irq_sync = 1;
}
netdev_lock(dev);
tg3_full_lock(tp, irq_sync);
if (epause->autoneg)
tg3_flag_set(tp, PAUSE_AUTONEG); else
tg3_flag_clear(tp, PAUSE_AUTONEG); if (epause->rx_pause)
tp->link_config.flowctrl |= FLOW_CTRL_RX; else
tp->link_config.flowctrl &= ~FLOW_CTRL_RX; if (epause->tx_pause)
tp->link_config.flowctrl |= FLOW_CTRL_TX; else
tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
if (netif_running(dev)) {
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); /* Reset PHY to avoid PHY lock up */ if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
tg3_asic_rev(tp) == ASIC_REV_5719 ||
tg3_asic_rev(tp) == ASIC_REV_5720)
reset_phy = true;
err = tg3_restart_hw(tp, reset_phy); if (!err)
tg3_netif_start(tp);
}
tg3_full_unlock(tp);
netdev_unlock(dev);
}
tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
return err;
}
staticint tg3_get_sset_count(struct net_device *dev, int sset)
{ switch (sset) { case ETH_SS_TEST: return TG3_NUM_TEST; case ETH_SS_STATS: return TG3_NUM_STATS; default: return -EOPNOTSUPP;
}
}
/* We require at least one supported parameter to be changed and no * change in any of the unsupported parameters
*/ if (rxfh->key ||
(rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE &&
rxfh->hfunc != ETH_RSS_HASH_TOP)) return -EOPNOTSUPP;
if (!rxfh->indir) return 0;
for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
tp->rss_ind_tbl[i] = rxfh->indir[i];
if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS)) return 0;
/* It is legal to write the indirection * table while the device is running.
*/
tg3_full_lock(tp, 0);
tg3_rss_write_indir_tbl(tp);
tg3_full_unlock(tp);
if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic)) return NULL;
if (magic == TG3_EEPROM_MAGIC) { for (offset = TG3_NVM_DIR_START;
offset < TG3_NVM_DIR_END;
offset += TG3_NVM_DIRENT_SIZE) { if (tg3_nvram_read(tp, offset, &val)) return NULL;
if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
TG3_NVM_DIRTYPE_EXTVPD) break;
}
if (offset != TG3_NVM_DIR_END) {
len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4; if (tg3_nvram_read(tp, offset + 4, &offset)) return NULL;
offset = tg3_nvram_logical_addr(tp, offset);
}
if (!offset || !len) {
offset = TG3_NVM_VPD_OFF;
len = TG3_NVM_VPD_LEN;
}
buf = kmalloc(len, GFP_KERNEL); if (!buf) return NULL;
for (i = 0; i < len; i += 4) { /* The data is in little-endian format in NVRAM. * Use the big-endian read routines to preserve * the byte order as it exists in NVRAM.
*/ if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4])) goto error;
}
*vpdlen = len;
} else {
buf = pci_vpd_alloc(tp->pdev, vpdlen); if (IS_ERR(buf)) return NULL;
}
if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
TG3_EEPROM_SB_REVISION_2) { /* For rev 2, the csum doesn't include the MBA. */ for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
csum8 += buf8[i]; for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
csum8 += buf8[i];
} else { for (i = 0; i < size; i++)
csum8 += buf8[i];
}
/* Separate the parity bits and the data bytes. */ for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { if ((i == 0) || (i == 8)) { int l;
u8 msk;
for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
parity[k++] = buf8[i] & msk;
i++;
} elseif (i == 16) { int l;
u8 msk;
for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
parity[k++] = buf8[i] & msk;
i++;
/* Write zero to the register, then make sure the read-only bits * are not changed and the read/write bits are all zeros.
*/
tw32(offset, 0);
val = tr32(offset);
/* Test the read-only and read/write bits. */ if (((val & read_mask) != read_val) || (val & write_mask)) goto out;
/* Write ones to all the bits defined by RdMask and WrMask, then * make sure the read-only bits are not changed and the * read/write bits are all ones.
*/
tw32(offset, read_mask | write_mask);
val = tr32(offset);
/* Test the read-only bits. */ if ((val & read_mask) != read_val) goto out;
/* Test the read/write bits. */ if ((val & write_mask) != write_mask) goto out;
tw32(offset, save_val);
}
return 0;
out: if (netif_msg_hw(tp))
netdev_err(tp->dev, "Register test failed at offset %x\n", offset);
tw32(offset, save_val); return -EIO;
}
/* 350 usec to allow enough time on some 10/100 Mbps devices. */ for (i = 0; i < 35; i++) {
tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
coal_now);
/* Reroute all rx packets to the 1st queue */ for (i = MAC_RSS_INDIR_TBL_0;
i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
tw32(i, 0x0);
}
/* HW errata - mac loopback fails in some cases on 5780. * Normal traffic and PHY loopback are not affected by * errata. Also, the MAC loopback test is deprecated for * all newer ASIC revisions.
*/ if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
!tg3_flag(tp, CPMU_PRESENT)) {
tg3_mac_loopback(tp, true);
if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
netdev_warn(tp->dev, "Board does not support EEE!\n"); return -EOPNOTSUPP;
}
if (!linkmode_equal(edata->advertised, tp->eee.advertised)) {
netdev_warn(tp->dev, "Direct manipulation of EEE advertisement is not supported\n"); return -EINVAL;
}
if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
netdev_warn(tp->dev, "Maximal Tx Lpi timer supported is %#x(u)\n",
TG3_CPMU_DBTMR1_LNKIDLE_MAX); return -EINVAL;
}
staticint tg3_change_mtu(struct net_device *dev, int new_mtu)
{ struct tg3 *tp = netdev_priv(dev); int err; bool reset_phy = false;
if (!netif_running(dev)) { /* We'll just catch it later when the * device is up'd.
*/
tg3_set_mtu(dev, tp, new_mtu); return 0;
}
tg3_phy_stop(tp);
tg3_netif_stop(tp);
tg3_set_mtu(dev, tp, new_mtu);
netdev_lock(dev);
tg3_full_lock(tp, 1);
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
/* Reset PHY, otherwise the read DMA engine will be in a mode that * breaks all requests to 256 bytes.
*/ if (tg3_asic_rev(tp) == ASIC_REV_57766 ||
tg3_asic_rev(tp) == ASIC_REV_5717 ||
tg3_asic_rev(tp) == ASIC_REV_5719 ||
tg3_asic_rev(tp) == ASIC_REV_5720)
reset_phy = true;
/* * Size the chip by reading offsets at increasing powers of two. * When we encounter our validation signature, we know the addressing * has wrapped around, and thus have our chip size.
*/
cursize = 0x10;
while (cursize < tp->nvram_size) { if (tg3_nvram_read(tp, cursize, &val) != 0) return;
if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0) return;
/* Selfboot format */ if (val != TG3_EEPROM_MAGIC) {
tg3_get_eeprom_size(tp); return;
}
if (tg3_nvram_read(tp, 0xf0, &val) == 0) { if (val != 0) { /* This is confusing. We want to operate on the * 16-bit value at offset 0xf2. The tg3_nvram_read() * call will read from NVRAM and byteswap the data * according to the byteswapping settings for all * other register accesses. This ensures the data we * want will always reside in the lower 16-bits. * However, the data in NVRAM is in LE format, which * means the data from the NVRAM read will always be * opposite the endianness of the CPU. The 16-bit * byteswap then brings the data to CPU endianness.
*/
tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; return;
}
}
tp->nvram_size = TG3_NVRAM_SIZE_512KB;
}
/* NVRAM protection for TPM */ if (nvcfg1 & (1 << 27))
tg3_flag_set(tp, PROTECTED_NVRAM);
switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
tp->nvram_jedecnum = JEDEC_ATMEL;
tg3_flag_set(tp, NVRAM_BUFFERED); break; case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
tp->nvram_jedecnum = JEDEC_ATMEL;
tg3_flag_set(tp, NVRAM_BUFFERED);
tg3_flag_set(tp, FLASH); break; case FLASH_5752VENDOR_ST_M45PE10: case FLASH_5752VENDOR_ST_M45PE20: case FLASH_5752VENDOR_ST_M45PE40:
tp->nvram_jedecnum = JEDEC_ST;
tg3_flag_set(tp, NVRAM_BUFFERED);
tg3_flag_set(tp, FLASH); break;
}
if (tg3_flag(tp, FLASH)) {
tg3_nvram_get_pagesize(tp, nvcfg1);
} else { /* For eeprom, set pagesize to maximum eeprom size */
tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
/* NVRAM protection for TPM */ if (nvcfg1 & (1 << 27)) {
tg3_flag_set(tp, PROTECTED_NVRAM);
protect = 1;
}
nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; switch (nvcfg1) { case FLASH_5761VENDOR_ATMEL_ADB021D: case FLASH_5761VENDOR_ATMEL_ADB041D: case FLASH_5761VENDOR_ATMEL_ADB081D: case FLASH_5761VENDOR_ATMEL_ADB161D: case FLASH_5761VENDOR_ATMEL_MDB021D: case FLASH_5761VENDOR_ATMEL_MDB041D: case FLASH_5761VENDOR_ATMEL_MDB081D: case FLASH_5761VENDOR_ATMEL_MDB161D:
tp->nvram_jedecnum = JEDEC_ATMEL;
tg3_flag_set(tp, NVRAM_BUFFERED);
tg3_flag_set(tp, FLASH);
tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
tp->nvram_pagesize = 256; break; case FLASH_5761VENDOR_ST_A_M45PE20: case FLASH_5761VENDOR_ST_A_M45PE40: case FLASH_5761VENDOR_ST_A_M45PE80: case FLASH_5761VENDOR_ST_A_M45PE16: case FLASH_5761VENDOR_ST_M_M45PE20: case FLASH_5761VENDOR_ST_M_M45PE40: case FLASH_5761VENDOR_ST_M_M45PE80: case FLASH_5761VENDOR_ST_M_M45PE16:
tp->nvram_jedecnum = JEDEC_ST;
tg3_flag_set(tp, NVRAM_BUFFERED);
tg3_flag_set(tp, FLASH);
tp->nvram_pagesize = 256; break;
}
if (protect) {
tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
} else { switch (nvcfg1) { case FLASH_5761VENDOR_ATMEL_ADB161D: case FLASH_5761VENDOR_ATMEL_MDB161D: case FLASH_5761VENDOR_ST_A_M45PE16: case FLASH_5761VENDOR_ST_M_M45PE16:
tp->nvram_size = TG3_NVRAM_SIZE_2MB; break; case FLASH_5761VENDOR_ATMEL_ADB081D: case FLASH_5761VENDOR_ATMEL_MDB081D: case FLASH_5761VENDOR_ST_A_M45PE80: case FLASH_5761VENDOR_ST_M_M45PE80:
tp->nvram_size = TG3_NVRAM_SIZE_1MB; break; case FLASH_5761VENDOR_ATMEL_ADB041D: case FLASH_5761VENDOR_ATMEL_MDB041D: case FLASH_5761VENDOR_ST_A_M45PE40: case FLASH_5761VENDOR_ST_M_M45PE40:
tp->nvram_size = TG3_NVRAM_SIZE_512KB; break; case FLASH_5761VENDOR_ATMEL_ADB021D: case FLASH_5761VENDOR_ATMEL_MDB021D: case FLASH_5761VENDOR_ST_A_M45PE20: case FLASH_5761VENDOR_ST_M_M45PE20:
tp->nvram_size = TG3_NVRAM_SIZE_256KB; break;
}
}
}
switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
tp->nvram_jedecnum = JEDEC_ATMEL;
tg3_flag_set(tp, NVRAM_BUFFERED);
tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
tw32(NVRAM_CFG1, nvcfg1); return; case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: case FLASH_57780VENDOR_ATMEL_AT45DB011D: case FLASH_57780VENDOR_ATMEL_AT45DB011B: case FLASH_57780VENDOR_ATMEL_AT45DB021D: case FLASH_57780VENDOR_ATMEL_AT45DB021B: case FLASH_57780VENDOR_ATMEL_AT45DB041D: case FLASH_57780VENDOR_ATMEL_AT45DB041B:
tp->nvram_jedecnum = JEDEC_ATMEL;
tg3_flag_set(tp, NVRAM_BUFFERED);
tg3_flag_set(tp, FLASH);
switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: case FLASH_57780VENDOR_ATMEL_AT45DB011D: case FLASH_57780VENDOR_ATMEL_AT45DB011B:
tp->nvram_size = TG3_NVRAM_SIZE_128KB; break; case FLASH_57780VENDOR_ATMEL_AT45DB021D: case FLASH_57780VENDOR_ATMEL_AT45DB021B:
tp->nvram_size = TG3_NVRAM_SIZE_256KB; break; case FLASH_57780VENDOR_ATMEL_AT45DB041D: case FLASH_57780VENDOR_ATMEL_AT45DB041B:
tp->nvram_size = TG3_NVRAM_SIZE_512KB; break;
} break; case FLASH_5752VENDOR_ST_M45PE10: case FLASH_5752VENDOR_ST_M45PE20: case FLASH_5752VENDOR_ST_M45PE40:
tp->nvram_jedecnum = JEDEC_ST;
tg3_flag_set(tp, NVRAM_BUFFERED);
tg3_flag_set(tp, FLASH);
switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { case FLASH_5752VENDOR_ST_M45PE10:
tp->nvram_size = TG3_NVRAM_SIZE_128KB; break; case FLASH_5752VENDOR_ST_M45PE20:
tp->nvram_size = TG3_NVRAM_SIZE_256KB; break; case FLASH_5752VENDOR_ST_M45PE40:
tp->nvram_size = TG3_NVRAM_SIZE_512KB; break;
} break; default:
tg3_flag_set(tp, NO_NVRAM); return;
}
switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { case FLASH_5717VENDOR_ATMEL_EEPROM: case FLASH_5717VENDOR_MICRO_EEPROM:
tp->nvram_jedecnum = JEDEC_ATMEL;
tg3_flag_set(tp, NVRAM_BUFFERED);
tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
tw32(NVRAM_CFG1, nvcfg1); return; case FLASH_5717VENDOR_ATMEL_MDB011D: case FLASH_5717VENDOR_ATMEL_ADB011B: case FLASH_5717VENDOR_ATMEL_ADB011D: case FLASH_5717VENDOR_ATMEL_MDB021D: case FLASH_5717VENDOR_ATMEL_ADB021B: case FLASH_5717VENDOR_ATMEL_ADB021D: case FLASH_5717VENDOR_ATMEL_45USPT:
tp->nvram_jedecnum = JEDEC_ATMEL;
tg3_flag_set(tp, NVRAM_BUFFERED);
tg3_flag_set(tp, FLASH);
switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { case FLASH_5717VENDOR_ATMEL_MDB021D: /* Detect size with tg3_nvram_get_size() */ break; case FLASH_5717VENDOR_ATMEL_ADB021B: case FLASH_5717VENDOR_ATMEL_ADB021D:
tp->nvram_size = TG3_NVRAM_SIZE_256KB; break; default:
tp->nvram_size = TG3_NVRAM_SIZE_128KB; break;
} break; case FLASH_5717VENDOR_ST_M_M25PE10: case FLASH_5717VENDOR_ST_A_M25PE10: case FLASH_5717VENDOR_ST_M_M45PE10: case FLASH_5717VENDOR_ST_A_M45PE10: case FLASH_5717VENDOR_ST_M_M25PE20: case FLASH_5717VENDOR_ST_A_M25PE20: case FLASH_5717VENDOR_ST_M_M45PE20: case FLASH_5717VENDOR_ST_A_M45PE20: case FLASH_5717VENDOR_ST_25USPT: case FLASH_5717VENDOR_ST_45USPT:
tp->nvram_jedecnum = JEDEC_ST;
tg3_flag_set(tp, NVRAM_BUFFERED);
tg3_flag_set(tp, FLASH);
switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { case FLASH_5717VENDOR_ST_M_M25PE20: case FLASH_5717VENDOR_ST_M_M45PE20: /* Detect size with tg3_nvram_get_size() */ break; case FLASH_5717VENDOR_ST_A_M25PE20: case FLASH_5717VENDOR_ST_A_M45PE20:
tp->nvram_size = TG3_NVRAM_SIZE_256KB; break; default:
tp->nvram_size = TG3_NVRAM_SIZE_128KB; break;
} break; default:
tg3_flag_set(tp, NO_NVRAM); return;
}
if (tg3_asic_rev(tp) == ASIC_REV_5762) { if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
tg3_flag_set(tp, NO_NVRAM); return;
}
switch (nvmpinstrp) { case FLASH_5762_MX25L_100: case FLASH_5762_MX25L_200: case FLASH_5762_MX25L_400: case FLASH_5762_MX25L_800: case FLASH_5762_MX25L_160_320:
tp->nvram_pagesize = 4096;
tp->nvram_jedecnum = JEDEC_MACRONIX;
tg3_flag_set(tp, NVRAM_BUFFERED);
tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
tg3_flag_set(tp, FLASH);
nv_status = tr32(NVRAM_AUTOSENSE_STATUS);
tp->nvram_size =
(1 << (nv_status >> AUTOSENSE_DEVID &
AUTOSENSE_DEVID_MASK)
<< AUTOSENSE_SIZE_IN_MB); return;
case FLASH_5762_EEPROM_HD:
nvmpinstrp = FLASH_5720_EEPROM_HD; break; case FLASH_5762_EEPROM_LD:
nvmpinstrp = FLASH_5720_EEPROM_LD; break; case FLASH_5720VENDOR_M_ST_M45PE20: /* This pinstrap supports multiple sizes, so force it * to read the actual size from location 0xf0.
*/
nvmpinstrp = FLASH_5720VENDOR_ST_45USPT; break;
}
}
switch (nvmpinstrp) { case FLASH_5720_EEPROM_HD: case FLASH_5720_EEPROM_LD:
tp->nvram_jedecnum = JEDEC_ATMEL;
tg3_flag_set(tp, NVRAM_BUFFERED);
nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
tw32(NVRAM_CFG1, nvcfg1); if (nvmpinstrp == FLASH_5720_EEPROM_HD)
tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; else
tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; return; case FLASH_5720VENDOR_M_ATMEL_DB011D: case FLASH_5720VENDOR_A_ATMEL_DB011B: case FLASH_5720VENDOR_A_ATMEL_DB011D: case FLASH_5720VENDOR_M_ATMEL_DB021D: case FLASH_5720VENDOR_A_ATMEL_DB021B: case FLASH_5720VENDOR_A_ATMEL_DB021D: case FLASH_5720VENDOR_M_ATMEL_DB041D: case FLASH_5720VENDOR_A_ATMEL_DB041B: case FLASH_5720VENDOR_A_ATMEL_DB041D: case FLASH_5720VENDOR_M_ATMEL_DB081D: case FLASH_5720VENDOR_A_ATMEL_DB081D: case FLASH_5720VENDOR_ATMEL_45USPT:
tp->nvram_jedecnum = JEDEC_ATMEL;
tg3_flag_set(tp, NVRAM_BUFFERED);
tg3_flag_set(tp, FLASH);
switch (nvmpinstrp) { case FLASH_5720VENDOR_M_ATMEL_DB021D: case FLASH_5720VENDOR_A_ATMEL_DB021B: case FLASH_5720VENDOR_A_ATMEL_DB021D:
tp->nvram_size = TG3_NVRAM_SIZE_256KB; break; case FLASH_5720VENDOR_M_ATMEL_DB041D: case FLASH_5720VENDOR_A_ATMEL_DB041B: case FLASH_5720VENDOR_A_ATMEL_DB041D:
tp->nvram_size = TG3_NVRAM_SIZE_512KB; break; case FLASH_5720VENDOR_M_ATMEL_DB081D: case FLASH_5720VENDOR_A_ATMEL_DB081D:
tp->nvram_size = TG3_NVRAM_SIZE_1MB; break; default: if (tg3_asic_rev(tp) != ASIC_REV_5762)
tp->nvram_size = TG3_NVRAM_SIZE_128KB; break;
} break; case FLASH_5720VENDOR_M_ST_M25PE10: case FLASH_5720VENDOR_M_ST_M45PE10: case FLASH_5720VENDOR_A_ST_M25PE10: case FLASH_5720VENDOR_A_ST_M45PE10: case FLASH_5720VENDOR_M_ST_M25PE20: case FLASH_5720VENDOR_M_ST_M45PE20: case FLASH_5720VENDOR_A_ST_M25PE20: case FLASH_5720VENDOR_A_ST_M45PE20: case FLASH_5720VENDOR_M_ST_M25PE40: case FLASH_5720VENDOR_M_ST_M45PE40: case FLASH_5720VENDOR_A_ST_M25PE40: case FLASH_5720VENDOR_A_ST_M45PE40: case FLASH_5720VENDOR_M_ST_M25PE80: case FLASH_5720VENDOR_M_ST_M45PE80: case FLASH_5720VENDOR_A_ST_M25PE80: case FLASH_5720VENDOR_A_ST_M45PE80: case FLASH_5720VENDOR_ST_25USPT: case FLASH_5720VENDOR_ST_45USPT:
tp->nvram_jedecnum = JEDEC_ST;
tg3_flag_set(tp, NVRAM_BUFFERED);
tg3_flag_set(tp, FLASH);
switch (nvmpinstrp) { case FLASH_5720VENDOR_M_ST_M25PE20: case FLASH_5720VENDOR_M_ST_M45PE20: case FLASH_5720VENDOR_A_ST_M25PE20: case FLASH_5720VENDOR_A_ST_M45PE20:
tp->nvram_size = TG3_NVRAM_SIZE_256KB; break; case FLASH_5720VENDOR_M_ST_M25PE40: case FLASH_5720VENDOR_M_ST_M45PE40: case FLASH_5720VENDOR_A_ST_M25PE40: case FLASH_5720VENDOR_A_ST_M45PE40:
tp->nvram_size = TG3_NVRAM_SIZE_512KB; break; case FLASH_5720VENDOR_M_ST_M25PE80: case FLASH_5720VENDOR_M_ST_M45PE80: case FLASH_5720VENDOR_A_ST_M25PE80: case FLASH_5720VENDOR_A_ST_M45PE80:
tp->nvram_size = TG3_NVRAM_SIZE_1MB; break; default: if (tg3_asic_rev(tp) != ASIC_REV_5762)
tp->nvram_size = TG3_NVRAM_SIZE_128KB; break;
} break; default:
tg3_flag_set(tp, NO_NVRAM); return;
}
/* Chips other than 5700/5701 use the NVRAM for fetching info. */ staticvoid tg3_nvram_init(struct tg3 *tp)
{ if (tg3_flag(tp, IS_SSB_CORE)) { /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
tg3_flag_clear(tp, NVRAM);
tg3_flag_clear(tp, NVRAM_BUFFERED);
tg3_flag_set(tp, NO_NVRAM); return;
}
switch (led_cfg) { default: case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
tp->led_ctrl = LED_CTRL_MODE_PHY_1; break;
case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
tp->led_ctrl = LED_CTRL_MODE_PHY_2; break;
case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
tp->led_ctrl = LED_CTRL_MODE_MAC;
/* Default to PHY_1_MODE if 0 (MAC_MODE) is * read on some older 5700/5701 bootcode.
*/ if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
tg3_asic_rev(tp) == ASIC_REV_5701)
tp->led_ctrl = LED_CTRL_MODE_PHY_1;
break;
case SHASTA_EXT_LED_SHARED:
tp->led_ctrl = LED_CTRL_MODE_SHARED; if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
LED_CTRL_MODE_PHY_2);
if (cfg2 & (1 << 17))
tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
/* serdes signal pre-emphasis in register 0x590 set by */ /* bootcode if bit 18 is set */ if (cfg2 & (1 << 18))
tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
/* Wait for up to 1 ms for command to execute. */ for (i = 0; i < 100; i++) {
val = tr32(OTP_STATUS); if (val & OTP_STATUS_CMD_DONE) break;
udelay(10);
}
/* Read the gphy configuration from the OTP region of the chip. The gphy * configuration is a 32-bit value that straddles the alignment boundary. * We do two 32-bit reads and then shift and merge the results.
*/ static u32 tg3_read_otp_phycfg(struct tg3 *tp)
{
u32 bhalf_otp, thalf_otp;
tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) return 0;
tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) return 0;
thalf_otp = tr32(OTP_READ_DATA);
tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) return 0;
if (tg3_flag(tp, USE_PHYLIB)) return tg3_phy_init(tp);
/* Reading the PHY ID register can conflict with ASF * firmware access to the PHY hardware.
*/
err = 0; if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
} else { /* Now read the physical PHY_ID from the chip and verify * that it is sane. If it doesn't look good, we fall back * to either the hard-coded table based PHY_ID and failing * that the value found in the eeprom area.
*/
err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
tp->phy_id = hw_phy_id; if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; else
tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
} else { if (tp->phy_id != TG3_PHY_ID_INVALID) { /* Do nothing, phy ID already set up in * tg3_get_eeprom_hw_cfg().
*/
} else { struct subsys_tbl_ent *p;
/* No eeprom signature? Try the hardcoded * subsys device table.
*/
p = tg3_lookup_by_subsys(tp); if (p) {
tp->phy_id = p->phy_id;
} elseif (!tg3_flag(tp, IS_SSB_CORE)) { /* For now we saw the IDs 0xbc050cd0, * 0xbc050f80 and 0xbc050c30 on devices * connected to an BCM4785 and there are * probably more. Just assume that the phy is * supported when it is connected to a SSB core * for now.
*/ return -ENODEV;
}
for (func = 0; func < 8; func++) {
peer = pci_get_slot(tp->pdev->bus, devnr | func); if (peer && peer != tp->pdev) break;
pci_dev_put(peer);
} /* 5704 can be configured in single-port mode, set peer to * tp->pdev in that case.
*/ if (!peer) {
peer = tp->pdev; return peer;
}
/* * We don't need to keep the refcount elevated; there's no way * to remove one half of this device without removing the other
*/
pci_dev_put(peer);
/* Wrong chip ID in 5752 A0. This code can be removed later * as A0 is not in production.
*/ if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
/* Force memory write invalidate off. If we leave it on, * then on 5700_BX chips we have to enable a workaround. * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary * to match the cacheline size. The Broadcom driver have this * workaround but turns MWI off all the times so never uses * it. This seems to suggest that the workaround is insufficient.
*/
pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
pci_cmd &= ~PCI_COMMAND_INVALIDATE;
pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
/* Important! -- Make sure register accesses are byteswapped * correctly. Also, for those chips that require it, make * sure that indirect register accesses are enabled before * the first operation.
*/
pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
&misc_ctrl_reg);
tp->misc_host_ctrl |= (misc_ctrl_reg &
MISC_HOST_CTRL_CHIPREV);
pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
tp->misc_host_ctrl);
tg3_detect_asic_rev(tp, misc_ctrl_reg);
/* If we have 5702/03 A1 or A2 on certain ICH chipsets, * we need to disable memory and use config. cycles * only to access all registers. The 5702/03 chips * can mistakenly decode the special cycles from the * ICH chipsets as memory write cycles, causing corruption * of register and memory space. Only certain ICH bridges * will drive special cycles with non-zero data during the * address phase which can fall within the 5703's address * range. This is not an ICH bug as the PCI spec allows * non-zero address during special cycles. However, only * these ICH bridges are known to drive non-zero addresses * during special cycles. * * Since special cycles do not cross PCI bridges, we only * enable this workaround if the 5703 is on the secondary * bus of these ICH bridges.
*/ if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
(tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) { staticstruct tg3_dev_id {
u32 vendor;
u32 device;
u32 rev;
} ich_chipsets[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
PCI_ANY_ID },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
PCI_ANY_ID },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
0xa },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
PCI_ANY_ID },
{ },
}; struct tg3_dev_id *pci_id = &ich_chipsets[0]; struct pci_dev *bridge = NULL;
while (pci_id->vendor != 0) {
bridge = pci_get_device(pci_id->vendor, pci_id->device,
bridge); if (!bridge) {
pci_id++; continue;
} if (pci_id->rev != PCI_ANY_ID) { if (bridge->revision > pci_id->rev) continue;
} if (bridge->subordinate &&
(bridge->subordinate->number ==
tp->pdev->bus->number)) {
tg3_flag_set(tp, ICH_WORKAROUND);
pci_dev_put(bridge); break;
}
}
}
/* The EPB bridge inside 5714, 5715, and 5780 cannot support * DMA addresses > 40-bit. This bridge may have other additional * 57xx devices behind it in some 4-port NIC designs for example. * Any tg3 device found behind the bridge will also need the 40-bit * DMA workaround.
*/ if (tg3_flag(tp, 5780_CLASS)) {
tg3_flag_set(tp, 40BIT_DMA_BUG);
tp->msi_cap = tp->pdev->msi_cap;
} else { struct pci_dev *bridge = NULL;
do {
bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
PCI_DEVICE_ID_SERVERWORKS_EPB,
bridge); if (bridge && bridge->subordinate &&
(bridge->subordinate->number <=
tp->pdev->bus->number) &&
(bridge->subordinate->busn_res.end >=
tp->pdev->bus->number)) {
tg3_flag_set(tp, 40BIT_DMA_BUG);
pci_dev_put(bridge); break;
}
} while (bridge);
}
pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl); if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { if (tg3_asic_rev(tp) == ASIC_REV_5906) {
tg3_flag_clear(tp, HW_TSO_2);
tg3_flag_clear(tp, TSO_CAPABLE);
} if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
tg3_asic_rev(tp) == ASIC_REV_5761 ||
tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
tg3_flag_set(tp, CLKREQ_BUG);
} elseif (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
tg3_flag_set(tp, L1PLLPD_EN);
}
} elseif (tg3_asic_rev(tp) == ASIC_REV_5785) { /* BCM5785 devices are effectively PCIe devices, and should * follow PCIe codepaths, but do not have a PCIe capabilities * section.
*/
tg3_flag_set(tp, PCI_EXPRESS);
} elseif (!tg3_flag(tp, 5705_PLUS) ||
tg3_flag(tp, 5780_CLASS)) {
tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); if (!tp->pcix_cap) {
dev_err(&tp->pdev->dev, "Cannot find PCI-X capability, aborting\n"); return -EIO;
}
if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
tg3_flag_set(tp, PCIX_MODE);
}
/* If we have an AMD 762 or VIA K8T800 chipset, write * reordering to the mailbox registers done by the host * controller can cause major troubles. We read back from * every mailbox register write to force the writes to be * posted to the chip in order.
*/ if (pci_dev_present(tg3_write_reorder_chipsets) &&
!tg3_flag(tp, PCI_EXPRESS))
tg3_flag_set(tp, MBOX_WRITE_REORDER);
/* Important! -- It is critical that the PCI-X hw workaround * situation is decided before the first MMIO register access.
*/ if (tg3_chip_rev(tp) == CHIPREV_5700_BX) { /* 5700 BX chips need to have their TX producer index * mailboxes written twice to workaround a bug.
*/
tg3_flag_set(tp, TXD_MBOX_HWBUG);
/* If we are in PCI-X mode, enable register write workaround. * * The workaround is to use indirect register accesses * for all chip writes not to mailbox registers.
*/ if (tg3_flag(tp, PCIX_MODE)) {
u32 pm_reg;
tg3_flag_set(tp, PCIX_TARGET_HWBUG);
/* The chip can have its power management PCI config * space registers clobbered due to this bug. * So explicitly force the chip into D0 here.
*/
pci_read_config_dword(tp->pdev,
tp->pdev->pm_cap + PCI_PM_CTRL,
&pm_reg);
pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
pci_write_config_dword(tp->pdev,
tp->pdev->pm_cap + PCI_PM_CTRL,
pm_reg);
/* Various workaround register access methods */ if (tg3_flag(tp, PCIX_TARGET_HWBUG))
tp->write32 = tg3_write_indirect_reg32; elseif (tg3_asic_rev(tp) == ASIC_REV_5701 ||
(tg3_flag(tp, PCI_EXPRESS) &&
tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) { /* * Back to back register writes can cause problems on these * chips, the workaround is to read back all reg writes * except those to mailbox regs. * * See tg3_write_indirect_reg32().
*/
tp->write32 = tg3_write_flush_reg32;
}
if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
tp->write32_tx_mbox = tg3_write32_tx_mbox; if (tg3_flag(tp, MBOX_WRITE_REORDER))
tp->write32_rx_mbox = tg3_write_flush_reg32;
}
/* The memory arbiter has to be enabled in order for SRAM accesses * to succeed. Normally on powerup the tg3 chip firmware will make * sure it is enabled, but other entities such as system netboot * code might disable it.
*/
val = tr32(MEMARB_MODE);
tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
/* Get eeprom hw config before calling tg3_set_power_state(). * In particular, the TG3_FLAG_IS_NIC flag must be * determined before calling tg3_set_power_state() so that * we know whether or not to switch out of Vaux power. * When the flag is set, it means that GPIO1 is used for eeprom * write protect and also implies that it is a LOM where GPIOs * are not used to switch power.
*/
tg3_get_eeprom_hw_cfg(tp);
if (tg3_flag(tp, ENABLE_APE)) { /* Allow reads and writes to the * APE register and memory space.
*/
pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
PCISTATE_ALLOW_APE_SHMEM_WR |
PCISTATE_ALLOW_APE_PSPACE_WR;
pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
pci_state_reg);
/* Set up tp->grc_local_ctrl before calling * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high * will bring 5700's external PHY out of reset. * It is also used as eeprom write protect on LOMs.
*/
tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
tg3_flag(tp, EEPROM_WRITE_PROT))
tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
GRC_LCLCTRL_GPIO_OUTPUT1); /* Unused GPIO3 must be driven as output on 5752 because there * are no pull-up resistors on unused GPIO pins.
*/ elseif (tg3_asic_rev(tp) == ASIC_REV_5752)
tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { /* Turn off the debug UART. */
tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; if (tg3_flag(tp, IS_NIC)) /* Keep VMain power. */
tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
GRC_LCLCTRL_GPIO_OUTPUT0;
}
if (tg3_asic_rev(tp) == ASIC_REV_5762)
tp->grc_local_ctrl |=
tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
/* Switch out of Vaux if it is a NIC */
tg3_pwrsrc_switch_to_vmain(tp);
/* Derive initial jumbo mode from MTU assigned in * ether_setup() via the alloc_etherdev() call
*/ if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
tg3_flag_set(tp, JUMBO_RING_ENABLE);
/* Write some dummy words into the SRAM status block * area, see if it reads back correctly. If the return * value is bad, force enable the PCIX workaround.
*/
sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
/* If the device has an NVRAM, no need to load patch firmware */ if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
!tg3_flag(tp, NO_NVRAM))
tp->fw_needed = NULL;
/* 5700 {AX,BX} chips have a broken status block link * change bit implementation, so we must use the * status register in those cases.
*/ if (tg3_asic_rev(tp) == ASIC_REV_5700)
tg3_flag_set(tp, USE_LINKCHG_REG); else
tg3_flag_clear(tp, USE_LINKCHG_REG);
/* The led_ctrl is set during tg3_phy_probe, here we might * have to force the link status polling mechanism based * upon subsystem IDs.
*/ if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
tg3_asic_rev(tp) == ASIC_REV_5701 &&
!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
tg3_flag_set(tp, USE_LINKCHG_REG);
}
/* For all SERDES we poll the MAC status register. */ if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
tg3_flag_set(tp, POLL_SERDES); else
tg3_flag_clear(tp, POLL_SERDES);
if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))
tg3_flag_set(tp, POLL_CPMU_LINK);
/* Increment the rx prod index on the rx std ring by at most * 8 for these chips to workaround hw errata.
*/ if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
tg3_asic_rev(tp) == ASIC_REV_5752 ||
tg3_asic_rev(tp) == ASIC_REV_5755)
tp->rx_std_max_post = 8;
if (tg3_flag(tp, ASPM_WORKAROUND))
tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
PCIE_PWR_MGMT_L1_THRESH_MSK;
return err;
}
staticint tg3_get_device_address(struct tg3 *tp, u8 *addr)
{
u32 hi, lo, mac_offset; int addr_ok = 0; int err;
if (!eth_platform_get_mac_address(&tp->pdev->dev, addr)) return 0;
if (tg3_flag(tp, IS_SSB_CORE)) {
err = ssb_gige_get_macaddr(tp->pdev, addr); if (!err && is_valid_ether_addr(addr)) return 0;
}
/* First try to get it from MAC address mailbox. */
tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); if ((hi >> 16) == 0x484b) {
addr[0] = (hi >> 8) & 0xff;
addr[1] = (hi >> 0) & 0xff;
tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
addr[2] = (lo >> 24) & 0xff;
addr[3] = (lo >> 16) & 0xff;
addr[4] = (lo >> 8) & 0xff;
addr[5] = (lo >> 0) & 0xff;
/* Some old bootcode may report a 0 MAC address in SRAM */
addr_ok = is_valid_ether_addr(addr);
} if (!addr_ok) {
__be32 be_hi, be_lo;
/* Next, try NVRAM. */ if (!tg3_flag(tp, NO_NVRAM) &&
!tg3_nvram_read_be32(tp, mac_offset + 0, &be_hi) &&
!tg3_nvram_read_be32(tp, mac_offset + 4, &be_lo)) {
memcpy(&addr[0], ((char *)&be_hi) + 2, 2);
memcpy(&addr[2], (char *)&be_lo, sizeof(be_lo));
} /* Finally just fetch it out of the MAC control regs. */ else {
hi = tr32(MAC_ADDR_0_HIGH);
lo = tr32(MAC_ADDR_0_LOW);
addr[5] = lo & 0xff;
addr[4] = (lo >> 8) & 0xff;
addr[3] = (lo >> 16) & 0xff;
addr[2] = (lo >> 24) & 0xff;
addr[1] = hi & 0xff;
addr[0] = (hi >> 8) & 0xff;
}
}
if (!is_valid_ether_addr(addr)) return -EINVAL; return 0;
}
/* On 5703 and later chips, the boundary bits have no * effect.
*/ if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
tg3_asic_rev(tp) != ASIC_REV_5701 &&
!tg3_flag(tp, PCI_EXPRESS)) goto out;
if (tg3_flag(tp, 57765_PLUS)) {
val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; goto out;
}
if (!goal) goto out;
/* PCI controllers on most RISC systems tend to disconnect * when a device tries to burst across a cache-line boundary. * Therefore, letting tg3 do so just wastes PCI bandwidth. * * Unfortunately, for PCI-E there are only limited * write-side controls for this, and thus for reads * we will still get the disconnects. We'll also waste * these PCI cycles for both read and write for chips * other than 5700 and 5701 which do not implement the * boundary bits.
*/ if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) { switch (cacheline_size) { case 16: case 32: case 64: case 128: if (goal == BOUNDARY_SINGLE_CACHELINE) {
val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
} else {
val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
} break;
case 256:
val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
DMA_RWCTRL_WRITE_BNDRY_256_PCIX); break;
default:
val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
DMA_RWCTRL_WRITE_BNDRY_384_PCIX); break;
}
} elseif (tg3_flag(tp, PCI_EXPRESS)) { switch (cacheline_size) { case 16: case 32: case 64: if (goal == BOUNDARY_SINGLE_CACHELINE) {
val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; break;
}
fallthrough; case 128: default:
val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; break;
}
} else { switch (cacheline_size) { case 16: if (goal == BOUNDARY_SINGLE_CACHELINE) {
val |= (DMA_RWCTRL_READ_BNDRY_16 |
DMA_RWCTRL_WRITE_BNDRY_16); break;
}
fallthrough; case 32: if (goal == BOUNDARY_SINGLE_CACHELINE) {
val |= (DMA_RWCTRL_READ_BNDRY_32 |
DMA_RWCTRL_WRITE_BNDRY_32); break;
}
fallthrough; case 64: if (goal == BOUNDARY_SINGLE_CACHELINE) {
val |= (DMA_RWCTRL_READ_BNDRY_64 |
DMA_RWCTRL_WRITE_BNDRY_64); break;
}
fallthrough; case 128: if (goal == BOUNDARY_SINGLE_CACHELINE) {
val |= (DMA_RWCTRL_READ_BNDRY_128 |
DMA_RWCTRL_WRITE_BNDRY_128); break;
}
fallthrough; case 256:
val |= (DMA_RWCTRL_READ_BNDRY_256 |
DMA_RWCTRL_WRITE_BNDRY_256); break; case 512:
val |= (DMA_RWCTRL_READ_BNDRY_512 |
DMA_RWCTRL_WRITE_BNDRY_512); break; case 1024: default:
val |= (DMA_RWCTRL_READ_BNDRY_1024 |
DMA_RWCTRL_WRITE_BNDRY_1024); break;
}
}
out: return val;
}
staticint tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, bool to_device)
{ struct tg3_internal_buffer_desc test_desc;
u32 sram_dma_descs; int i, ret;
/* * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz * the *second* time the tg3 driver was getting loaded after an * initial scan. * * Broadcom tells me: * ...the DMA engine is connected to the GRC block and a DMA * reset may affect the GRC block in some unpredictable way... * The behavior of resets to individual blocks has not been tested. * * Broadcom noted the GRC reset will also reset all sub-components.
*/ if (to_device) {
test_desc.cqid_sqid = (13 << 8) | 2;
for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
u32 val;
val = *(((u32 *)&test_desc) + i);
pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
sram_dma_descs + (i * sizeof(u32)));
pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
}
pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
if (to_device)
tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); else
tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
ret = -ENODEV; for (i = 0; i < 40; i++) {
u32 val;
if (to_device)
val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); else
val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); if ((val & 0xffff) == sram_dma_descs) {
ret = 0; break;
}
if (tg3_flag(tp, PCI_EXPRESS)) { /* DMA read watermark not used on PCIE */
tp->dma_rwctrl |= 0x00180000;
} elseif (!tg3_flag(tp, PCIX_MODE)) { if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
tg3_asic_rev(tp) == ASIC_REV_5750)
tp->dma_rwctrl |= 0x003f0000; else
tp->dma_rwctrl |= 0x003f000f;
} else { if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
tg3_asic_rev(tp) == ASIC_REV_5704) {
u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
u32 read_water = 0x7;
/* If the 5704 is behind the EPB bridge, we can * do the less restrictive ONE_DMA workaround for * better performance.
*/ if (tg3_flag(tp, 40BIT_DMA_BUG) &&
tg3_asic_rev(tp) == ASIC_REV_5704)
tp->dma_rwctrl |= 0x8000; elseif (ccval == 0x6 || ccval == 0x7)
tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
tg3_asic_rev(tp) == ASIC_REV_5701) { /* Remove this if it causes problems for some boards. */
tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
/* On 5700/5701 chips, we need to set this bit. * Otherwise the chip will issue cacheline transactions * to streamable DMA memory with not all the byte * enables turned on. This is an error on several * RISC PCI controllers, in particular sparc64. * * On 5703/5704 chips, this bit has been reassigned * a different meaning. In particular, it is used * on those chips to enable a PCI-X workaround.
*/
tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
}
tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
tg3_asic_rev(tp) != ASIC_REV_5701) goto out;
/* It is best to perform DMA test with maximum write burst size * to expose the 5700/5701 write DMA bug.
*/
saved_dma_rwctrl = tp->dma_rwctrl;
tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
while (1) {
u32 *p = buf, i;
for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
p[i] = i;
/* Send the buffer to the chip. */
ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true); if (ret) {
dev_err(&tp->pdev->dev, "%s: Buffer write failed. err = %d\n",
__func__, ret); break;
}
/* Now read it back. */
ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false); if (ret) {
dev_err(&tp->pdev->dev, "%s: Buffer read failed. " "err = %d\n", __func__, ret); break;
}
/* Verify it. */ for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { if (p[i] == i) continue;
if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { /* Success. */
ret = 0; break;
}
} if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
DMA_RWCTRL_WRITE_BNDRY_16) { /* DMA test passed without adjusting DMA boundary, * now look for chipsets that are known to expose the * DMA bug without failing the test.
*/ if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
} else { /* Safe to use the calculated DMA boundary. */
tp->dma_rwctrl = saved_dma_rwctrl;
}
staticchar *tg3_phy_string(struct tg3 *tp)
{ switch (tp->phy_id & TG3_PHY_ID_MASK) { case TG3_PHY_ID_BCM5400: return"5400"; case TG3_PHY_ID_BCM5401: return"5401"; case TG3_PHY_ID_BCM5411: return"5411"; case TG3_PHY_ID_BCM5701: return"5701"; case TG3_PHY_ID_BCM5703: return"5703"; case TG3_PHY_ID_BCM5704: return"5704"; case TG3_PHY_ID_BCM5705: return"5705"; case TG3_PHY_ID_BCM5750: return"5750"; case TG3_PHY_ID_BCM5752: return"5752"; case TG3_PHY_ID_BCM5714: return"5714"; case TG3_PHY_ID_BCM5780: return"5780"; case TG3_PHY_ID_BCM5755: return"5755"; case TG3_PHY_ID_BCM5787: return"5787"; case TG3_PHY_ID_BCM5784: return"5784"; case TG3_PHY_ID_BCM5756: return"5722/5756"; case TG3_PHY_ID_BCM5906: return"5906"; case TG3_PHY_ID_BCM5761: return"5761"; case TG3_PHY_ID_BCM5718C: return"5718C"; case TG3_PHY_ID_BCM5718S: return"5718S"; case TG3_PHY_ID_BCM57765: return"57765"; case TG3_PHY_ID_BCM5719C: return"5719C"; case TG3_PHY_ID_BCM5720C: return"5720C"; case TG3_PHY_ID_BCM5762: return"5762C"; case TG3_PHY_ID_BCM8002: return"8002/serdes"; case 0: return"serdes"; default: return"unknown";
}
}
if (pdev_is_ssb_gige_core(pdev)) {
tg3_flag_set(tp, IS_SSB_CORE); if (ssb_gige_must_flush_posted_writes(pdev))
tg3_flag_set(tp, FLUSH_POSTED_WRITES); if (ssb_gige_one_dma_at_once(pdev))
tg3_flag_set(tp, ONE_DMA_AT_ONCE); if (ssb_gige_have_roboswitch(pdev)) {
tg3_flag_set(tp, USE_PHYLIB);
tg3_flag_set(tp, ROBOSWITCH);
} if (ssb_gige_is_rgmii(pdev))
tg3_flag_set(tp, RGMII_MODE);
}
/* The word/byte swap controls here control register access byte * swapping. DMA data byte swapping is controlled in the GRC_MODE * setting below.
*/
tp->misc_host_ctrl =
MISC_HOST_CTRL_MASK_PCI_INT |
MISC_HOST_CTRL_WORD_SWAP |
MISC_HOST_CTRL_INDIR_ACCESS |
MISC_HOST_CTRL_PCISTATE_RW;
/* The NONFRM (non-frame) byte/word swap controls take effect * on descriptor entries, anything which isn't packet data. * * The StrongARM chips on the board (one for tx, one for rx) * are running in big-endian mode.
*/
tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
GRC_MODE_WSWAP_NONFRM_DATA); #ifdef __BIG_ENDIAN
tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; #endif
spin_lock_init(&tp->lock);
spin_lock_init(&tp->indirect_lock);
INIT_WORK(&tp->reset_task, tg3_reset_task);
err = tg3_get_invariants(tp, ent); if (err) {
dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n"); goto err_out_apeunmap;
}
/* The EPB bridge inside 5714, 5715, and 5780 and any * device behind the EPB cannot support DMA addresses > 40-bit. * On 64-bit systems with IOMMU, use 40-bit dma_mask. * On 64-bit systems without IOMMU, use 64-bit dma_mask and * do DMA address check in __tg3_start_xmit().
*/ if (tg3_flag(tp, IS_5788))
persist_dma_mask = dma_mask = DMA_BIT_MASK(32); elseif (tg3_flag(tp, 40BIT_DMA_BUG)) {
persist_dma_mask = dma_mask = DMA_BIT_MASK(40); #ifdef CONFIG_HIGHMEM
dma_mask = DMA_BIT_MASK(64); #endif
} else
persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
if (tg3_asic_rev(tp) == ASIC_REV_57766)
persist_dma_mask = DMA_BIT_MASK(31);
/* Configure DMA attributes. */ if (dma_mask > DMA_BIT_MASK(32)) {
err = dma_set_mask(&pdev->dev, dma_mask); if (!err) {
features |= NETIF_F_HIGHDMA;
err = dma_set_coherent_mask(&pdev->dev,
persist_dma_mask); if (err < 0) {
dev_err(&pdev->dev, "Unable to obtain 64 bit " "DMA for consistent allocations\n"); goto err_out_apeunmap;
}
}
} if (err || dma_mask == DMA_BIT_MASK(32)) {
err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); if (err) {
dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); goto err_out_apeunmap;
}
}
tg3_init_bufmgr_config(tp);
/* 5700 B0 chips do not support checksumming correctly due * to hardware bugs.
*/ if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
if (tg3_flag(tp, 5755_PLUS))
features |= NETIF_F_IPV6_CSUM;
}
/* TSO is on by default on chips that support hardware TSO. * Firmware TSO on older chips gives lower performance, so it * is off by default, but can be enabled using ethtool.
*/ if ((tg3_flag(tp, HW_TSO_1) ||
tg3_flag(tp, HW_TSO_2) ||
tg3_flag(tp, HW_TSO_3)) &&
(features & NETIF_F_IP_CSUM))
features |= NETIF_F_TSO; if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) { if (features & NETIF_F_IPV6_CSUM)
features |= NETIF_F_TSO6; if (tg3_flag(tp, HW_TSO_3) ||
tg3_asic_rev(tp) == ASIC_REV_5761 ||
(tg3_asic_rev(tp) == ASIC_REV_5784 &&
tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
tg3_asic_rev(tp) == ASIC_REV_5785 ||
tg3_asic_rev(tp) == ASIC_REV_57780)
features |= NETIF_F_TSO_ECN;
}
dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX |
NETIF_F_HW_VLAN_CTAG_RX;
dev->vlan_features |= features;
/* * Add loopback capability only for a subset of devices that support * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY * loopback for the remaining devices.
*/ if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
!tg3_flag(tp, CPMU_PRESENT)) /* Add the loopback capability */
features |= NETIF_F_LOOPBACK;
if (i)
tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); else
tnapi->coal_now = HOSTCC_MODE_NOW;
if (!tg3_flag(tp, SUPPORT_MSIX)) break;
/* * If we support MSIX, we'll be using RSS. If we're using * RSS, the first vector only handles link interrupts and the * remaining vectors handle rx and tx interrupts. Reuse the * mailbox values for the next iteration. The values we setup * above are still useful for the single vectored mode.
*/ if (!i) continue;
/* * Reset chip in case UNDI or EFI driver did not shutdown * DMA self test will enable WDMAC and we'll see (spurious) * pending DMA on the PCI bus at that point.
*/ if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
tg3_full_lock(tp, 0);
tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
tg3_full_unlock(tp);
}
err = tg3_test_dma(tp); if (err) {
dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); goto err_out_apeunmap;
}
if (system_state == SYSTEM_POWER_OFF)
tg3_power_down(tp); elseif (system_state == SYSTEM_RESTART &&
dmi_first_match(tg3_restart_aer_quirk_table) &&
pdev->current_state != PCI_D3cold &&
pdev->current_state != PCI_UNKNOWN) { /* Disable PCIe AER on the tg3 to avoid a fatal * error during this system restart.
*/
pcie_capability_clear_word(pdev, PCI_EXP_DEVCTL,
PCI_EXP_DEVCTL_CERE |
PCI_EXP_DEVCTL_NFERE |
PCI_EXP_DEVCTL_FERE |
PCI_EXP_DEVCTL_URRE);
}
rtnl_unlock();
pci_disable_device(pdev);
}
/** * tg3_io_error_detected - called when PCI error is detected * @pdev: Pointer to PCI device * @state: The current pci connection state * * This function is called after a PCI bus error affecting * this device has been detected.
*/ static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
pci_channel_state_t state)
{ struct net_device *netdev = pci_get_drvdata(pdev); struct tg3 *tp = netdev_priv(netdev);
pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
netdev_info(netdev, "PCI I/O error detected\n");
/* Want to make sure that the reset task doesn't run */
tg3_reset_task_cancel(tp);
rtnl_lock();
/* Could be second call or maybe we don't have netdev yet */ if (!netdev || tp->pcierr_recovery || !netif_running(netdev)) goto done;
/* We needn't recover from permanent error */ if (state == pci_channel_io_frozen)
tp->pcierr_recovery = true;
tg3_phy_stop(tp);
tg3_netif_stop(tp);
tg3_timer_stop(tp);
netif_device_detach(netdev);
/* Clean up software state, even if MMIO is blocked */
tg3_full_lock(tp, 0);
tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
tg3_full_unlock(tp);
/** * tg3_io_slot_reset - called after the pci bus has been reset. * @pdev: Pointer to PCI device * * Restart the card from scratch, as if from a cold-boot. * At this point, the card has experienced a hard reset, * followed by fixups by BIOS, and has its config space * set up identically to what it was at cold boot.
*/ static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
{ struct net_device *netdev = pci_get_drvdata(pdev); struct tg3 *tp = netdev_priv(netdev);
pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT; int err;
rtnl_lock();
if (pci_enable_device(pdev)) {
dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n"); goto done;
}
/** * tg3_io_resume - called when traffic can start flowing again. * @pdev: Pointer to PCI device * * This callback is called when the error recovery driver tells * us that its OK to resume normal operation.
*/ staticvoid tg3_io_resume(struct pci_dev *pdev)
{ struct net_device *netdev = pci_get_drvdata(pdev); struct tg3 *tp = netdev_priv(netdev); int err;
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