/* MDI setting is only allowed when autoneg enabled because * some hardware doesn't allow MDI setting when speed or * duplex is forced.
*/ if (cmd->base.eth_tp_mdix_ctrl) { if (hw->media_type != e1000_media_type_copper) return -EOPNOTSUPP;
if ((cmd->base.eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&
(cmd->base.autoneg != AUTONEG_ENABLE)) {
e_err(drv, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n"); return -EINVAL;
}
}
while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
msleep(1);
/* If the link is not reported up to netdev, interrupts are disabled, * and so the physical link state may have changed since we last * looked. Set get_link_status to make sure that the true link * state is interrogated, rather than pulling a cached and possibly * stale link state from the driver.
*/ if (!netif_carrier_ok(netdev))
adapter->hw.get_link_status = 1;
if (eeprom->offset & 1) { /* need read/modify/write of first changed EEPROM word * only the second byte of the word is being modified
*/
ret_val = e1000_read_eeprom(hw, first_word, 1,
&eeprom_buff[0]);
ptr++;
} if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) { /* need read/modify/write of last changed EEPROM word * only the first byte of the word is being modified
*/
ret_val = e1000_read_eeprom(hw, last_word, 1,
&eeprom_buff[last_word - first_word]);
}
/* Device's eeprom is always little-endian, word addressable */ for (i = 0; i < last_word - first_word + 1; i++)
le16_to_cpus(&eeprom_buff[i]);
memcpy(ptr, bytes, eeprom->len);
for (i = 0; i < last_word - first_word + 1; i++)
cpu_to_le16s(&eeprom_buff[i]);
/* Update the checksum over the first part of the EEPROM if needed */ if ((ret_val == 0) && (first_word <= EEPROM_CHECKSUM_REG))
e1000_update_eeprom_checksum(hw);
for (i = 0; i < adapter->num_tx_queues; i++)
txdr[i].count = txdr->count; for (i = 0; i < adapter->num_rx_queues; i++)
rxdr[i].count = rxdr->count;
err = 0; if (netif_running(adapter->netdev)) { /* Try to get new resources before deleting old */
err = e1000_setup_all_rx_resources(adapter); if (err) goto err_setup_rx;
err = e1000_setup_all_tx_resources(adapter); if (err) goto err_setup_tx;
/* save the new, restore the old in order to free it, * then restore the new back again
*/
*data = 0; /* Read and add up the contents of the EEPROM */ for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { if ((e1000_read_eeprom(hw, i, 1, &temp)) < 0) {
*data = 1; break;
}
checksum += temp;
}
/* If Checksum is not Correct return error else test passed */ if ((checksum != (u16)EEPROM_SUM) && !(*data))
*data = 2;
/* NOTE: we don't test MSI interrupts here, yet * Hook up test interrupt handler just for this test
*/ if (!request_irq(irq, e1000_test_intr, IRQF_PROBE_SHARED, netdev->name,
netdev))
shared_int = false; elseif (request_irq(irq, e1000_test_intr, IRQF_SHARED,
netdev->name, netdev)) {
*data = 1; return -1;
}
e_info(hw, "testing %s interrupt\n", (shared_int ? "shared" : "unshared"));
/* Disable all the interrupts */
ew32(IMC, 0xFFFFFFFF);
E1000_WRITE_FLUSH();
msleep(10);
/* Test each interrupt */ for (; i < 10; i++) { /* Interrupt to test */
mask = 1 << i;
if (!shared_int) { /* Disable the interrupt to be reported in * the cause register and then force the same * interrupt and see if one gets posted. If * an interrupt was posted to the bus, the * test failed.
*/
adapter->test_icr = 0;
ew32(IMC, mask);
ew32(ICS, mask);
E1000_WRITE_FLUSH();
msleep(10);
/* Enable the interrupt to be reported in * the cause register and then force the same * interrupt and see if one gets posted. If * an interrupt was not posted to the bus, the * test failed.
*/
adapter->test_icr = 0;
ew32(IMS, mask);
ew32(ICS, mask);
E1000_WRITE_FLUSH();
msleep(10);
if (!(adapter->test_icr & mask)) {
*data = 4; break;
}
if (!shared_int) { /* Disable the other interrupts to be reported in * the cause register and then force the other * interrupts and see if any get posted. If * an interrupt was posted to the bus, the * test failed.
*/
adapter->test_icr = 0;
ew32(IMC, ~mask & 0x00007FFF);
ew32(ICS, ~mask & 0x00007FFF);
E1000_WRITE_FLUSH();
msleep(10);
if (adapter->test_icr) {
*data = 5; break;
}
}
}
/* Disable all the interrupts */
ew32(IMC, 0xFFFFFFFF);
E1000_WRITE_FLUSH();
msleep(10);
/* Unhook test interrupt handler */
free_irq(irq, netdev);
if (txdr->desc && txdr->buffer_info) { for (i = 0; i < txdr->count; i++) { if (txdr->buffer_info[i].dma)
dma_unmap_single(&pdev->dev,
txdr->buffer_info[i].dma,
txdr->buffer_info[i].length,
DMA_TO_DEVICE);
dev_kfree_skb(txdr->buffer_info[i].skb);
}
}
if (rxdr->desc && rxdr->buffer_info) { for (i = 0; i < rxdr->count; i++) { if (rxdr->buffer_info[i].dma)
dma_unmap_single(&pdev->dev,
rxdr->buffer_info[i].dma,
E1000_RXBUFFER_2048,
DMA_FROM_DEVICE);
kfree(rxdr->buffer_info[i].rxbuf.data);
}
}
/* Because we reset the PHY above, we need to re-force TX_CLK in the * Extended PHY Specific Control Register to 25MHz clock. This * value defaults back to a 2.5MHz clock when the PHY is reset.
*/
e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_reg);
phy_reg |= M88E1000_EPSCR_TX_CLK_25;
e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_reg);
/* In addition, because of the s/w reset above, we need to enable * CRS on TX. This must be set for both full and half duplex * operation.
*/
e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_reg);
phy_reg |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_reg);
}
/* Setup the Device Control Register for PHY loopback test. */
ctrl_reg = er32(CTRL);
ctrl_reg |= (E1000_CTRL_ILOS | /* Invert Loss-Of-Signal */
E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */
E1000_CTRL_FD); /* Force Duplex to FULL */
ew32(CTRL, ctrl_reg);
/* Read the PHY Specific Control Register (0x10) */
e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_reg);
/* Clear Auto-Crossover bits in PHY Specific Control Register * (bits 6:5).
*/
phy_reg &= ~M88E1000_PSCR_AUTO_X_MODE;
e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_reg);
/* Perform software reset on the PHY */
e1000_phy_reset(hw);
/* Have to setup TX_CLK and TX_CRS after software reset */
e1000_phy_reset_clk_and_crs(adapter);
e1000_write_phy_reg(hw, PHY_CTRL, 0x8100);
/* Wait for reset to complete. */
udelay(500);
/* Have to setup TX_CLK and TX_CRS after software reset */
e1000_phy_reset_clk_and_crs(adapter);
/* Write out to PHY registers 29 and 30 to disable the Receiver. */
e1000_phy_disable_receiver(adapter);
/* Set the loopback bit in the PHY control register. */
e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
phy_reg |= MII_CR_LOOPBACK;
e1000_write_phy_reg(hw, PHY_CTRL, phy_reg);
/* Setup TX_CLK and TX_CRS one more time. */
e1000_phy_reset_clk_and_crs(adapter);
if (hw->phy_type == e1000_phy_m88) { /* Auto-MDI/MDIX Off */
e1000_write_phy_reg(hw,
M88E1000_PHY_SPEC_CTRL, 0x0808); /* reset to update Auto-MDI/MDIX */
e1000_write_phy_reg(hw, PHY_CTRL, 0x9140); /* autoneg off */
e1000_write_phy_reg(hw, PHY_CTRL, 0x8140);
}
ctrl_reg = er32(CTRL);
/* force 1000, set loopback */
e1000_write_phy_reg(hw, PHY_CTRL, 0x4140);
/* Now set up the MAC to the same speed/duplex as the PHY. */
ctrl_reg = er32(CTRL);
ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
E1000_CTRL_FD); /* Force Duplex to FULL */
if (hw->media_type == e1000_media_type_copper &&
hw->phy_type == e1000_phy_m88)
ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ else { /* Set the ILOS bit on the fiber Nic is half * duplex link is detected.
*/
stat_reg = er32(STATUS); if ((stat_reg & E1000_STATUS_FD) == 0)
ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
}
ew32(CTRL, ctrl_reg);
/* Disable the receiver on the PHY so when a cable is plugged in, the * PHY does not begin to autoneg when a cable is reconnected to the NIC.
*/ if (hw->phy_type == e1000_phy_m88)
e1000_phy_disable_receiver(adapter);
switch (hw->mac_type) { case e1000_82543: if (hw->media_type == e1000_media_type_copper) { /* Attempt to setup Loopback mode on Non-integrated PHY. * Some PHY registers get corrupted at random, so * attempt this 10 times.
*/ while (e1000_nonintegrated_phy_loopback(adapter) &&
count++ < 10); if (count < 11) return 0;
} break;
case e1000_82544: case e1000_82540: case e1000_82545: case e1000_82545_rev_3: case e1000_82546: case e1000_82546_rev_3: case e1000_82541: case e1000_82541_rev_2: case e1000_82547: case e1000_82547_rev_2: return e1000_integrated_phy_loopback(adapter); default: /* Default PHY loopback work is to read the MII * control register and assert bit 14 (loopback mode).
*/
e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
phy_reg |= MII_CR_LOOPBACK;
e1000_write_phy_reg(hw, PHY_CTRL, phy_reg); return 0;
}
/* Calculate the loop count based on the largest descriptor ring * The idea is to wrap the largest ring a number of times using 64 * send/receive pairs during each loop
*/
k = l = 0; for (j = 0; j <= lc; j++) { /* loop count loop */ for (i = 0; i < 64; i++) { /* send the packets */
e1000_create_lbtest_frame(txdr->buffer_info[i].skb,
1024);
dma_sync_single_for_device(&pdev->dev,
txdr->buffer_info[k].dma,
txdr->buffer_info[k].length,
DMA_TO_DEVICE); if (unlikely(++k == txdr->count))
k = 0;
}
ew32(TDT, k);
E1000_WRITE_FLUSH();
msleep(200);
time = jiffies; /* set the start time for the receive */
good_cnt = 0; do { /* receive the sent packets */
dma_sync_single_for_cpu(&pdev->dev,
rxdr->buffer_info[l].dma,
E1000_RXBUFFER_2048,
DMA_FROM_DEVICE);
ret_val = e1000_check_lbtest_frame(
rxdr->buffer_info[l].rxbuf.data +
NET_SKB_PAD + NET_IP_ALIGN,
1024); if (!ret_val)
good_cnt++; if (unlikely(++l == rxdr->count))
l = 0; /* time + 20 msecs (200 msecs on 2.4) is more than * enough time to complete the receives, if it's * exceeded, break and error off
*/
} while (good_cnt < 64 && time_after(time + 20, jiffies));
if (good_cnt != 64) {
ret_val = 13; /* ret_val is the same as mis-compare */ break;
} if (time_after_eq(jiffies, time + 2)) {
ret_val = 14; /* error code for time out error */ break;
}
} /* end loop count loop */ return ret_val;
}
staticint e1000_link_test(struct e1000_adapter *adapter, u64 *data)
{ struct e1000_hw *hw = &adapter->hw;
*data = 0; if (hw->media_type == e1000_media_type_internal_serdes) { int i = 0;
hw->serdes_has_link = false;
/* On some blade server designs, link establishment * could take as long as 2-3 minutes
*/ do {
e1000_check_for_link(hw); if (hw->serdes_has_link) return *data;
msleep(20);
} while (i++ < 3750);
*data = 1;
} else {
e1000_check_for_link(hw); if (hw->autoneg) /* if auto_neg is set wait for it */
msleep(4000);
/* Link test performed before hardware reset so autoneg doesn't * interfere with test result
*/ if (e1000_link_test(adapter, &data[4]))
eth_test->flags |= ETH_TEST_FL_FAILED;
if (if_running) /* indicate we're in test mode */
e1000_close(netdev); else
e1000_reset(adapter);
if (e1000_reg_test(adapter, &data[0]))
eth_test->flags |= ETH_TEST_FL_FAILED;
e1000_reset(adapter); if (e1000_eeprom_test(adapter, &data[1]))
eth_test->flags |= ETH_TEST_FL_FAILED;
e1000_reset(adapter); if (e1000_intr_test(adapter, &data[2]))
eth_test->flags |= ETH_TEST_FL_FAILED;
e1000_reset(adapter); /* make sure the phy is powered up */
e1000_power_up_phy(adapter); if (e1000_loopback_test(adapter, &data[3]))
eth_test->flags |= ETH_TEST_FL_FAILED;
switch (hw->device_id) { case E1000_DEV_ID_82542: case E1000_DEV_ID_82543GC_FIBER: case E1000_DEV_ID_82543GC_COPPER: case E1000_DEV_ID_82544EI_FIBER: case E1000_DEV_ID_82546EB_QUAD_COPPER: case E1000_DEV_ID_82545EM_FIBER: case E1000_DEV_ID_82545EM_COPPER: case E1000_DEV_ID_82546GB_QUAD_COPPER: case E1000_DEV_ID_82546GB_PCIE: /* these don't support WoL at all */
wol->supported = 0; break; case E1000_DEV_ID_82546EB_FIBER: case E1000_DEV_ID_82546GB_FIBER: /* Wake events not supported on port B */ if (er32(STATUS) & E1000_STATUS_FUNC_1) {
wol->supported = 0; break;
} /* return success for non excluded adapter ports */
retval = 0; break; case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: /* quad port adapters only support WoL on port A */ if (!adapter->quad_port_a) {
wol->supported = 0; break;
} /* return success for non excluded adapter ports */
retval = 0; break; default: /* dual port cards only support WoL on port A from now on * unless it was enabled in the eeprom for port B * so exclude FUNC_1 ports from having WoL enabled
*/ if (er32(STATUS) & E1000_STATUS_FUNC_1 &&
!adapter->eeprom_wol) {
wol->supported = 0; break;
}
/* this function will set ->supported = 0 and return 1 if wol is not * supported by this hardware
*/ if (e1000_wol_exclusion(adapter, wol) ||
!device_can_wakeup(&adapter->pdev->dev)) return;
/* apply any specific unsupported masks here */ switch (hw->device_id) { case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: /* KSP3 does not support UCAST wake-ups */
wol->supported &= ~WAKE_UCAST;
if (adapter->wol & E1000_WUFC_EX)
e_err(drv, "Interface does not support directed " "(unicast) frame wake-up packets\n"); break; default: break;
}
if (adapter->wol & E1000_WUFC_EX)
wol->wolopts |= WAKE_UCAST; if (adapter->wol & E1000_WUFC_MC)
wol->wolopts |= WAKE_MCAST; if (adapter->wol & E1000_WUFC_BC)
wol->wolopts |= WAKE_BCAST; if (adapter->wol & E1000_WUFC_MAG)
wol->wolopts |= WAKE_MAGIC;
}
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