/** * ice_dump_phy_type - helper function to dump phy_type * @hw: pointer to the HW structure * @low: 64 bit value for phy_type_low * @high: 64 bit value for phy_type_high * @prefix: prefix string to differentiate multiple dumps
*/ staticvoid
ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, constchar *prefix)
{
ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low);
for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { if (low & BIT_ULL(i))
ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n",
prefix, i, ice_link_mode_str_low[i]);
}
for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { if (high & BIT_ULL(i))
ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n",
prefix, i, ice_link_mode_str_high[i]);
}
}
/** * ice_set_mac_type - Sets MAC type * @hw: pointer to the HW structure * * This function sets the MAC type of the adapter based on the * vendor ID and device ID stored in the HW structure.
*/ staticint ice_set_mac_type(struct ice_hw *hw)
{ if (hw->vendor_id != PCI_VENDOR_ID_INTEL) return -ENODEV;
switch (hw->device_id) { case ICE_DEV_ID_E810C_BACKPLANE: case ICE_DEV_ID_E810C_QSFP: case ICE_DEV_ID_E810C_SFP: case ICE_DEV_ID_E810_XXV_BACKPLANE: case ICE_DEV_ID_E810_XXV_QSFP: case ICE_DEV_ID_E810_XXV_SFP:
hw->mac_type = ICE_MAC_E810; break; case ICE_DEV_ID_E823C_10G_BASE_T: case ICE_DEV_ID_E823C_BACKPLANE: case ICE_DEV_ID_E823C_QSFP: case ICE_DEV_ID_E823C_SFP: case ICE_DEV_ID_E823C_SGMII: case ICE_DEV_ID_E822C_10G_BASE_T: case ICE_DEV_ID_E822C_BACKPLANE: case ICE_DEV_ID_E822C_QSFP: case ICE_DEV_ID_E822C_SFP: case ICE_DEV_ID_E822C_SGMII: case ICE_DEV_ID_E822L_10G_BASE_T: case ICE_DEV_ID_E822L_BACKPLANE: case ICE_DEV_ID_E822L_SFP: case ICE_DEV_ID_E822L_SGMII: case ICE_DEV_ID_E823L_10G_BASE_T: case ICE_DEV_ID_E823L_1GBE: case ICE_DEV_ID_E823L_BACKPLANE: case ICE_DEV_ID_E823L_QSFP: case ICE_DEV_ID_E823L_SFP:
hw->mac_type = ICE_MAC_GENERIC; break; case ICE_DEV_ID_E825C_BACKPLANE: case ICE_DEV_ID_E825C_QSFP: case ICE_DEV_ID_E825C_SFP: case ICE_DEV_ID_E825C_SGMII:
hw->mac_type = ICE_MAC_GENERIC_3K_E825; break; case ICE_DEV_ID_E830CC_BACKPLANE: case ICE_DEV_ID_E830CC_QSFP56: case ICE_DEV_ID_E830CC_SFP: case ICE_DEV_ID_E830CC_SFP_DD: case ICE_DEV_ID_E830C_BACKPLANE: case ICE_DEV_ID_E830_XXV_BACKPLANE: case ICE_DEV_ID_E830C_QSFP: case ICE_DEV_ID_E830_XXV_QSFP: case ICE_DEV_ID_E830C_SFP: case ICE_DEV_ID_E830_XXV_SFP: case ICE_DEV_ID_E835CC_BACKPLANE: case ICE_DEV_ID_E835CC_QSFP56: case ICE_DEV_ID_E835CC_SFP: case ICE_DEV_ID_E835C_BACKPLANE: case ICE_DEV_ID_E835C_QSFP: case ICE_DEV_ID_E835C_SFP: case ICE_DEV_ID_E835_L_BACKPLANE: case ICE_DEV_ID_E835_L_QSFP: case ICE_DEV_ID_E835_L_SFP:
hw->mac_type = ICE_MAC_E830; break; default:
hw->mac_type = ICE_MAC_UNKNOWN; break;
}
/** * ice_aq_manage_mac_read - manage MAC address read command * @hw: pointer to the HW struct * @buf: a virtual buffer to hold the manage MAC read response * @buf_size: Size of the virtual buffer * @cd: pointer to command details structure or NULL * * This function is used to return per PF station MAC address (0x0107). * NOTE: Upon successful completion of this command, MAC address information * is returned in user specified buffer. Please interpret user specified * buffer as "manage_mac_read" response. * Response such as various MAC addresses are stored in HW struct (port.mac) * ice_discover_dev_caps is expected to be called before this function is * called.
*/ staticint
ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, struct ice_sq_cd *cd)
{ struct ice_aqc_manage_mac_read_resp *resp; struct ice_aqc_manage_mac_read *cmd; struct libie_aq_desc desc; int status;
u16 flags;
u8 i;
if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); return -EIO;
}
/* A single port can report up to two (LAN and WoL) addresses */ for (i = 0; i < cmd->num_addr; i++) if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
ether_addr_copy(hw->port_info->mac.lan_addr,
resp[i].mac_addr);
ether_addr_copy(hw->port_info->mac.perm_addr,
resp[i].mac_addr); break;
}
return 0;
}
/** * ice_aq_get_phy_caps - returns PHY capabilities * @pi: port information structure * @qual_mods: report qualified modules * @report_mode: report mode capabilities * @pcaps: structure for PHY capabilities to be filled * @cd: pointer to command details structure or NULL * * Returns the various PHY capabilities supported on the Port (0x0600)
*/ int
ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, struct ice_aqc_get_phy_caps_data *pcaps, struct ice_sq_cd *cd)
{ struct ice_aqc_get_phy_caps *cmd;
u16 pcaps_size = sizeof(*pcaps); struct libie_aq_desc desc; constchar *prefix; struct ice_hw *hw; int status;
/** * ice_aq_get_link_topo_handle - get link topology node return status * @pi: port information structure * @node_type: requested node type * @cd: pointer to command details structure or NULL * * Get link topology node return status for specified node type (0x06E0) * * Node type cage can be used to determine if cage is present. If AQC * returns error (ENOENT), then no cage present. If no cage present, then * connection type is backplane or BASE-T.
*/ staticint
ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, struct ice_sq_cd *cd)
{ struct ice_aqc_get_link_topo *cmd; struct libie_aq_desc desc;
if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) return -EINTR;
if (node_handle)
*node_handle = le16_to_cpu(resp->addr.handle); if (node_part_number)
*node_part_number = resp->node_part_num;
return 0;
}
/** * ice_find_netlist_node * @hw: pointer to the hw struct * @node_type: type of netlist node to look for * @ctx: context of the search * @node_part_number: node part number to look for * @node_handle: output parameter if node found - optional * * Scan the netlist for a node handle of the given node type and part number. * * If node_handle is non-NULL it will be modified on function exit. It is only * valid if the function returns zero, and should be ignored on any non-zero * return value. * * Return: * * 0 if the node is found, * * -ENOENT if no handle was found, * * negative error code on failure to access the AQ.
*/ staticint ice_find_netlist_node(struct ice_hw *hw, u8 node_type, u8 ctx,
u8 node_part_number, u16 *node_handle)
{
u8 idx;
for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) { struct ice_aqc_get_link_topo cmd = {};
u8 rec_node_part_number; int status;
status = ice_aq_get_netlist_node(hw, &cmd,
&rec_node_part_number,
node_handle); if (status) return status;
if (rec_node_part_number == node_part_number) return 0;
}
return -ENOENT;
}
/** * ice_is_media_cage_present * @pi: port information structure * * Returns true if media cage is present, else false. If no cage, then * media type is backplane or BASE-T.
*/ staticbool ice_is_media_cage_present(struct ice_port_info *pi)
{ /* Node type cage can be used to determine if cage is present. If AQC * returns error (ENOENT), then no cage present. If no cage present then * connection type is backplane or BASE-T.
*/ return !ice_aq_get_link_topo_handle(pi,
ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
NULL);
}
/** * ice_get_media_type - Gets media type * @pi: port information structure
*/ staticenum ice_media_type ice_get_media_type(struct ice_port_info *pi)
{ struct ice_link_status *hw_link_info;
if (!pi) return ICE_MEDIA_UNKNOWN;
hw_link_info = &pi->phy.link_info; if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) /* If more than one media type is selected, report unknown */ return ICE_MEDIA_UNKNOWN;
if (hw_link_info->phy_type_low) { /* 1G SGMII is a special case where some DA cable PHYs * may show this as an option when it really shouldn't * be since SGMII is meant to be between a MAC and a PHY * in a backplane. Try to detect this case and handle it
*/ if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII &&
(hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE ||
hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) return ICE_MEDIA_DA;
switch (hw_link_info->phy_type_low) { case ICE_PHY_TYPE_LOW_1000BASE_SX: case ICE_PHY_TYPE_LOW_1000BASE_LX: case ICE_PHY_TYPE_LOW_10GBASE_SR: case ICE_PHY_TYPE_LOW_10GBASE_LR: case ICE_PHY_TYPE_LOW_10G_SFI_C2C: case ICE_PHY_TYPE_LOW_25GBASE_SR: case ICE_PHY_TYPE_LOW_25GBASE_LR: case ICE_PHY_TYPE_LOW_40GBASE_SR4: case ICE_PHY_TYPE_LOW_40GBASE_LR4: case ICE_PHY_TYPE_LOW_50GBASE_SR2: case ICE_PHY_TYPE_LOW_50GBASE_LR2: case ICE_PHY_TYPE_LOW_50GBASE_SR: case ICE_PHY_TYPE_LOW_50GBASE_FR: case ICE_PHY_TYPE_LOW_50GBASE_LR: case ICE_PHY_TYPE_LOW_100GBASE_SR4: case ICE_PHY_TYPE_LOW_100GBASE_LR4: case ICE_PHY_TYPE_LOW_100GBASE_SR2: case ICE_PHY_TYPE_LOW_100GBASE_DR: case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: return ICE_MEDIA_FIBER; case ICE_PHY_TYPE_LOW_100BASE_TX: case ICE_PHY_TYPE_LOW_1000BASE_T: case ICE_PHY_TYPE_LOW_2500BASE_T: case ICE_PHY_TYPE_LOW_5GBASE_T: case ICE_PHY_TYPE_LOW_10GBASE_T: case ICE_PHY_TYPE_LOW_25GBASE_T: return ICE_MEDIA_BASET; case ICE_PHY_TYPE_LOW_10G_SFI_DA: case ICE_PHY_TYPE_LOW_25GBASE_CR: case ICE_PHY_TYPE_LOW_25GBASE_CR_S: case ICE_PHY_TYPE_LOW_25GBASE_CR1: case ICE_PHY_TYPE_LOW_40GBASE_CR4: case ICE_PHY_TYPE_LOW_50GBASE_CR2: case ICE_PHY_TYPE_LOW_50GBASE_CP: case ICE_PHY_TYPE_LOW_100GBASE_CR4: case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: case ICE_PHY_TYPE_LOW_100GBASE_CP2: return ICE_MEDIA_DA; case ICE_PHY_TYPE_LOW_25G_AUI_C2C: case ICE_PHY_TYPE_LOW_40G_XLAUI: case ICE_PHY_TYPE_LOW_50G_LAUI2: case ICE_PHY_TYPE_LOW_50G_AUI2: case ICE_PHY_TYPE_LOW_50G_AUI1: case ICE_PHY_TYPE_LOW_100G_AUI4: case ICE_PHY_TYPE_LOW_100G_CAUI4: if (ice_is_media_cage_present(pi)) return ICE_MEDIA_DA;
fallthrough; case ICE_PHY_TYPE_LOW_1000BASE_KX: case ICE_PHY_TYPE_LOW_2500BASE_KX: case ICE_PHY_TYPE_LOW_2500BASE_X: case ICE_PHY_TYPE_LOW_5GBASE_KR: case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: case ICE_PHY_TYPE_LOW_25GBASE_KR: case ICE_PHY_TYPE_LOW_25GBASE_KR1: case ICE_PHY_TYPE_LOW_25GBASE_KR_S: case ICE_PHY_TYPE_LOW_40GBASE_KR4: case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: case ICE_PHY_TYPE_LOW_50GBASE_KR2: case ICE_PHY_TYPE_LOW_100GBASE_KR4: case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: return ICE_MEDIA_BACKPLANE;
}
} else { switch (hw_link_info->phy_type_high) { case ICE_PHY_TYPE_HIGH_100G_AUI2: case ICE_PHY_TYPE_HIGH_100G_CAUI2: if (ice_is_media_cage_present(pi)) return ICE_MEDIA_DA;
fallthrough; case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: return ICE_MEDIA_BACKPLANE; case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: return ICE_MEDIA_FIBER;
}
} return ICE_MEDIA_UNKNOWN;
}
/** * ice_get_link_status_datalen * @hw: pointer to the HW struct * * Returns datalength for the Get Link Status AQ command, which is bigger for * newer adapter families handled by ice driver.
*/ static u16 ice_get_link_status_datalen(struct ice_hw *hw)
{ switch (hw->mac_type) { case ICE_MAC_E830: return ICE_AQC_LS_DATA_SIZE_V2; case ICE_MAC_E810: default: return ICE_AQC_LS_DATA_SIZE_V1;
}
}
/** * ice_aq_get_link_info * @pi: port information structure * @ena_lse: enable/disable LinkStatusEvent reporting * @link: pointer to link status structure - optional * @cd: pointer to command details structure or NULL * * Get Link Status (0x607). Returns the link status of the adapter.
*/ int
ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, struct ice_link_status *link, struct ice_sq_cd *cd)
{ struct ice_aqc_get_link_status_data link_data = { 0 }; struct ice_aqc_get_link_status *resp; struct ice_link_status *li_old, *li; enum ice_media_type *hw_media_type; struct ice_fc_info *hw_fc_info; struct libie_aq_desc desc; bool tx_pause, rx_pause; struct ice_hw *hw;
u16 cmd_flags; int status;
if (!pi) return -EINVAL;
hw = pi->hw;
li_old = &pi->phy.link_info_old;
hw_media_type = &pi->phy.media_type;
li = &pi->phy.link_info;
hw_fc_info = &pi->fc;
/* save link status information */ if (link)
*link = *li;
/* flag cleared so calling functions don't call AQ again */
pi->phy.get_link_info = false;
return 0;
}
/** * ice_fill_tx_timer_and_fc_thresh * @hw: pointer to the HW struct * @cmd: pointer to MAC cfg structure * * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command * descriptor
*/ staticvoid
ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, struct ice_aqc_set_mac_cfg *cmd)
{
u32 val, fc_thres_m;
/* We read back the transmit timer and FC threshold value of * LFC. Thus, we will use index = * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. * * Also, because we are operating on transmit timer and FC * threshold of LFC, we don't turn on any bit in tx_tmr_priority
*/ #define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX #define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR
if (hw->mac_type == ICE_MAC_E830) { /* Retrieve the transmit timer */
val = rd32(hw, E830_PRTMAC_CL01_PS_QNT);
cmd->tx_tmr_value =
le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M);
/* Retrieve the fc threshold */
val = rd32(hw, E830_PRTMAC_CL01_QNT_THR);
fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M;
} else { /* Retrieve the transmit timer */
val = rd32(hw,
E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC));
cmd->tx_tmr_value =
le16_encode_bits(val,
E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M);
/* Retrieve the fc threshold */
val = rd32(hw,
E800_REFRESH_TMR(E800_IDX_OF_LFC));
fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M;
}
cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m);
}
/** * ice_aq_set_mac_cfg * @hw: pointer to the HW struct * @max_frame_size: Maximum Frame Size to be supported * @cd: pointer to command details structure or NULL * * Set MAC configuration (0x0603)
*/ int
ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
{ struct ice_aqc_set_mac_cfg *cmd; struct libie_aq_desc desc;
/** * ice_get_itr_intrl_gran * @hw: pointer to the HW struct * * Determines the ITR/INTRL granularities based on the maximum aggregate * bandwidth according to the device's configuration during power-on.
*/ staticvoid ice_get_itr_intrl_gran(struct ice_hw *hw)
{
u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M,
rd32(hw, GL_PWR_MODE_CTL));
switch (max_agg_bw) { case ICE_MAX_AGG_BW_200G: case ICE_MAX_AGG_BW_100G: case ICE_MAX_AGG_BW_50G:
hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; break; case ICE_MAX_AGG_BW_25G:
hw->itr_gran = ICE_ITR_GRAN_MAX_25;
hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; break;
}
}
/** * ice_wait_for_fw - wait for full FW readiness * @hw: pointer to the hardware structure * @timeout: milliseconds that can elapse before timing out * * Return: 0 on success, -ETIMEDOUT on timeout.
*/ staticint ice_wait_for_fw(struct ice_hw *hw, u32 timeout)
{ int fw_loading;
u32 elapsed = 0;
/* Query the allocated resources for Tx scheduler */
status = ice_sched_query_res_alloc(hw); if (status) {
ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); goto err_unroll_alloc;
}
ice_sched_get_psm_clk_freq(hw);
/* Initialize port_info struct with scheduler data */
status = ice_sched_init_port(hw->port_info); if (status) goto err_unroll_sched;
pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); if (!pcaps) {
status = -ENOMEM; goto err_unroll_sched;
}
/* Initialize port_info struct with PHY capabilities */
status = ice_aq_get_phy_caps(hw->port_info, false,
ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps,
NULL); if (status)
dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n",
status);
/* Initialize port_info struct with link information */
status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); if (status) goto err_unroll_sched;
/* need a valid SW entry point to build a Tx tree */ if (!hw->sw_entry_point_layer) {
ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
status = -EIO; goto err_unroll_sched;
}
INIT_LIST_HEAD(&hw->agg_list); /* Initialize max burst size */ if (!hw->max_burst_size)
ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
status = ice_init_fltr_mgmt_struct(hw); if (status) goto err_unroll_sched;
/* Get MAC information */ /* A single port can report up to two (LAN and WoL) addresses */
mac_buf = kcalloc(2, sizeof(struct ice_aqc_manage_mac_read_resp),
GFP_KERNEL); if (!mac_buf) {
status = -ENOMEM; goto err_unroll_fltr_mgmt_struct;
}
if (status) goto err_unroll_fltr_mgmt_struct; /* enable jumbo frame support at MAC level */
status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); if (status) goto err_unroll_fltr_mgmt_struct; /* Obtain counter base index which would be used by flow director */
status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); if (status) goto err_unroll_fltr_mgmt_struct;
status = ice_init_hw_tbls(hw); if (status) goto err_unroll_fltr_mgmt_struct;
mutex_init(&hw->tnl_lock);
ice_init_chk_recipe_reuse_support(hw);
/* Some cards require longer initialization times * due to necessity of loading FW from an external source. * This can take even half a minute.
*/ if (ice_is_pf_c827(hw)) {
status = ice_wait_for_fw(hw, 30000); if (status) {
dev_err(ice_hw_to_dev(hw), "ice_wait_for_fw timed out"); goto err_unroll_fltr_mgmt_struct;
}
}
/** * ice_deinit_hw - unroll initialization operations done by ice_init_hw * @hw: pointer to the hardware structure * * This should be called only during nominal operation, not as a result of * ice_init_hw() failing since ice_init_hw() will take care of unrolling * applicable initializations if it fails for any reason.
*/ void ice_deinit_hw(struct ice_hw *hw)
{
ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
ice_cleanup_fltr_mgmt_struct(hw);
/* Clear VSI contexts if not already cleared */
ice_clear_all_vsi_ctx(hw);
}
/** * ice_check_reset - Check to see if a global reset is complete * @hw: pointer to the hardware structure
*/ int ice_check_reset(struct ice_hw *hw)
{
u32 cnt, reg = 0, grst_timeout, uld_mask;
/* Poll for Device Active state in case a recent CORER, GLOBR, * or EMPR has occurred. The grst delay value is in 100ms units. * Add 1sec for outstanding AQ commands that can take a long time.
*/
grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M,
rd32(hw, GLGEN_RSTCTL)) + 10;
for (cnt = 0; cnt < grst_timeout; cnt++) {
mdelay(100);
reg = rd32(hw, GLGEN_RSTAT); if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) break;
}
if (cnt == grst_timeout) {
ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); return -EIO;
}
/* Device is Active; check Global Reset processes are done */ for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
reg = rd32(hw, GLNVM_ULD) & uld_mask; if (reg == uld_mask) {
ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); break;
}
mdelay(10);
}
if (cnt == ICE_PF_RESET_WAIT_COUNT) {
ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
reg); return -EIO;
}
return 0;
}
/** * ice_pf_reset - Reset the PF * @hw: pointer to the hardware structure * * If a global reset has been triggered, this function checks * for its completion and then issues the PF reset
*/ staticint ice_pf_reset(struct ice_hw *hw)
{
u32 cnt, reg;
/* If at function entry a global reset was already in progress, i.e. * state is not 'device active' or any of the reset done bits are not * set in GLNVM_ULD, there is no need for a PF Reset; poll until the * global reset is done.
*/ if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
(rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { /* poll on global reset currently in progress until done */ if (ice_check_reset(hw)) return -EIO;
return 0;
}
/* Reset the PF */
reg = rd32(hw, PFGEN_CTRL);
wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
/* Wait for the PFR to complete. The wait time is the global config lock * timeout plus the PFR timeout which will account for a possible reset * that is occurring during a download package operation.
*/ for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
ICE_PF_RESET_WAIT_COUNT; cnt++) {
reg = rd32(hw, PFGEN_CTRL); if (!(reg & PFGEN_CTRL_PFSWR_M)) break;
mdelay(1);
}
if (cnt == ICE_PF_RESET_WAIT_COUNT) {
ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); return -EIO;
}
return 0;
}
/** * ice_reset - Perform different types of reset * @hw: pointer to the hardware structure * @req: reset request * * This function triggers a reset as specified by the req parameter. * * Note: * If anything other than a PF reset is triggered, PXE mode is restored. * This has to be cleared using ice_clear_pxe_mode again, once the AQ * interface has been restored in the rebuild flow.
*/ int ice_reset(struct ice_hw *hw, enum ice_reset_req req)
{
u32 val = 0;
switch (req) { case ICE_RESET_PFR: return ice_pf_reset(hw); case ICE_RESET_CORER:
ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
val = GLGEN_RTRIG_CORER_M; break; case ICE_RESET_GLOBR:
ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
val = GLGEN_RTRIG_GLOBR_M; break; default: return -EINVAL;
}
val |= rd32(hw, GLGEN_RTRIG);
wr32(hw, GLGEN_RTRIG, val);
ice_flush(hw);
/* wait for the FW to be ready */ return ice_check_reset(hw);
}
/** * ice_copy_rxq_ctx_to_hw - Copy packed Rx queue context to HW registers * @hw: pointer to the hardware structure * @rxq_ctx: pointer to the packed Rx queue context * @rxq_index: the index of the Rx queue
*/ staticvoid ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, const ice_rxq_ctx_buf_t *rxq_ctx,
u32 rxq_index)
{ /* Copy each dword separately to HW */ for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
u32 ctx = ((const u32 *)rxq_ctx)[i];
wr32(hw, QRX_CONTEXT(i, rxq_index), ctx);
ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, ctx);
}
}
/** * ice_copy_rxq_ctx_from_hw - Copy packed Rx Queue context from HW registers * @hw: pointer to the hardware structure * @rxq_ctx: pointer to the packed Rx queue context * @rxq_index: the index of the Rx queue
*/ staticvoid ice_copy_rxq_ctx_from_hw(struct ice_hw *hw,
ice_rxq_ctx_buf_t *rxq_ctx,
u32 rxq_index)
{
u32 *ctx = (u32 *)rxq_ctx;
/* Copy each dword separately from HW */ for (int i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++, ctx++) {
*ctx = rd32(hw, QRX_CONTEXT(i, rxq_index));
ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx);
}
}
/** * ice_pack_rxq_ctx - Pack Rx queue context into a HW buffer * @ctx: the Rx queue context to pack * @buf: the HW buffer to pack into * * Pack the Rx queue context from the CPU-friendly unpacked buffer into its * bit-packed HW layout.
*/ staticvoid ice_pack_rxq_ctx(conststruct ice_rlan_ctx *ctx,
ice_rxq_ctx_buf_t *buf)
{
pack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields,
QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST);
}
/** * ice_unpack_rxq_ctx - Unpack Rx queue context from a HW buffer * @buf: the HW buffer to unpack from * @ctx: the Rx queue context to unpack * * Unpack the Rx queue context from the HW buffer into the CPU-friendly * structure.
*/ staticvoid ice_unpack_rxq_ctx(const ice_rxq_ctx_buf_t *buf, struct ice_rlan_ctx *ctx)
{
unpack_fields(buf, sizeof(*buf), ctx, ice_rlan_ctx_fields,
QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST);
}
/** * ice_write_rxq_ctx - Write Rx Queue context to hardware * @hw: pointer to the hardware structure * @rlan_ctx: pointer to the unpacked Rx queue context * @rxq_index: the index of the Rx queue * * Pack the sparse Rx Queue context into dense hardware format and write it * into the HW register space. * * Return: 0 on success, or -EINVAL if the Rx queue index is invalid.
*/ int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
u32 rxq_index)
{
ice_rxq_ctx_buf_t buf = {};
if (rxq_index > QRX_CTRL_MAX_INDEX) return -EINVAL;
/** * ice_read_rxq_ctx - Read Rx queue context from HW * @hw: pointer to the hardware structure * @rlan_ctx: pointer to the Rx queue context * @rxq_index: the index of the Rx queue * * Read the Rx queue context from the hardware registers, and unpack it into * the sparse Rx queue context structure. * * Returns: 0 on success, or -EINVAL if the Rx queue index is invalid.
*/ int ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
u32 rxq_index)
{
ice_rxq_ctx_buf_t buf = {};
if (rxq_index > QRX_CTRL_MAX_INDEX) return -EINVAL;
/** * ice_pack_txq_ctx - Pack Tx queue context into Admin Queue buffer * @ctx: the Tx queue context to pack * @buf: the Admin Queue HW buffer to pack into * * Pack the Tx queue context from the CPU-friendly unpacked buffer into its * bit-packed Admin Queue layout.
*/ void ice_pack_txq_ctx(conststruct ice_tlan_ctx *ctx, ice_txq_ctx_buf_t *buf)
{
pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields,
QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST);
}
/** * ice_pack_txq_ctx_full - Pack Tx queue context into a HW buffer * @ctx: the Tx queue context to pack * @buf: the HW buffer to pack into * * Pack the Tx queue context from the CPU-friendly unpacked buffer into its * bit-packed HW layout, including the internal data portion.
*/ staticvoid ice_pack_txq_ctx_full(conststruct ice_tlan_ctx *ctx,
ice_txq_ctx_buf_full_t *buf)
{
pack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields,
QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST);
}
/** * ice_unpack_txq_ctx_full - Unpack Tx queue context from a HW buffer * @buf: the HW buffer to unpack from * @ctx: the Tx queue context to unpack * * Unpack the Tx queue context from the HW buffer (including the full internal * state) into the CPU-friendly structure.
*/ staticvoid ice_unpack_txq_ctx_full(const ice_txq_ctx_buf_full_t *buf, struct ice_tlan_ctx *ctx)
{
unpack_fields(buf, sizeof(*buf), ctx, ice_tlan_ctx_fields,
QUIRK_LITTLE_ENDIAN | QUIRK_LSW32_IS_FIRST);
}
/** * ice_copy_txq_ctx_from_hw - Copy Tx Queue context from HW registers * @hw: pointer to the hardware structure * @txq_ctx: pointer to the packed Tx queue context, including internal state * @txq_index: the index of the Tx queue * * Copy Tx Queue context from HW register space to dense structure
*/ staticvoid ice_copy_txq_ctx_from_hw(struct ice_hw *hw,
ice_txq_ctx_buf_full_t *txq_ctx,
u32 txq_index)
{ struct ice_pf *pf = container_of(hw, struct ice_pf, hw);
u32 *ctx = (u32 *)txq_ctx;
u32 txq_base, reg;
/* Get Tx queue base within card space */
txq_base = rd32(hw, PFLAN_TX_QALLOC(hw->pf_id));
txq_base = FIELD_GET(PFLAN_TX_QALLOC_FIRSTQ_M, txq_base);
/** * ice_read_txq_ctx - Read Tx queue context from HW * @hw: pointer to the hardware structure * @tlan_ctx: pointer to the Tx queue context * @txq_index: the index of the Tx queue * * Read the Tx queue context from the HW registers, then unpack it into the * ice_tlan_ctx structure for use. * * Returns: 0 on success, or -EINVAL on an invalid Tx queue index.
*/ int ice_read_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx,
u32 txq_index)
{
ice_txq_ctx_buf_full_t buf = {};
if (txq_index > QTX_COMM_HEAD_MAX_INDEX) return -EINVAL;
/** * ice_write_txq_ctx - Write Tx queue context to HW * @hw: pointer to the hardware structure * @tlan_ctx: pointer to the Tx queue context * @txq_index: the index of the Tx queue * * Pack the Tx queue context into the dense HW layout, then write it into the * HW registers. * * Returns: 0 on success, or -EINVAL on an invalid Tx queue index.
*/ int ice_write_txq_ctx(struct ice_hw *hw, struct ice_tlan_ctx *tlan_ctx,
u32 txq_index)
{
ice_txq_ctx_buf_full_t buf = {};
if (txq_index > QTX_COMM_HEAD_MAX_INDEX) return -EINVAL;
if (in->opcode)
msg.data = cpu_to_le32(in->data); else /* data read comes back in completion, so shorten the struct by * sizeof(msg.data)
*/
msg_len -= sizeof(msg.data);
/* Software lock/mutex that is meant to be held while the Global Config Lock * in firmware is acquired by the software to prevent most (but not all) types * of AQ commands from being sent to FW
*/
DEFINE_MUTEX(ice_global_cfg_lock_sw);
/** * ice_should_retry_sq_send_cmd * @opcode: AQ opcode * * Decide if we should retry the send command routine for the ATQ, depending * on the opcode.
*/ staticbool ice_should_retry_sq_send_cmd(u16 opcode)
{ switch (opcode) { case ice_aqc_opc_get_link_topo: case ice_aqc_opc_lldp_stop: case ice_aqc_opc_lldp_start: case ice_aqc_opc_lldp_filter_ctrl: returntrue;
}
returnfalse;
}
/** * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) * @hw: pointer to the HW struct * @cq: pointer to the specific Control queue * @desc: prefilled descriptor describing the command * @buf: buffer to use for indirect commands (or NULL for direct commands) * @buf_size: size of buffer for indirect commands (or 0 for direct commands) * @cd: pointer to command details structure * * Retry sending the FW Admin Queue command, multiple times, to the FW Admin * Queue if the EBUSY AQ error is returned.
*/ staticint
ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, struct libie_aq_desc *desc, void *buf, u16 buf_size, struct ice_sq_cd *cd)
{ struct libie_aq_desc desc_cpy; bool is_cmd_for_retry;
u8 idx = 0;
u16 opcode; int status;
if (is_cmd_for_retry) { /* All retryable cmds are direct, without buf. */
WARN_ON(buf);
memcpy(&desc_cpy, desc, sizeof(desc_cpy));
}
do {
status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd);
if (!is_cmd_for_retry || !status ||
hw->adminq.sq_last_status != LIBIE_AQ_RC_EBUSY) break;
memcpy(desc, &desc_cpy, sizeof(desc_cpy));
msleep(ICE_SQ_SEND_DELAY_TIME_MS);
} while (++idx < ICE_SQ_SEND_MAX_EXECUTE);
return status;
}
/** * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue * @hw: pointer to the HW struct * @desc: descriptor describing the command * @buf: buffer to use for indirect commands (NULL for direct commands) * @buf_size: size of buffer for indirect commands (0 for direct commands) * @cd: pointer to command details structure * * Helper function to send FW Admin Queue commands to the FW Admin Queue.
*/ int
ice_aq_send_cmd(struct ice_hw *hw, struct libie_aq_desc *desc, void *buf,
u16 buf_size, struct ice_sq_cd *cd)
{ struct libie_aqc_req_res *cmd = libie_aq_raw(desc); bool lock_acquired = false; int status;
/* When a package download is in process (i.e. when the firmware's * Global Configuration Lock resource is held), only the Download * Package, Get Version, Get Package Info List, Upload Section, * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get * Recipes to Profile Association, and Release Resource (with resource * ID set to Global Config Lock) AdminQ commands are allowed; all others * must block until the package download completes and the Global Config * Lock is released. See also ice_acquire_global_cfg_lock().
*/ switch (le16_to_cpu(desc->opcode)) { case ice_aqc_opc_download_pkg: case ice_aqc_opc_get_pkg_info_list: case ice_aqc_opc_get_ver: case ice_aqc_opc_upload_section: case ice_aqc_opc_update_pkg: case ice_aqc_opc_set_port_params: case ice_aqc_opc_get_vlan_mode_parameters: case ice_aqc_opc_set_vlan_mode_parameters: case ice_aqc_opc_set_tx_topo: case ice_aqc_opc_get_tx_topo: case ice_aqc_opc_add_recipe: case ice_aqc_opc_recipe_to_profile: case ice_aqc_opc_get_recipe: case ice_aqc_opc_get_recipe_to_profile: break; case ice_aqc_opc_release_res: if (le16_to_cpu(cmd->res_id) == LIBIE_AQC_RES_ID_GLBL_LOCK) break;
fallthrough; default:
mutex_lock(&ice_global_cfg_lock_sw);
lock_acquired = true; break;
}
status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); if (lock_acquired)
mutex_unlock(&ice_global_cfg_lock_sw);
return status;
}
/** * ice_aq_get_fw_ver * @hw: pointer to the HW struct * @cd: pointer to command details structure or NULL * * Get the firmware version (0x0001) from the admin queue commands
*/ int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
{ struct libie_aqc_get_ver *resp; struct libie_aq_desc desc; int status;
/** * ice_aq_send_driver_ver * @hw: pointer to the HW struct * @dv: driver's major, minor version * @cd: pointer to command details structure or NULL * * Send the driver version (0x0002) to the firmware
*/ int
ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, struct ice_sq_cd *cd)
{ struct libie_aqc_driver_ver *cmd; struct libie_aq_desc desc;
u16 len;
/** * ice_aq_q_shutdown * @hw: pointer to the HW struct * @unloading: is the driver unloading itself * * Tell the Firmware that we're shutting down the AdminQ and whether * or not the driver is unloading as well (0x0003).
*/ int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
{ struct ice_aqc_q_shutdown *cmd; struct libie_aq_desc desc;
/** * ice_aq_req_res * @hw: pointer to the HW struct * @res: resource ID * @access: access type * @sdp_number: resource number * @timeout: the maximum time in ms that the driver may hold the resource * @cd: pointer to command details structure or NULL * * Requests common resource using the admin queue commands (0x0008). * When attempting to acquire the Global Config Lock, the driver can * learn of three states: * 1) 0 - acquired lock, and can perform download package * 2) -EIO - did not get lock, driver should fail to load * 3) -EALREADY - did not get lock, but another driver has * successfully downloaded the package; the driver does * not have to download the package and can continue * loading * * Note that if the caller is in an acquire lock, perform action, release lock * phase of operation, it is possible that the FW may detect a timeout and issue * a CORER. In this case, the driver will receive a CORER interrupt and will * have to determine its cause. The calling thread that is handling this flow * will likely get an error propagated back to it indicating the Download * Package, Update Package or the Release Resource AQ commands timed out.
*/ staticint
ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, struct ice_sq_cd *cd)
{ struct libie_aqc_req_res *cmd_resp; struct libie_aq_desc desc; int status;
/* The completion specifies the maximum time in ms that the driver * may hold the resource in the Timeout field.
*/
/* Global config lock response utilizes an additional status field. * * If the Global config lock resource is held by some other driver, the * command completes with LIBIE_AQ_RES_GLBL_IN_PROG in the status field * and the timeout field indicates the maximum time the current owner * of the resource has to free it.
*/ if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { if (le16_to_cpu(cmd_resp->status) == LIBIE_AQ_RES_GLBL_SUCCESS) {
*timeout = le32_to_cpu(cmd_resp->timeout); return 0;
} elseif (le16_to_cpu(cmd_resp->status) ==
LIBIE_AQ_RES_GLBL_IN_PROG) {
*timeout = le32_to_cpu(cmd_resp->timeout); return -EIO;
} elseif (le16_to_cpu(cmd_resp->status) ==
LIBIE_AQ_RES_GLBL_DONE) { return -EALREADY;
}
/* invalid FW response, force a timeout immediately */
*timeout = 0; return -EIO;
}
/* If the resource is held by some other driver, the command completes * with a busy return value and the timeout field indicates the maximum * time the current owner of the resource has to free it.
*/ if (!status || hw->adminq.sq_last_status == LIBIE_AQ_RC_EBUSY)
*timeout = le32_to_cpu(cmd_resp->timeout);
return status;
}
/** * ice_aq_release_res * @hw: pointer to the HW struct * @res: resource ID * @sdp_number: resource number * @cd: pointer to command details structure or NULL * * release common resource using the admin queue commands (0x0009)
*/ staticint
ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, struct ice_sq_cd *cd)
{ struct libie_aqc_req_res *cmd; struct libie_aq_desc desc;
/** * ice_acquire_res * @hw: pointer to the HW structure * @res: resource ID * @access: access type (read or write) * @timeout: timeout in milliseconds * * This function will attempt to acquire the ownership of a resource.
*/ int
ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, enum ice_aq_res_access_type access, u32 timeout)
{ #define ICE_RES_POLLING_DELAY_MS 10
u32 delay = ICE_RES_POLLING_DELAY_MS;
u32 time_left = timeout; int status;
status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
/* A return code of -EALREADY means that another driver has * previously acquired the resource and performed any necessary updates; * in this case the caller does not obtain the resource and has no * further work to do.
*/ if (status == -EALREADY) goto ice_acquire_res_exit;
if (status)
ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access);
/* If necessary, poll until the current lock owner timeouts */
timeout = time_left; while (status && timeout && time_left) {
mdelay(delay);
timeout = (timeout > delay) ? timeout - delay : 0;
status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
if (status == -EALREADY) /* lock free, but no work to do */ break;
if (!status) /* lock acquired */ break;
} if (status && status != -EALREADY)
ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
ice_acquire_res_exit: if (status == -EALREADY) { if (access == ICE_RES_WRITE)
ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); else
ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n");
} return status;
}
/** * ice_release_res * @hw: pointer to the HW structure * @res: resource ID * * This function will release a resource using the proper Admin Command.
*/ void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
{ unsignedlong timeout; int status;
/* there are some rare cases when trying to release the resource * results in an admin queue timeout, so handle them correctly
*/
timeout = jiffies + 10 * ICE_CTL_Q_SQ_CMD_TIMEOUT; do {
status = ice_aq_release_res(hw, res, 0, NULL); if (status != -EIO) break;
usleep_range(1000, 2000);
} while (time_before(jiffies, timeout));
}
/** * ice_aq_alloc_free_res - command to allocate/free resources * @hw: pointer to the HW struct * @buf: Indirect buffer to hold data parameters and response * @buf_size: size of buffer for indirect commands * @opc: pass in the command opcode * * Helper function to allocate/free resources using the admin queue commands
*/ int ice_aq_alloc_free_res(struct ice_hw *hw, struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, enum ice_adminq_opc opc)
{ struct ice_aqc_alloc_free_res_cmd *cmd; struct libie_aq_desc desc;
cmd = libie_aq_raw(&desc);
if (!buf || buf_size < flex_array_size(buf, elem, 1)) return -EINVAL;
/** * ice_alloc_hw_res - allocate resource * @hw: pointer to the HW struct * @type: type of resource * @num: number of resources to allocate * @btm: allocate from bottom * @res: pointer to array that will receive the resources
*/ int
ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
{ struct ice_aqc_alloc_free_res_elem *buf;
u16 buf_len; int status;
status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res); if (status) goto ice_alloc_res_exit;
memcpy(res, buf->elem, sizeof(*buf->elem) * num);
ice_alloc_res_exit:
kfree(buf); return status;
}
/** * ice_free_hw_res - free allocated HW resource * @hw: pointer to the HW struct * @type: type of resource to free * @num: number of resources * @res: pointer to array that contains the resources to free
*/ int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
{ struct ice_aqc_alloc_free_res_elem *buf;
u16 buf_len; int status;
status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res); if (status)
ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
kfree(buf); return status;
}
/** * ice_get_num_per_func - determine number of resources per PF * @hw: pointer to the HW structure * @max: value to be evenly split between each PF * * Determine the number of valid functions by going through the bitmap returned * from parsing capabilities and use this to calculate the number of resources * per PF based on the max value passed in.
*/ static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
{
u8 funcs;
/** * ice_parse_common_caps - parse common device/function capabilities * @hw: pointer to the HW struct * @caps: pointer to common capabilities structure * @elem: the capability element to parse * @prefix: message prefix for tracing capabilities * * Given a capability element, extract relevant details into the common * capability structure. * * Returns: true if the capability matches one of the common capability ids, * false otherwise.
*/ staticbool
ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, struct libie_aqc_list_caps_elem *elem, constchar *prefix)
{
u32 logical_id = le32_to_cpu(elem->logical_id);
u32 phys_id = le32_to_cpu(elem->phys_id);
u32 number = le32_to_cpu(elem->number);
u16 cap = le16_to_cpu(elem->cap); bool found = true;
/** * ice_recalc_port_limited_caps - Recalculate port limited capabilities * @hw: pointer to the HW structure * @caps: pointer to capabilities structure to fix * * Re-calculate the capabilities that are dependent on the number of physical * ports; i.e. some features are not supported or function differently on * devices with more than 4 ports.
*/ staticvoid
ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps)
{ /* This assumes device capabilities are always scanned before function * capabilities during the initialization flow.
*/ if (hw->dev_caps.num_funcs > 4) { /* Max 4 TCs per port */
caps->maxtc = 4;
ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n",
caps->maxtc); if (caps->rdma) {
ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n");
caps->rdma = 0;
}
/* print message only when processing device capabilities * during initialization.
*/ if (caps == &hw->dev_caps.common_cap)
dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n");
}
}
/** * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps * @hw: pointer to the HW struct * @func_p: pointer to function capabilities structure * @cap: pointer to the capability element to parse * * Extract function capabilities for ICE_AQC_CAPS_VF.
*/ staticvoid
ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, struct libie_aqc_list_caps_elem *cap)
{
u32 logical_id = le32_to_cpu(cap->logical_id);
u32 number = le32_to_cpu(cap->number);
/** * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps * @hw: pointer to the HW struct * @func_p: pointer to function capabilities structure * @cap: pointer to the capability element to parse * * Extract function capabilities for ICE_AQC_CAPS_VSI.
*/ staticvoid
ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, struct libie_aqc_list_caps_elem *cap)
{
func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI);
ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n",
le32_to_cpu(cap->number));
ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n",
func_p->guar_num_vsi);
}
/** * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps * @hw: pointer to the HW struct * @func_p: pointer to function capabilities structure * @cap: pointer to the capability element to parse * * Extract function capabilities for ICE_AQC_CAPS_1588.
*/ staticvoid
ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, struct libie_aqc_list_caps_elem *cap)
{ struct ice_ts_func_info *info = &func_p->ts_func_info;
u32 number = le32_to_cpu(cap->number);
/** * ice_parse_func_caps - Parse function capabilities * @hw: pointer to the HW struct * @func_p: pointer to function capabilities structure * @buf: buffer containing the function capability records * @cap_count: the number of capabilities * * Helper function to parse function (0x000A) capabilities list. For * capabilities shared between device and function, this relies on * ice_parse_common_caps. * * Loop through the list of provided capabilities and extract the relevant * data into the function capabilities structured.
*/ staticvoid
ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, void *buf, u32 cap_count)
{ struct libie_aqc_list_caps_elem *cap_resp;
u32 i;
cap_resp = buf;
memset(func_p, 0, sizeof(*func_p));
for (i = 0; i < cap_count; i++) {
u16 cap = le16_to_cpu(cap_resp[i].cap); bool found;
found = ice_parse_common_caps(hw, &func_p->common_cap,
&cap_resp[i], "func caps");
switch (cap) { case LIBIE_AQC_CAPS_VF:
ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); break; case LIBIE_AQC_CAPS_VSI:
ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); break; case LIBIE_AQC_CAPS_1588:
ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); break; case LIBIE_AQC_CAPS_FD:
ice_parse_fdir_func_caps(hw, func_p); break; default: /* Don't list common capabilities as unknown */ if (!found)
ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n",
i, cap); break;
}
}
/** * ice_func_id_to_logical_id - map from function id to logical pf id * @active_function_bitmap: active function bitmap * @pf_id: function number of device * * Return: logical PF ID.
*/ staticint ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id)
{
u8 logical_id = 0;
u8 i;
for (i = 0; i < pf_id; i++) if (active_function_bitmap & BIT(i))
logical_id++;
return logical_id;
}
/** * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps * @hw: pointer to the HW struct * @dev_p: pointer to device capabilities structure * @cap: capability element to parse * * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities.
*/ staticvoid
ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, struct libie_aqc_list_caps_elem *cap)
{
u32 number = le32_to_cpu(cap->number);
/** * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap * @hw: pointer to the HW struct * @dev_p: pointer to device capabilities structure * @cap: capability element to parse * * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities.
*/ staticvoid ice_parse_nac_topo_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, struct libie_aqc_list_caps_elem *cap)
{
dev_p->nac_topo.mode = le32_to_cpu(cap->number);
dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M;
dev_info(ice_hw_to_dev(hw), "PF is configured in %s mode with IP instance ID %d\n",
(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ? "primary" : "secondary", dev_p->nac_topo.id);
/** * ice_parse_dev_caps - Parse device capabilities * @hw: pointer to the HW struct * @dev_p: pointer to device capabilities structure * @buf: buffer containing the device capability records * @cap_count: the number of capabilities * * Helper device to parse device (0x000B) capabilities list. For * capabilities shared between device and function, this relies on * ice_parse_common_caps. * * Loop through the list of provided capabilities and extract the relevant * data into the device capabilities structured.
*/ staticvoid
ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, void *buf, u32 cap_count)
{ struct libie_aqc_list_caps_elem *cap_resp;
u32 i;
cap_resp = buf;
memset(dev_p, 0, sizeof(*dev_p));
for (i = 0; i < cap_count; i++) {
u16 cap = le16_to_cpu(cap_resp[i].cap); bool found;
found = ice_parse_common_caps(hw, &dev_p->common_cap,
&cap_resp[i], "dev caps");
switch (cap) { case LIBIE_AQC_CAPS_VALID_FUNCTIONS:
ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); break; case LIBIE_AQC_CAPS_VF:
ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); break; case LIBIE_AQC_CAPS_VSI:
ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); break; case LIBIE_AQC_CAPS_1588:
ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); break; case LIBIE_AQC_CAPS_FD:
ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); break; case LIBIE_AQC_CAPS_SENSOR_READING:
ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); break; case LIBIE_AQC_CAPS_NAC_TOPOLOGY:
ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); break; default: /* Don't list common capabilities as unknown */ if (!found)
ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n",
i, cap); break;
}
}
/** * ice_is_phy_rclk_in_netlist * @hw: pointer to the hw struct * * Check if the PHY Recovered Clock device is present in the netlist
*/ bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw)
{ if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY,
ICE_AQC_LINK_TOPO_NODE_CTX_PORT,
ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) &&
ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY,
ICE_AQC_LINK_TOPO_NODE_CTX_PORT,
ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL)) returnfalse;
returntrue;
}
/** * ice_is_clock_mux_in_netlist * @hw: pointer to the hw struct * * Check if the Clock Multiplexer device is present in the netlist
*/ bool ice_is_clock_mux_in_netlist(struct ice_hw *hw)
{ if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX,
ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL,
ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX,
NULL)) returnfalse;
returntrue;
}
/** * ice_is_cgu_in_netlist - check for CGU presence * @hw: pointer to the hw struct * * Check if the Clock Generation Unit (CGU) device is present in the netlist. * Save the CGU part number in the hw structure for later use. * Return: * * true - cgu is present * * false - cgu is not present
*/ bool ice_is_cgu_in_netlist(struct ice_hw *hw)
{ if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL,
ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL,
ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032,
NULL)) {
hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032; returntrue;
} elseif (!ice_find_netlist_node(hw,
ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL,
ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL,
ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384,
NULL)) {
hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384; returntrue;
}
returnfalse;
}
/** * ice_is_gps_in_netlist * @hw: pointer to the hw struct * * Check if the GPS generic device is present in the netlist
*/ bool ice_is_gps_in_netlist(struct ice_hw *hw)
{ if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS,
ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL,
ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL)) returnfalse;
returntrue;
}
/** * ice_aq_list_caps - query function/device capabilities * @hw: pointer to the HW struct * @buf: a buffer to hold the capabilities * @buf_size: size of the buffer * @cap_count: if not NULL, set to the number of capabilities reported * @opc: capabilities type to discover, device or function * @cd: pointer to command details structure or NULL * * Get the function (0x000A) or device (0x000B) capabilities description from * firmware and store it in the buffer. * * If the cap_count pointer is not NULL, then it is set to the number of * capabilities firmware will report. Note that if the buffer size is too * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The * cap_count will still be updated in this case. It is recommended that the * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that * firmware could return) to avoid this.
*/ int
ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, enum ice_adminq_opc opc, struct ice_sq_cd *cd)
{ struct libie_aqc_list_caps *cmd; struct libie_aq_desc desc; int status;
cmd = &desc.params.get_cap;
if (opc != ice_aqc_opc_list_func_caps &&
opc != ice_aqc_opc_list_dev_caps) return -EINVAL;
ice_fill_dflt_direct_cmd_desc(&desc, opc);
status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
if (cap_count)
*cap_count = le32_to_cpu(cmd->count);
return status;
}
/** * ice_discover_dev_caps - Read and extract device capabilities * @hw: pointer to the hardware structure * @dev_caps: pointer to device capabilities structure * * Read the device capabilities and extract them into the dev_caps structure * for later use.
*/ int
ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps)
{
u32 cap_count = 0; void *cbuf; int status;
cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); if (!cbuf) return -ENOMEM;
/* Although the driver doesn't know the number of capabilities the * device will return, we can simply send a 4KB buffer, the maximum * possible size that firmware can return.
*/
cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem);
status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
ice_aqc_opc_list_dev_caps, NULL); if (!status)
ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count);
kfree(cbuf);
return status;
}
/** * ice_discover_func_caps - Read and extract function capabilities * @hw: pointer to the hardware structure * @func_caps: pointer to function capabilities structure * * Read the function capabilities and extract them into the func_caps structure * for later use.
*/ staticint
ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps)
{
u32 cap_count = 0; void *cbuf; int status;
cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); if (!cbuf) return -ENOMEM;
/* Although the driver doesn't know the number of capabilities the * device will return, we can simply send a 4KB buffer, the maximum * possible size that firmware can return.
*/
cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct libie_aqc_list_caps_elem);
status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
ice_aqc_opc_list_func_caps, NULL); if (!status)
ice_parse_func_caps(hw, func_caps, cbuf, cap_count);
kfree(cbuf);
return status;
}
/** * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode * @hw: pointer to the hardware structure
*/ void ice_set_safe_mode_caps(struct ice_hw *hw)
{ struct ice_hw_func_caps *func_caps = &hw->func_caps; struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; struct ice_hw_common_caps cached_caps;
u32 num_funcs;
/* cache some func_caps values that should be restored after memset */
cached_caps = func_caps->common_cap;
/** * ice_aq_manage_mac_write - manage MAC address write command * @hw: pointer to the HW struct * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address * @flags: flags to control write behavior * @cd: pointer to command details structure or NULL * * This function is used to write MAC address to the NVM (0x0108).
*/ int
ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, struct ice_sq_cd *cd)
{ struct ice_aqc_manage_mac_write *cmd; struct libie_aq_desc desc;
/** * ice_aq_clear_pxe_mode * @hw: pointer to the HW struct * * Tell the firmware that the driver is taking over from PXE (0x0110).
*/ staticint ice_aq_clear_pxe_mode(struct ice_hw *hw)
{ struct ice_aqc_clear_pxe *cmd; struct libie_aq_desc desc;
/** * ice_clear_pxe_mode - clear pxe operations mode * @hw: pointer to the HW struct * * Make sure all PXE mode settings are cleared, including things * like descriptor fetch/write-back mode.
*/ void ice_clear_pxe_mode(struct ice_hw *hw)
{ if (ice_check_sq_alive(hw, &hw->adminq))
ice_aq_clear_pxe_mode(hw);
}
/** * ice_aq_set_port_params - set physical port parameters. * @pi: pointer to the port info struct * @double_vlan: if set double VLAN is enabled * @cd: pointer to command details structure or NULL * * Set Physical port parameters (0x0203)
*/ int
ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, struct ice_sq_cd *cd)
/** * ice_is_100m_speed_supported * @hw: pointer to the HW struct * * returns true if 100M speeds are supported by the device, * false otherwise.
*/ bool ice_is_100m_speed_supported(struct ice_hw *hw)
{ switch (hw->device_id) { case ICE_DEV_ID_E822C_SGMII: case ICE_DEV_ID_E822L_SGMII: case ICE_DEV_ID_E823L_1GBE: case ICE_DEV_ID_E823C_SGMII: returntrue; default: returnfalse;
}
}
/** * ice_get_link_speed_based_on_phy_type - returns link speed * @phy_type_low: lower part of phy_type * @phy_type_high: higher part of phy_type * * This helper function will convert an entry in PHY type structure * [phy_type_low, phy_type_high] to its corresponding link speed. * Note: In the structure of [phy_type_low, phy_type_high], there should * be one bit set, as this function will convert one PHY type to its * speed. * * Return: * * PHY speed for recognized PHY type * * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned * * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
*/
u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
{
u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
switch (phy_type_low) { case ICE_PHY_TYPE_LOW_100BASE_TX: case ICE_PHY_TYPE_LOW_100M_SGMII:
speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; break; case ICE_PHY_TYPE_LOW_1000BASE_T: case ICE_PHY_TYPE_LOW_1000BASE_SX: case ICE_PHY_TYPE_LOW_1000BASE_LX: case ICE_PHY_TYPE_LOW_1000BASE_KX: case ICE_PHY_TYPE_LOW_1G_SGMII:
speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; break; case ICE_PHY_TYPE_LOW_2500BASE_T: case ICE_PHY_TYPE_LOW_2500BASE_X: case ICE_PHY_TYPE_LOW_2500BASE_KX:
speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; break; case ICE_PHY_TYPE_LOW_5GBASE_T: case ICE_PHY_TYPE_LOW_5GBASE_KR:
speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; break; case ICE_PHY_TYPE_LOW_10GBASE_T: case ICE_PHY_TYPE_LOW_10G_SFI_DA: case ICE_PHY_TYPE_LOW_10GBASE_SR: case ICE_PHY_TYPE_LOW_10GBASE_LR: case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; break; case ICE_PHY_TYPE_LOW_25GBASE_T: case ICE_PHY_TYPE_LOW_25GBASE_CR: case ICE_PHY_TYPE_LOW_25GBASE_CR_S: case ICE_PHY_TYPE_LOW_25GBASE_CR1: case ICE_PHY_TYPE_LOW_25GBASE_SR: case ICE_PHY_TYPE_LOW_25GBASE_LR: case ICE_PHY_TYPE_LOW_25GBASE_KR: case ICE_PHY_TYPE_LOW_25GBASE_KR_S: case ICE_PHY_TYPE_LOW_25GBASE_KR1: case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; break; case ICE_PHY_TYPE_LOW_40GBASE_CR4: case ICE_PHY_TYPE_LOW_40GBASE_SR4: case ICE_PHY_TYPE_LOW_40GBASE_LR4: case ICE_PHY_TYPE_LOW_40GBASE_KR4: case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: case ICE_PHY_TYPE_LOW_40G_XLAUI:
speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; break; case ICE_PHY_TYPE_LOW_50GBASE_CR2: case ICE_PHY_TYPE_LOW_50GBASE_SR2: case ICE_PHY_TYPE_LOW_50GBASE_LR2: case ICE_PHY_TYPE_LOW_50GBASE_KR2: case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: case ICE_PHY_TYPE_LOW_50G_LAUI2: case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: case ICE_PHY_TYPE_LOW_50G_AUI2: case ICE_PHY_TYPE_LOW_50GBASE_CP: case ICE_PHY_TYPE_LOW_50GBASE_SR: case ICE_PHY_TYPE_LOW_50GBASE_FR: case ICE_PHY_TYPE_LOW_50GBASE_LR: case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: case ICE_PHY_TYPE_LOW_50G_AUI1:
speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; break; case ICE_PHY_TYPE_LOW_100GBASE_CR4: case ICE_PHY_TYPE_LOW_100GBASE_SR4: case ICE_PHY_TYPE_LOW_100GBASE_LR4: case ICE_PHY_TYPE_LOW_100GBASE_KR4: case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: case ICE_PHY_TYPE_LOW_100G_CAUI4: case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: case ICE_PHY_TYPE_LOW_100G_AUI4: case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: case ICE_PHY_TYPE_LOW_100GBASE_CP2: case ICE_PHY_TYPE_LOW_100GBASE_SR2: case ICE_PHY_TYPE_LOW_100GBASE_DR:
speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; break; default:
speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; break;
}
switch (phy_type_high) { case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: case ICE_PHY_TYPE_HIGH_100G_CAUI2: case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: case ICE_PHY_TYPE_HIGH_100G_AUI2:
speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; break; case ICE_PHY_TYPE_HIGH_200G_CR4_PAM4: case ICE_PHY_TYPE_HIGH_200G_SR4: case ICE_PHY_TYPE_HIGH_200G_FR4: case ICE_PHY_TYPE_HIGH_200G_LR4: case ICE_PHY_TYPE_HIGH_200G_DR4: case ICE_PHY_TYPE_HIGH_200G_KR4_PAM4: case ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC: case ICE_PHY_TYPE_HIGH_200G_AUI4:
speed_phy_type_high = ICE_AQ_LINK_SPEED_200GB; break; default:
speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; break;
}
/** * ice_update_phy_type * @phy_type_low: pointer to the lower part of phy_type * @phy_type_high: pointer to the higher part of phy_type * @link_speeds_bitmap: targeted link speeds bitmap * * Note: For the link_speeds_bitmap structure, you can check it at * [ice_aqc_get_link_status->link_speed]. Caller can pass in * link_speeds_bitmap include multiple speeds. * * Each entry in this [phy_type_low, phy_type_high] structure will * present a certain link speed. This helper function will turn on bits * in [phy_type_low, phy_type_high] structure based on the value of * link_speeds_bitmap input parameter.
*/ void
ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
u16 link_speeds_bitmap)
{
u64 pt_high;
u64 pt_low; int index;
u16 speed;
/* We first check with low part of phy_type */ for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
pt_low = BIT_ULL(index);
speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
if (link_speeds_bitmap & speed)
*phy_type_low |= BIT_ULL(index);
}
/* We then check with high part of phy_type */ for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
pt_high = BIT_ULL(index);
speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
if (link_speeds_bitmap & speed)
*phy_type_high |= BIT_ULL(index);
}
}
/** * ice_aq_set_phy_cfg * @hw: pointer to the HW struct * @pi: port info structure of the interested logical port * @cfg: structure with PHY configuration data to be set * @cd: pointer to command details structure or NULL * * Set the various PHY configuration parameters supported on the Port. * One or more of the Set PHY config parameters may be ignored in an MFP * mode as the PF may not have the privilege to set some of the PHY Config * parameters. This status will be indicated by the command response (0x0601).
*/ int
ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
{ struct ice_aqc_set_phy_cfg *cmd; struct libie_aq_desc desc; int status;
if (!cfg) return -EINVAL;
/* Ensure that only valid bits of cfg->caps can be turned on. */ if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
cfg->caps);
status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); if (hw->adminq.sq_last_status == LIBIE_AQ_RC_EMODE)
status = 0;
if (!status)
pi->phy.curr_user_phy_cfg = *cfg;
return status;
}
/** * ice_update_link_info - update status of the HW network link * @pi: port info structure of the interested logical port
*/ int ice_update_link_info(struct ice_port_info *pi)
{ struct ice_link_status *li; int status;
if (!pi) return -EINVAL;
li = &pi->phy.link_info;
status = ice_aq_get_link_info(pi, true, NULL, NULL); if (status) return status;
pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); if (!pcaps) return -ENOMEM;
status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA,
pcaps, NULL);
}
return status;
}
/** * ice_aq_get_phy_equalization - function to read serdes equaliser * value from firmware using admin queue command. * @hw: pointer to the HW struct * @data_in: represents the serdes equalization parameter requested * @op_code: represents the serdes number and flag to represent tx or rx * @serdes_num: represents the serdes number * @output: pointer to the caller-supplied buffer to return serdes equaliser * * Return: non-zero status on error and 0 on success.
*/ int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code,
u8 serdes_num, int *output)
{ struct ice_aqc_dnl_call_command *cmd; struct ice_aqc_dnl_call buf = {}; struct libie_aq_desc desc; int err;
/** * ice_aq_get_fec_stats - reads fec stats from phy * @hw: pointer to the HW struct * @pcs_quad: represents pcsquad of user input serdes * @pcs_port: represents the pcs port number part of above pcs quad * @fec_type: represents FEC stats type * @output: pointer to the caller-supplied buffer to return requested fec stats * * Return: non-zero status on error and 0 on success.
*/ int ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port, enum ice_fec_stats_types fec_type, u32 *output)
{
u16 flag = (LIBIE_AQ_FLAG_RD | LIBIE_AQ_FLAG_BUF | LIBIE_AQ_FLAG_SI); struct ice_sbq_msg_input msg = {};
u32 receiver_id, reg_offset; int err;
if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
ICE_AQC_PHY_FEC_25G_RS_544_REQ |
ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) return ICE_FEC_RS;
return ICE_FEC_NONE;
}
/** * ice_cfg_phy_fc - Configure PHY FC data based on FC mode * @pi: port information structure * @cfg: PHY configuration data to set FC mode * @req_mode: FC mode to configure
*/ int
ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fc_mode req_mode)
{ struct ice_phy_cache_mode_data cache_data;
u8 pause_mask = 0x0;
if (!pi || !cfg) return -EINVAL;
switch (req_mode) { case ICE_FC_FULL:
pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; break; case ICE_FC_RX_PAUSE:
pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; break; case ICE_FC_TX_PAUSE:
pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; break; default: break;
}
/* clear the old pause settings */
cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
ICE_AQC_PHY_EN_RX_LINK_PAUSE);
/* set the new capabilities */
cfg->caps |= pause_mask;
/* Cache user FC request */
cache_data.data.curr_user_fc_req = req_mode;
ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
return 0;
}
/** * ice_set_fc * @pi: port information structure * @aq_failures: pointer to status code, specific to ice_set_fc routine * @ena_auto_link_update: enable automatic link update * * Set the requested flow control mode.
*/ int
ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
{ struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; struct ice_aqc_set_phy_cfg_data cfg = { 0 }; struct ice_hw *hw; int status;
if (!pi || !aq_failures) return -EINVAL;
*aq_failures = 0;
hw = pi->hw;
pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); if (!pcaps) return -ENOMEM;
/* Get the current PHY config */
status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
pcaps, NULL); if (status) {
*aq_failures = ICE_SET_FC_AQ_FAIL_GET; goto out;
}
ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg);
/* Configure the set PHY data */
status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); if (status) goto out;
/* If the capabilities have changed, then set the new config */ if (cfg.caps != pcaps->caps) { int retry_count, retry_max = 10;
/* Auto restart link so settings take effect */ if (ena_auto_link_update)
cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); if (status) {
*aq_failures = ICE_SET_FC_AQ_FAIL_SET; goto out;
}
/* Update the link info * It sometimes takes a really long time for link to * come back from the atomic reset. Thus, we wait a * little bit.
*/ for (retry_count = 0; retry_count < retry_max; retry_count++) {
status = ice_update_link_info(pi);
if (!status) break;
mdelay(100);
}
if (status)
*aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
}
/* These bits are not common between capabilities and configuration. * Do not use them to determine equality.
*/
caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
ICE_AQC_GET_PHY_EN_MOD_QUAL);
cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
/** * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data * @pi: port information structure * @caps: PHY ability structure to copy date from * @cfg: PHY configuration structure to copy data to * * Helper function to copy AQC PHY get ability data to PHY set configuration * data structure
*/ void
ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, struct ice_aqc_get_phy_caps_data *caps, struct ice_aqc_set_phy_cfg_data *cfg)
{ if (!pi || !caps || !cfg) return;
/** * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode * @pi: port information structure * @cfg: PHY configuration data to set FEC mode * @fec: FEC mode to configure
*/ int
ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec)
{ struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL; struct ice_hw *hw; int status;
if (!pi || !cfg) return -EINVAL;
hw = pi->hw;
pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); if (!pcaps) return -ENOMEM;
status = ice_aq_get_phy_caps(pi, false,
(ice_fw_supports_report_dflt_cfg(hw) ?
ICE_AQC_REPORT_DFLT_CFG :
ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); if (status) goto out;
/** * ice_get_link_status - get status of the HW network link * @pi: port information structure * @link_up: pointer to bool (true/false = linkup/linkdown) * * Variable link_up is true if link is up, false if link is down. * The variable link_up is invalid if status is non zero. As a * result of this call, link status reporting becomes enabled
*/ int ice_get_link_status(struct ice_port_info *pi, bool *link_up)
{ struct ice_phy_info *phy_info; int status = 0;
if (!pi || !link_up) return -EINVAL;
phy_info = &pi->phy;
if (phy_info->get_link_info) {
status = ice_update_link_info(pi);
if (status)
ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n",
status);
}
/** * ice_aq_set_link_restart_an * @pi: pointer to the port information structure * @ena_link: if true: enable link, if false: disable link * @cd: pointer to command details structure or NULL * * Sets up the link and restarts the Auto-Negotiation over the link.
*/ int
ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, struct ice_sq_cd *cd)
{ struct ice_aqc_restart_an *cmd; struct libie_aq_desc desc;
/** * ice_aq_set_event_mask * @hw: pointer to the HW struct * @port_num: port number of the physical function * @mask: event mask to be set * @cd: pointer to command details structure or NULL * * Set event mask (0x0613)
*/ int
ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, struct ice_sq_cd *cd)
{ struct ice_aqc_set_event_mask *cmd; struct libie_aq_desc desc;
/** * ice_aq_set_mac_loopback * @hw: pointer to the HW struct * @ena_lpbk: Enable or Disable loopback * @cd: pointer to command details structure or NULL * * Enable/disable loopback on a given port
*/ int
ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
{ struct ice_aqc_set_mac_lb *cmd; struct libie_aq_desc desc;
cmd = libie_aq_raw(&desc);
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); if (ena_lpbk)
cmd->lb_mode = ICE_AQ_MAC_LB_EN;
return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
}
/** * ice_aq_set_port_id_led * @pi: pointer to the port information * @is_orig_mode: is this LED set to original mode (by the net-list) * @cd: pointer to command details structure or NULL * * Set LED value for the given port (0x06e9)
*/ int
ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, struct ice_sq_cd *cd)
{ struct ice_aqc_set_port_id_led *cmd; struct ice_hw *hw = pi->hw; struct libie_aq_desc desc;
if (is_orig_mode)
cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; else
cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
}
/** * ice_aq_get_port_options * @hw: pointer to the HW struct * @options: buffer for the resultant port options * @option_count: input - size of the buffer in port options structures, * output - number of returned port options * @lport: logical port to call the command with (optional) * @lport_valid: when false, FW uses port owned by the PF instead of lport, * when PF owns more than 1 port it must be true * @active_option_idx: index of active port option in returned buffer * @active_option_valid: active option in returned buffer is valid * @pending_option_idx: index of pending port option in returned buffer * @pending_option_valid: pending option in returned buffer is valid * * Calls Get Port Options AQC (0x06ea) and verifies result.
*/ int
ice_aq_get_port_options(struct ice_hw *hw, struct ice_aqc_get_port_options_elem *options,
u8 *option_count, u8 lport, bool lport_valid,
u8 *active_option_idx, bool *active_option_valid,
u8 *pending_option_idx, bool *pending_option_valid)
{ struct ice_aqc_get_port_options *cmd; struct libie_aq_desc desc; int status;
u8 i;
/* options buffer shall be able to hold max returned options */ if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) return -EINVAL;
/* mask output options fields */ for (i = 0; i < *option_count; i++) {
options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M,
options[i].pmd);
options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M,
options[i].max_lane_speed);
ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n",
options[i].pmd, options[i].max_lane_speed);
}
return 0;
}
/** * ice_aq_set_port_option * @hw: pointer to the HW struct * @lport: logical port to call the command with * @lport_valid: when false, FW uses port owned by the PF instead of lport, * when PF owns more than 1 port it must be true * @new_option: new port option to be written * * Calls Set Port Options AQC (0x06eb).
*/ int
ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid,
u8 new_option)
{ struct ice_aqc_set_port_option *cmd; struct libie_aq_desc desc;
if (new_option > ICE_AQC_PORT_OPT_COUNT_M) return -EINVAL;
/** * ice_get_phy_lane_number - Get PHY lane number for current adapter * @hw: pointer to the hw struct * * Return: PHY lane number on success, negative error code otherwise.
*/ int ice_get_phy_lane_number(struct ice_hw *hw)
{ struct ice_aqc_get_port_options_elem *options; unsignedint lport = 0; unsignedint lane; int err;
options = kcalloc(ICE_AQC_PORT_OPT_MAX, sizeof(*options), GFP_KERNEL); if (!options) return -ENOMEM;
for (lane = 0; lane < ICE_MAX_PORT_PER_PCI_DEV; lane++) {
u8 options_count = ICE_AQC_PORT_OPT_MAX;
u8 speed, active_idx, pending_idx; bool active_valid, pending_valid;
speed = options[active_idx].max_lane_speed; /* If we don't get speed for this lane, it's unoccupied */ if (speed > ICE_AQC_PORT_OPT_MAX_LANE_40G) continue;
if (hw->pf_id == lport) { if (hw->mac_type == ICE_MAC_GENERIC_3K_E825 &&
ice_is_dual(hw) && !ice_is_primary(hw))
lane += ICE_PORTS_PER_QUAD;
kfree(options); return lane;
}
lport++;
}
/* PHY lane not found */
err = -ENXIO;
err:
kfree(options); return err;
}
/** * ice_aq_sff_eeprom * @hw: pointer to the HW struct * @lport: bits [7:0] = logical port, bit [8] = logical port valid * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. * @page: QSFP page * @set_page: set or ignore the page * @data: pointer to data buffer to be read/written to the I2C device. * @length: 1-16 for read, 1 for write. * @write: 0 read, 1 for write. * @cd: pointer to command details structure or NULL * * Read/Write SFF EEPROM (0x06EE)
*/ int
ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, bool write, struct ice_sq_cd *cd)
{ struct ice_aqc_sff_eeprom *cmd; struct libie_aq_desc desc;
u16 i2c_bus_addr; int status;
/** * ice_aq_get_rss_lut * @hw: pointer to the hardware structure * @get_params: RSS LUT parameters used to specify which RSS LUT to get * * get the RSS lookup table, PF or VSI type
*/ int
ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params)
{ return __ice_aq_get_set_rss_lut(hw, get_params, false);
}
/** * ice_aq_set_rss_lut * @hw: pointer to the hardware structure * @set_params: RSS LUT parameters used to specify how to set the RSS LUT * * set the RSS lookup table, PF or VSI type
*/ int
ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params)
{ return __ice_aq_get_set_rss_lut(hw, set_params, true);
}
/** * __ice_aq_get_set_rss_key * @hw: pointer to the HW struct * @vsi_id: VSI FW index * @key: pointer to key info struct * @set: set true to set the key, false to get the key * * get (0x0B04) or set (0x0B02) the RSS key per VSI
*/ staticint
__ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, struct ice_aqc_get_set_rss_keys *key, bool set)
{ struct ice_aqc_get_set_rss_key *desc_params;
u16 key_size = sizeof(*key); struct libie_aq_desc desc;
/** * ice_aq_get_rss_key * @hw: pointer to the HW struct * @vsi_handle: software VSI handle * @key: pointer to key info struct * * get the RSS key per VSI
*/ int
ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, struct ice_aqc_get_set_rss_keys *key)
{ if (!ice_is_vsi_valid(hw, vsi_handle) || !key) return -EINVAL;
/** * ice_aq_set_rss_key * @hw: pointer to the HW struct * @vsi_handle: software VSI handle * @keys: pointer to key info struct * * set the RSS key per VSI
*/ int
ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, struct ice_aqc_get_set_rss_keys *keys)
{ if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) return -EINVAL;
/** * ice_aq_add_lan_txq * @hw: pointer to the hardware structure * @num_qgrps: Number of added queue groups * @qg_list: list of queue groups to be added * @buf_size: size of buffer for indirect command * @cd: pointer to command details structure or NULL * * Add Tx LAN queue (0x0C30) * * NOTE: * Prior to calling add Tx LAN queue: * Initialize the following as part of the Tx queue context: * Completion queue ID if the queue uses Completion queue, Quanta profile, * Cache profile and Packet shaper profile. * * After add Tx LAN queue AQ command is completed: * Interrupts should be associated with specific queues, * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue * flow.
*/ staticint
ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, struct ice_sq_cd *cd)
{ struct ice_aqc_add_tx_qgrp *list; struct ice_aqc_add_txqs *cmd; struct libie_aq_desc desc;
u16 i, sum_size = 0;
if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) return -EINVAL;
for (i = 0, list = qg_list; i < num_qgrps; i++) {
sum_size += struct_size(list, txqs, list->num_txqs);
list = (struct ice_aqc_add_tx_qgrp *)(list->txqs +
list->num_txqs);
}
/** * ice_aq_dis_lan_txq * @hw: pointer to the hardware structure * @num_qgrps: number of groups in the list * @qg_list: the list of groups to disable * @buf_size: the total size of the qg_list buffer in bytes * @rst_src: if called due to reset, specifies the reset source * @vmvf_num: the relative VM or VF number that is undergoing the reset * @cd: pointer to command details structure or NULL * * Disable LAN Tx queue (0x0C31)
*/ staticint
ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, enum ice_disq_rst_src rst_src, u16 vmvf_num, struct ice_sq_cd *cd)
{ struct ice_aqc_dis_txq_item *item; struct ice_aqc_dis_txqs *cmd; struct libie_aq_desc desc;
u16 vmvf_and_timeout;
u16 i, sz = 0; int status;
/* flush pipe on time out */
cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; /* If no queue group info, we are in a reset flow. Issue the AQ */ if (!qg_list) goto do_aq;
/* set RD bit to indicate that command buffer is provided by the driver * and it needs to be read by the firmware
*/
desc.flags |= cpu_to_le16(LIBIE_AQ_FLAG_RD);
for (i = 0, item = qg_list; i < num_qgrps; i++) {
u16 item_size = struct_size(item, q_id, item->num_qs);
/* If the num of queues is even, add 2 bytes of padding */ if ((item->num_qs % 2) == 0)
item_size += 2;
/** * ice_aq_cfg_lan_txq * @hw: pointer to the hardware structure * @buf: buffer for command * @buf_size: size of buffer in bytes * @num_qs: number of queues being configured * @oldport: origination lport * @newport: destination lport * @cd: pointer to command details structure or NULL * * Move/Configure LAN Tx queue (0x0C32) * * There is a better AQ command to use for moving nodes, so only coding * this one for configuring the node.
*/ int
ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf,
u16 buf_size, u16 num_qs, u8 oldport, u8 newport, struct ice_sq_cd *cd)
{ struct ice_aqc_cfg_txqs *cmd; struct libie_aq_desc desc; int status;
/** * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC * @hw: pointer to the HW struct * @vsi_handle: software VSI handle * @tc: TC number * @q_handle: software queue handle
*/ struct ice_q_ctx *
ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
{ struct ice_vsi_ctx *vsi; struct ice_q_ctx *q_ctx;
vsi = ice_get_vsi_ctx(hw, vsi_handle); if (!vsi) return NULL; if (q_handle >= vsi->num_lan_q_entries[tc]) return NULL; if (!vsi->lan_q_ctx[tc]) return NULL;
q_ctx = vsi->lan_q_ctx[tc]; return &q_ctx[q_handle];
}
/** * ice_ena_vsi_txq * @pi: port information structure * @vsi_handle: software VSI handle * @tc: TC number * @q_handle: software queue handle * @num_qgrps: Number of added queue groups * @buf: list of queue groups to be added * @buf_size: size of buffer for indirect command * @cd: pointer to command details structure or NULL * * This function adds one LAN queue
*/ int
ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, struct ice_sq_cd *cd)
{ struct ice_aqc_txsched_elem_data node = { 0 }; struct ice_sched_node *parent; struct ice_q_ctx *q_ctx; struct ice_hw *hw; int status;
if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) return -EIO;
if (num_qgrps > 1 || buf->num_txqs > 1) return -ENOSPC;
hw = pi->hw;
if (!ice_is_vsi_valid(hw, vsi_handle)) return -EINVAL;
/* find a parent node */
parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
ICE_SCHED_NODE_OWNER_LAN); if (!parent) {
status = -EINVAL; goto ena_txq_exit;
}
buf->parent_teid = parent->info.node_teid;
node.parent_teid = parent->info.node_teid; /* Mark that the values in the "generic" section as valid. The default * value in the "generic" section is zero. This means that : * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. * - 0 priority among siblings, indicated by Bit 1-3. * - WFQ, indicated by Bit 4. * - 0 Adjustment value is used in PSM credit update flow, indicated by * Bit 5-6. * - Bit 7 is reserved. * Without setting the generic section as valid in valid_sections, the * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
*/
buf->txqs[0].info.valid_sections =
ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |
ICE_AQC_ELEM_VALID_EIR;
buf->txqs[0].info.generic = 0;
buf->txqs[0].info.cir_bw.bw_profile_idx =
cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
buf->txqs[0].info.cir_bw.bw_alloc =
cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
buf->txqs[0].info.eir_bw.bw_profile_idx =
cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
buf->txqs[0].info.eir_bw.bw_alloc =
cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
/* add the LAN queue */
status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); if (status) {
ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
le16_to_cpu(buf->txqs[0].txq_id),
hw->adminq.sq_last_status); goto ena_txq_exit;
}
/* add a leaf node into scheduler tree queue layer */
status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); if (!status)
status = ice_sched_replay_q_bw(pi, q_ctx);
/** * ice_dis_vsi_txq * @pi: port information structure * @vsi_handle: software VSI handle * @tc: TC number * @num_queues: number of queues * @q_handles: pointer to software queue handle array * @q_ids: pointer to the q_id array * @q_teids: pointer to queue node teids * @rst_src: if called due to reset, specifies the reset source * @vmvf_num: the relative VM or VF number that is undergoing the reset * @cd: pointer to command details structure or NULL * * This function removes queues and their corresponding nodes in SW DB
*/ int
ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
u16 *q_handles, u16 *q_ids, u32 *q_teids, enum ice_disq_rst_src rst_src, u16 vmvf_num, struct ice_sq_cd *cd)
{
DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1);
u16 i, buf_size = __struct_size(qg_list); struct ice_q_ctx *q_ctx; int status = -ENOENT; struct ice_hw *hw;
if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) return -EIO;
hw = pi->hw;
if (!num_queues) { /* if queue is disabled already yet the disable queue command * has to be sent to complete the VF reset, then call * ice_aq_dis_lan_txq without any queue information
*/ if (rst_src) return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src,
vmvf_num, NULL); return -EIO;
}
mutex_lock(&pi->sched_lock);
for (i = 0; i < num_queues; i++) { struct ice_sched_node *node;
/** * ice_cfg_vsi_qs - configure the new/existing VSI queues * @pi: port information structure * @vsi_handle: software VSI handle * @tc_bitmap: TC bitmap * @maxqs: max queues array per TC * @owner: LAN or RDMA * * This function adds/updates the VSI queues per TC.
*/ staticint
ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
u16 *maxqs, u8 owner)
{ int status = 0;
u8 i;
if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) return -EIO;
if (!ice_is_vsi_valid(pi->hw, vsi_handle)) return -EINVAL;
mutex_lock(&pi->sched_lock);
ice_for_each_traffic_class(i) { /* configuration is possible only if TC node is present */ if (!ice_sched_get_tc_node(pi, i)) continue;
status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
ice_is_tc_ena(tc_bitmap, i)); if (status) break;
}
mutex_unlock(&pi->sched_lock); return status;
}
/** * ice_cfg_vsi_lan - configure VSI LAN queues * @pi: port information structure * @vsi_handle: software VSI handle * @tc_bitmap: TC bitmap * @max_lanqs: max LAN queues array per TC * * This function adds/updates the VSI LAN queues per TC.
*/ int
ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
u16 *max_lanqs)
{ return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
ICE_SCHED_NODE_OWNER_LAN);
}
/** * ice_cfg_vsi_rdma - configure the VSI RDMA queues * @pi: port information structure * @vsi_handle: software VSI handle * @tc_bitmap: TC bitmap * @max_rdmaqs: max RDMA queues array per TC * * This function adds/updates the VSI RDMA queues per TC.
*/ int
ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
u16 *max_rdmaqs)
{ return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs,
ICE_SCHED_NODE_OWNER_RDMA);
}
/** * ice_ena_vsi_rdma_qset * @pi: port information structure * @vsi_handle: software VSI handle * @tc: TC number * @rdma_qset: pointer to RDMA Qset * @num_qsets: number of RDMA Qsets * @qset_teid: pointer to Qset node TEIDs * * This function adds RDMA Qset
*/ int
ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
u16 *rdma_qset, u16 num_qsets, u32 *qset_teid)
{ struct ice_aqc_txsched_elem_data node = { 0 }; struct ice_aqc_add_rdma_qset_data *buf; struct ice_sched_node *parent; struct ice_hw *hw;
u16 i, buf_size; int ret;
status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size,
ICE_NO_RESET, 0, NULL); if (status) break;
ice_free_sched_node(pi, node);
}
mutex_unlock(&pi->sched_lock); return status;
}
/** * ice_aq_get_cgu_input_pin_measure - get input pin signal measurements * @hw: pointer to the HW struct * @dpll_idx: index of dpll to be measured * @meas: array to be filled with results * @meas_num: max number of results array can hold * * Get CGU measurements (0x0C59) of phase and frequency offsets for input * pins on given dpll. * * Return: 0 on success or negative value on failure.
*/ int ice_aq_get_cgu_input_pin_measure(struct ice_hw *hw, u8 dpll_idx, struct ice_cgu_input_measure *meas,
u16 meas_num)
{ struct ice_aqc_get_cgu_input_measure *cmd; struct libie_aq_desc desc;
ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); if (!ret) { if (flags)
*flags = cmd->flags; if (src_sel)
*src_sel = cmd->src_sel; if (freq)
*freq = le32_to_cpu(cmd->freq); if (src_freq)
*src_freq = le32_to_cpu(cmd->src_freq);
}
return ret;
}
/** * ice_aq_get_cgu_dpll_status - get dpll status * @hw: pointer to the HW struct * @dpll_num: DPLL index * @ref_state: Reference clock state * @config: current DPLL config * @dpll_state: current DPLL state * @phase_offset: Phase offset in ns * @eec_mode: EEC_mode * * Get CGU DPLL status (0x0C66) * Return: 0 on success or negative value on failure.
*/ int
ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state,
u8 *dpll_state, u8 *config, s64 *phase_offset,
u8 *eec_mode)
{ struct ice_aqc_get_cgu_dpll_status *cmd; struct libie_aq_desc desc; int status;
status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); if (!status)
*ref_prio = cmd->ref_priority;
return status;
}
/** * ice_aq_get_cgu_info - get cgu info * @hw: pointer to the HW struct * @cgu_id: CGU ID * @cgu_cfg_ver: CGU config version * @cgu_fw_ver: CGU firmware version * * Get CGU info (0x0C6A) * Return: 0 on success or negative value on failure.
*/ int
ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver,
u32 *cgu_fw_ver)
{ struct ice_aqc_get_cgu_info *cmd; struct libie_aq_desc desc; int status;
status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); if (!status) {
*cgu_id = le32_to_cpu(cmd->cgu_id);
*cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver);
*cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver);
}
return status;
}
/** * ice_aq_set_phy_rec_clk_out - set RCLK phy out * @hw: pointer to the HW struct * @phy_output: PHY reference clock output pin * @enable: GPIO state to be applied * @freq: PHY output frequency * * Set phy recovered clock as reference (0x0630) * Return: 0 on success or negative value on failure.
*/ int
ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable,
u32 *freq)
{ struct ice_aqc_set_phy_rec_clk_out *cmd; struct libie_aq_desc desc; int status;
status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); if (!status)
*freq = le32_to_cpu(cmd->freq);
return status;
}
/** * ice_aq_get_phy_rec_clk_out - get phy recovered signal info * @hw: pointer to the HW struct * @phy_output: PHY reference clock output pin * @port_num: Port number * @flags: PHY flags * @node_handle: PHY output frequency * * Get PHY recovered clock output info (0x0631) * Return: 0 on success or negative value on failure.
*/ int
ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num,
u8 *flags, u16 *node_handle)
{ struct ice_aqc_get_phy_rec_clk_out *cmd; struct libie_aq_desc desc; int status;
status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); if (!status) {
*phy_output = cmd->phy_output; if (port_num)
*port_num = cmd->port_num; if (flags)
*flags = cmd->flags; if (node_handle)
*node_handle = le16_to_cpu(cmd->node_handle);
}
return status;
}
/** * ice_aq_get_sensor_reading * @hw: pointer to the HW struct * @data: pointer to data to be read from the sensor * * Get sensor reading (0x0632)
*/ int ice_aq_get_sensor_reading(struct ice_hw *hw, struct ice_aqc_get_sensor_reading_resp *data)
{ struct ice_aqc_get_sensor_reading *cmd; struct libie_aq_desc desc; int status;
status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); if (!status)
memcpy(data, &desc.params.raw, sizeof(*data));
return status;
}
/** * ice_replay_pre_init - replay pre initialization * @hw: pointer to the HW struct * * Initializes required config data for VSI, FD, ACL, and RSS before replay.
*/ staticint ice_replay_pre_init(struct ice_hw *hw)
{ struct ice_switch_info *sw = hw->switch_info;
u8 i;
/* Delete old entries from replay filter list head if there is any */
ice_rm_all_sw_replay_rule_info(hw); /* In start of replay, move entries into replay_rules list, it * will allow adding rules entries back to filt_rules list, * which is operational list.
*/ for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
list_replace_init(&sw->recp_list[i].filt_rules,
&sw->recp_list[i].filt_replay_rules);
ice_sched_replay_agg_vsi_preinit(hw);
return 0;
}
/** * ice_replay_vsi - replay VSI configuration * @hw: pointer to the HW struct * @vsi_handle: driver VSI handle * * Restore all VSI configuration after reset. It is required to call this * function with main VSI first.
*/ int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
{ int status;
if (!ice_is_vsi_valid(hw, vsi_handle)) return -EINVAL;
/* Replay pre-initialization if there is any */ if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
status = ice_replay_pre_init(hw); if (status) return status;
} /* Replay per VSI all RSS configurations */
status = ice_replay_rss_cfg(hw, vsi_handle); if (status) return status; /* Replay per VSI all filters */
status = ice_replay_vsi_all_fltr(hw, vsi_handle); if (!status)
status = ice_replay_vsi_agg(hw, vsi_handle); return status;
}
/** * ice_replay_post - post replay configuration cleanup * @hw: pointer to the HW struct * * Post replay cleanup.
*/ void ice_replay_post(struct ice_hw *hw)
{ /* Delete old entries from replay filter list head */
ice_rm_all_sw_replay_rule_info(hw);
ice_sched_replay_agg(hw);
}
/** * ice_stat_update40 - read 40 bit stat from the chip and update stat values * @hw: ptr to the hardware info * @reg: offset of 64 bit HW register to read from * @prev_stat_loaded: bool to specify if previous stats are loaded * @prev_stat: ptr to previous loaded stat value * @cur_stat: ptr to current stat value
*/ void
ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
u64 *prev_stat, u64 *cur_stat)
{
u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
/* device stats are not reset at PFR, they likely will not be zeroed * when the driver starts. Thus, save the value from the first read * without adding to the statistic value so that we report stats which * count up from zero.
*/ if (!prev_stat_loaded) {
*prev_stat = new_data; return;
}
/* Calculate the difference between the new and old values, and then * add it to the software stat value.
*/ if (new_data >= *prev_stat)
*cur_stat += new_data - *prev_stat; else /* to manage the potential roll-over */
*cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
/* Update the previously stored value to prepare for next read */
*prev_stat = new_data;
}
/** * ice_stat_update32 - read 32 bit stat from the chip and update stat values * @hw: ptr to the hardware info * @reg: offset of HW register to read from * @prev_stat_loaded: bool to specify if previous stats are loaded * @prev_stat: ptr to previous loaded stat value * @cur_stat: ptr to current stat value
*/ void
ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
u64 *prev_stat, u64 *cur_stat)
{
u32 new_data;
new_data = rd32(hw, reg);
/* device stats are not reset at PFR, they likely will not be zeroed * when the driver starts. Thus, save the value from the first read * without adding to the statistic value so that we report stats which * count up from zero.
*/ if (!prev_stat_loaded) {
*prev_stat = new_data; return;
}
/* Calculate the difference between the new and old values, and then * add it to the software stat value.
*/ if (new_data >= *prev_stat)
*cur_stat += new_data - *prev_stat; else /* to manage the potential roll-over */
*cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
/* Update the previously stored value to prepare for next read */
*prev_stat = new_data;
}
/** * ice_sched_query_elem - query element information from HW * @hw: pointer to the HW struct * @node_teid: node TEID to be queried * @buf: buffer to element information * * This function queries HW element information
*/ int
ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, struct ice_aqc_txsched_elem_data *buf)
{
u16 buf_size, num_elem_ret = 0; int status;
/** * ice_get_pca9575_handle - find and return the PCA9575 controller * @hw: pointer to the hw struct * @pca9575_handle: GPIO controller's handle * * Find and return the GPIO controller's handle in the netlist. * When found - the value will be cached in the hw structure and following calls * will return cached value. * * Return: 0 on success, -ENXIO when there's no PCA9575 present.
*/ int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle)
{ struct ice_aqc_get_link_topo *cmd; struct libie_aq_desc desc; int err;
u8 idx;
/* If handle was read previously return cached value */ if (hw->io_expander_handle) {
*pca9575_handle = hw->io_expander_handle; return 0;
}
/* Check if the SW IO expander controlling SMA exists in the netlist. */ if (hw->device_id == ICE_DEV_ID_E810C_SFP)
idx = SW_PCA9575_SFP_TOPO_IDX; elseif (hw->device_id == ICE_DEV_ID_E810C_QSFP)
idx = SW_PCA9575_QSFP_TOPO_IDX; else return -ENXIO;
/* If handle was not detected read it from the netlist */
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
cmd = libie_aq_raw(&desc);
cmd->addr.topo_params.node_type_ctx =
ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL;
cmd->addr.topo_params.index = idx;
/* Verify if we found the right IO expander type */ if (cmd->node_part_num != ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) return -ENXIO;
/* If present save the handle and return it */
hw->io_expander_handle =
le16_to_cpu(cmd->addr.handle);
*pca9575_handle = hw->io_expander_handle;
return 0;
}
/** * ice_read_pca9575_reg - read the register from the PCA9575 controller * @hw: pointer to the hw struct * @offset: GPIO controller register offset * @data: pointer to data to be read from the GPIO controller * * Return: 0 on success, negative error code otherwise.
*/ int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data)
{ struct ice_aqc_link_topo_addr link_topo;
__le16 addr;
u16 handle; int err;
memset(&link_topo, 0, sizeof(link_topo));
err = ice_get_pca9575_handle(hw, &handle); if (err) return err;
/** * ice_aq_set_gpio * @hw: pointer to the hw struct * @gpio_ctrl_handle: GPIO controller node handle * @pin_idx: IO Number of the GPIO that needs to be set * @value: SW provide IO value to set in the LSB * @cd: pointer to command details structure or NULL * * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology
*/ int
ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, struct ice_sq_cd *cd)
{ struct libie_aq_desc desc; struct ice_aqc_gpio *cmd;
/** * ice_aq_get_gpio * @hw: pointer to the hw struct * @gpio_ctrl_handle: GPIO controller node handle * @pin_idx: IO Number of the GPIO that needs to be set * @value: IO value read * @cd: pointer to command details structure or NULL * * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of * the topology
*/ int
ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool *value, struct ice_sq_cd *cd)
{ struct libie_aq_desc desc; struct ice_aqc_gpio *cmd; int status;
status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); if (status) return status;
*value = !!cmd->gpio_val; return 0;
}
/** * ice_is_fw_api_min_ver * @hw: pointer to the hardware structure * @maj: major version * @min: minor version * @patch: patch version * * Checks if the firmware API is minimum version
*/ staticbool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch)
{ if (hw->api_maj_ver == maj) { if (hw->api_min_ver > min) returntrue; if (hw->api_min_ver == min && hw->api_patch >= patch) returntrue;
} elseif (hw->api_maj_ver > maj) { returntrue;
}
returnfalse;
}
/** * ice_fw_supports_link_override * @hw: pointer to the hardware structure * * Checks if the firmware supports link override
*/ bool ice_fw_supports_link_override(struct ice_hw *hw)
{ return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ,
ICE_FW_API_LINK_OVERRIDE_MIN,
ICE_FW_API_LINK_OVERRIDE_PATCH);
}
/** * ice_get_link_default_override * @ldo: pointer to the link default override struct * @pi: pointer to the port info struct * * Gets the link default override for a port
*/ int
ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, struct ice_port_info *pi)
{
u16 i, tlv, tlv_len, tlv_start, buf, offset; struct ice_hw *hw = pi->hw; int status;
status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,
ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); if (status) {
ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); return status;
}
/* Each port has its own config; calculate for our port */
tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +
ICE_SR_PFA_LINK_OVERRIDE_OFFSET;
/* link options first */
status = ice_read_sr_word(hw, tlv_start, &buf); if (status) {
ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); return status;
}
ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf);
ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
ICE_LINK_OVERRIDE_PHY_CFG_S;
/* link PHY config */
offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;
status = ice_read_sr_word(hw, offset, &buf); if (status) {
ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); return status;
}
ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
/* PHY types low */
offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
status = ice_read_sr_word(hw, (offset + i), &buf); if (status) {
ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); return status;
} /* shift 16 bits at a time to fill 64 bits */
ldo->phy_type_low |= ((u64)buf << (i * 16));
}
/* PHY types high */
offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +
ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
status = ice_read_sr_word(hw, (offset + i), &buf); if (status) {
ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); return status;
} /* shift 16 bits at a time to fill 64 bits */
ldo->phy_type_high |= ((u64)buf << (i * 16));
}
return status;
}
/** * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled * @caps: get PHY capability data
*/ bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps)
{ if (caps->caps & ICE_AQC_PHY_AN_MODE ||
caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 |
ICE_AQC_PHY_AN_EN_CLAUSE73 |
ICE_AQC_PHY_AN_EN_CLAUSE37)) returntrue;
returnfalse;
}
/** * ice_is_fw_health_report_supported - checks if firmware supports health events * @hw: pointer to the hardware structure * * Return: true if firmware supports health status reports, * false otherwise
*/ bool ice_is_fw_health_report_supported(struct ice_hw *hw)
{ return ice_is_fw_api_min_ver(hw, ICE_FW_API_HEALTH_REPORT_MAJ,
ICE_FW_API_HEALTH_REPORT_MIN,
ICE_FW_API_HEALTH_REPORT_PATCH);
}
/** * ice_aq_set_health_status_cfg - Configure FW health events * @hw: pointer to the HW struct * @event_source: type of diagnostic events to enable * * Configure the health status event types that the firmware will send to this * PF. The supported event types are: PF-specific, all PFs, and global. * * Return: 0 on success, negative error code otherwise.
*/ int ice_aq_set_health_status_cfg(struct ice_hw *hw, u8 event_source)
{ struct ice_aqc_set_health_status_cfg *cmd; struct libie_aq_desc desc;
/** * ice_aq_set_lldp_mib - Set the LLDP MIB * @hw: pointer to the HW struct * @mib_type: Local, Remote or both Local and Remote MIBs * @buf: pointer to the caller-supplied buffer to store the MIB block * @buf_size: size of the buffer (in bytes) * @cd: pointer to command details structure or NULL * * Set the LLDP MIB. (0x0A08)
*/ int
ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, struct ice_sq_cd *cd)
{ struct ice_aqc_lldp_set_local_mib *cmd; struct libie_aq_desc desc;
/** * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter * @hw: pointer to HW struct * @vsi: VSI to add the filter to * @add: boolean for if adding or removing a filter * * Return: 0 on success, -EOPNOTSUPP if the operation cannot be performed * with this HW or VSI, otherwise an error corresponding to * the AQ transaction result.
*/ int ice_lldp_fltr_add_remove(struct ice_hw *hw, struct ice_vsi *vsi, bool add)
{ struct ice_aqc_lldp_filter_ctrl *cmd; struct libie_aq_desc desc;
if (vsi->type != ICE_VSI_PF || !ice_fw_supports_lldp_fltr_ctrl(hw)) return -EOPNOTSUPP;
/** * ice_fw_supports_report_dflt_cfg * @hw: pointer to the hardware structure * * Checks if the firmware supports report default configuration
*/ bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw)
{ return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ,
ICE_FW_API_REPORT_DFLT_CFG_MIN,
ICE_FW_API_REPORT_DFLT_CFG_PATCH);
}
/* each of the indexes into the following array match the speed of a return * value from the list of AQ returned speeds like the range: * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this * array. The array is defined as 15 elements long because the link_speed * returned by the firmware is a 16 bit * value, but is indexed * by [fls(speed) - 1]
*/ staticconst u32 ice_aq_to_link_speed[] = {
SPEED_10, /* BIT(0) */
SPEED_100,
SPEED_1000,
SPEED_2500,
SPEED_5000,
SPEED_10000,
SPEED_20000,
SPEED_25000,
SPEED_40000,
SPEED_50000,
SPEED_100000, /* BIT(10) */
SPEED_200000,
};
/** * ice_get_link_speed - get integer speed from table * @index: array index from fls(aq speed) - 1 * * Returns: u32 value containing integer speed
*/
u32 ice_get_link_speed(u16 index)
{ if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) return 0;
return ice_aq_to_link_speed[index];
}
/** * ice_read_cgu_reg - Read a CGU register * @hw: Pointer to the HW struct * @addr: Register address to read * @val: Storage for register value read * * Read the contents of a register of the Clock Generation Unit. Only * applicable to E82X devices. * * Return: 0 on success, other error codes when failed to read from CGU.
*/ int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val)
{ struct ice_sbq_msg_input cgu_msg = {
.opcode = ice_sbq_msg_rd,
.dest_dev = ice_sbq_dev_cgu,
.msg_addr_low = addr
}; int err;
/** * ice_write_cgu_reg - Write a CGU register * @hw: Pointer to the HW struct * @addr: Register address to write * @val: Value to write into the register * * Write the specified value to a register of the Clock Generation Unit. Only * applicable to E82X devices. * * Return: 0 on success, other error codes when failed to write to CGU.
*/ int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val)
{ struct ice_sbq_msg_input cgu_msg = {
.opcode = ice_sbq_msg_wr,
.dest_dev = ice_sbq_dev_cgu,
.msg_addr_low = addr,
.data = val
}; int err;
err = ice_sbq_rw_reg(hw, &cgu_msg, LIBIE_AQ_FLAG_RD); if (err)
ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n",
addr, err);
return err;
}
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