/* B2_TST_CTRL1 8 bit Test Control Register 1 */ enum {
TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
};
/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ enum {
CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */ /* Bit 3.. 2: reserved */
CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
};
/* B2_CHIP_ID 8 bit Chip Identification Number */ enum {
CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
/* B2_TI_TEST 8 Bit Timer Test */ /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ enum {
TIM_T_ON = 1<<2, /* Test mode on */
TIM_T_OFF = 1<<1, /* Test mode off */
TIM_T_STEP = 1<<0, /* Test step */
};
/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
#define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
/* TXA_CTRL 8 bit Tx Arbiter Control Register */ enum {
TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
TXA_START_RC = 1<<3, /* Start sync Rate Control */
TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
};
/* * Bank 4 - 5
*/ /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ enum {
TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
};
/* Queue Register Offsets, use Q_ADDR() to access */ enum {
B8_Q_REGS = 0x0400, /* base of Queue registers */
Q_D = 0x00, /* 8*32 bit Current Descriptor */
Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
Q_BC = 0x30, /* 32 bit Current Byte Counter */
Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
Q_F = 0x38, /* 32 bit Flag Register */
Q_T1 = 0x3c, /* 32 bit Test Register 1 */
Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
Q_T2 = 0x40, /* 32 bit Test Register 2 */
Q_T3 = 0x44, /* 32 bit Test Register 3 */
/* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */ enum {
RX_MFF_EA = 0x0c00,/* 32 bit Receive MAC FIFO End Address */
RX_MFF_WP = 0x0c04,/* 32 bit Receive MAC FIFO Write Pointer */
RX_MFF_RP = 0x0c0c,/* 32 bit Receive MAC FIFO Read Pointer */
RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */
RX_MFF_LEV = 0x0c14,/* 32 bit Receive MAC FIFO Level */
RX_MFF_CTRL1 = 0x0c18,/* 16 bit Receive MAC FIFO Control Reg 1*/
RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */
RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */
RX_MFF_CTRL2 = 0x0c1c,/* 8 bit Receive MAC FIFO Control Reg 2*/
RX_MFF_TST1 = 0x0c1d,/* 8 bit Receive MAC FIFO Test Reg 1 */
RX_MFF_TST2 = 0x0c1e,/* 8 bit Receive MAC FIFO Test Reg 2 */
RX_LED_INI = 0x0c20,/* 32 bit Receive LED Cnt Init Value */
RX_LED_VAL = 0x0c24,/* 32 bit Receive LED Cnt Current Value */
RX_LED_CTRL = 0x0c28,/* 8 bit Receive LED Cnt Control Reg */
RX_LED_TST = 0x0c29,/* 8 bit Receive LED Cnt Test Register */
LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
};
/* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */ /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */ enum {
MFF_WSP_T_ON = 1<<6, /* Tx: Write Shadow Ptr TestOn */
MFF_WSP_T_OFF = 1<<5, /* Tx: Write Shadow Ptr TstOff */
MFF_WSP_INC = 1<<4, /* Tx: Write Shadow Ptr Increment */
MFF_PC_DEC = 1<<3, /* Packet Counter Decrement */
MFF_PC_T_ON = 1<<2, /* Packet Counter Test On */
MFF_PC_T_OFF = 1<<1, /* Packet Counter Test Off */
MFF_PC_INC = 1<<0, /* Packet Counter Increment */
};
/* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */ /* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */ enum {
MFF_WP_T_ON = 1<<6, /* Write Pointer Test On */
MFF_WP_T_OFF = 1<<5, /* Write Pointer Test Off */
MFF_WP_INC = 1<<4, /* Write Pointer Increm */
MFF_RP_T_ON = 1<<2, /* Read Pointer Test On */
MFF_RP_T_OFF = 1<<1, /* Read Pointer Test Off */
MFF_RP_DEC = 1<<0, /* Read Pointer Decrement */
};
/* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */ /* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */ enum {
MFF_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
MFF_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
MFF_RST_CLR = 1<<1, /* Clear MAC FIFO Reset */
MFF_RST_SET = 1<<0, /* Set MAC FIFO Reset */
};
/* Link LED Counter Registers (GENESIS only) */
/* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */ /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */ /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */ enum {
LED_START = 1<<2, /* Start Timer */
LED_STOP = 1<<1, /* Stop Timer */
LED_STATE = 1<<0, /* Rx/Tx: LED State, 1=LED on */
};
/* RX_LED_TST 8 bit Receive LED Cnt Test Register */ /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */ /* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */ enum {
LED_T_ON = 1<<2, /* LED Counter Test mode On */
LED_T_OFF = 1<<1, /* LED Counter Test mode Off */
LED_T_STEP = 1<<0, /* LED Counter Step */
};
/* LNK_LED_REG 8 bit Link LED Register */ enum {
LED_BLK_ON = 1<<5, /* Link LED Blinking On */
LED_BLK_OFF = 1<<4, /* Link LED Blinking Off */
LED_SYNC_ON = 1<<3, /* Use Sync Wire to switch LED */
LED_SYNC_OFF = 1<<2, /* Disable Sync Wire Input */
LED_REG_ON = 1<<1, /* switch LED on */
LED_REG_OFF = 1<<0, /* switch LED off */
};
/* Receive GMAC FIFO (YUKON) */ enum {
RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
};
/* TXA_TEST 8 bit Tx Arbiter Test Register */ enum {
TXA_INT_T_ON = 1<<5, /* Tx Arb Interval Timer Test On */
TXA_INT_T_OFF = 1<<4, /* Tx Arb Interval Timer Test Off */
TXA_INT_T_STEP = 1<<3, /* Tx Arb Interval Timer Step */
TXA_LIM_T_ON = 1<<2, /* Tx Arb Limit Timer Test On */
TXA_LIM_T_OFF = 1<<1, /* Tx Arb Limit Timer Test Off */
TXA_LIM_T_STEP = 1<<0, /* Tx Arb Limit Timer Step */
};
/* TXA_STAT 8 bit Tx Arbiter Status Register */ enum {
TXA_PRIO_XS = 1<<0, /* sync queue has prio to send */
};
/* Q_BC 32 bit Current Byte Counter */
/* BMU Control Status Registers */ /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */ /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */ /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */ /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */ /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */ /* Q_CSR 32 bit BMU Control/Status Register */
enum {
CSR_SV_IDLE = 1<<24, /* BMU SM Idle */
CSR_DESC_CLR = 1<<21, /* Clear Reset for Descr */
CSR_DESC_SET = 1<<20, /* Set Reset for Descr */
CSR_FIFO_CLR = 1<<19, /* Clear Reset for FIFO */
CSR_FIFO_SET = 1<<18, /* Set Reset for FIFO */
CSR_HPI_RUN = 1<<17, /* Release HPI SM */
CSR_HPI_RST = 1<<16, /* Reset HPI SM to Idle */
CSR_SV_RUN = 1<<15, /* Release Supervisor SM */
CSR_SV_RST = 1<<14, /* Reset Supervisor SM */
CSR_DREAD_RUN = 1<<13, /* Release Descr Read SM */
CSR_DREAD_RST = 1<<12, /* Reset Descr Read SM */
CSR_DWRITE_RUN = 1<<11, /* Release Descr Write SM */
CSR_DWRITE_RST = 1<<10, /* Reset Descr Write SM */
CSR_TRANS_RUN = 1<<9, /* Release Transfer SM */
CSR_TRANS_RST = 1<<8, /* Reset Transfer SM */
CSR_ENA_POL = 1<<7, /* Enable Descr Polling */
CSR_DIS_POL = 1<<6, /* Disable Descr Polling */
CSR_STOP = 1<<5, /* Stop Rx/Tx Queue */
CSR_START = 1<<4, /* Start Rx/Tx Queue */
CSR_IRQ_CL_P = 1<<3, /* (Rx) Clear Parity IRQ */
CSR_IRQ_CL_B = 1<<2, /* Clear EOB IRQ */
CSR_IRQ_CL_F = 1<<1, /* Clear EOF IRQ */
CSR_IRQ_CL_C = 1<<0, /* Clear ERR IRQ */
};
/* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */ enum {
TX_MFF_EA = 0x0d00,/* 32 bit Transmit MAC FIFO End Address */
TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */
TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */
TX_MFF_RP = 0x0d0c,/* 32 bit Transmit MAC FIFO RD Pointer */
TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */
TX_MFF_LEV = 0x0d14,/* 32 bit Transmit MAC FIFO Level */
TX_MFF_CTRL1 = 0x0d18,/* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
TX_MFF_WAF = 0x0d1a,/* 8 bit Transmit MAC Wait after flush */
TX_MFF_CTRL2 = 0x0d1c,/* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
TX_MFF_TST1 = 0x0d1d,/* 8 bit Transmit MAC FIFO Test Reg 1 */
TX_MFF_TST2 = 0x0d1e,/* 8 bit Transmit MAC FIFO Test Reg 2 */
TX_LED_INI = 0x0d20,/* 32 bit Transmit LED Cnt Init Value */
TX_LED_VAL = 0x0d24,/* 32 bit Transmit LED Cnt Current Val */
TX_LED_CTRL = 0x0d28,/* 8 bit Transmit LED Cnt Control Reg */
TX_LED_TST = 0x0d29,/* 8 bit Transmit LED Cnt Test Reg */
};
/* Counter and Timer constants, for a host clock of 62.5 MHz */ #define SK_XMIT_DUR 0x002faf08UL /* 50 ms */ #define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
#define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
#define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */ /* 215 ms at 78.12 MHz */
#define SK_FACT_62 100 /* is given in percent */ #define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */ #define SK_FACT_78 125 /* on YUKON: 78.12 MHz */
/* Transmit GMAC FIFO (YUKON only) */ enum {
TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
/* Descriptor Poll Timer Registers */
B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
/* Time Stamp Timer Registers (YUKON only) */
GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
};
/* GMAC and GPHY Control Registers (YUKON only) */ enum {
GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
/* Wake-up Frame Pattern Match Control Registers (YUKON only) */
WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
/* WOL Pattern Length Registers (YUKON only) */
WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
/* WOL Pattern Counter Registers (YUKON only) */
WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
}; #define WOL_REGS(port, x) (x + (port)*0x80)
enum {
WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
}; #define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400)
XMR_FS_BURST = 1<<11, /* Bit 11: Burst Mode */
XMR_FS_CEX_ERR = 1<<10, /* Bit 10: Carrier Ext. Error */
XMR_FS_802_3 = 1<<9, /* Bit 9: 802.3 Frame */
XMR_FS_COL_ERR = 1<<8, /* Bit 8: Collision Error */
XMR_FS_CAR_ERR = 1<<7, /* Bit 7: Carrier Event Error */
XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
XMR_FS_FRA_ERR = 1<<5, /* Bit 5: Framing Error */
XMR_FS_RUNT = 1<<4, /* Bit 4: Runt Frame */
XMR_FS_LNG_ERR = 1<<3, /* Bit 3: Giant (Jumbo) Frame */
XMR_FS_FCS_ERR = 1<<2, /* Bit 2: Frame Check Sequ Err */
XMR_FS_ERR = 1<<1, /* Bit 1: Frame Error */
XMR_FS_MCTRL = 1<<0, /* Bit 0: MAC Control Packet */
/* * XMR_FS_ERR will be set if * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT, * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue * XMR_FS_ERR unless the corresponding bit in the Receive Command * Register is set.
*/
};
/* ,* XMAC-PHY Registers, indirect addressed over the XMAC
*/ enum {
PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */
PHY_XMAC_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
PHY_XMAC_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */
PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */
PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */
PHY_XMAC_RES_ABI = 0x10,/* 16 bit r/o PHY Resolved Ability */
}; /* * Broadcom-PHY Registers, indirect addressed over XMAC
*/ enum {
PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
PHY_BCOM_STAT = 0x01,/* 16 bit r/o PHY Status Register */
PHY_BCOM_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
PHY_BCOM_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
PHY_BCOM_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
PHY_BCOM_NEPG = 0x07,/* 16 bit r/w Next Page Register */
PHY_BCOM_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */ /* Broadcom-specific registers */
PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
PHY_BCOM_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */
PHY_BCOM_P_EXT_STAT = 0x11,/* 16 bit r/o PHY Extended Stat Reg */
PHY_BCOM_RE_CTR = 0x12,/* 16 bit r/w Receive Error Counter */
PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */
PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */
PHY_BCOM_AUX_CTRL = 0x18,/* 16 bit r/w Auxiliary Control Reg */
PHY_BCOM_AUX_STAT = 0x19,/* 16 bit r/o Auxiliary Stat Summary */
PHY_BCOM_INT_STAT = 0x1a,/* 16 bit r/o Interrupt Status Reg */
PHY_BCOM_INT_MASK = 0x1b,/* 16 bit r/w Interrupt Mask Reg */
};
/* * Marvel-PHY Registers, indirect addressed over GMAC
*/ enum {
PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */ /* Marvel-specific registers */
PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
/* for 10/100 Fast Ethernet PHY (88E3082 only) */
PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
};
enum {
PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
};
enum {
PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occurred */
PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
};
enum {
PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
};
/* Advertisement register bits */ enum {
PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
PHY_AN_100HALF | PHY_AN_100FULL,
};
/* Xmac Specific */ enum {
PHY_X_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
PHY_X_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
PHY_X_AN_RFB = 3<<12,/* Bit 13..12: Remote Fault Bits */
PHY_X_AN_PAUSE = 3<<7,/* Bit 8.. 7: Pause Bits */
PHY_X_AN_HD = 1<<6, /* Bit 6: Half Duplex */
PHY_X_AN_FD = 1<<5, /* Bit 5: Full Duplex */
};
/* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */ enum {
PHY_X_P_NO_PAUSE= 0<<7,/* Bit 8..7: no Pause Mode */
PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: symmetric Pause Mode */
PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: asymmetric Pause Mode */
PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: both Pause Mode */
};
/***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/ enum {
PHY_X_EX_FD = 1<<15, /* Bit 15: Device Supports Full Duplex */
PHY_X_EX_HD = 1<<14, /* Bit 14: Device Supports Half Duplex */
};
/***** PHY_XMAC_RES_ABI 16 bit r/o PHY Resolved Ability *****/ enum {
PHY_X_RS_PAUSE = 3<<7, /* Bit 8..7: selected Pause Mode */
PHY_X_RS_HD = 1<<6, /* Bit 6: Half Duplex Mode selected */
PHY_X_RS_FD = 1<<5, /* Bit 5: Full Duplex Mode selected */
PHY_X_RS_ABLMIS = 1<<4, /* Bit 4: duplex or pause cap mismatch */
PHY_X_RS_PAUMIS = 1<<3, /* Bit 3: pause capability mismatch */
};
/* Remote Fault Bits (PHY_X_AN_RFB) encoding */ enum {
X_RFB_OK = 0<<12,/* Bit 13..12 No errors, Link OK */
X_RFB_LF = 1<<12,/* Bit 13..12 Link Failure */
X_RFB_OFF = 2<<12,/* Bit 13..12 Offline */
X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */
};
/* Broadcom-Specific */ /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ enum {
PHY_B_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
PHY_B_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
PHY_B_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
PHY_B_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
PHY_B_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
PHY_B_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
};
/***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ enum {
PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */ /* Bit 9..8: reserved */
PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
};
/***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/ enum {
PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
};
/***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/ enum {
PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */
PHY_B_PEC_DIS_CROSS = 1<<14, /* Bit 14: Disable MDI Crossover */
PHY_B_PEC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */
PHY_B_PEC_INT_DIS = 1<<12, /* Bit 12: Interrupts Disabled */
PHY_B_PEC_F_INT = 1<<11, /* Bit 11: Force Interrupt */
PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */
PHY_B_PEC_BY_SCR = 1<<9, /* Bit 9: Bypass Scrambler */
PHY_B_PEC_BY_MLT3 = 1<<8, /* Bit 8: Bypass MLT3 Encoder */
PHY_B_PEC_BY_RXA = 1<<7, /* Bit 7: Bypass Rx Alignm. */
PHY_B_PEC_RES_SCR = 1<<6, /* Bit 6: Reset Scrambler */
PHY_B_PEC_EN_LTR = 1<<5, /* Bit 5: Ena LED Traffic Mode */
PHY_B_PEC_LED_ON = 1<<4, /* Bit 4: Force LED's on */
PHY_B_PEC_LED_OFF = 1<<3, /* Bit 3: Force LED's off */
PHY_B_PEC_EX_IPG = 1<<2, /* Bit 2: Extend Tx IPG Mode */
PHY_B_PEC_3_LED = 1<<1, /* Bit 1: Three Link LED mode */
PHY_B_PEC_HIGH_LA = 1<<0, /* Bit 0: GMII FIFO Elasticy */
};
/***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/ enum {
PHY_B_PES_CROSS_STAT = 1<<13, /* Bit 13: MDI Crossover Status */
PHY_B_PES_INT_STAT = 1<<12, /* Bit 12: Interrupt Status */
PHY_B_PES_RRS = 1<<11, /* Bit 11: Remote Receiver Stat. */
PHY_B_PES_LRS = 1<<10, /* Bit 10: Local Receiver Stat. */
PHY_B_PES_LOCKED = 1<<9, /* Bit 9: Locked */
PHY_B_PES_LS = 1<<8, /* Bit 8: Link Status */
PHY_B_PES_RF = 1<<7, /* Bit 7: Remote Fault */
PHY_B_PES_CE_ER = 1<<6, /* Bit 6: Carrier Ext Error */
PHY_B_PES_BAD_SSD = 1<<5, /* Bit 5: Bad SSD */
PHY_B_PES_BAD_ESD = 1<<4, /* Bit 4: Bad ESD */
PHY_B_PES_RX_ER = 1<<3, /* Bit 3: Receive Error */
PHY_B_PES_TX_ER = 1<<2, /* Bit 2: Transmit Error */
PHY_B_PES_LOCK_ER = 1<<1, /* Bit 1: Lock Error */
PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */
};
/* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ /* PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/ enum {
PHY_B_AN_RF = 1<<13, /* Bit 13: Remote Fault */
PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
PHY_B_AN_PC = 1<<10, /* Bit 10: Pause Capable */
};
/***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ enum {
PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */ /* (88E1111 only) */
}; #define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK) #define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
enum {
PHY_M_LEDC_LINK_MSK = 3<<3, /* Bit 4.. 3: Link Control Mask */ /* (88E1011 only) */
PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
};
enum {
PULS_NO_STR = 0, /* no pulse stretching */
PULS_21MS = 1, /* 21 ms to 42 ms */
PULS_42MS = 2, /* 42 ms to 84 ms */
PULS_84MS = 3, /* 84 ms to 170 ms */
PULS_170MS = 4, /* 170 ms to 340 ms */
PULS_340MS = 5, /* 340 ms to 670 ms */
PULS_670MS = 6, /* 670 ms to 1.3 s */
PULS_1300MS = 7, /* 1.3 s to 2.7 s */
};
enum {
BLINK_42MS = 0, /* 42 ms */
BLINK_84MS = 1, /* 84 ms */
BLINK_170MS = 2, /* 170 ms */
BLINK_340MS = 3, /* 340 ms */
BLINK_670MS = 4, /* 670 ms */
};
/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */ /* Bit 13..12: reserved */ #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */ #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */ #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */ #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */ #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */ #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
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