/* * Copyright (c) 2018, Mellanox Technologies. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE.
*/
mlx5_port_query_eth_autoneg(dev, &an_status, &an_disable_cap,
&an_disable_admin); if (!an_disable_cap && an_disable) return -EPERM;
memset(in, 0, sizeof(in));
MLX5_SET(ptys_reg, in, local_port, 1);
MLX5_SET(ptys_reg, in, an_disable_admin, an_disable);
MLX5_SET(ptys_reg, in, proto_mask, MLX5_PTYS_EN); if (ext)
MLX5_SET(ptys_reg, in, ext_eth_proto_admin, proto_admin); else
MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_PTYS, 0, 1);
}
MLX5_SET(sbpr_reg, in, desc, desc);
MLX5_SET(sbpr_reg, in, dir, dir);
MLX5_SET(sbpr_reg, in, pool, pool_idx);
MLX5_SET(sbpr_reg, in, infi_size, infi_size);
MLX5_SET(sbpr_reg, in, size, size);
MLX5_SET(sbpr_reg, in, mode, 1);
return mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out), MLX5_REG_SBPR, 0, 1);
}
MLX5_SET(sbcm_reg, in, desc, desc);
MLX5_SET(sbcm_reg, in, local_port, 1);
MLX5_SET(sbcm_reg, in, pg_buff, pg_buff_idx);
MLX5_SET(sbcm_reg, in, dir, dir);
return mlx5_core_access_reg(mdev, in, sizeof(in), out, size_out, MLX5_REG_SBCM, 0, 0);
}
MLX5_SET(sbcm_reg, in, desc, desc);
MLX5_SET(sbcm_reg, in, local_port, 1);
MLX5_SET(sbcm_reg, in, pg_buff, pg_buff_idx);
MLX5_SET(sbcm_reg, in, dir, dir);
MLX5_SET(sbcm_reg, in, exc, exc);
MLX5_SET(sbcm_reg, in, min_buff, min_buff);
MLX5_SET(sbcm_reg, in, infi_max, infi_size);
MLX5_SET(sbcm_reg, in, max_buff, max_buff);
MLX5_SET(sbcm_reg, in, pool, pool_idx);
return mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out), MLX5_REG_SBCM, 0, 1);
}
/* buffer[i]: buffer that priority i mapped to */ int mlx5e_port_query_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer)
{ int sz = MLX5_ST_SZ_BYTES(pptb_reg);
u32 prio_x_buff; void *out; void *in; int prio; int err;
in = kzalloc(sz, GFP_KERNEL);
out = kzalloc(sz, GFP_KERNEL); if (!in || !out) {
err = -ENOMEM; goto out;
}
MLX5_SET(pptb_reg, in, local_port, 1);
err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPTB, 0, 0); if (err) goto out;
int mlx5e_port_set_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer)
{ int sz = MLX5_ST_SZ_BYTES(pptb_reg);
u32 prio_x_buff; void *out; void *in; int prio; int err;
in = kzalloc(sz, GFP_KERNEL);
out = kzalloc(sz, GFP_KERNEL); if (!in || !out) {
err = -ENOMEM; goto out;
}
/* First query the pptb register */
MLX5_SET(pptb_reg, in, local_port, 1);
err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPTB, 0, 0); if (err) goto out;
memcpy(in, out, sz);
MLX5_SET(pptb_reg, in, local_port, 1);
/* Update the pm and prio_x_buff */
MLX5_SET(pptb_reg, in, pm, 0xFF);
static u16 mlx5e_remap_fec_conf_mode(enum mlx5e_fec_supported_link_mode link_mode,
u16 conf_fec)
{ /* RS fec in ethtool is originally mapped to MLX5E_FEC_RS_528_514. * For link modes up to 25G per lane, the value is kept. * For 50G or 100G per lane, it's remapped to MLX5E_FEC_RS_544_514. * For 200G per lane, remapped to MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD.
*/ if (conf_fec != BIT(MLX5E_FEC_RS_528_514)) return conf_fec;
if (link_mode >= MLX5E_FEC_FIRST_200G_PER_LANE_MODE) return BIT(MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD);
if (link_mode >= MLX5E_FEC_FIRST_50G_PER_LANE_MODE) return BIT(MLX5E_FEC_RS_544_514);
return conf_fec;
}
int mlx5e_set_fec_mode(struct mlx5_core_dev *dev, u16 fec_policy)
{ bool fec_50g_per_lane = MLX5_CAP_PCAM_FEATURE(dev, fec_50G_per_lane_in_pplm);
u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {}; int sz = MLX5_ST_SZ_BYTES(pplm_reg);
u16 fec_policy_auto = 0; int err; int i;
if (!MLX5_CAP_GEN(dev, pcam_reg)) return -EOPNOTSUPP;
if (!MLX5_CAP_PCAM_REG(dev, pplm)) return -EOPNOTSUPP;
if (fec_policy >= (1 << MLX5E_FEC_LLRS_272_257_1) && !fec_50g_per_lane) return -EOPNOTSUPP;
if (fec_policy && !mlx5e_fec_in_caps(dev, fec_policy)) return -EOPNOTSUPP;
MLX5_SET(pplm_reg, in, local_port, 1);
err = mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PPLM, 0, 0); if (err) return err;
MLX5_SET(pplm_reg, out, local_port, 1);
for (i = 0; i < MLX5E_MAX_FEC_SUPPORTED_LINK_MODE; i++) {
u16 conf_fec = fec_policy;
u16 fec_caps = 0;
if (!mlx5e_is_fec_supported_link_mode(dev, i)) break;
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