/* SGCR - Switch General Configuration Register * -------------------------------------------- * This register is used for configuration of the switch capabilities.
*/ #define MLXSW_REG_SGCR_ID 0x2000 #define MLXSW_REG_SGCR_LEN 0x10
/* reg_sgcr_lag_lookup_pgt_base * Base address used for lookup in PGT table * Supported when CONFIG_PROFILE.lag_mode = 1 * Note: when IGCR.ddd_lag_mode=0, the address shall be aligned to 8 entries. * Access: RW
*/
MLXSW_ITEM32(reg, sgcr, lag_lookup_pgt_base, 0x0C, 0, 16);
/* reg_spad_base_mac * Base MAC address for the switch partitions. * Per switch partition MAC address is equal to: * base_mac + swid * Access: RW
*/
MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
/* SSPR - Switch System Port Record Register * ----------------------------------------- * Configures the system port to local port mapping.
*/ #define MLXSW_REG_SSPR_ID 0x2008 #define MLXSW_REG_SSPR_LEN 0x8
/* reg_sspr_m * Master - if set, then the record describes the master system port. * This is needed in case a local port is mapped into several system ports * (for multipathing). That number will be reported as the source system * port when packets are forwarded to the CPU. Only one master port is allowed * per local port. * * Note: Must be set for Spectrum. * Access: RW
*/
MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
/* reg_sspr_local_port * Local port number. * * Access: RW
*/
MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12);
/* reg_sspr_system_port * Unique identifier within the stacking domain that represents all the ports * that are available in the system (external ports). * * Currently, only single-ASIC configurations are supported, so we default to * 1:1 mapping between system ports and local ports. * Access: Index
*/
MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
/* SFDAT - Switch Filtering Database Aging Time * -------------------------------------------- * Controls the Switch aging time. Aging time is able to be set per Switch * Partition.
*/ #define MLXSW_REG_SFDAT_ID 0x2009 #define MLXSW_REG_SFDAT_LEN 0x8
/* SFD - Switch Filtering Database * ------------------------------- * The following register defines the access to the filtering database. * The register supports querying, adding, removing and modifying the database. * The access is optimized for bulk updates in which case more than one * FDB record is present in the same command.
*/ #define MLXSW_REG_SFD_ID 0x200A #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ #define MLXSW_REG_SFD_REC_MAX_COUNT 64 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
/* reg_sfd_swid * Switch partition ID for queries. Reserved on Write. * Access: Index
*/
MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
enum mlxsw_reg_sfd_op { /* Dump entire FDB a (process according to record_locator) */
MLXSW_REG_SFD_OP_QUERY_DUMP = 0, /* Query records by {MAC, VID/FID} value */
MLXSW_REG_SFD_OP_QUERY_QUERY = 1, /* Query and clear activity. Query records by {MAC, VID/FID} value */
MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, /* Test. Response indicates if each of the records could be * added to the FDB.
*/
MLXSW_REG_SFD_OP_WRITE_TEST = 0, /* Add/modify. Aged-out records cannot be added. This command removes * the learning notification of the {MAC, VID/FID}. Response includes * the entries that were added to the FDB.
*/
MLXSW_REG_SFD_OP_WRITE_EDIT = 1, /* Remove record by {MAC, VID/FID}. This command also removes * the learning notification and aged-out notifications * of the {MAC, VID/FID}. The response provides current (pre-removal) * entries as non-aged-out.
*/
MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, /* Remove learned notification by {MAC, VID/FID}. The response provides * the removed learning notification.
*/
MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
};
/* reg_sfd_record_locator * Used for querying the FDB. Use record_locator=0 to initiate the * query. When a record is returned, a new record_locator is * returned to be used in the subsequent query. * Reserved for database update. * Access: Index
*/
MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
/* reg_sfd_num_rec * Request: Number of records to read/add/modify/remove * Response: Number of records read/added/replaced/removed * See above description for more details. * Ranges 0..64 * Access: RW
*/
MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
/* reg_sfd_rec_a * Activity. Set for new static entries. Set for static entries if a frame SMAC * lookup hits on the entry. * To clear the a bit, use "query and clear activity" op. * Access: RO
*/
MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
MLXSW_REG_SFD_REC_LEN, 0x00, false);
/* reg_sfd_rec_mac * MAC address. * Access: Index
*/
MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
MLXSW_REG_SFD_REC_LEN, 0x02);
enum mlxsw_reg_sfd_rec_action { /* forward */
MLXSW_REG_SFD_REC_ACTION_NOP = 0, /* forward and trap, trap_id is FDB_TRAP */
MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, /* trap and do not forward, trap_id is FDB_TRAP */
MLXSW_REG_SFD_REC_ACTION_TRAP = 2, /* forward to IP router */
MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
};
/* reg_sfd_rec_action * Action to apply on the packet. * Note: Dynamic entries can only be configured with NOP action. * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
MLXSW_REG_SFD_REC_LEN, 0x0C, false);
/* reg_sfd_uc_sub_port * VEPA channel on local port. * Valid only if local port is a non-stacking port. Must be 0 if multichannel * VEPA is not enabled. * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
MLXSW_REG_SFD_REC_LEN, 0x08, false);
/* reg_sfd_uc_set_vid * Set VID. * 0 - Do not update VID. * 1 - Set VID. * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. * Access: RW * * Note: Reserved when legacy bridge model is used.
*/
MLXSW_ITEM32_INDEXED(reg, sfd, uc_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1,
MLXSW_REG_SFD_REC_LEN, 0x08, false);
/* reg_sfd_uc_fid_vid * Filtering ID or VLAN ID * For SwitchX and SwitchX-2: * - Dynamic entries (policy 2,3) use FID * - Static entries (policy 0) use VID * - When independent learning is configured, VID=FID * For Spectrum: use FID for both Dynamic and Static entries. * VID should not be used. * Access: Index
*/
MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
MLXSW_REG_SFD_REC_LEN, 0x08, false);
/* reg_sfd_uc_vid * New VID when set_vid=1. * Access: RW * * Note: Reserved when legacy bridge model is used and when set_vid=0.
*/
MLXSW_ITEM32_INDEXED(reg, sfd, uc_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
MLXSW_REG_SFD_REC_LEN, 0x0C, false);
/* reg_sfd_uc_system_port * Unique port identifier for the final destination of the packet. * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
MLXSW_REG_SFD_REC_LEN, 0x0C, false);
/* reg_sfd_uc_lag_sub_port * LAG sub port. * Must be 0 if multichannel VEPA is not enabled. * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
MLXSW_REG_SFD_REC_LEN, 0x08, false);
/* reg_sfd_uc_lag_set_vid * Set VID. * 0 - Do not update VID. * 1 - Set VID. * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. * Access: RW * * Note: Reserved when legacy bridge model is used.
*/
MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1,
MLXSW_REG_SFD_REC_LEN, 0x08, false);
/* reg_sfd_uc_lag_fid_vid * Filtering ID or VLAN ID * For SwitchX and SwitchX-2: * - Dynamic entries (policy 2,3) use FID * - Static entries (policy 0) use VID * - When independent learning is configured, VID=FID * For Spectrum: use FID for both Dynamic and Static entries. * VID should not be used. * Access: Index
*/
MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
MLXSW_REG_SFD_REC_LEN, 0x08, false);
/* reg_sfd_uc_lag_lag_vid * New vlan ID. * Access: RW * * Note: Reserved when legacy bridge model is used and set_vid=0.
*/
MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
MLXSW_REG_SFD_REC_LEN, 0x0C, false);
/* reg_sfd_uc_lag_lag_id * LAG Identifier - pointer into the LAG descriptor table. * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
MLXSW_REG_SFD_REC_LEN, 0x0C, false);
/* reg_sfd_mc_pgi * * Multicast port group index - index into the port group table. * Value 0x1FFF indicates the pgi should point to the MID entry. * For Spectrum this value must be set to 0x1FFF * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
MLXSW_REG_SFD_REC_LEN, 0x08, false);
/* reg_sfd_mc_fid_vid * * Filtering ID or VLAN ID * Access: Index
*/
MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
MLXSW_REG_SFD_REC_LEN, 0x08, false);
/* reg_sfd_mc_mid * * Multicast identifier - global identifier that represents the multicast * group across all devices. * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
MLXSW_REG_SFD_REC_LEN, 0x0C, false);
/* reg_sfd_uc_tunnel_uip_msb * When protocol is IPv4, the most significant byte of the underlay IPv4 * destination IP. * When protocol is IPv6, reserved. * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24,
8, MLXSW_REG_SFD_REC_LEN, 0x08, false);
/* reg_sfd_uc_tunnel_uip_lsb * When protocol is IPv4, the least significant bytes of the underlay * IPv4 destination IP. * When protocol is IPv6, pointer to the underlay IPv6 destination IP * which is configured by RIPS. * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0,
24, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
/* reg_sfn_end * Forces the current session to end. * Access: OP
*/
MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
/* reg_sfn_num_rec * Request: Number of learned notifications and aged-out notification * records requested. * Response: Number of notification records returned (must be smaller * than or equal to the value requested) * Ranges 0..64 * Access: OP
*/
MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
enum mlxsw_reg_sfn_rec_type { /* MAC addresses learned on a regular port. */
MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, /* MAC addresses learned on a LAG port. */
MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, /* Aged-out MAC address on a regular port. */
MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, /* Aged-out MAC address on a LAG port. */
MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, /* Learned unicast tunnel record. */
MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, /* Aged-out unicast tunnel record. */
MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE,
};
/* reg_sfn_mac_sub_port * VEPA channel on the local port. * 0 if multichannel VEPA is not enabled. * Access: RO
*/
MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
MLXSW_REG_SFN_REC_LEN, 0x08, false);
/* reg_sfn_mac_system_port * Unique port identifier for the final destination of the packet. * Access: RO
*/
MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
MLXSW_REG_SFN_REC_LEN, 0x0C, false);
/* reg_sfn_mac_lag_lag_id * LAG ID (pointer into the LAG descriptor table). * Access: RO
*/
MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
MLXSW_REG_SFN_REC_LEN, 0x0C, false);
/* reg_sfn_uc_tunnel_uip_msb * When protocol is IPv4, the most significant byte of the underlay IPv4 * address of the remote VTEP. * When protocol is IPv6, reserved. * Access: RO
*/
MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24,
8, MLXSW_REG_SFN_REC_LEN, 0x08, false);
/* reg_sfn_uc_tunnel_uip_lsb * When protocol is IPv4, the least significant bytes of the underlay * IPv4 address of the remote VTEP. * When protocol is IPv6, ipv6_id to be queried from TNIPSD. * Access: RO
*/
MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0,
24, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
/* SPMS - Switch Port MSTP/RSTP State Register * ------------------------------------------- * Configures the spanning tree state of a physical port.
*/ #define MLXSW_REG_SPMS_ID 0x200D #define MLXSW_REG_SPMS_LEN 0x404
/* reg_spms_state * Spanning tree state of each VLAN ID (VID) of the local port. * 0 - Do not change spanning tree state (used only when writing). * 1 - Discarding. No learning or forwarding to/from this port (default). * 2 - Learning. Port is learning, but not forwarding. * 3 - Forwarding. Port is learning and forwarding. * Access: RW
*/
MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
/* SPVID - Switch Port VID * ----------------------- * The switch port VID configures the default VID for a port.
*/ #define MLXSW_REG_SPVID_ID 0x200E #define MLXSW_REG_SPVID_LEN 0x08
/* reg_spvid_tport * Port is tunnel port. * Reserved when SwitchX/-2 or Spectrum-1. * Access: Index
*/
MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1);
/* reg_spvid_local_port * When tport = 0: Local port number. Not supported for CPU port. * When tport = 1: Tunnel port. * Access: Index
*/
MLXSW_ITEM32_LP(reg, spvid, 0x00, 16, 0x00, 12);
/* reg_spvid_sub_port * Virtual port within the physical port. * Should be set to 0 when virtual ports are not enabled on the port. * Access: Index
*/
MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
/* reg_spvid_egr_et_set * When VLAN is pushed at ingress (for untagged packets or for * QinQ push mode) then the EtherType is decided at the egress port. * Reserved when Spectrum-1. * Access: RW
*/
MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1);
/* reg_spvid_et_vlan * EtherType used for when VLAN is pushed at ingress (for untagged * packets or for QinQ push mode). * 0: ether_type0 - (default) * 1: ether_type1 * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2 * Ethertype IDs are configured by SVER. * Reserved when egr_et_set = 1. * Access: RW
*/
MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2);
/* reg_spvid_pvid * Port default VID * Access: RW
*/
MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
/* SPVM - Switch Port VLAN Membership * ---------------------------------- * The Switch Port VLAN Membership register configures the VLAN membership * of a port in a VLAN denoted by VID. VLAN membership is managed per * virtual port. The register can be used to add and remove VID(s) from a port.
*/ #define MLXSW_REG_SPVM_ID 0x200F #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
/* reg_spvm_pt * Priority tagged. If this bit is set, packets forwarded to the port with * untagged VLAN membership (u bit is set) will be tagged with priority tag * (VID=0) * Access: RW
*/
MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
/* reg_spvm_pte * Priority Tagged Update Enable. On Write operations, if this bit is cleared, * the pt bit will NOT be updated. To update the pt bit, pte must be set. * Access: WO
*/
MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
/* reg_spvm_local_port * Local port number. * Access: Index
*/
MLXSW_ITEM32_LP(reg, spvm, 0x00, 16, 0x00, 12);
/* reg_spvm_sub_port * Virtual port within the physical port. * Should be set to 0 when virtual ports are not enabled on the port. * Access: Index
*/
MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
/* reg_spvm_num_rec * Number of records to update. Each record contains: i, e, u, vid. * Access: OP
*/
MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
for (i = 0; i < size; i++) {
mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
}
}
/* SPAFT - Switch Port Acceptable Frame Types * ------------------------------------------ * The Switch Port Acceptable Frame Types register configures the frame * admittance of the port.
*/ #define MLXSW_REG_SPAFT_ID 0x2010 #define MLXSW_REG_SPAFT_LEN 0x08
/* reg_spaft_local_port * Local port number. * Access: Index * * Note: CPU port is not supported (all tag types are allowed).
*/
MLXSW_ITEM32_LP(reg, spaft, 0x00, 16, 0x00, 12);
/* reg_spaft_sub_port * Virtual port within the physical port. * Should be set to 0 when virtual ports are not enabled on the port. * Access: RW
*/
MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
/* reg_spaft_allow_untagged * When set, untagged frames on the ingress are allowed (default). * Access: RW
*/
MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
/* reg_spaft_allow_prio_tagged * When set, priority tagged frames on the ingress are allowed (default). * Access: RW
*/
MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
/* reg_spaft_allow_tagged * When set, tagged frames on the ingress are allowed (default). * Access: RW
*/
MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
/* SFGC - Switch Flooding Group Configuration * ------------------------------------------ * The following register controls the association of flooding tables and MIDs * to packet types used for flooding. * * Reserved when CONFIG_PROFILE.flood_mode = CFF.
*/ #define MLXSW_REG_SFGC_ID 0x2011 #define MLXSW_REG_SFGC_LEN 0x14
/* reg_sfgc_type * The traffic type to reach the flooding table. * Access: Index
*/
MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
/* bridge_type is used in SFGC and SFMR. */ enum mlxsw_reg_bridge_type {
MLXSW_REG_BRIDGE_TYPE_0 = 0, /* Used for .1q FIDs. */
MLXSW_REG_BRIDGE_TYPE_1 = 1, /* Used for .1d FIDs. */
};
/* reg_sfgc_bridge_type * Access: Index * * Note: SwitchX-2 only supports 802.1Q mode.
*/
MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
/* reg_sfgc_table_type * See mlxsw_flood_table_type * Access: RW * * Note: FID offset and FID types are not supported in SwitchX-2.
*/
MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
/* reg_sfgc_flood_table * Flooding table index to associate with the specific type on the specific * switch partition. * Access: RW
*/
MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
/* reg_sfgc_counter_set_type * Counter Set Type for flow counters. * Access: RW
*/
MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
/* reg_sfgc_counter_index * Counter Index for flow counters. * Access: RW
*/
MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
/* reg_sfgc_mid_base * MID Base. * Access: RW * * Note: Reserved when legacy bridge model is used.
*/
MLXSW_ITEM32(reg, sfgc, mid_base, 0x10, 0, 16);
/* SFDF - Switch Filtering DB Flush * -------------------------------- * The switch filtering DB flush register is used to flush the FDB. * Note that FDB notifications are flushed as well.
*/ #define MLXSW_REG_SFDF_ID 0x2013 #define MLXSW_REG_SFDF_LEN 0x14
/* reg_sfdf_flush_type * Flush type. * 0 - All SWID dynamic entries are flushed. * 1 - All FID dynamic entries are flushed. * 2 - All dynamic entries pointing to port are flushed. * 3 - All FID dynamic entries pointing to port are flushed. * 4 - All dynamic entries pointing to LAG are flushed. * 5 - All FID dynamic entries pointing to LAG are flushed. * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are * flushed. * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are * flushed, per FID. * Access: RW
*/
MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
/* reg_sfdf_flush_static * Static. * 0 - Flush only dynamic entries. * 1 - Flush both dynamic and static entries. * Access: RW
*/
MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
/* reg_sfdf_system_port * Port to flush. * Access: RW
*/
MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
/* reg_sfdf_port_fid_system_port * Port to flush, pointed to by FID. * Access: RW
*/
MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
/* reg_sfdf_lag_id * LAG ID to flush. * Access: RW
*/
MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
/* reg_sfdf_lag_fid_lag_id * LAG ID to flush, pointed to by FID. * Access: RW
*/
MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
/* SLDR - Switch LAG Descriptor Register * ----------------------------------------- * The switch LAG descriptor register is populated by LAG descriptors. * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to * max_lag-1.
*/ #define MLXSW_REG_SLDR_ID 0x2014 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
enum mlxsw_reg_sldr_op { /* Indicates a creation of a new LAG-ID, lag_id must be valid */
MLXSW_REG_SLDR_OP_LAG_CREATE,
MLXSW_REG_SLDR_OP_LAG_DESTROY, /* Ports that appear in the list have the Distributor enabled */
MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, /* Removes ports from the disributor list */
MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
};
/* reg_sldr_lag_id * LAG identifier. The lag_id is the index into the LAG descriptor table. * Access: Index
*/
MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
/* reg_sldr_num_ports * The number of member ports of the LAG. * Reserved for Create / Destroy operations * For Add / Remove operations - indicates the number of ports in the list. * Access: RW
*/
MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
/* SLCR - Switch LAG Configuration 2 Register * ------------------------------------------- * The Switch LAG Configuration register is used for configuring the * LAG properties of the switch.
*/ #define MLXSW_REG_SLCR_ID 0x2015 #define MLXSW_REG_SLCR_LEN 0x10
enum mlxsw_reg_slcr_pp { /* Global Configuration (for all ports) */
MLXSW_REG_SLCR_PP_GLOBAL, /* Per port configuration, based on local_port field */
MLXSW_REG_SLCR_PP_PER_PORT,
};
/* reg_slcr_pp * Per Port Configuration * Note: Reading at Global mode results in reading port 1 configuration. * Access: Index
*/
MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
/* reg_slcr_local_port * Local port number * Supported from CPU port * Not supported from router port * Reserved when pp = Global Configuration * Access: Index
*/
MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12);
/* Ingress port */ #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) /* SMAC - for IPv4 and IPv6 packets */ #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) /* SMAC - for non-IP packets */ #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) #define MLXSW_REG_SLCR_LAG_HASH_SMAC \
(MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) /* DMAC - for IPv4 and IPv6 packets */ #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) /* DMAC - for non-IP packets */ #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) #define MLXSW_REG_SLCR_LAG_HASH_DMAC \
(MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) /* Ethertype - for IPv4 and IPv6 packets */ #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) /* Ethertype - for non-IP packets */ #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
(MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) /* VLAN ID - for IPv4 and IPv6 packets */ #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) /* VLAN ID - for non-IP packets */ #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) #define MLXSW_REG_SLCR_LAG_HASH_VLANID \
(MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) /* Source IP address (can be IPv4 or IPv6) */ #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) /* Destination IP address (can be IPv4 or IPv6) */ #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) /* TCP/UDP source port */ #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) /* TCP/UDP destination port*/ #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) /* IPv4 Protocol/IPv6 Next Header */ #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) /* IPv6 Flow label */ #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) /* SID - FCoE source ID */ #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) /* DID - FCoE destination ID */ #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) /* OXID - FCoE originator exchange ID */ #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) /* Destination QP number - for RoCE packets */ #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
/* reg_slcr_lag_hash * LAG hashing configuration. This is a bitmask, in which each set * bit includes the corresponding item in the LAG hash calculation. * The default lag_hash contains SMAC, DMAC, VLANID and * Ethertype (for all packet types). * Access: RW
*/
MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
/* reg_slcr_seed * LAG seed value. The seed is the same for all ports. * Access: RW
*/
MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
/* SLCOR - Switch LAG Collector Register * ------------------------------------- * The Switch LAG Collector register controls the Local Port membership * in a LAG and enablement of the collector.
*/ #define MLXSW_REG_SLCOR_ID 0x2016 #define MLXSW_REG_SLCOR_LEN 0x10
/* reg_slcor_local_port * Local port number * Not supported for CPU port * Access: Index
*/
MLXSW_ITEM32_LP(reg, slcor, 0x00, 16, 0x00, 12);
/* reg_slcor_lag_id * LAG Identifier. Index into the LAG descriptor table. * Access: Index
*/
MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
/* reg_slcor_port_index * Port index in the LAG list. Only valid on Add Port to LAG col. * Valid range is from 0 to cap_max_lag_members-1 * Access: RW
*/
MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
/* reg_spmlr_local_port * Local port number. * Access: Index
*/
MLXSW_ITEM32_LP(reg, spmlr, 0x00, 16, 0x00, 12);
/* reg_spmlr_sub_port * Virtual port within the physical port. * Should be set to 0 when virtual ports are not enabled on the port. * Access: Index
*/
MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
/* reg_spmlr_learn_mode * Learning mode on the port. * 0 - Learning disabled. * 2 - Learning enabled. * 3 - Security mode. * * In security mode the switch does not learn MACs on the port, but uses the * SMAC to see if it exists on another ingress port. If so, the packet is * classified as a bad packet and is discarded unless the software registers * to receive port security error packets usign HPKT.
*/
MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
/* SVFA - Switch VID to FID Allocation Register * -------------------------------------------- * Controls the VID to FID mapping and {Port, VID} to FID mapping for * virtualized ports.
*/ #define MLXSW_REG_SVFA_ID 0x201C #define MLXSW_REG_SVFA_LEN 0x18
/* reg_svfa_counter_set_type * Counter set type for flow counters. * Access: RW * * Note: Reserved for SwitchX-2.
*/
MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
/* reg_svfa_counter_index * Counter index for flow counters. * Access: RW * * Note: Reserved for SwitchX-2.
*/
MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
/* reg_svfa_vni * Virtual Network Identifier. * Access: Index * * Note: Reserved when mapping_table is not 2 (VNI mapping table).
*/
MLXSW_ITEM32(reg, svfa, vni, 0x10, 0, 24);
/* reg_svfa_irif_v * Ingress RIF valid. * 0 - Ingress RIF is not valid, no ingress RIF assigned. * 1 - Ingress RIF valid. * Must not be set for a non enabled RIF. * Access: RW * * Note: Reserved when legacy bridge model is used.
*/
MLXSW_ITEM32(reg, svfa, irif_v, 0x14, 24, 1);
/* reg_svfa_irif * Ingress RIF (Router Interface). * Range is 0..cap_max_router_interfaces-1. * Access: RW * * Note: Reserved when legacy bridge model is used and when irif_v=0.
*/
MLXSW_ITEM32(reg, svfa, irif, 0x14, 0, 16);
/* SPVTR - Switch Port VLAN Stacking Register * ------------------------------------------ * The Switch Port VLAN Stacking register configures the VLAN mode of the port * to enable VLAN stacking.
*/ #define MLXSW_REG_SPVTR_ID 0x201D #define MLXSW_REG_SPVTR_LEN 0x10
/* reg_spvtr_tport * Port is tunnel port. * Access: Index * * Note: Reserved when SwitchX/-2 or Spectrum-1.
*/
MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1);
/* reg_spvtr_local_port * When tport = 0: local port number (Not supported from/to CPU). * When tport = 1: tunnel port. * Access: Index
*/
MLXSW_ITEM32_LP(reg, spvtr, 0x00, 16, 0x00, 12);
/* reg_spvtr_ippe * Ingress Port Prio Mode Update Enable. * When set, the Port Prio Mode is updated with the provided ipprio_mode field. * Reserved on Get operations. * Access: OP
*/
MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1);
/* reg_spvtr_ipve * Ingress Port VID Mode Update Enable. * When set, the Ingress Port VID Mode is updated with the provided ipvid_mode * field. * Reserved on Get operations. * Access: OP
*/
MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1);
/* reg_spvtr_epve * Egress Port VID Mode Update Enable. * When set, the Egress Port VID Mode is updated with the provided epvid_mode * field. * Access: OP
*/
MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1);
/* reg_spvtr_ipprio_mode * Ingress Port Priority Mode. * This controls the PCP and DEI of the new outer VLAN * Note: for SwitchX/-2 the DEI is not affected. * 0: use port default PCP and DEI (configured by QPDPC). * 1: use C-VLAN PCP and DEI. * Has no effect when ipvid_mode = 0. * Reserved when tport = 1. * Access: RW
*/
MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4);
/* reg_spvtr_epvid_mode * Egress Port VLAN-ID Mode. * For Spectrum family, this affects the values of SPVM.e,u,pt. * Access: WO
*/
MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4);
/* reg_svpe_local_port * Local port number * Access: Index * * Note: CPU port is not supported (uses VLAN mode only).
*/
MLXSW_ITEM32_LP(reg, svpe, 0x00, 16, 0x00, 12);
/* reg_svpe_vp_en * Virtual port enable. * 0 - Disable, VLAN mode (VID to FID). * 1 - Enable, Virtual port mode ({Port, VID} to FID). * Access: RW
*/
MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
/* reg_sfmr_flood_rsp * Router sub-port flooding table. * 0 - Regular flooding table. * 1 - Router sub-port flooding table. For this FID the flooding is per * router-sub-port local_port. Must not be set for a FID which is not a * router-sub-port and must be set prior to enabling the relevant RIF. * Access: RW * * Note: Reserved when legacy bridge model is used. * Reserved when CONFIG_PROFILE.flood_mode = CFF.
*/
MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1);
/* reg_sfmr_flood_bridge_type * Flood bridge type (see SFGC.bridge_type). * 0 - type_0. * 1 - type_1. * Access: RW * * Note: Reserved when legacy bridge model is used and when flood_rsp=1. * Reserved when CONFIG_PROFILE.flood_mode = CFF
*/
MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1);
/* reg_sfmr_fid_offset * FID offset. * Used to point into the flooding table selected by SFGC register if * the table is of type FID-Offset. Otherwise, this field is reserved. * Access: RW * * Note: Reserved when CONFIG_PROFILE.flood_mode = CFF
*/
MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
/* reg_sfmr_vtfp * Valid Tunnel Flood Pointer. * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. * Access: RW * * Note: Reserved for 802.1Q FIDs.
*/
MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
/* reg_sfmr_nve_tunnel_flood_ptr * Underlay Flooding and BC Pointer. * Used as a pointer to the first entry of the group based link lists of * flooding or BC entries (for NVE tunnels). * Access: RW
*/
MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
/* reg_sfmr_vv * VNI Valid. * If not set, then vni is reserved. * Access: RW * * Note: Reserved for 802.1Q FIDs.
*/
MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
/* reg_sfmr_vni * Virtual Network Identifier. * When legacy bridge model is used, a given VNI can only be assigned to one * FID. When unified bridge model is used, it configures only the FID->VNI, * the VNI->FID is done by SVFA. * Access: RW
*/
MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
/* reg_sfmr_irif_v * Ingress RIF valid. * 0 - Ingress RIF is not valid, no ingress RIF assigned. * 1 - Ingress RIF valid. * Must not be set for a non valid RIF. * Access: RW * * Note: Reserved when legacy bridge model is used.
*/
MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1);
/* reg_sfmr_irif * Ingress RIF (Router Interface). * Range is 0..cap_max_router_interfaces-1. * Access: RW * * Note: Reserved when legacy bridge model is used and when irif_v=0.
*/
MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16);
/* reg_sfmr_cff_mid_base * Pointer to PGT table. * Range: 0..(cap_max_pgt-1) * Access: RW * * Note: Reserved when SwitchX/-2 and Spectrum-1. * Supported when CONFIG_PROFILE.flood_mode = CFF.
*/
MLXSW_ITEM32(reg, sfmr, cff_mid_base, 0x20, 0, 16);
/* reg_sfmr_nve_flood_prf_id * FID flooding profile_id for NVE Encap * Range 0..(max_cap_nve_flood_prf-1) * Access: RW * * Note: Reserved when SwitchX/-2 and Spectrum-1
*/
MLXSW_ITEM32(reg, sfmr, nve_flood_prf_id, 0x24, 8, 2);
/* reg_sfmr_cff_prf_id * Compressed Fid Flooding profile_id * Range 0..(max_cap_nve_flood_prf-1) * Access: RW * * Note: Reserved when SwitchX/-2 and Spectrum-1 * Supported only when CONFIG_PROFLE.flood_mode = CFF.
*/
MLXSW_ITEM32(reg, sfmr, cff_prf_id, 0x24, 0, 2);
/* reg_sfmr_smpe_valid * SMPE is valid. * Access: RW * * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on * Spectrum-1.
*/
MLXSW_ITEM32(reg, sfmr, smpe_valid, 0x28, 20, 1);
/* reg_sfmr_smpe * Switch multicast port to egress VID. * Range is 0..cap_max_rmpe-1 * Access: RW * * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on * Spectrum-1.
*/
MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16);
/* reg_spvmlr_local_port * Local ingress port. * Access: Index * * Note: CPU port is not supported.
*/
MLXSW_ITEM32_LP(reg, spvmlr, 0x00, 16, 0x00, 12);
/* reg_spvmlr_num_rec * Number of records to update. * Access: OP
*/
MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
/* reg_spvmlr_rec_vid * VLAN ID to be added/removed from port or for querying. * Access: Index
*/
MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
for (i = 0; i < num_rec; i++) {
mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
}
}
/* SPFSR - Switch Port FDB Security Register * ----------------------------------------- * Configures the security mode per port.
*/ #define MLXSW_REG_SPFSR_ID 0x2023 #define MLXSW_REG_SPFSR_LEN 0x08
/* SPVC - Switch Port VLAN Classification Register * ----------------------------------------------- * Configures the port to identify packets as untagged / single tagged / * double packets based on the packet EtherTypes. * Ethertype IDs are configured by SVER.
*/ #define MLXSW_REG_SPVC_ID 0x2026 #define MLXSW_REG_SPVC_LEN 0x0C
/* reg_spvc_local_port * Local port. * Access: Index * * Note: applies both to Rx port and Tx port, so if a packet traverses * through Rx port i and a Tx port j then port i and port j must have the * same configuration.
*/
MLXSW_ITEM32_LP(reg, spvc, 0x00, 16, 0x00, 12);
/* reg_spvc_inner_et2 * Vlan Tag1 EtherType2 enable. * Packet is initially classified as double VLAN Tag if in addition to * being classified with a tag0 VLAN Tag its tag1 EtherType value is * equal to ether_type2. * 0: disable (default) * 1: enable * Access: RW
*/
MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1);
/* reg_spvc_et2 * Vlan Tag0 EtherType2 enable. * Packet is initially classified as VLAN Tag if its tag0 EtherType is * equal to ether_type2. * 0: disable (default) * 1: enable * Access: RW
*/
MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1);
/* reg_spvc_inner_et1 * Vlan Tag1 EtherType1 enable. * Packet is initially classified as double VLAN Tag if in addition to * being classified with a tag0 VLAN Tag its tag1 EtherType value is * equal to ether_type1. * 0: disable * 1: enable (default) * Access: RW
*/
MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1);
/* reg_spvc_et1 * Vlan Tag0 EtherType1 enable. * Packet is initially classified as VLAN Tag if its tag0 EtherType is * equal to ether_type1. * 0: disable * 1: enable (default) * Access: RW
*/
MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1);
/* reg_inner_et0 * Vlan Tag1 EtherType0 enable. * Packet is initially classified as double VLAN Tag if in addition to * being classified with a tag0 VLAN Tag its tag1 EtherType value is * equal to ether_type0. * 0: disable * 1: enable (default) * Access: RW
*/
MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1);
/* reg_et0 * Vlan Tag0 EtherType0 enable. * Packet is initially classified as VLAN Tag if its tag0 EtherType is * equal to ether_type0. * 0: disable * 1: enable (default) * Access: RW
*/
MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1);
/* reg_sffp_profile_id * Profile ID a.k.a. SFMR.nve_flood_prf_id or SFMR.cff_prf_id * Range 0..max_cap_nve_flood_prf-1 * Access: Index
*/
MLXSW_ITEM32(reg, sffp, profile_id, 0x00, 16, 2);
/* reg_sffp_type * The traffic type to reach the flooding table. * Same as SFGC.type * Access: Index
*/
MLXSW_ITEM32(reg, sffp, type, 0x00, 0, 4);
/* reg_sffp_flood_offset * Flood offset. Offset to add to SFMR.cff_mid_base to get the final PGT address * for FID flood; or offset to add to SFMR.nve_tunnel_flood_ptr to get KVD * pointer for NVE underlay. * Access: RW
*/
MLXSW_ITEM32(reg, sffp, flood_offset, 0x04, 0, 3);
/* SPEVET - Switch Port Egress VLAN EtherType * ------------------------------------------ * The switch port egress VLAN EtherType configures which EtherType to push at * egress for packets incoming through a local port for which 'SPVID.egr_et_set' * is set.
*/ #define MLXSW_REG_SPEVET_ID 0x202A #define MLXSW_REG_SPEVET_LEN 0x08
/* SMPE - Switch Multicast Port to Egress VID * ------------------------------------------ * The switch multicast port to egress VID maps * {egress_port, SMPE index} -> {VID}.
*/ #define MLXSW_REG_SMPE_ID 0x202B #define MLXSW_REG_SMPE_LEN 0x0C
/* reg_smpe_local_port * Local port number. * CPU port is not supported. * Access: Index
*/
MLXSW_ITEM32_LP(reg, smpe, 0x00, 16, 0x00, 12);
/* reg_smpe_smpe_index * Switch multicast port to egress VID. * Range is 0..cap_max_rmpe-1. * Access: Index
*/
MLXSW_ITEM32(reg, smpe, smpe_index, 0x04, 0, 16);
/* SMID-V2 - Switch Multicast ID Version 2 Register * ------------------------------------------------ * The MID record maps from a MID (Multicast ID), which is a unique identifier * of the multicast group within the stacking domain, into a list of local * ports into which the packet is replicated.
*/ #define MLXSW_REG_SMID2_ID 0x2034 #define MLXSW_REG_SMID2_LEN 0x120
/* reg_smid2_mid * Multicast identifier - global identifier that represents the multicast group * across all devices. * Access: Index
*/
MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16);
/* reg_smid2_smpe_valid * SMPE is valid. * When not valid, the egress VID will not be modified by the SMPE table. * Access: RW * * Note: Reserved when legacy bridge model is used and on Spectrum-2.
*/
MLXSW_ITEM32(reg, smid2, smpe_valid, 0x08, 20, 1);
/* reg_smid2_smpe * Switch multicast port to egress VID. * Access: RW * * Note: Reserved when legacy bridge model is used and on Spectrum-2.
*/
MLXSW_ITEM32(reg, smid2, smpe, 0x08, 0, 16);
/* reg_smid2_port * Local port memebership (1 bit per port). * Access: RW
*/
MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1);
/* reg_smid2_port_mask * Local port mask (1 bit per port). * Access: WO
*/
MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1);
/* reg_cwtp_local_port * Local port number * Not supported for CPU port * Access: Index
*/
MLXSW_ITEM32_LP(reg, cwtp, 0x00, 16, 0x00, 12);
/* reg_cwtp_traffic_class * Traffic Class to configure * Access: Index
*/
MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
/* reg_cwtp_profile_min * Minimum Average Queue Size of the profile in cells. * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);
/* reg_cwtp_profile_percent * Percentage of WRED and ECN marking for maximum Average Queue size * Range is 0 to 100, units of integer percentage * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
/* reg_cwtp_profile_max * Maximum Average Queue size of the profile in cells * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {
mlxsw_reg_cwtp_profile_min_set(payload, i,
MLXSW_REG_CWTP_MIN_VALUE);
mlxsw_reg_cwtp_profile_max_set(payload, i,
MLXSW_REG_CWTP_MIN_VALUE);
}
}
/* CWTPM - Congestion WRED ECN TClass and Pool Mapping * --------------------------------------------------- * The CWTPM register maps each egress port and traffic class to profile num.
*/ #define MLXSW_REG_CWTPM_ID 0x2803 #define MLXSW_REG_CWTPM_LEN 0x44
/* reg_cwtpm_local_port * Local port number * Not supported for CPU port * Access: Index
*/
MLXSW_ITEM32_LP(reg, cwtpm, 0x00, 16, 0x00, 12);
/* reg_cwtpm_traffic_class * Traffic Class to configure * Access: Index
*/
MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
/* reg_cwtpm_ew * Control enablement of WRED for traffic class: * 0 - Disable * 1 - Enable * Access: RW
*/
MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
/* reg_cwtpm_ee * Control enablement of ECN for traffic class: * 0 - Disable * 1 - Enable * Access: RW
*/
MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
/* reg_cwtpm_tcp_g * TCP Green Profile. * Index of the profile within {port, traffic class} to use. * 0 for disabling both WRED and ECN for this type of traffic. * Access: RW
*/
MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
/* reg_cwtpm_tcp_y * TCP Yellow Profile. * Index of the profile within {port, traffic class} to use. * 0 for disabling both WRED and ECN for this type of traffic. * Access: RW
*/
MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
/* reg_cwtpm_tcp_r * TCP Red Profile. * Index of the profile within {port, traffic class} to use. * 0 for disabling both WRED and ECN for this type of traffic. * Access: RW
*/
MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
/* reg_cwtpm_ntcp_g * Non-TCP Green Profile. * Index of the profile within {port, traffic class} to use. * 0 for disabling both WRED and ECN for this type of traffic. * Access: RW
*/
MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
/* reg_cwtpm_ntcp_y * Non-TCP Yellow Profile. * Index of the profile within {port, traffic class} to use. * 0 for disabling both WRED and ECN for this type of traffic. * Access: RW
*/
MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
/* reg_cwtpm_ntcp_r * Non-TCP Red Profile. * Index of the profile within {port, traffic class} to use. * 0 for disabling both WRED and ECN for this type of traffic. * Access: RW
*/
MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
/* reg_pgcr_default_action_pointer_base * Default action pointer base. Each region has a default action pointer * which is equal to default_action_pointer_base + region_id. * Access: RW
*/
MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24);
/* PPBT - Policy-Engine Port Binding Table * --------------------------------------- * This register is used for configuration of the Port Binding Table.
*/ #define MLXSW_REG_PPBT_ID 0x3002 #define MLXSW_REG_PPBT_LEN 0x14
/* reg_ppbt_local_port * Local port. Not including CPU port. * Access: Index
*/
MLXSW_ITEM32_LP(reg, ppbt, 0x00, 16, 0x00, 12);
/* reg_ppbt_g * group - When set, the binding is of an ACL group. When cleared, * the binding is of an ACL. * Must be set to 1 for Spectrum. * Access: RW
*/
MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);
/* reg_ppbt_acl_info * ACL/ACL group identifier. If the g bit is set, this field should hold * the acl_group_id, else it should hold the acl_id. * Access: RW
*/
MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
/* PACL - Policy-Engine ACL Register * --------------------------------- * This register is used for configuration of the ACL.
*/ #define MLXSW_REG_PACL_ID 0x3004 #define MLXSW_REG_PACL_LEN 0x70
/* reg_pacl_v * Valid. Setting the v bit makes the ACL valid. It should not be cleared * while the ACL is bounded to either a port, VLAN or ACL rule. * Access: RW
*/
MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
/* reg_pacl_acl_id * An identifier representing the ACL (managed by software) * Range 0 .. cap_max_acl_regions - 1 * Access: Index
*/
MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);
#define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16
/* reg_pacl_tcam_region_info * Opaque object that represents a TCAM region. * Obtained through PTAR register. * Access: RW
*/
MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,
MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
/* reg_pagt_size * Number of ACLs in the group. * Size 0 invalidates a group. * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) * Total number of ACLs in all groups must be lower or equal * to cap_max_acl_tot_groups * Note: a group which is binded must not be invalidated * Access: Index
*/
MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);
/* reg_pagt_acl_group_id * An identifier (numbered from 0..cap_max_acl_groups-1) representing * the ACL Group identifier (managed by software). * Access: Index
*/
MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
/* reg_pagt_multi * Multi-ACL * 0 - This ACL is the last ACL in the multi-ACL * 1 - This ACL is part of a multi-ACL * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false);
if (index >= size)
mlxsw_reg_pagt_size_set(payload, index + 1);
mlxsw_reg_pagt_multi_set(payload, index, multi);
mlxsw_reg_pagt_acl_id_set(payload, index, acl_id);
}
/* PTAR - Policy-Engine TCAM Allocation Register * --------------------------------------------- * This register is used for allocation of regions in the TCAM. * Note: Query method is not supported on this register.
*/ #define MLXSW_REG_PTAR_ID 0x3006 #define MLXSW_REG_PTAR_BASE_LEN 0x20 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \
MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)
enum mlxsw_reg_ptar_op { /* allocate a TCAM region */
MLXSW_REG_PTAR_OP_ALLOC, /* resize a TCAM region */
MLXSW_REG_PTAR_OP_RESIZE, /* deallocate TCAM region */
MLXSW_REG_PTAR_OP_FREE, /* test allocation */
MLXSW_REG_PTAR_OP_TEST,
};
/* reg_ptar_action_set_type * Type of action set to be used on this region. * For Spectrum and Spectrum-2, this is always type 2 - "flexible" * Access: WO
*/
MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);
/* reg_ptar_key_type * TCAM key type for the region. * Access: WO
*/
MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);
/* reg_ptar_region_size * TCAM region size. When allocating/resizing this is the requested size, * the response is the actual size. Note that actual size may be * larger than requested. * Allowed range 1 .. cap_max_rules-1 * Reserved during op deallocate. * Access: WO
*/
MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);
/* reg_ptar_region_id * Region identifier * Range 0 .. cap_max_regions-1 * Access: Index
*/
MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);
/* reg_ptar_tcam_region_info * Opaque object that represents the TCAM region. * Returned when allocating a region. * Provided by software for ACL generation and region deallocation and resize. * Access: RW
*/
MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,
MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
/* reg_ptar_flexible_key_id * Identifier of the Flexible Key. * Only valid if key_type == "FLEX_KEY" * The key size will be rounded up to one of the following values: * 9B, 18B, 36B, 54B. * This field is reserved for in resize operation. * Access: WO
*/
MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,
MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false);
/* PPRR - Policy-Engine Port Range Register * ---------------------------------------- * This register is used for configuring port range identification.
*/ #define MLXSW_REG_PPRR_ID 0x3008 #define MLXSW_REG_PPRR_LEN 0x14
/* reg_pprr_ipv4 * Apply port range register to IPv4 packets. * Access: RW
*/
MLXSW_ITEM32(reg, pprr, ipv4, 0x00, 31, 1);
/* reg_pprr_ipv6 * Apply port range register to IPv6 packets. * Access: RW
*/
MLXSW_ITEM32(reg, pprr, ipv6, 0x00, 30, 1);
/* reg_pprr_src * Apply port range register to source L4 ports. * Access: RW
*/
MLXSW_ITEM32(reg, pprr, src, 0x00, 29, 1);
/* reg_pprr_dst * Apply port range register to destination L4 ports. * Access: RW
*/
MLXSW_ITEM32(reg, pprr, dst, 0x00, 28, 1);
/* reg_pprr_tcp * Apply port range register to TCP packets. * Access: RW
*/
MLXSW_ITEM32(reg, pprr, tcp, 0x00, 27, 1);
/* reg_pprr_udp * Apply port range register to UDP packets. * Access: RW
*/
MLXSW_ITEM32(reg, pprr, udp, 0x00, 26, 1);
/* reg_pprr_register_index * Index of Port Range Register being accessed. * Range is 0..cap_max_acl_l4_port_range-1. * Access: Index
*/
MLXSW_ITEM32(reg, pprr, register_index, 0x00, 0, 8);
/* reg_prrr_port_range_min * Minimum port range for comparison. * Match is defined as: * port_range_min <= packet_port <= port_range_max. * Access: RW
*/
MLXSW_ITEM32(reg, pprr, port_range_min, 0x04, 16, 16);
/* reg_prrr_port_range_max * Maximum port range for comparison. * Access: RW
*/
MLXSW_ITEM32(reg, pprr, port_range_max, 0x04, 0, 16);
/* reg_ppbs_pbs_ptr * Index into the PBS table. * For Spectrum, the index points to the KVD Linear. * Access: Index
*/
MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);
/* reg_ppbs_system_port * Unique port identifier for the final destination of the packet. * Access: RW
*/
MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);
/* PRCR - Policy-Engine Rules Copy Register * ---------------------------------------- * This register is used for accessing rules within a TCAM region.
*/ #define MLXSW_REG_PRCR_ID 0x300D #define MLXSW_REG_PRCR_LEN 0x40
enum mlxsw_reg_prcr_op { /* Move rules. Moves the rules from "tcam_region_info" starting * at offset "offset" to "dest_tcam_region_info" * at offset "dest_offset."
*/
MLXSW_REG_PRCR_OP_MOVE, /* Copy rules. Copies the rules from "tcam_region_info" starting * at offset "offset" to "dest_tcam_region_info" * at offset "dest_offset."
*/
MLXSW_REG_PRCR_OP_COPY,
};
/* PEFA - Policy-Engine Extended Flexible Action Register * ------------------------------------------------------ * This register is used for accessing an extended flexible action entry * in the central KVD Linear Database.
*/ #define MLXSW_REG_PEFA_ID 0x300F #define MLXSW_REG_PEFA_LEN 0xB0
/* reg_pefa_index * Index in the KVD Linear Centralized Database. * Access: Index
*/
MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);
/* reg_pefa_a * Index in the KVD Linear Centralized Database. * Activity * For a new entry: set if ca=0, clear if ca=1 * Set if a packet lookup has hit on the specific entry * Access: RO
*/
MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1);
/* reg_pefa_ca * Clear activity * When write: activity is according to this field * When read: after reading the activity is cleared according to ca * Access: OP
*/
MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1);
#define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8
/* reg_pefa_flex_action_set * Action-set to perform when rule is matched. * Must be zero padded if action set is shorter. * Access: RW
*/
MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);
/* PEMRBT - Policy-Engine Multicast Router Binding Table Register * -------------------------------------------------------------- * This register is used for binding Multicast router to an ACL group * that serves the MC router. * This register is not supported by SwitchX/-2 and Spectrum.
*/ #define MLXSW_REG_PEMRBT_ID 0x3014 #define MLXSW_REG_PEMRBT_LEN 0x14
/* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 * ----------------------------------------------------- * This register is used for accessing rules within a TCAM region. * It is a new version of PTCE in order to support wider key, * mask and action within a TCAM region. This register is not supported * by SwitchX and SwitchX-2.
*/ #define MLXSW_REG_PTCE2_ID 0x3017 #define MLXSW_REG_PTCE2_LEN 0x1D8
/* reg_ptce2_a * Activity. Set if a packet lookup has hit on the specific entry. * To clear the "a" bit, use "clear activity" op or "clear on read" op. * Access: RO
*/
MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);
enum mlxsw_reg_ptce2_op { /* Read operation. */
MLXSW_REG_PTCE2_OP_QUERY_READ = 0, /* clear on read operation. Used to read entry * and clear Activity bit.
*/
MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, /* Write operation. Used to write a new entry to the table. * All R/W fields are relevant for new entry. Activity bit is set * for new entries - Note write with v = 0 will delete the entry.
*/
MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, /* Update action. Only action set will be updated. */
MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, /* Clear activity. A bit is cleared for the entry. */
MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2,
};
/* reg_ptce2_priority * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. * Note: priority does not have to be unique per rule. * Within a region, higher priority should have lower offset (no limitation * between regions in a multi-region). * Access: RW
*/
MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);
/* reg_ptce2_tcam_region_info * Opaque object that represents the TCAM region. * Access: Index
*/
MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,
MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
/* reg_ptce2_mask * mask- in the same size as key. A bit that is set directs the TCAM * to compare the corresponding bit in key. A bit that is clear directs * the TCAM to ignore the corresponding bit in key. * Access: RW
*/
MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,
MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
/* reg_perpt_erpt_index * Index to eRP table within the eRP bank. * Range is 0 .. cap_max_erp_table_bank_size - 1 * Access: Index
*/
MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8);
/* reg_perpt_bf_bypass * 0 - The eRP is used only if bloom filter state is set for the given * rule. * 1 - The eRP is used regardless of bloom filter state. * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass * Access: RW
*/
MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1);
/* reg_perpt_erp_id * eRP ID for use by the rules. * Access: RW
*/
MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4);
/* reg_perpt_erpt_base_bank * Base eRP table bank, points to head of erp_vector * Range is 0 .. cap_max_erp_table_banks - 1 * Access: OP
*/
MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4);
/* reg_perpt_erpt_base_index * Base index to eRP table within the eRP bank * Range is 0 .. cap_max_erp_table_bank_size - 1 * Access: OP
*/
MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8);
/* reg_perpt_erp_index_in_vector * eRP index in the vector. * Access: OP
*/
MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4);
/* reg_perpt_mask * Mask * 0 - A-TCAM will ignore the bit in key * 1 - A-TCAM will compare the bit in key * Access: RW
*/
MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
/* PERAR - Policy-Engine Region Association Register * ------------------------------------------------- * This register associates a hw region for region_id's. Changing on the fly * is supported by the device.
*/ #define MLXSW_REG_PERAR_ID 0x3026 #define MLXSW_REG_PERAR_LEN 0x08
/* reg_perar_hw_region * HW Region * Range 0 .. cap_max_regions-1 * Default: hw_region = region_id * For a 8 key block region, 2 consecutive regions are used * For a 12 key block region, 3 consecutive regions are used * Access: RW
*/
MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16);
/* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 * ----------------------------------------------------- * This register is a new version of PTCE-V2 in order to support the * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum.
*/ #define MLXSW_REG_PTCE3_ID 0x3027 #define MLXSW_REG_PTCE3_LEN 0xF0
enum mlxsw_reg_ptce3_op { /* Write operation. Used to write a new entry to the table. * All R/W fields are relevant for new entry. Activity bit is set * for new entries. Write with v = 0 will delete the entry. Must * not be used if an entry exists.
*/
MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, /* Update operation */
MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, /* Read operation */
MLXSW_REG_PTCE3_OP_QUERY_READ = 0,
};
/* reg_ptce3_priority * Priority of the rule. Higher values win. * For Spectrum-2 range is 1..cap_kvd_size - 1 * Note: Priority does not have to be unique per rule. * Access: RW
*/
MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);
/* reg_ptce3_tcam_region_info * Opaque object that represents the TCAM region. * Access: Index
*/
MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10,
MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
/* reg_ptce3_flex2_key_blocks * ACL key. The key must be masked according to eRP (if exists) or * according to master mask. * Access: Index
*/
MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20,
MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
/* reg_ptce3_delta_start * Start point of delta_value and delta_mask, in bits. Must not exceed * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. * Access: Index
*/
MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10);
/* reg_ptce3_delta_mask * Delta mask. * 0 - Ignore relevant bit in delta_value * 1 - Compare relevant bit in delta_value * Delta mask must not be set for reserved fields in the key blocks. * Note: No delta when no eRPs. Thus, for regions with * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. * Access: Index
*/
MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8);
/* reg_ptce3_delta_value * Delta value. * Bits which are masked by delta_mask must be 0. * Access: Index
*/
MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8);
/* reg_ptce3_prune_vector * Pruning vector relative to the PERPT.erp_id. * Used for reducing lookups. * 0 - NEED: Do a lookup using the eRP. * 1 - PRUNE: Do not perform a lookup using the eRP. * Maybe be modified by PEAPBL and PEAPBM. * Note: In Spectrum-2, a region of 8 key blocks must be set to either * all 1's or all 0's. * Access: RW
*/
MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1);
/* reg_ptce3_prune_ctcam * Pruning on C-TCAM. Used for reducing lookups. * 0 - NEED: Do a lookup in the C-TCAM. * 1 - PRUNE: Do not perform a lookup in the C-TCAM. * Access: RW
*/
MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1);
/* reg_ptce3_large_exists * Large entry key ID exists. * Within the region: * 0 - SINGLE: The large_entry_key_id is not currently in use. * For rule insert: The MSB of the key (blocks 6..11) will be added. * For rule delete: The MSB of the key will be removed. * 1 - NON_SINGLE: The large_entry_key_id is currently in use. * For rule insert: The MSB of the key (blocks 6..11) will not be added. * For rule delete: The MSB of the key will not be removed. * Access: WO
*/
MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1);
/* reg_ptce3_large_entry_key_id * Large entry key ID. * A key for 12 key blocks rules. Reserved when region has less than 12 key * blocks. Must be different for different keys which have the same common * 6 key blocks (MSB, blocks 6..11) key within a region. * Range is 0..cap_max_pe_large_key_id - 1 * Access: RW
*/
MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24);
/* reg_ptce3_action_pointer * Pointer to action. * Range is 0..cap_max_kvd_action_sets - 1 * Access: RW
*/
MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24);
/* PERCR - Policy-Engine Region Configuration Register * --------------------------------------------------- * This register configures the region parameters. The region_id must be * allocated.
*/ #define MLXSW_REG_PERCR_ID 0x302A #define MLXSW_REG_PERCR_LEN 0x80
/* reg_percr_region_id * Region identifier. * Range 0..cap_max_regions-1 * Access: Index
*/
MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16);
/* reg_percr_atcam_ignore_prune * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. * Access: RW
*/
MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1);
/* reg_percr_ctcam_ignore_prune * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. * Access: RW
*/
MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1);
/* reg_percr_bf_bypass * Bloom filter bypass. * 0 - Bloom filter is used (default) * 1 - Bloom filter is bypassed. The bypass is an OR condition of * region_id or eRP. See PERPT.bf_bypass * Access: RW
*/
MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1);
/* reg_percr_master_mask * Master mask. Logical OR mask of all masks of all rules of a region * (both A-TCAM and C-TCAM). When there are no eRPs * (erpt_pointer_valid = 0), then this provides the mask. * Access: RW
*/
MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96);
/* PERERP - Policy-Engine Region eRP Register * ------------------------------------------ * This register configures the region eRP. The region_id must be * allocated.
*/ #define MLXSW_REG_PERERP_ID 0x302B #define MLXSW_REG_PERERP_LEN 0x1C
/* reg_pererp_erpt_bank_pointer * Pointer to eRP table bank. May be modified at any time. * Range 0..cap_max_erp_table_banks-1 * Reserved when erpt_pointer_valid = 0
*/
MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4);
/* reg_pererp_erpt_pointer * Pointer to eRP table within the eRP bank. Can be changed for an * existing region. * Range 0..cap_max_erp_table_size-1 * Reserved when erpt_pointer_valid = 0 * Access: RW
*/
MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8);
/* reg_pererp_erpt_vector * Vector of allowed eRP indexes starting from erpt_pointer within the * erpt_bank_pointer. Next entries will be in next bank. * Note that eRP index is used and not eRP ID. * Reserved when erpt_pointer_valid = 0 * Access: RW
*/
MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1);
/* reg_pererp_master_rp_id * Master RP ID. When there are no eRPs, then this provides the eRP ID * for the lookup. Can be changed for an existing region. * Reserved when erpt_pointer_valid = 1 * Access: RW
*/
MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4);
/* IEDR - Infrastructure Entry Delete Register * ---------------------------------------------------- * This register is used for deleting entries from the entry tables. * It is legitimate to attempt to delete a nonexisting entry (the device will * respond as a good flow).
*/ #define MLXSW_REG_IEDR_ID 0x3804 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \
MLXSW_REG_IEDR_REC_LEN * \
MLXSW_REG_IEDR_REC_MAX_COUNT)
/* reg_iedr_rec_size * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. * Access: OP
*/
MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13,
MLXSW_REG_IEDR_REC_LEN, 0x00, false);
/* reg_iedr_rec_index_start * Resource index start. * Access: OP
*/
MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24,
MLXSW_REG_IEDR_REC_LEN, 0x04, false);
/* QPTS - QoS Priority Trust State Register * ---------------------------------------- * This register controls the port policy to calculate the switch priority and * packet color based on incoming packet fields.
*/ #define MLXSW_REG_QPTS_ID 0x4002 #define MLXSW_REG_QPTS_LEN 0x8
/* QPCR - QoS Policer Configuration Register * ----------------------------------------- * The QPCR register is used to create policers - that limit * the rate of bytes or packets via some trap group.
*/ #define MLXSW_REG_QPCR_ID 0x4004 #define MLXSW_REG_QPCR_LEN 0x28
/* reg_qpcr_color_aware * Is the policer aware of colors. * Must be 0 (unaware) for cpu port. * Access: RW for unbounded policer. RO for bounded policer.
*/
MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);
/* reg_qpcr_bytes * Is policer limit is for bytes per sec or packets per sec. * 0 - packets * 1 - bytes * Access: RW for unbounded policer. RO for bounded policer.
*/
MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);
/* reg_qpcr_rate_type * Policer can have one limit (single rate) or 2 limits with specific operation * for packets that exceed the lower rate but not the upper one. * (For cpu port must be single rate) * Access: RW for unbounded policer. RO for bounded policer.
*/
MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);
/* reg_qpc_cbs * Policer's committed burst size. * The policer is working with time slices of 50 nano sec. By default every * slice is granted the proportionate share of the committed rate. If we want to * allow a slice to exceed that share (while still keeping the rate per sec) we * can allow burst. The burst size is between the default proportionate share * (and no lower than 8) to 32Gb. (Even though giving a number higher than the * committed rate will result in exceeding the rate). The burst size must be a * log of 2 and will be determined by 2^cbs. * Access: RW
*/
MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);
/* reg_qpcr_cir * Policer's committed rate. * The rate used for sungle rate, the lower rate for double rate. * For bytes limits, the rate will be this value * the unit from ir_units. * (Resolution error is up to 1%). * Access: RW
*/
MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);
/* reg_qpcr_eir * Policer's exceed rate. * The higher rate for double rate, reserved for single rate. * Lower rate for double rate policer. * For bytes limits, the rate will be this value * the unit from ir_units. * (Resolution error is up to 1%). * Access: RW
*/
MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);
#define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2
/* reg_qpcr_exceed_action. * What to do with packets between the 2 limits for double rate. * Access: RW for unbounded policer. RO for bounded policer.
*/
MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);
enum mlxsw_reg_qpcr_action { /* Discard */
MLXSW_REG_QPCR_ACTION_DISCARD = 1, /* Forward and set color to red. * If the packet is intended to cpu port, it will be dropped.
*/
MLXSW_REG_QPCR_ACTION_FORWARD = 2,
};
/* reg_qpcr_violate_action * What to do with packets that cross the cir limit (for single rate) or the eir * limit (for double rate). * Access: RW for unbounded policer. RO for bounded policer.
*/
MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
/* reg_qpcr_violate_count * Counts the number of times violate_action happened on this PID. * Access: RW
*/
MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64);
/* QTCT - QoS Switch Traffic Class Table * ------------------------------------- * Configures the mapping between the packet switch priority and the * traffic class on the transmit port.
*/ #define MLXSW_REG_QTCT_ID 0x400A #define MLXSW_REG_QTCT_LEN 0x08
/* reg_qtct_local_port * Local port number. * Access: Index * * Note: CPU port is not supported.
*/
MLXSW_ITEM32_LP(reg, qtct, 0x00, 16, 0x00, 12);
/* reg_qtct_sub_port * Virtual port within the physical port. * Should be set to 0 when virtual ports are not enabled on the port. * Access: Index
*/
MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
/* reg_qeec_element_hierarchy * 0 - Port * 1 - Group * 2 - Subgroup * 3 - Traffic Class * Access: Index
*/
MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
/* reg_qeec_element_index * The index of the element in the hierarchy. * Access: Index
*/
MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
/* reg_qeec_next_element_index * The index of the next (lower) element in the hierarchy. * Access: RW * * Note: Reserved for element_hierarchy 0.
*/
MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
/* reg_qeec_mise * Min shaper configuration enable. Enables configuration of the min * shaper on this ETS element * 0 - Disable * 1 - Enable * Access: RW
*/
MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1);
/* reg_qeec_ptps * PTP shaper * 0: regular shaper mode * 1: PTP oriented shaper * Allowed only for hierarchy 0 * Not supported for CPU port * Note that ptps mode may affect the shaper rates of all hierarchies * Supported only on Spectrum-1 * Access: RW
*/
MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1);
/* reg_qeec_pb * Packets or bytes mode. * 0 - Bytes mode * 1 - Packets mode * Access: RW * * Note: Used for max shaper configuration. For Spectrum, packets mode * is supported only for traffic classes of CPU port.
*/
MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
/* The smallest permitted min shaper rate. */ #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */
/* reg_qeec_min_shaper_rate * Min shaper information rate. * For CPU port, can only be configured for port hierarchy. * When in bytes mode, value is specified in units of 1000bps. * Access: RW
*/
MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28);
/* reg_qeec_mase * Max shaper configuration enable. Enables configuration of the max * shaper on this ETS element. * 0 - Disable * 1 - Enable * Access: RW
*/
MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
/* The largest max shaper value possible to disable the shaper. */ #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */
/* reg_qeec_max_shaper_rate * Max shaper information rate. * For CPU port, can only be configured for port hierarchy. * When in bytes mode, value is specified in units of 1000bps. * Access: RW
*/
MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31);
/* reg_qeec_de * DWRR configuration enable. Enables configuration of the dwrr and * dwrr_weight. * 0 - Disable * 1 - Enable * Access: RW
*/
MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
/* reg_qeec_dwrr * Transmission selection algorithm to use on the link going down from * the ETS element. * 0 - Strict priority * 1 - DWRR * Access: RW
*/
MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
/* reg_qeec_dwrr_weight * DWRR weight on the link going down from the ETS element. The * percentage of bandwidth guaranteed to an ETS element within * its hierarchy. The sum of all weights across all ETS elements * within one hierarchy should be equal to 100. Reserved when * transmission selection algorithm is strict priority. * Access: RW
*/
MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
/* reg_qeec_max_shaper_bs * Max shaper burst size * Burst size is 2^max_shaper_bs * 512 bits * For Spectrum-1: Range is: 5..25 * For Spectrum-2: Range is: 11..25 * Reserved when ptps = 1 * Access: RW
*/
MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6);
/* reg_qrwe_local_port * Local port number. * Access: Index * * Note: CPU port is supported. No support for router port.
*/
MLXSW_ITEM32_LP(reg, qrwe, 0x00, 16, 0x00, 12);
/* reg_qpdsm_local_port * Local Port. Supported for data packets from CPU port. * Access: Index
*/
MLXSW_ITEM32_LP(reg, qpdsm, 0x00, 16, 0x00, 12);
/* reg_qpdsm_prio_entry_color0_e * Enable update of the entry for color 0 and a given port. * Access: WO
*/
MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e,
MLXSW_REG_QPDSM_BASE_LEN, 31, 1,
MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
/* reg_qpdsm_prio_entry_color0_dscp * DSCP field in the outer label of the packet for color 0 and a given port. * Reserved when e=0. * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp,
MLXSW_REG_QPDSM_BASE_LEN, 24, 6,
MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
/* reg_qpdsm_prio_entry_color1_e * Enable update of the entry for color 1 and a given port. * Access: WO
*/
MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e,
MLXSW_REG_QPDSM_BASE_LEN, 23, 1,
MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
/* reg_qpdsm_prio_entry_color1_dscp * DSCP field in the outer label of the packet for color 1 and a given port. * Reserved when e=0. * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp,
MLXSW_REG_QPDSM_BASE_LEN, 16, 6,
MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
/* reg_qpdsm_prio_entry_color2_e * Enable update of the entry for color 2 and a given port. * Access: WO
*/
MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e,
MLXSW_REG_QPDSM_BASE_LEN, 15, 1,
MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
/* reg_qpdsm_prio_entry_color2_dscp * DSCP field in the outer label of the packet for color 2 and a given port. * Reserved when e=0. * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
MLXSW_REG_QPDSM_BASE_LEN, 8, 6,
MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
/* QPDP - QoS Port DSCP to Priority Mapping Register * ------------------------------------------------- * This register controls the port default Switch Priority and Color. The * default Switch Priority and Color are used for frames where the trust state * uses default values. All member ports of a LAG should be configured with the * same default values.
*/ #define MLXSW_REG_QPDP_ID 0x4007 #define MLXSW_REG_QPDP_LEN 0x8
/* QPDPM - QoS Port DSCP to Priority Mapping Register * -------------------------------------------------- * This register controls the mapping from DSCP field to * Switch Priority for IP packets.
*/ #define MLXSW_REG_QPDPM_ID 0x4013 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \
MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \
MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT)
/* reg_qpdpm_local_port * Local Port. Supported for data packets from CPU port. * Access: Index
*/
MLXSW_ITEM32_LP(reg, qpdpm, 0x00, 16, 0x00, 12);
/* reg_qpdpm_dscp_e * Enable update of the specific entry. When cleared, the switch_prio and color * fields are ignored and the previous switch_prio and color values are * preserved. * Access: WO
*/
MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1,
MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
/* reg_qpdpm_dscp_prio * The new Switch Priority value for the relevant DSCP value. * Access: RW
*/
MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
MLXSW_REG_QPDPM_BASE_LEN, 0, 4,
MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
/* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register * ------------------------------------------------------------------ * This register configures if the Switch Priority to Traffic Class mapping is * based on Multicast packet indication. If so, then multicast packets will get * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by * QTCT. * By default, Switch Priority to Traffic Class mapping is not based on * Multicast packet indication.
*/ #define MLXSW_REG_QTCTM_ID 0x401A #define MLXSW_REG_QTCTM_LEN 0x08
/* reg_qtctm_local_port * Local port number. * No support for CPU port. * Access: Index
*/
MLXSW_ITEM32_LP(reg, qtctm, 0x00, 16, 0x00, 12);
/* reg_qtctm_mc * Multicast Mode * Whether Switch Priority to Traffic Class mapping is based on Multicast packet * indication (default is 0, not based on Multicast packet indication).
*/
MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
/* reg_qpsc_shaper_inc * Number of tokens added to shaper on each update. * Units of 8B. * Access: RW
*/
MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5);
/* reg_qpsc_shaper_bs * Max shaper Burst size. * Burst size is 2 ^ max_shaper_bs * 512 [bits] * Range is: 5..25 (from 2KB..2GB) * Access: RW
*/
MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6);
/* reg_qpsc_ptsc_we * Write enable to port_to_shaper_credits. * Access: WO
*/
MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1);
/* reg_qpsc_port_to_shaper_credits * For split ports: range 1..57 * For non-split ports: range 1..112 * Written only when ptsc_we is set. * Access: RW
*/
MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8);
/* reg_qpsc_ing_timestamp_inc * Ingress timestamp increment. * 2's complement. * The timestamp of MTPPTR at ingress will be incremented by this value. Global * value for all ports. * Same units as used by MTPPTR. * Access: RW
*/
MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32);
/* reg_qpsc_egr_timestamp_inc * Egress timestamp increment. * 2's complement. * The timestamp of MTPPTR at egress will be incremented by this value. Global * value for all ports. * Same units as used by MTPPTR. * Access: RW
*/
MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32);
/* PMLP - Ports Module to Local Port Register * ------------------------------------------ * Configures the assignment of modules to local ports.
*/ #define MLXSW_REG_PMLP_ID 0x5002 #define MLXSW_REG_PMLP_LEN 0x40
/* reg_pmlp_rxtx * 0 - Tx value is used for both Tx and Rx. * 1 - Rx value is taken from a separte field. * Access: RW
*/
MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
/* reg_pmlp_local_port * Local port number. * Access: Index
*/
MLXSW_ITEM32_LP(reg, pmlp, 0x00, 16, 0x00, 12);
/* reg_pmlp_width * 0 - Unmap local port. * 1 - Lane 0 is used. * 2 - Lanes 0 and 1 are used. * 4 - Lanes 0, 1, 2 and 3 are used. * 8 - Lanes 0-7 are used. * Access: RW
*/
MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
/* reg_pmlp_slot_index * Module number. * Slot_index * Slot_index = 0 represent the onboard (motherboard). * In case of non-modular system only slot_index = 0 is available. * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, pmlp, slot_index, 0x04, 8, 4, 0x04, 0x00, false);
/* reg_pmlp_tx_lane * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false);
/* reg_pmlp_rx_lane * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is * equal to Tx lane. * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false);
/* PMTU - Port MTU Register * ------------------------ * Configures and reports the port MTU.
*/ #define MLXSW_REG_PMTU_ID 0x5003 #define MLXSW_REG_PMTU_LEN 0x10
/* reg_pmtu_local_port * Local port number. * Access: Index
*/
MLXSW_ITEM32_LP(reg, pmtu, 0x00, 16, 0x00, 12);
/* reg_pmtu_max_mtu * Maximum MTU. * When port type (e.g. Ethernet) is configured, the relevant MTU is * reported, otherwise the minimum between the max_mtu of the different * types is reported. * Access: RO
*/
MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
/* reg_pmtu_admin_mtu * MTU value to set port to. Must be smaller or equal to max_mtu. * Note: If port type is Infiniband, then port must be disabled, when its * MTU is set. * Access: RW
*/
MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
/* reg_pmtu_oper_mtu * The actual MTU configured on the port. Packets exceeding this size * will be dropped. * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband * oper_mtu might be smaller than admin_mtu. * Access: RO
*/
MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
/* PTYS - Port Type and Speed Register * ----------------------------------- * Configures and reports the port speed type. * * Note: When set while the link is up, the changes will not take effect * until the port transitions from down to up state.
*/ #define MLXSW_REG_PTYS_ID 0x5004 #define MLXSW_REG_PTYS_LEN 0x40
/* reg_ptys_eth_proto_cap * Ethernet port supported speeds and protocols. * Access: RO
*/
MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
/* reg_ptys_ext_eth_proto_admin * Extended speed and protocol to set port to. * Access: RW
*/
MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32);
/* reg_ptys_eth_proto_admin * Speed and protocol to set port to. * Access: RW
*/
MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
/* reg_ptys_ext_eth_proto_oper * The extended current speed and protocol configured for the port. * Access: RO
*/
MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32);
/* reg_ptys_eth_proto_oper * The current speed and protocol configured for the port. * Access: RO
*/
MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
staticinlinevoid mlxsw_reg_ptys_eth_unpack(char *payload,
u32 *p_eth_proto_cap,
u32 *p_eth_proto_admin,
u32 *p_eth_proto_oper)
{ if (p_eth_proto_cap)
*p_eth_proto_cap =
mlxsw_reg_ptys_eth_proto_cap_get(payload); if (p_eth_proto_admin)
*p_eth_proto_admin =
mlxsw_reg_ptys_eth_proto_admin_get(payload); if (p_eth_proto_oper)
*p_eth_proto_oper =
mlxsw_reg_ptys_eth_proto_oper_get(payload);
}
staticinlinevoid mlxsw_reg_ptys_ext_eth_unpack(char *payload,
u32 *p_eth_proto_cap,
u32 *p_eth_proto_admin,
u32 *p_eth_proto_oper)
{ if (p_eth_proto_cap)
*p_eth_proto_cap =
mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); if (p_eth_proto_admin)
*p_eth_proto_admin =
mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); if (p_eth_proto_oper)
*p_eth_proto_oper =
mlxsw_reg_ptys_ext_eth_proto_oper_get(payload);
}
/* PPAD - Port Physical Address Register * ------------------------------------- * The PPAD register configures the per port physical MAC address.
*/ #define MLXSW_REG_PPAD_ID 0x5005 #define MLXSW_REG_PPAD_LEN 0x10
/* reg_ppad_single_base_mac * 0: base_mac, local port should be 0 and mac[7:0] is * reserved. HW will set incremental * 1: single_mac - mac of the local_port * Access: RW
*/
MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
/* reg_ppad_local_port * port number, if single_base_mac = 0 then local_port is reserved * Access: RW
*/
MLXSW_ITEM32_LP(reg, ppad, 0x00, 16, 0x00, 24);
/* reg_ppad_mac * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. * If single_base_mac = 1 - the per port MAC address * Access: RW
*/
MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
/* PAOS - Ports Administrative and Operational Status Register * ----------------------------------------------------------- * Configures and retrieves per port administrative and operational status.
*/ #define MLXSW_REG_PAOS_ID 0x5006 #define MLXSW_REG_PAOS_LEN 0x10
/* reg_paos_swid * Switch partition ID with which to associate the port. * Note: while external ports uses unique local port numbers (and thus swid is * redundant), router ports use the same local port number where swid is the * only indication for the relevant port. * Access: Index
*/
MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
/* reg_paos_local_port * Local port number. * Access: Index
*/
MLXSW_ITEM32_LP(reg, paos, 0x00, 16, 0x00, 12);
/* reg_paos_admin_status * Port administrative state (the desired state of the port): * 1 - Up. * 2 - Down. * 3 - Up once. This means that in case of link failure, the port won't go * into polling mode, but will wait to be re-enabled by software. * 4 - Disabled by system. Can only be set by hardware. * Access: RW
*/
MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
/* reg_paos_oper_status * Port operational state (the current state): * 1 - Up. * 2 - Down. * 3 - Down by port failure. This means that the device will not let the * port up again until explicitly specified by software. * Access: RO
*/
MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
/* reg_paos_ase * Admin state update enabled. * Access: WO
*/
MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
/* reg_paos_ee * Event update enable. If this bit is set, event generation will be * updated based on the e field. * Access: WO
*/
MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
/* reg_paos_e * Event generation on operational state change: * 0 - Do not generate event. * 1 - Generate Event. * 2 - Generate Single Event. * Access: RW
*/
MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
/* PFCC - Ports Flow Control Configuration Register * ------------------------------------------------ * Configures and retrieves the per port flow control configuration.
*/ #define MLXSW_REG_PFCC_ID 0x5007 #define MLXSW_REG_PFCC_LEN 0x20
/* reg_pfcc_local_port * Local port number. * Access: Index
*/
MLXSW_ITEM32_LP(reg, pfcc, 0x00, 16, 0x00, 12);
/* reg_pfcc_pnat * Port number access type. Determines the way local_port is interpreted: * 0 - Local port number. * 1 - IB / label port number. * Access: Index
*/
MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
/* reg_pfcc_shl_cap * Send to higher layers capabilities: * 0 - No capability of sending Pause and PFC frames to higher layers. * 1 - Device has capability of sending Pause and PFC frames to higher * layers. * Access: RO
*/
MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
/* reg_pfcc_shl_opr * Send to higher layers operation: * 0 - Pause and PFC frames are handled by the port (default). * 1 - Pause and PFC frames are handled by the port and also sent to * higher layers. Only valid if shl_cap = 1. * Access: RW
*/
MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
/* reg_pfcc_ppan * Pause policy auto negotiation. * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. * 1 - Enabled. When auto-negotiation is performed, set the Pause policy * based on the auto-negotiation resolution. * Access: RW * * Note: The auto-negotiation advertisement is set according to pptx and * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
*/
MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
/* reg_pfcc_prio_mask_tx * Bit per priority indicating if Tx flow control policy should be * updated based on bit pfctx. * Access: WO
*/
MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
/* reg_pfcc_prio_mask_rx * Bit per priority indicating if Rx flow control policy should be * updated based on bit pfcrx. * Access: WO
*/
MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
/* reg_pfcc_pptx * Admin Pause policy on Tx. * 0 - Never generate Pause frames (default). * 1 - Generate Pause frames according to Rx buffer threshold. * Access: RW
*/
MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
/* reg_pfcc_aptx * Active (operational) Pause policy on Tx. * 0 - Never generate Pause frames. * 1 - Generate Pause frames according to Rx buffer threshold. * Access: RO
*/
MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
/* reg_pfcc_pfctx * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: * 0 - Never generate priority Pause frames on the specified priority * (default). * 1 - Generate priority Pause frames according to Rx buffer threshold on * the specified priority. * Access: RW * * Note: pfctx and pptx must be mutually exclusive.
*/
MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
/* reg_ppcnt_swid * For HCA: must be always 0. * Switch partition ID to associate port with. * Switch partitions are numbered from 0 to 7 inclusively. * Switch partition 254 indicates stacking ports. * Switch partition 255 indicates all switch partitions. * Only valid on Set() operation with local_port=255. * Access: Index
*/
MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
/* reg_ppcnt_local_port * Local port number. * Access: Index
*/
MLXSW_ITEM32_LP(reg, ppcnt, 0x00, 16, 0x00, 12);
/* reg_ppcnt_pnat * Port number access type: * 0 - Local port number * 1 - IB port number * Access: Index
*/
MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
/* reg_ppcnt_grp * Performance counter group. * Group 63 indicates all groups. Only valid on Set() operation with * clr bit set. * 0x0: IEEE 802.3 Counters * 0x1: RFC 2863 Counters * 0x2: RFC 2819 Counters * 0x3: RFC 3635 Counters * 0x5: Ethernet Extended Counters * 0x6: Ethernet Discard Counters * 0x8: Link Level Retransmission Counters * 0x10: Per Priority Counters * 0x11: Per Traffic Class Counters * 0x12: Physical Layer Counters * 0x13: Per Traffic Class Congestion Counters * Access: Index
*/
MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
/* reg_ppcnt_clr * Clear counters. Setting the clr bit will reset the counter value * for all counters in the counter group. This bit can be set * for both Set() and Get() operation. * Access: OP
*/
MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
/* reg_ppcnt_lp_gl * Local port global variable. * 0: local_port 255 = all ports of the device. * 1: local_port indicates local port number for all ports. * Access: OP
*/
MLXSW_ITEM32(reg, ppcnt, lp_gl, 0x04, 30, 1);
/* reg_ppcnt_prio_tc * Priority for counter set that support per priority, valid values: 0-7. * Traffic class for counter set that support per traffic class, * valid values: 0- cap_max_tclass-1 . * For HCA: cap_max_tclass is always 8. * Otherwise must be 0. * Access: Index
*/
MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
/* reg_ppcnt_tc_transmit_queue * Contains the transmit queue depth in cells of traffic class * selected by prio_tc and the port selected by local_port. * The field cannot be cleared. * Access: RO
*/
MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue,
MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
/* reg_ppcnt_tc_no_buffer_discard_uc * The number of unicast packets dropped due to lack of shared * buffer resources. * Access: RO
*/
MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc,
MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
/* Ethernet Per Traffic Class Congestion Group Counters */
/* reg_pptb_mm * Mapping mode. * 0 - Map both unicast and multicast packets to the same buffer. * 1 - Map only unicast packets. * 2 - Map only multicast packets. * Access: Index * * Note: SwitchX-2 only supports the first option.
*/
MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
/* reg_pptb_local_port * Local port number. * Access: Index
*/
MLXSW_ITEM32_LP(reg, pptb, 0x00, 16, 0x00, 12);
/* reg_pptb_um * Enables the update of the untagged_buf field. * Access: RW
*/
MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
/* reg_pptb_pm * Enables the update of the prio_to_buff field. * Bit <i> is a flag for updating the mapping for switch priority <i>. * Access: RW
*/
MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
/* reg_pptb_prio_to_buff * Mapping of switch priority <i> to one of the allocated receive port * buffers. * Access: RW
*/
MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
/* reg_pptb_pm_msb * Enables the update of the prio_to_buff field. * Bit <i> is a flag for updating the mapping for switch priority <i+8>. * Access: RW
*/
MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
/* reg_pptb_untagged_buff * Mapping of untagged frames to one of the allocated receive port buffers. * Access: RW * * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for * Spectrum, as it maps untagged packets based on the default switch priority.
*/
MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
/* reg_pptb_prio_to_buff_msb * Mapping of switch priority <i+8> to one of the allocated receive port * buffers. * Access: RW
*/
MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
/* PBMC - Port Buffer Management Control Register * ---------------------------------------------- * The PBMC register configures and retrieves the port packet buffer * allocation for different Prios, and the Pause threshold management.
*/ #define MLXSW_REG_PBMC_ID 0x500C #define MLXSW_REG_PBMC_LEN 0x6C
/* reg_pbmc_local_port * Local port number. * Access: Index
*/
MLXSW_ITEM32_LP(reg, pbmc, 0x00, 16, 0x00, 12);
/* reg_pbmc_xoff_timer_value * When device generates a pause frame, it uses this value as the pause * timer (time for the peer port to pause in quota-512 bit time). * Access: RW
*/
MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
/* reg_pbmc_xoff_refresh * The time before a new pause frame should be sent to refresh the pause RW * state. Using the same units as xoff_timer_value above (in quota-512 bit * time). * Access: RW
*/
MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
#define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
/* reg_pbmc_buf_lossy * The field indicates if the buffer is lossy. * 0 - Lossless * 1 - Lossy * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
/* reg_pbmc_buf_epsb * Eligible for Port Shared buffer. * If epsb is set, packets assigned to buffer are allowed to insert the port * shared buffer. * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
/* reg_pbmc_buf_size * The part of the packet buffer array is allocated for the specific buffer. * Units are represented in cells. * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
/* reg_pbmc_buf_xoff_threshold * Once the amount of data in the buffer goes above this value, device * starts sending PFC frames for all priorities associated with the * buffer. Units are represented in cells. Reserved in case of lossy * buffer. * Access: RW * * Note: In Spectrum, reserved for buffer[9].
*/
MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
0x08, 0x04, false);
/* reg_pbmc_buf_xon_threshold * When the amount of data in the buffer goes below this value, device * stops sending PFC frames for the priorities associated with the * buffer. Units are represented in cells. Reserved in case of lossy * buffer. * Access: RW * * Note: In Spectrum, reserved for buffer[9].
*/
MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
0x08, 0x04, false);
/* PSPA - Port Switch Partition Allocation * --------------------------------------- * Controls the association of a port with a switch partition and enables * configuring ports as stacking ports.
*/ #define MLXSW_REG_PSPA_ID 0x500D #define MLXSW_REG_PSPA_LEN 0x8
/* reg_pspa_local_port * Local port number. * Access: Index
*/
MLXSW_ITEM32_LP(reg, pspa, 0x00, 16, 0x00, 0);
/* reg_pspa_sub_port * Virtual port within the local port. Set to 0 when virtual ports are * disabled on the local port. * Access: Index
*/
MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
/* PMAOS - Ports Module Administrative and Operational Status * ---------------------------------------------------------- * This register configures and retrieves the per module status.
*/ #define MLXSW_REG_PMAOS_ID 0x5012 #define MLXSW_REG_PMAOS_LEN 0x10
/* reg_pmaos_rst * Module reset toggle. * Note: Setting reset while module is plugged-in will result in transition to * "initializing" operational state. * Access: OP
*/
MLXSW_ITEM32(reg, pmaos, rst, 0x00, 31, 1);
enum mlxsw_reg_pmaos_admin_status {
MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED = 1,
MLXSW_REG_PMAOS_ADMIN_STATUS_DISABLED = 2, /* If the module is active and then unplugged, or experienced an error * event, the operational status should go to "disabled" and can only * be enabled upon explicit enable command.
*/
MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED_ONCE = 3,
};
/* reg_pmaos_admin_status * Module administrative state (the desired state of the module). * Note: To disable a module, all ports associated with the port must be * administatively down first. * Access: RW
*/
MLXSW_ITEM32(reg, pmaos, admin_status, 0x00, 8, 4);
/* reg_pmaos_ase * Admin state update enable. * If this bit is set, admin state will be updated based on admin_state field. * Only relevant on Set() operations. * Access: WO
*/
MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1);
/* reg_pmaos_ee * Event update enable. * If this bit is set, event generation will be updated based on the e field. * Only relevant on Set operations. * Access: WO
*/
MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1);
/* reg_pplr_local_port * Local port number. * Access: Index
*/
MLXSW_ITEM32_LP(reg, pplr, 0x00, 16, 0x00, 12);
/* Phy local loopback. When set the port's egress traffic is looped back * to the receiver and the port transmitter is disabled.
*/ #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1)
/* PMTDB - Port Module To local DataBase Register * ---------------------------------------------- * The PMTDB register allows to query the possible module<->local port * mapping than can be used in PMLP. It does not represent the actual/current * mapping of the local to module. Actual mapping is only defined by PMLP.
*/ #define MLXSW_REG_PMTDB_ID 0x501A #define MLXSW_REG_PMTDB_LEN 0x40
/* reg_pmtdb_port_num * The local_port value which can be assigned to the module. * In case of more than one port, port<x> represent the /<x> port of * the module. * Access: RO
*/
MLXSW_ITEM16_INDEXED(reg, pmtdb, port_num, 0x04, 0, 10, 0x02, 0x00, false);
/* PMECR - Ports Mapping Event Configuration Register * -------------------------------------------------- * The PMECR register is used to enable/disable event triggering * in case of local port mapping change.
*/ #define MLXSW_REG_PMECR_ID 0x501B #define MLXSW_REG_PMECR_LEN 0x20
/* reg_pmecr_local_port * Local port number. * Access: Index
*/
MLXSW_ITEM32_LP(reg, pmecr, 0x00, 16, 0x00, 12);
/* reg_pmecr_ee * Event update enable. If this bit is set, event generation will be updated * based on the e field. Only relevant on Set operations. * Access: WO
*/
MLXSW_ITEM32(reg, pmecr, ee, 0x04, 30, 1);
/* reg_pmecr_eswi * Software ignore enable bit. If this bit is set, the value of swi is used. * If this bit is clear, the value of swi is ignored. * Only relevant on Set operations. * Access: WO
*/
MLXSW_ITEM32(reg, pmecr, eswi, 0x04, 24, 1);
/* reg_pmecr_swi * Software ignore. If this bit is set, the device shouldn't generate events * in case of PMLP SET operation but only upon self local port mapping change * (if applicable according to e configuration). This is supplementary * configuration on top of e value. * Access: RW
*/
MLXSW_ITEM32(reg, pmecr, swi, 0x04, 8, 1);
/* PMPE - Port Module Plug/Unplug Event Register * --------------------------------------------- * This register reports any operational status change of a module. * A change in the module’s state will generate an event only if the change * happens after arming the event mechanism. Any changes to the module state * while the event mechanism is not armed will not be reported. Software can * query the PMPE register for module status.
*/ #define MLXSW_REG_PMPE_ID 0x5024 #define MLXSW_REG_PMPE_LEN 0x10
/* PMMP - Port Module Memory Map Properties Register * ------------------------------------------------- * The PMMP register allows to override the module memory map advertisement. * The register can only be set when the module is disabled by PMAOS register.
*/ #define MLXSW_REG_PMMP_ID 0x5044 #define MLXSW_REG_PMMP_LEN 0x2C
/* reg_pmmp_sticky * When set, will keep eeprom_override values after plug-out event. * Access: OP
*/
MLXSW_ITEM32(reg, pmmp, sticky, 0x00, 0, 1);
/* reg_pmmp_eeprom_override_mask * Write mask bit (negative polarity). * 0 - Allow write * 1 - Ignore write * On write, indicates which of the bits from eeprom_override field are * updated. * Access: WO
*/
MLXSW_ITEM32(reg, pmmp, eeprom_override_mask, 0x04, 16, 16);
enum { /* Set module to low power mode */
MLXSW_REG_PMMP_EEPROM_OVERRIDE_LOW_POWER_MASK = BIT(8),
};
/* PLLP - Port Local port to Label Port mapping Register * ----------------------------------------------------- * The PLLP register returns the mapping from Local Port into Label Port.
*/ #define MLXSW_REG_PLLP_ID 0x504A #define MLXSW_REG_PLLP_LEN 0x10
/* PMTM - Port Module Type Mapping Register * ---------------------------------------- * The PMTM register allows query or configuration of module types. * The register can only be set when the module is disabled by PMAOS register
*/ #define MLXSW_REG_PMTM_ID 0x5067 #define MLXSW_REG_PMTM_LEN 0x10
/* reg_htgt_trap_group * Trap group number. User defined number specifying which trap groups * should be forwarded to the CPU. The mapping between trap IDs and trap * groups is configured using HPKT register. * Access: Index
*/
MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
/* reg_htgt_pide * Enable policer ID specified using 'pid' field. * Access: RW
*/
MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
#define MLXSW_REG_HTGT_INVALID_POLICER 0xff
/* reg_htgt_pid * Policer ID for the trap group. * Access: RW
*/
MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
#define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
/* reg_htgt_mirror_action * Mirror action to use. * 0 - Trap to CPU. * 1 - Trap to CPU and mirror to a mirroring agent. * 2 - Mirror to a mirroring agent and do not trap to CPU. * Access: RW * * Note: Mirroring to a mirroring agent is only supported in Spectrum.
*/
MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
/* reg_htgt_priority * Trap group priority. * In case a packet matches multiple classification rules, the packet will * only be trapped once, based on the trap ID associated with the group (via * register HPKT) with the highest priority. * Supported values are 0-7, with 7 represnting the highest priority. * Access: RW * * Note: In SwitchX-2 this field is ignored and the priority value is replaced * by the 'trap_group' field.
*/
MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
#define MLXSW_REG_HTGT_DEFAULT_TC 7
/* reg_htgt_local_path_cpu_tclass * CPU ingress traffic class for the trap group. * Access: RW
*/
MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
enum mlxsw_reg_htgt_local_path_rdq {
MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13,
MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14,
MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15,
MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15,
}; /* reg_htgt_local_path_rdq * Receive descriptor queue (RDQ) to use for the trap group. * Access: RW
*/
MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
/* reg_hpkt_ack * Require acknowledgements from the host for events. * If set, then the device will wait for the event it sent to be acknowledged * by the host. This option is only relevant for event trap IDs. * Access: RW * * Note: Currently not supported by firmware.
*/
MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
/* reg_hpkt_action * Action to perform on packet when trapped. * 0 - No action. Forward to CPU based on switching rules. * 1 - Trap to CPU (CPU receives sole copy). * 2 - Mirror to CPU (CPU receives a replica of the packet). * 3 - Discard. * 4 - Soft discard (allow other traps to act on the packet). * 5 - Trap and soft discard (allow other traps to overwrite this trap). * 6 - Trap to CPU (CPU receives sole copy) and count it as error. * 15 - Restore the firmware's default action. * Access: RW * * Note: Must be set to 0 (forward) for event trap IDs, as they are already * addressed to the CPU.
*/
MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
/* reg_hpkt_trap_group * Trap group to associate the trap with. * Access: RW
*/
MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
/* reg_hpkt_trap_id * Trap ID. * Access: Index * * Note: A trap ID can only be associated with a single trap group. The device * will associate the trap ID with the last trap group configured.
*/
MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10);
/* reg_hpkt_ctrl * Configure dedicated buffer resources for control packets. * Ignored by SwitchX-2. * 0 - Keep factory defaults. * 1 - Do not use control buffer for this trap ID. * 2 - Use control buffer for this trap ID. * Access: RW
*/
MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
/* RGCR - Router General Configuration Register * -------------------------------------------- * The register is used for setting up the router configuration.
*/ #define MLXSW_REG_RGCR_ID 0x8001 #define MLXSW_REG_RGCR_LEN 0x28
/* reg_rgcr_max_router_interfaces * Defines the maximum number of active router interfaces for all virtual * routers. * Access: RW
*/
MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
/* reg_rgcr_usp * Update switch priority and packet color. * 0 - Preserve the value of Switch Priority and packet color. * 1 - Recalculate the value of Switch Priority and packet color. * Access: RW * * Note: Not supported by SwitchX and SwitchX-2.
*/
MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
/* reg_rgcr_pcp_rw * Indicates how to handle the pcp_rewrite_en value: * 0 - Preserve the value of pcp_rewrite_en. * 2 - Disable PCP rewrite. * 3 - Enable PCP rewrite. * Access: RW * * Note: Not supported by SwitchX and SwitchX-2.
*/
MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
/* reg_rgcr_activity_dis * Activity disable: * 0 - Activity will be set when an entry is hit (default). * 1 - Activity will not be set when an entry is hit. * * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry * (RALUE). * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host * Entry (RAUHT). * Bits 2:7 are reserved. * Access: RW * * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
*/
MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
/* reg_ritr_op * Opcode: * 0 - Create or edit RIF. * 1 - Delete RIF. * Reserved for SwitchX-2. For Spectrum, editing of interface properties * is not supported. An interface must be deleted and re-created in order * to update properties. * Access: WO
*/
MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
/* reg_ritr_rif * Router interface index. A pointer to the Router Interface Table. * Access: Index
*/
MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
/* reg_ritr_ipv4_fe * IPv4 Forwarding Enable. * Enables routing of IPv4 traffic on the router interface. When disabled, * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. * Not supported in SwitchX-2. * Access: RW
*/
MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
/* reg_ritr_ipv6_fe * IPv6 Forwarding Enable. * Enables routing of IPv6 traffic on the router interface. When disabled, * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. * Not supported in SwitchX-2. * Access: RW
*/
MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
/* reg_ritr_ipv4_mc_fe * IPv4 Multicast Forwarding Enable. * When disabled, forwarding is blocked but local traffic (traps and IP to me) * will be enabled. * Access: RW
*/
MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1);
/* reg_ritr_ipv6_mc_fe * IPv6 Multicast Forwarding Enable. * When disabled, forwarding is blocked but local traffic (traps and IP to me) * will be enabled. * Access: RW
*/
MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1);
/* reg_ritr_lb_en * Loop-back filter enable for unicast packets. * If the flag is set then loop-back filter for unicast packets is * implemented on the RIF. Multicast packets are always subject to * loop-back filtering. * Access: RW
*/
MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
/* reg_ritr_virtual_router * Virtual router ID associated with the router interface. * Access: RW
*/
MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
/* reg_ritr_if_mac * Router interface MAC address. * In Spectrum, all MAC addresses must have the same 38 MSBits. * Access: RW
*/
MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
/* reg_ritr_if_vrrp_id_ipv6 * VRRP ID for IPv6 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. * Access: RW
*/
MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8);
/* reg_ritr_if_vrrp_id_ipv4 * VRRP ID for IPv4 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. * Access: RW
*/
MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8);
/* reg_ritr_vlan_if_efid * Egress FID. * Used to connect the RIF to a bridge. * Access: RW * * Note: Reserved when legacy bridge model is used and on Spectrum-1.
*/
MLXSW_ITEM32(reg, ritr, vlan_if_efid, 0x0C, 0, 16);
/* FID Interface */
/* reg_ritr_fid_if_fid * Filtering ID. Used to connect a bridge to the router. * When legacy bridge model is used, only FIDs from the vFID range are * supported. When unified bridge model is used, this is the egress FID for * router to bridge. * Access: RW
*/
MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
/* Sub-port Interface */
/* reg_ritr_sp_if_lag * LAG indication. When this bit is set the system_port field holds the * LAG identifier. * Access: RW
*/
MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
/* reg_ritr_sp_system_port * Port unique indentifier. When lag bit is set, this field holds the * lag_id in bits 0:9. * Access: RW
*/
MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
/* reg_ritr_sp_if_efid * Egress filtering ID. * Used to connect the eRIF to a bridge if eRIF-ACL has modified the DMAC or * the VID. * Access: RW * * Note: Reserved when legacy bridge model is used.
*/
MLXSW_ITEM32(reg, ritr, sp_if_efid, 0x0C, 0, 16);
enum mlxsw_reg_ritr_loopback_ipip_type { /* Tunnel is IPinIP. */
MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, /* Tunnel is GRE, no key. */
MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, /* Tunnel is GRE, with a key. */
MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP,
};
/* reg_ritr_loopback_ipip_gre_key * GRE Key. * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. * Access: RW
*/
MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32);
/* Shared between ingress/egress */ enum mlxsw_reg_ritr_counter_set_type { /* No Count. */
MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, /* Basic. Used for router interfaces, counting the following: * - Error and Discard counters. * - Unicast, Multicast and Broadcast counters. Sharing the * same set of counters for the different type of traffic * (IPv4, IPv6 and mpls).
*/
MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9,
};
/* reg_ritr_ingress_counter_index * Counter Index for flow counter. * Access: RW
*/
MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24);
/* reg_ritr_ingress_counter_set_type * Igress Counter Set Type for router interface counter. * Access: RW
*/
MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8);
/* reg_ritr_egress_counter_index * Counter Index for flow counter. * Access: RW
*/
MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24);
/* reg_ritr_egress_counter_set_type * Egress Counter Set Type for router interface counter. * Access: RW
*/
MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8);
/* RTAR - Router TCAM Allocation Register * -------------------------------------- * This register is used for allocation of regions in the TCAM table.
*/ #define MLXSW_REG_RTAR_ID 0x8004 #define MLXSW_REG_RTAR_LEN 0x20
/* reg_rtar_key_type * TCAM key type for the region. * Access: WO
*/
MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8);
/* reg_rtar_region_size * TCAM region size. When allocating/resizing this is the requested * size, the response is the actual size. * Note: Actual size may be larger than requested. * Reserved for op = Deallocate * Access: WO
*/
MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16);
enum mlxsw_reg_ratr_op { /* Read */
MLXSW_REG_RATR_OP_QUERY_READ = 0, /* Read and clear activity */
MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, /* Write Adjacency entry */
MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, /* Write Adjacency entry only if the activity is cleared. * The write may not succeed if the activity is set. There is not * direct feedback if the write has succeeded or not, however * the get will reveal the actual entry (SW can compare the get * response to the set command).
*/
MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
};
/* reg_ratr_op * Note that Write operation may also be used for updating * counter_set_type and counter_index. In this case all other * fields must not be updated. * Access: OP
*/
MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
/* reg_ratr_v * Valid bit. Indicates if the adjacency entry is valid. * Note: the device may need some time before reusing an invalidated * entry. During this time the entry can not be reused. It is * recommended to use another entry before reusing an invalidated * entry (e.g. software can put it at the end of the list for * reusing). Trying to access an invalidated entry not yet cleared * by the device results with failure indicating "Try Again" status. * When valid is '0' then egress_router_interface,trap_action, * adjacency_parameters and counters are reserved * Access: RW
*/
MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
/* reg_ratr_a * Activity. Set for new entries. Set if a packet lookup has hit on * the specific entry. To clear the a bit, use "clear activity". * Access: RO
*/
MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
enum mlxsw_reg_ratr_type { /* Ethernet */
MLXSW_REG_RATR_TYPE_ETHERNET, /* IPoIB Unicast without GRH. * Reserved for Spectrum.
*/
MLXSW_REG_RATR_TYPE_IPOIB_UC, /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast * adjacency). * Reserved for Spectrum.
*/
MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, /* IPoIB Multicast. * Reserved for Spectrum.
*/
MLXSW_REG_RATR_TYPE_IPOIB_MC, /* MPLS. * Reserved for SwitchX/-2.
*/
MLXSW_REG_RATR_TYPE_MPLS, /* IPinIP Encap. * Reserved for SwitchX/-2.
*/
MLXSW_REG_RATR_TYPE_IPIP,
};
/* reg_ratr_adjacency_index_low * Bits 15:0 of index into the adjacency table. * For SwitchX and SwitchX-2, the adjacency table is linear and * used for adjacency entries only. * For Spectrum, the index is to the KVD linear. * Access: Index
*/
MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
/* reg_ratr_egress_router_interface * Range is 0 .. cap_max_router_interfaces - 1 * Access: RW
*/
MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
/* reg_ratr_trap_id * Trap ID to be reported to CPU. * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. * For trap_action of NOP, MIRROR and DISCARD_ERROR * Access: RW
*/
MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
/* reg_ratr_eth_destination_mac * MAC address of the destination next-hop. * Access: RW
*/
MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
enum mlxsw_reg_ratr_ipip_type { /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */
MLXSW_REG_RATR_IPIP_TYPE_IPV4, /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */
MLXSW_REG_RATR_IPIP_TYPE_IPV6,
};
/* reg_ratr_ipip_type * Underlay destination ip type. * Note: the type field must match the protocol of the router interface. * Access: RW
*/
MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4);
enum mlxsw_reg_ricnt_counter_set_type { /* No Count. */
MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, /* Basic. Used for router interfaces, counting the following: * - Error and Discard counters. * - Unicast, Multicast and Broadcast counters. Sharing the * same set of counters for the different type of traffic * (IPv4, IPv6 and mpls).
*/
MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09,
};
/* reg_ricnt_counter_set_type * Counter Set Type for router interface counter * Access: RW
*/
MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8);
enum mlxsw_reg_ricnt_opcode { /* Nop. Supported only for read access*/
MLXSW_REG_RICNT_OPCODE_NOP = 0x00, /* Clear. Setting the clr bit will reset the counter value for * all counters of the specified Router Interface.
*/
MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08,
};
/* reg_ricnt_good_unicast_bytes * A count of L3 data and padding octets not including L2 headers * for good unicast frames. * Access: RW
*/
MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64);
/* reg_ricnt_good_multicast_bytes * A count of L3 data and padding octets not including L2 headers * for good multicast frames. * Access: RW
*/
MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64);
/* reg_ritr_good_broadcast_bytes * A count of L3 data and padding octets not including L2 headers * for good broadcast frames. * Access: RW
*/
MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64);
/* reg_ricnt_error_packets * A count of errored frames that do not pass the router checks. * Access: RW
*/
MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64);
/* reg_ricnt_discrad_packets * A count of non-errored frames that do not pass the router checks. * Access: RW
*/
MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64);
/* reg_ricnt_error_bytes * A count of L3 data and padding octets not including L2 headers * for errored frames. * Access: RW
*/
MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64);
/* reg_ricnt_discard_bytes * A count of L3 data and padding octets not including L2 headers * for non-errored frames that do not pass the router checks. * Access: RW
*/
MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64);
/* reg_rrcr_offset * Offset within the region from which to copy/move. * Access: Index
*/
MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16);
/* reg_rrcr_size * The number of rules to copy/move. * Access: WO
*/
MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16);
/* reg_rrcr_table_id * Identifier of the table on which to perform the operation. Encoding is the * same as in RTAR.key_type * Access: Index
*/
MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4);
/* reg_rrcr_dest_offset * Offset within the region to which to copy/move * Access: Index
*/
MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16);
/* RALTA - Router Algorithmic LPM Tree Allocation Register * ------------------------------------------------------- * RALTA is used to allocate the LPM trees of the SHSPM method.
*/ #define MLXSW_REG_RALTA_ID 0x8010 #define MLXSW_REG_RALTA_LEN 0x04
/* reg_ralta_op * opcode (valid for Write, must be 0 on Read) * 0 - allocate a tree * 1 - deallocate a tree * Access: OP
*/
MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
/* reg_ralta_tree_id * An identifier (numbered from 1..cap_shspm_max_trees-1) representing * the tree identifier (managed by software). * Note that tree_id 0 is allocated for a default-route tree. * Access: Index
*/
MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
/* RALST - Router Algorithmic LPM Structure Tree Register * ------------------------------------------------------ * RALST is used to set and query the structure of an LPM tree. * The structure of the tree must be sorted as a sorted binary tree, while * each node is a bin that is tagged as the length of the prefixes the lookup * will refer to. Therefore, bin X refers to a set of entries with prefixes * of X bits to match with the destination address. The bin 0 indicates * the default action, when there is no match of any prefix.
*/ #define MLXSW_REG_RALST_ID 0x8011 #define MLXSW_REG_RALST_LEN 0x104
/* reg_ralst_root_bin * The bin number of the root bin. * 0<root_bin=<(length of IP address) * For a default-route tree configure 0xff * Access: RW
*/
MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
/* reg_ralst_tree_id * Tree identifier numbered from 1..(cap_shspm_max_trees-1). * Access: Index
*/
MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
/* reg_ralst_left_child_bin * Holding the children of the bin according to the stored tree's structure. * For trees composed of less than 4 blocks, the bins in excess are reserved. * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff * Access: RW
*/
MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
/* reg_ralst_right_child_bin * Holding the children of the bin according to the stored tree's structure. * For trees composed of less than 4 blocks, the bins in excess are reserved. * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff * Access: RW
*/
MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, false);
/* Initialize all bins to have no left or right child */
memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
/* RALTB - Router Algorithmic LPM Tree Binding Register * ---------------------------------------------------- * RALTB is used to bind virtual router and protocol to an allocated LPM tree.
*/ #define MLXSW_REG_RALTB_ID 0x8012 #define MLXSW_REG_RALTB_LEN 0x04
/* reg_raltb_virtual_router * Virtual Router ID * Range is 0..cap_max_virtual_routers-1 * Access: Index
*/
MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
/* reg_raltb_tree_id * Tree to be used for the {virtual_router, protocol} * Tree identifier numbered from 1..(cap_shspm_max_trees-1). * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. * Access: RW
*/
MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
enum mlxsw_reg_ralue_op { /* Read operation. If entry doesn't exist, the operation fails. */
MLXSW_REG_RALUE_OP_QUERY_READ = 0, /* Clear on read operation. Used to read entry and * clear Activity bit.
*/
MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, /* Write operation. Used to write a new entry to the table. All RW * fields are written for new entry. Activity bit is set * for new entries.
*/
MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, /* Update operation. Used to update an existing route entry and * only update the RW fields that are detailed in the field * op_u_mask. If entry doesn't exist, the operation fails.
*/
MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, /* Clear activity. The Activity bit (the field a) is cleared * for the entry.
*/
MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, /* Delete operation. Used to delete an existing entry. If entry * doesn't exist, the operation fails.
*/
MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
};
/* reg_ralue_a * Activity. Set for new entries. Set if a packet lookup has hit on the * specific entry, only if the entry is a route. To clear the a bit, use * "clear activity" op. * Enabled by activity_dis in RGCR * Access: RO
*/
MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
/* reg_ralue_virtual_router * Virtual Router ID * Range is 0..cap_max_virtual_routers-1 * Access: Index
*/
MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
/* reg_ralue_op_u_mask * opcode update mask. * On read operation, this field is reserved. * This field is valid for update opcode, otherwise - reserved. * This field is a bitmask of the fields that should be updated. * Access: WO
*/
MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
/* reg_ralue_prefix_len * Number of bits in the prefix of the LPM route. * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes * two entries in the physical HW table. * Access: Index
*/
MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
/* reg_ralue_dip* * The prefix of the route or of the marker that the object of the LPM * is compared with. The most significant bits of the dip are the prefix. * The least significant bits must be '0' if the prefix_len is smaller * than 128 for IPv6 or smaller than 32 for IPv4. * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. * Access: Index
*/
MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16);
/* reg_ralue_entry_type * Entry type. * Note - for Marker entries, the action_type and action fields are reserved. * Access: RW
*/
MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
/* reg_ralue_bmp_len * The best match prefix length in the case that there is no match for * longer prefixes. * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len * Note for any update operation with entry_type modification this * field must be set. * Access: RW
*/
MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
/* reg_ralue_action_type * Action Type * Indicates how the IP address is connected. * It can be connected to a local subnet through local_erif or can be * on a remote subnet connected through a next-hop router, * or transmitted to the CPU. * Reserved when entry_type = MARKER_ENTRY * Access: RW
*/
MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
/* reg_ralue_trap_action * Trap action. * For IP2ME action, only NOP and MIRROR are possible. * Access: RW
*/
MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
/* reg_ralue_trap_id * Trap ID to be reported to CPU. * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. * Access: RW
*/
MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
/* reg_ralue_adjacency_index * Points to the first entry of the group-based ECMP. * Only relevant in case of REMOTE action. * Access: RW
*/
MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
/* reg_ralue_ecmp_size * Amount of sequential entries starting * from the adjacency_index (the number of ECMPs). * The valid range is 1-64, 512, 1024, 2048 and 4096. * Reserved when trap_action is TRAP or DISCARD_ERROR. * Only relevant in case of REMOTE action. * Access: RW
*/
MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
/* reg_ralue_local_erif * Egress Router Interface. * Only relevant in case of LOCAL action. * Access: RW
*/
MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
/* reg_ralue_ip2me_v * Valid bit for the tunnel_ptr field. * If valid = 0 then trap to CPU as IP2ME trap ID. * If valid = 1 and the packet format allows NVE or IPinIP tunnel * decapsulation then tunnel decapsulation is done. * If valid = 1 and packet format does not allow NVE or IPinIP tunnel * decapsulation then trap as IP2ME trap ID. * Only relevant in case of IP2ME action. * Access: RW
*/
MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1);
/* reg_ralue_ip2me_tunnel_ptr * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. * For Spectrum, pointer to KVD Linear. * Only relevant in case of IP2ME action. * Access: RW
*/
MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24);
/* RAUHT - Router Algorithmic LPM Unicast Host Table Register * ---------------------------------------------------------- * The RAUHT register is used to configure and query the Unicast Host table in * devices that implement the Algorithmic LPM.
*/ #define MLXSW_REG_RAUHT_ID 0x8014 #define MLXSW_REG_RAUHT_LEN 0x74
enum mlxsw_reg_rauht_op {
MLXSW_REG_RAUHT_OP_QUERY_READ = 0, /* Read operation */
MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, /* Clear on read operation. Used to read entry and clear * activity bit.
*/
MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, /* Add. Used to write a new entry to the table. All R/W fields are * relevant for new entry. Activity bit is set for new entries.
*/
MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, /* Update action. Used to update an existing route entry and * only update the following fields: * trap_action, trap_id, mac, counter_set_type, counter_index
*/
MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, /* Clear activity. A bit is cleared for the entry. */
MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, /* Delete entry */
MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, /* Delete all host entries on a RIF. In this command, dip * field is reserved.
*/
};
/* reg_rauht_a * Activity. Set for new entries. Set if a packet lookup has hit on * the specific entry. * To clear the a bit, use "clear activity" op. * Enabled by activity_dis in RGCR * Access: RO
*/
MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
/* reg_rauht_trap_id * Trap ID to be reported to CPU. * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. * For trap_action of NOP, MIRROR and DISCARD_ERROR, * trap_id is reserved. * Access: RW
*/
MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
/* reg_rauht_counter_set_type * Counter set type for flow counters * Access: RW
*/
MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
/* reg_rauht_counter_index * Counter index for flow counters * Access: RW
*/
MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
/* RALEU - Router Algorithmic LPM ECMP Update Register * --------------------------------------------------- * The register enables updating the ECMP section in the action for multiple * LPM Unicast entries in a single operation. The update is executed to * all entries of a {virtual router, protocol} tuple using the same ECMP group.
*/ #define MLXSW_REG_RALEU_ID 0x8015 #define MLXSW_REG_RALEU_LEN 0x28
/* reg_raleu_virtual_router * Virtual Router ID * Range is 0..cap_max_virtual_routers-1 * Access: Index
*/
MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
/* reg_raleu_adjacency_index * Adjacency Index used for matching on the existing entries. * Access: Index
*/
MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
/* reg_raleu_ecmp_size * ECMP Size used for matching on the existing entries. * Access: Index
*/
MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
/* reg_raleu_new_adjacency_index * New Adjacency Index. * Access: WO
*/
MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
/* reg_raleu_new_ecmp_size * New ECMP Size. * Access: WO
*/
MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
/* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register * ---------------------------------------------------------------- * The RAUHTD register allows dumping entries from the Router Unicast Host * Table. For a given session an entry is dumped no more than one time. The * first RAUHTD access after reset is a new session. A session ends when the * num_rec response is smaller than num_rec request or for IPv4 when the * num_entries is smaller than 4. The clear activity affect the current session * or the last session if a new session has not started.
*/ #define MLXSW_REG_RAUHTD_ID 0x8018 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
/* reg_rauhtd_filter_fields * if a bit is '0' then the relevant field is ignored and dump is done * regardless of the field value * Bit0 - filter by activity: entry_a * Bit3 - filter by entry rip: entry_rif * Access: Index
*/
MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
/* reg_rauhtd_num_rec * At request: number of records requested * At response: number of records dumped * For IPv4, each record has 4 entries at request and up to 4 entries * at response * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM * Access: Index
*/
MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
/* reg_rauhtd_entry_a * Dump only if activity has value of entry_a * Reserved if filter_fields bit0 is '0' * Access: Index
*/
MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
/* reg_rauhtd_type * Dump only if record type is: * 0 - IPv4 * 1 - IPv6 * Access: Index
*/
MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
/* reg_rauhtd_entry_rif * Dump only if RIF has value of entry_rif * Reserved if filter_fields bit3 is '0' * Access: Index
*/
MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
/* reg_rauhtd_ipv4_ent_a * Activity. Set for new entries. Set if a packet lookup has hit on the * specific entry. * Access: RO
*/
MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
/* reg_rauhtd_ipv6_ent_a * Activity. Set for new entries. Set if a packet lookup has hit on the * specific entry. * Access: RO
*/
MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
/* RTDP - Routing Tunnel Decap Properties Register * ----------------------------------------------- * The RTDP register is used for configuring the tunnel decap properties of NVE * and IPinIP.
*/ #define MLXSW_REG_RTDP_ID 0x8020 #define MLXSW_REG_RTDP_LEN 0x44
/* reg_rtdp_type * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. * Access: RW
*/
MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4);
/* reg_rtdp_tunnel_index * Index to the Decap entry. * For Spectrum, Index to KVD Linear. * Access: Index
*/
MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24);
/* reg_rtdp_egress_router_interface * Underlay egress router interface. * Valid range is from 0 to cap_max_router_interfaces - 1 * Access: RW
*/
MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16);
/* IPinIP */
/* reg_rtdp_ipip_irif * Ingress Router Interface for the overlay router * Access: RW
*/
MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16);
enum mlxsw_reg_rtdp_ipip_sip_check { /* No sip checks. */
MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, /* Filter packet if underlay is not IPv4 or if underlay SIP does not * equal ipv4_usip.
*/
MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, /* Filter packet if underlay is not IPv6 or if underlay SIP does not * equal ipv6_usip.
*/
MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3,
};
/* reg_rtdp_ipip_sip_check * SIP check to perform. If decapsulation failed due to these configurations * then trap_id is IPIP_DECAP_ERROR. * Access: RW
*/
MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3);
/* If set, allow decapsulation of IPinIP (without GRE). */ #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) /* If set, allow decapsulation of IPinGREinIP without a key. */ #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) /* If set, allow decapsulation of IPinGREinIP with a key. */ #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2)
/* reg_rtdp_ipip_type_check * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to * these configurations then trap_id is IPIP_DECAP_ERROR. * Access: RW
*/
MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3);
/* reg_rtdp_ipip_gre_key_check * Whether GRE key should be checked. When check is enabled: * - A packet received as IPinIP (without GRE) will always pass. * - A packet received as IPinGREinIP without a key will not pass the check. * - A packet received as IPinGREinIP with a key will pass the check only if the * key in the packet is equal to expected_gre_key. * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. * Access: RW
*/
MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1);
/* reg_rtdp_ipip_ipv4_usip * Underlay IPv4 address for ipv4 source address check. * Reserved when sip_check is not '1'. * Access: RW
*/
MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32);
/* reg_rtdp_ipip_ipv6_usip_ptr * This field is valid when sip_check is "sipv6 check explicitly". This is a * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index * is to the KVD linear. * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. * Access: RW
*/
MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24);
/* reg_rtdp_ipip_expected_gre_key * GRE key for checking. * Reserved when gre_key_check is '0'. * Access: RW
*/
MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32);
/* RIPS - Router IP version Six Register * ------------------------------------- * The RIPS register is used to store IPv6 addresses for use by the NVE and * IPinIP
*/ #define MLXSW_REG_RIPS_ID 0x8021 #define MLXSW_REG_RIPS_LEN 0x14
/* reg_rips_index * Index to IPv6 address. * For Spectrum, the index is to the KVD linear. * Access: Index
*/
MLXSW_ITEM32(reg, rips, index, 0x00, 0, 24);
/* RIGR-V2 - Router Interface Group Register Version 2 * --------------------------------------------------- * The RIGR_V2 register is used to add, remove and query egress interface list * of a multicast forwarding entry.
*/ #define MLXSW_REG_RIGR2_ID 0x8023 #define MLXSW_REG_RIGR2_LEN 0xB0
/* reg_rigr2_rigr_index * KVD Linear index. * Access: Index
*/
MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24);
/* reg_rigr2_vnext * Next RIGR Index is valid. * Access: RW
*/
MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1);
/* reg_rigr2_next_rigr_index * Next RIGR Index. The index is to the KVD linear. * Reserved when vnxet = '0'. * Access: RW
*/
MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);
/* reg_rigr2_vrmid * RMID Index is valid. * Access: RW
*/
MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);
/* reg_rigr2_rmid_index * RMID Index. * Range 0 .. max_mid - 1 * Reserved when vrmid = '0'. * The index is to the Port Group Table (PGT) * Access: RW
*/
MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);
/* reg_rigr2_erif_entry_v * Egress Router Interface is valid. * Note that low-entries must be set if high-entries are set. For * example: if erif_entry[2].v is set then erif_entry[1].v and * erif_entry[0].v must be set. * Index can be from 0 to cap_mc_erif_list_entries-1 * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);
/* reg_rigr2_erif_entry_erif * Egress Router Interface. * Valid range is from 0 to cap_max_router_interfaces - 1 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);
enum { /* Enable IPv4 fields if packet is not TCP and not UDP */
MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, /* Enable IPv4 fields if packet is TCP or UDP */
MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, /* Enable IPv6 fields if packet is not TCP and not UDP */
MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, /* Enable IPv6 fields if packet is TCP or UDP */
MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, /* Enable TCP/UDP header fields if packet is IPv4 */
MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, /* Enable TCP/UDP header fields if packet is IPv6 */
MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8,
__MLXSW_REG_RECR2_HEADER_CNT,
};
/* reg_recr2_outer_header_enables * Bit mask where each bit enables a specific layer to be included in * the hash calculation. * Access: RW
*/
MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1);
/* reg_recr2_outer_header_fields_enable * Packet fields to enable for ECMP hash subject to outer_header_enable. * Access: RW
*/
MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1);
/* reg_recr2_inner_header_enables * Bit mask where each bit enables a specific inner layer to be included in the * hash calculation. Same values as reg_recr2_outer_header_enables. * Access: RW
*/
MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_enables, 0x2C, 0x04, 1);
/* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register * -------------------------------------------------------------- * The RMFT_V2 register is used to configure and query the multicast table.
*/ #define MLXSW_REG_RMFT2_ID 0x8027 #define MLXSW_REG_RMFT2_LEN 0x174
enum mlxsw_sp_reg_rmft2_op { /* For Write: * Write operation. Used to write a new entry to the table. All RW * fields are relevant for new entry. Activity bit is set for new * entries - Note write with v (Valid) 0 will delete the entry. * For Query: * Read operation
*/
MLXSW_REG_RMFT2_OP_READ_WRITE,
};
/* reg_rmft2_a * Activity. Set for new entries. Set if a packet lookup has hit on the specific * entry. * Access: RO
*/
MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1);
/* reg_rmft2_offset * Offset within the multicast forwarding table to write to. * Access: Index
*/
MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16);
/* reg_rmft2_virtual_router * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 * Access: RW
*/
MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16);
/* reg_rmft2_dip{4,6}_mask * A bit that is set directs the TCAM to compare the corresponding bit in key. A * bit that is clear directs the TCAM to ignore the corresponding bit in key. * Access: RW
*/
MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16);
MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32);
/* reg_rmft2_sip{4,6}_mask * A bit that is set directs the TCAM to compare the corresponding bit in key. A * bit that is clear directs the TCAM to ignore the corresponding bit in key. * Access: RW
*/
MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16);
MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32);
/* reg_rmft2_flexible_action_set * ACL action set. The only supported action types in this field and in any * action-set pointed from here are as follows: * 00h: ACTION_NULL * 01h: ACTION_MAC_TTL, only TTL configuration is supported. * 03h: ACTION_TRAP * 06h: ACTION_QOS * 08h: ACTION_POLICING_MONITORING * 10h: ACTION_ROUTER_MC * Access: RW
*/
MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80,
MLXSW_REG_FLEX_ACTION_SET_LEN);
/* REIV - Router Egress Interface to VID Register * ---------------------------------------------- * The REIV register maps {eRIF, egress_port} -> VID. * This mapping is done at the egress, after the ACLs. * This mapping always takes effect after router, regardless of cast * (for unicast/multicast/port-base multicast), regardless of eRIF type and * regardless of bridge decisions (e.g. SFD for unicast or SMPE). * Reserved when the RIF is a loopback RIF. * * Note: Reserved when legacy bridge model is used.
*/ #define MLXSW_REG_REIV_ID 0x8034 #define MLXSW_REG_REIV_BASE_LEN 0x20 /* base length, without records */ #define MLXSW_REG_REIV_REC_LEN 0x04 /* record length */ #define MLXSW_REG_REIV_REC_MAX_COUNT 256 /* firmware limitation */ #define MLXSW_REG_REIV_LEN (MLXSW_REG_REIV_BASE_LEN + \
MLXSW_REG_REIV_REC_LEN * \
MLXSW_REG_REIV_REC_MAX_COUNT)
/* MFCR - Management Fan Control Register * -------------------------------------- * This register controls the settings of the Fan Speed PWM mechanism.
*/ #define MLXSW_REG_MFCR_ID 0x9001 #define MLXSW_REG_MFCR_LEN 0x08
/* reg_mfcr_pwm_frequency * Controls the frequency of the PWM signal. * Access: RW
*/
MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7);
#define MLXSW_MFCR_TACHOS_MAX 10
/* reg_mfcr_tacho_active * Indicates which of the tachometer is active (bit per tachometer). * Access: RO
*/
MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
#define MLXSW_MFCR_PWMS_MAX 5
/* reg_mfcr_pwm_active * Indicates which of the PWM control is active (bit per PWM). * Access: RO
*/
MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
/* MFSC - Management Fan Speed Control Register * -------------------------------------------- * This register controls the settings of the Fan Speed PWM mechanism.
*/ #define MLXSW_REG_MFSC_ID 0x9002 #define MLXSW_REG_MFSC_LEN 0x08
/* reg_mfsc_pwm * Fan pwm to control / monitor. * Access: Index
*/
MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
/* reg_mfsc_pwm_duty_cycle * Controls the duty cycle of the PWM. Value range from 0..255 to * represent duty cycle of 0%...100%. * Access: RW
*/
MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
/* MFSM - Management Fan Speed Measurement * --------------------------------------- * This register controls the settings of the Tacho measurements and * enables reading the Tachometer measurements.
*/ #define MLXSW_REG_MFSM_ID 0x9003 #define MLXSW_REG_MFSM_LEN 0x08
/* MFSL - Management Fan Speed Limit Register * ------------------------------------------ * The Fan Speed Limit register is used to configure the fan speed * event / interrupt notification mechanism. Fan speed threshold are * defined for both under-speed and over-speed.
*/ #define MLXSW_REG_MFSL_ID 0x9004 #define MLXSW_REG_MFSL_LEN 0x0C
if (p_tach_max)
*p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload);
}
/* FORE - Fan Out of Range Event Register * -------------------------------------- * This register reports the status of the controlled fans compared to the * range defined by the MFSL register.
*/ #define MLXSW_REG_FORE_ID 0x9007 #define MLXSW_REG_FORE_LEN 0x0C
/* fan_under_limit * Fan speed is below the low limit defined in MFSL register. Each bit relates * to a single tachometer and indicates the specific tachometer reading is * below the threshold. * Access: RO
*/
MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10);
/* MTCAP - Management Temperature Capabilities * ------------------------------------------- * This register exposes the capabilities of the device and * system temperature sensing.
*/ #define MLXSW_REG_MTCAP_ID 0x9009 #define MLXSW_REG_MTCAP_LEN 0x08
/* reg_mtcap_sensor_count * Number of sensors supported by the device. * This includes the QSFP module sensors (if exists in the QSFP module). * Access: RO
*/
MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
/* MTMP - Management Temperature * ----------------------------- * This register controls the settings of the temperature measurements * and enables reading the temperature measurements. Note that temperature * is in 0.125 degrees Celsius.
*/ #define MLXSW_REG_MTMP_ID 0x900A #define MLXSW_REG_MTMP_LEN 0x20
/* reg_mtmp_slot_index * Slot index (0: Main board). * Access: Index
*/
MLXSW_ITEM32(reg, mtmp, slot_index, 0x00, 16, 4);
#define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 /* reg_mtmp_sensor_index * Sensors index to access. * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially * (module 0 is mapped to sensor_index 64). * Access: Index
*/
MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12);
/* reg_mtmp_max_operational_temperature * The highest temperature in the nominal operational range. Reading is in * 0.125 Celsius degrees units. * In case of module this is SFF critical temperature threshold. * Access: RO
*/
MLXSW_ITEM32(reg, mtmp, max_operational_temperature, 0x04, 16, 16);
/* reg_mtmp_temperature * Temperature reading from the sensor. Reading is in 0.125 Celsius * degrees units. * Access: RO
*/
MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
/* reg_mtmp_mte * Max Temperature Enable - enables measuring the max temperature on a sensor. * Access: RW
*/
MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
/* reg_mtmp_mtr * Max Temperature Reset - clears the value of the max temperature register. * Access: WO
*/
MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
/* reg_mtmp_max_temperature * The highest measured temperature from the sensor. * When the bit mte is cleared, the field max_temperature is reserved. * Access: RO
*/
MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
/* reg_mtmp_tee * Temperature Event Enable. * 0 - Do not generate event * 1 - Generate event * 2 - Generate single event * Access: RW
*/
staticinlinevoid mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, int *p_max_temp, int *p_temp_hi, int *p_max_oper_temp, char *sensor_name)
{
s16 temp;
if (p_temp) {
temp = mlxsw_reg_mtmp_temperature_get(payload);
*p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
} if (p_max_temp) {
temp = mlxsw_reg_mtmp_max_temperature_get(payload);
*p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
} if (p_temp_hi) {
temp = mlxsw_reg_mtmp_temperature_threshold_hi_get(payload);
*p_temp_hi = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
} if (p_max_oper_temp) {
temp = mlxsw_reg_mtmp_max_operational_temperature_get(payload);
*p_max_oper_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
} if (sensor_name)
mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
}
/* MTWE - Management Temperature Warning Event * ------------------------------------------- * This register is used for over temperature warning.
*/ #define MLXSW_REG_MTWE_ID 0x900B #define MLXSW_REG_MTWE_LEN 0x10
/* reg_mtwe_sensor_warning * Bit vector indicating which of the sensor reading is above threshold. * Address 00h bit31 is sensor_warning[127]. * Address 0Ch bit0 is sensor_warning[0]. * Access: RO
*/
MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1);
/* MTBR - Management Temperature Bulk Register * ------------------------------------------- * This register is used for bulk temperature reading.
*/ #define MLXSW_REG_MTBR_ID 0x900F #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ #define MLXSW_REG_MTBR_REC_MAX_COUNT 1 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \
MLXSW_REG_MTBR_REC_LEN * \
MLXSW_REG_MTBR_REC_MAX_COUNT)
/* reg_mtbr_slot_index * Slot index (0: Main board). * Access: Index
*/
MLXSW_ITEM32(reg, mtbr, slot_index, 0x00, 16, 4);
/* reg_mtbr_base_sensor_index * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, * 64-127 are mapped to the SFP+/QSFP modules sequentially). * Access: Index
*/
MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12);
/* reg_mtbr_num_rec * Request: Number of records to read * Response: Number of records read * See above description for more details. * Range 1..255 * Access: RW
*/
MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8);
/* reg_mtbr_rec_max_temp * The highest measured temperature from the sensor. * When the bit mte is cleared, the field max_temperature is reserved. * Access: RO
*/
MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16,
16, MLXSW_REG_MTBR_REC_LEN, 0x00, false);
/* reg_mtbr_rec_temp * Temperature reading from the sensor. Reading is in 0..125 Celsius * degrees units. * Access: RO
*/
MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16,
MLXSW_REG_MTBR_REC_LEN, 0x00, false);
/* This is used to access the optional upper pages (1-3) in the QSFP+ * memory map. Page 1 is available on offset 256 through 383, page 2 - * on offset 384 through 511, page 3 - on offset 512 through 639.
*/ #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \
MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \
MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1)
/* MPAT - Monitoring Port Analyzer Table * ------------------------------------- * MPAT Register is used to query and configure the Switch PortAnalyzer Table. * For an enabled analyzer, all fields except e (enable) cannot be modified.
*/ #define MLXSW_REG_MPAT_ID 0x901A #define MLXSW_REG_MPAT_LEN 0x78
/* reg_mpat_system_port * A unique port identifier for the final destination of the packet. * Access: RW
*/
MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
/* reg_mpat_e * Enable. Indicating the Port Analyzer is enabled. * Access: RW
*/
MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
/* reg_mpat_qos * Quality Of Service Mode. * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation * PCP, DEI, DSCP or VL) are configured. * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the * same as in the original packet that has triggered the mirroring. For * SPAN also the pcp,dei are maintained. * Access: RW
*/
MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
/* reg_mpat_be * Best effort mode. Indicates mirroring traffic should not cause packet * drop or back pressure, but will discard the mirrored packets. Mirrored * packets will be forwarded on a best effort manner. * 0: Do not discard mirrored packets * 1: Discard mirrored packets if causing congestion * Access: RW
*/
MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
enum mlxsw_reg_mpat_span_type { /* Local SPAN Ethernet. * The original packet is not encapsulated.
*/
MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0,
/* Remote SPAN Ethernet VLAN. * The packet is forwarded to the monitoring port on the monitoring * VLAN.
*/
MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1,
/* Encapsulated Remote SPAN Ethernet L3 GRE. * The packet is encapsulated with GRE header.
*/
MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3,
};
/* reg_mpat_eth_rspan_dip* * Destination IP address. The IP version is configured by protocol. * Access: RW
*/
MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32);
MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16);
/* reg_mpat_eth_rspan_sip* * Source IP address. The IP version is configured by protocol. * Access: RW
*/
MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32);
MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16);
/* MPAR - Monitoring Port Analyzer Register * ---------------------------------------- * MPAR register is used to query and configure the port analyzer port mirroring * properties.
*/ #define MLXSW_REG_MPAR_ID 0x901B #define MLXSW_REG_MPAR_LEN 0x0C
/* reg_mpar_enable * Enable mirroring * By default, port mirroring is disabled for all ports. * Access: RW
*/
MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
/* MGIR - Management General Information Register * ---------------------------------------------- * MGIR register allows software to query the hardware and firmware general * information.
*/ #define MLXSW_REG_MGIR_ID 0x9020 #define MLXSW_REG_MGIR_LEN 0x9C
/* MRSR - Management Reset and Shutdown Register * --------------------------------------------- * MRSR register is used to reset or shutdown the switch or * the entire system (when applicable).
*/ #define MLXSW_REG_MRSR_ID 0x9023 #define MLXSW_REG_MRSR_LEN 0x08
enum mlxsw_reg_mrsr_command { /* Switch soft reset, does not reset PCI firmware. */
MLXSW_REG_MRSR_COMMAND_SOFTWARE_RESET = 1, /* Reset will be done when PCI link will be disabled. * This command will reset PCI firmware also.
*/
MLXSW_REG_MRSR_COMMAND_RESET_AT_PCI_DISABLE = 6,
};
/* reg_mlcr_local_port * Local port number. * Access: RW
*/
MLXSW_ITEM32_LP(reg, mlcr, 0x00, 16, 0x00, 24);
#define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
/* reg_mlcr_beacon_duration * Duration of the beacon to be active, in seconds. * 0x0 - Will turn off the beacon. * 0xFFFF - Will turn on the beacon until explicitly turned off. * Access: RW
*/
MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
/* reg_mlcr_beacon_remain * Remaining duration of the beacon, in seconds. * 0xFFFF indicates an infinite amount of time. * Access: RO
*/
MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
/* MCION - Management Cable IO and Notifications Register * ------------------------------------------------------ * The MCION register is used to query transceiver modules' IO pins and other * notifications.
*/ #define MLXSW_REG_MCION_ID 0x9052 #define MLXSW_REG_MCION_LEN 0x18
/* MTPPS - Management Pulse Per Second Register * -------------------------------------------- * This register provides the device PPS capabilities, configure the PPS in and * out modules and holds the PPS in time stamp.
*/ #define MLXSW_REG_MTPPS_ID 0x9053 #define MLXSW_REG_MTPPS_LEN 0x3C
/* reg_mtpps_pin_mode * Pin mode to be used. The mode must comply with the supported modes of the * requested pin. * Access: RW
*/
MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4);
#define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7
/* reg_mtpps_pin * Pin to be configured or queried out of the supported pins. * Access: Index
*/
MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8);
/* reg_mtpps_time_stamp * When pin_mode = pps_in, the latched device time when it was triggered from * the external GPIO pin. * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target * time to generate next output signal. * Time is in units of device clock. * Access: RW
*/
MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64);
/* reg_mtutc_freq_adjustment * Frequency adjustment: Every PPS the HW frequency will be * adjusted by this value. Units of HW clock, where HW counts * 10^9 HW clocks for 1 HW second. Range is from -50,000,000 to +50,000,000. * In Spectrum-2, the field is reversed, positive values mean to decrease the * frequency. * Access: RW
*/
MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32);
/* reg_mtutc_utc_sec * UTC seconds. * Access: WO
*/
MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32);
/* reg_mtutc_utc_nsec * UTC nSecs. * Range 0..(10^9-1) * Updated when operation is SET_TIME_IMMEDIATE. * Reserved on Spectrum-1. * Access: WO
*/
MLXSW_ITEM32(reg, mtutc, utc_nsec, 0x14, 0, 30);
/* reg_mtutc_time_adjustment * Time adjustment. * Units of nSec. * Range is from -32768 to +32767. * Updated when operation is ADJUST_TIME. * Reserved on Spectrum-1. * Access: WO
*/
MLXSW_ITEM32(reg, mtutc, time_adjustment, 0x18, 0, 32);
/* reg_mcqi_offset * The requested/returned data offset from the section start, given in bytes. * Must be DWORD aligned. * Access: RW
*/
MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32);
/* reg_mcqi_data_size * The requested/returned data size, given in bytes. If data_size is not DWORD * aligned, the last bytes are zero padded. * Access: RW
*/
MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16);
/* reg_mcqi_cap_max_component_size * Maximum size for this component, given in bytes. * Access: RO
*/
MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32);
/* reg_mcqi_cap_log_mcda_word_size * Log 2 of the access word size in bytes. Read and write access must be aligned * to the word size. Write access must be done for an integer number of words. * Access: RO
*/
MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4);
/* reg_mcc_instruction * Command to be executed by the FSM. * Applicable for write operation only. * Access: RW
*/
MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8);
/* reg_mcc_component_index * Index of the accessed component. Applicable only for commands that * refer to components. Otherwise, this field is reserved. * Access: Index
*/
MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16);
/* reg_mcc_update_handle * Token representing the current flow executed by the FSM. * Access: WO
*/
MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24);
/* reg_mcc_error_code * Indicates the successful completion of the instruction, or the reason it * failed * Access: RO
*/
MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8);
/* reg_mcc_control_state * Current FSM state * Access: RO
*/
MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4);
/* reg_mcc_component_size * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying * the size may shorten the update time. Value 0x0 means that size is * unspecified. * Access: WO
*/
MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32);
/* reg_mcda_update_handle * Token representing the current flow executed by the FSM. * Access: RW
*/
MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24);
/* reg_mcda_offset * Offset of accessed address relative to component start. Accesses must be in * accordance to log_mcda_word_size in MCQI reg. * Access: RW
*/
MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32);
/* reg_mcda_size * Size of the data accessed, given in bytes. * Access: RW
*/
MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16);
/* reg_mcam_feature_group * Feature list mask index. * Access: Index
*/
MLXSW_ITEM32(reg, mcam, feature_group, 0x00, 16, 8);
enum mlxsw_reg_mcam_mng_feature_cap_mask_bits { /* If set, MCIA supports 128 bytes payloads. Otherwise, 48 bytes. */
MLXSW_REG_MCAM_MCIA_128B = 34, /* If set, MRSR.command=6 is supported. */
MLXSW_REG_MCAM_PCI_RESET = 48, /* If set, MRSR.command=6 is supported with Secondary Bus Reset. */
MLXSW_REG_MCAM_PCI_RESET_SBR = 67,
};
#define MLXSW_REG_BYTES_PER_DWORD 0x4
/* reg_mcam_mng_feature_cap_mask * Supported port's enhanced features. * Based on feature_group index. * When bit is set, the feature is supported in the device. * Access: RO
*/ #define MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(_dw_num, _offset) \
MLXSW_ITEM_BIT_ARRAY(reg, mcam, mng_feature_cap_mask_dw##_dw_num, \
_offset, MLXSW_REG_BYTES_PER_DWORD, 1)
/* The access to the bits in the field 'mng_feature_cap_mask' is not same to * other mask fields in other registers. In most of the cases bit #0 is the * first one in the last dword. In MCAM register, the first dword contains bits * #0-#31 and so on, so the access to the bits is simpler using bit array per * dword. Declare each dword of 'mng_feature_cap_mask' field separately.
*/
MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(0, 0x28);
MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(1, 0x2C);
MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(2, 0x30);
MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(3, 0x34);
/* MGPC - Monitoring General Purpose Counter Set Register * The MGPC register retrieves and sets the General Purpose Counter Set.
*/ #define MLXSW_REG_MGPC_ID 0x9081 #define MLXSW_REG_MGPC_LEN 0x18
/* MPRS - Monitoring Parsing State Register * ---------------------------------------- * The MPRS register is used for setting up the parsing for hash, * policy-engine and routing.
*/ #define MLXSW_REG_MPRS_ID 0x9083 #define MLXSW_REG_MPRS_LEN 0x14
/* reg_mprs_parsing_depth * Minimum parsing depth. * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. * Access: RW
*/
MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16);
/* reg_mprs_parsing_en * Parsing enable. * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and * NVGRE. Default is enabled. Reserved when SwitchX-2. * Access: RW
*/
MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16);
/* reg_mprs_vxlan_udp_dport * VxLAN UDP destination port. * Used for identifying VxLAN packets and for dport field in * encapsulation. Default is 4789. * Access: RW
*/
MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16);
/* reg_mogcr_ptp_iftc * PTP Ingress FIFO Trap Clear * The PTP_ING_FIFO trap provides MTPPTR with clr according * to this value. Default 0. * Reserved when IB switches and when SwitchX/-2, Spectrum-2 * Access: RW
*/
MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1);
/* reg_mogcr_ptp_eftc * PTP Egress FIFO Trap Clear * The PTP_EGR_FIFO trap provides MTPPTR with clr according * to this value. Default 0. * Reserved when IB switches and when SwitchX/-2, Spectrum-2 * Access: RW
*/
MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1);
/* reg_mogcr_mirroring_pid_base * Base policer id for mirroring policers. * Must have an even value (e.g. 1000, not 1001). * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum. * Access: RW
*/
MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14);
/* MPAGR - Monitoring Port Analyzer Global Register * ------------------------------------------------ * This register is used for global port analyzer configurations. * Note: This register is not supported by current FW versions for Spectrum-1.
*/ #define MLXSW_REG_MPAGR_ID 0x9089 #define MLXSW_REG_MPAGR_LEN 0x0C
/* MOMTE - Monitoring Mirror Trigger Enable Register * ------------------------------------------------- * This register is used to configure the mirror enable for different mirror * reasons.
*/ #define MLXSW_REG_MOMTE_ID 0x908D #define MLXSW_REG_MOMTE_LEN 0x10
/* MTPPPC - Time Precision Packet Port Configuration * ------------------------------------------------- * This register serves for configuration of which PTP messages should be * timestamped. This is a global configuration, despite the register name. * * Reserved when Spectrum-2.
*/ #define MLXSW_REG_MTPPPC_ID 0x9090 #define MLXSW_REG_MTPPPC_LEN 0x28
/* reg_mtpppc_ing_timestamp_message_type * Bitwise vector of PTP message types to timestamp at ingress. * MessageType field as defined by IEEE 1588 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) * Default all 0 * Access: RW
*/
MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16);
/* reg_mtpppc_egr_timestamp_message_type * Bitwise vector of PTP message types to timestamp at egress. * MessageType field as defined by IEEE 1588 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) * Default all 0 * Access: RW
*/
MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16);
/* MTPPTR - Time Precision Packet Timestamping Reading * --------------------------------------------------- * The MTPPTR is used for reading the per port PTP timestamp FIFO. * There is a trap for packets which are latched to the timestamp FIFO, thus the * SW knows which FIFO to read. Note that packets enter the FIFO before been * trapped. The sequence number is used to synchronize the timestamp FIFO * entries and the trapped packets. * Reserved when Spectrum-2.
*/
#define MLXSW_REG_MTPPTR_ID 0x9091 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \
MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT)
/* reg_mtpptr_clr * Clear the records. * Access: OP
*/
MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1);
/* reg_mtpptr_num_rec * Number of valid records in the response * Range 0.. cap_ptp_timestamp_fifo * Access: RO
*/
MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4);
/* reg_mtpptr_rec_message_type * MessageType field as defined by IEEE 1588 Each bit corresponds to a value * (e.g. Bit0: Sync, Bit1: Delay_Req) * Access: RO
*/
MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type,
MLXSW_REG_MTPPTR_BASE_LEN, 8, 4,
MLXSW_REG_MTPPTR_REC_LEN, 0, false);
/* reg_mtpptr_rec_domain_number * DomainNumber field as defined by IEEE 1588 * Access: RO
*/
MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number,
MLXSW_REG_MTPPTR_BASE_LEN, 0, 8,
MLXSW_REG_MTPPTR_REC_LEN, 0, false);
/* reg_mtpptr_rec_sequence_id * SequenceId field as defined by IEEE 1588 * Access: RO
*/
MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id,
MLXSW_REG_MTPPTR_BASE_LEN, 0, 16,
MLXSW_REG_MTPPTR_REC_LEN, 0x4, false);
/* reg_mtpptr_rec_timestamp_high * Timestamp of when the PTP packet has passed through the port Units of PLL * clock time. * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. * Access: RO
*/
MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high,
MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
MLXSW_REG_MTPPTR_REC_LEN, 0x8, false);
/* MTPTPT - Monitoring Precision Time Protocol Trap Register * --------------------------------------------------------- * This register is used for configuring under which trap to deliver PTP * packets depending on type of the packet.
*/ #define MLXSW_REG_MTPTPT_ID 0x9092 #define MLXSW_REG_MTPTPT_LEN 0x08
/* reg_mtptpt_message_type * Bitwise vector of PTP message types to trap. This is a necessary but * non-sufficient condition since need to enable also per port. See MTPPPC. * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. * Bit0: Sync, Bit1: Delay_Req)
*/
MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16);
/* reg_mtpcpc_pport * Per port: * 0: config is global. When reading - the local_port is 1. * 1: config is per port. * Access: Index
*/
MLXSW_ITEM32(reg, mtpcpc, pport, 0x00, 31, 1);
/* reg_mtpcpc_local_port * Local port number. * Supported to/from CPU port. * Reserved when pport = 0. * Access: Index
*/
MLXSW_ITEM32_LP(reg, mtpcpc, 0x00, 16, 0x00, 12);
/* reg_mtpcpc_ptp_trap_en * Enable PTP traps. * The trap_id is configured by MTPTPT. * Access: RW
*/
MLXSW_ITEM32(reg, mtpcpc, ptp_trap_en, 0x04, 0, 1);
/* reg_mtpcpc_ing_correction_message_type * Bitwise vector of PTP message types to update correction-field at ingress. * MessageType field as defined by IEEE 1588 Each bit corresponds to a value * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port. * Default all 0 * Access: RW
*/
MLXSW_ITEM32(reg, mtpcpc, ing_correction_message_type, 0x10, 0, 16);
/* reg_mtpcpc_egr_correction_message_type * Bitwise vector of PTP message types to update correction-field at egress. * MessageType field as defined by IEEE 1588 Each bit corresponds to a value * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port. * Default all 0 * Access: RW
*/
MLXSW_ITEM32(reg, mtpcpc, egr_correction_message_type, 0x14, 0, 16);
/* MGPIR - Management General Peripheral Information Register * ---------------------------------------------------------- * MGPIR register allows software to query the hardware and * firmware general information of peripheral entities.
*/ #define MLXSW_REG_MGPIR_ID 0x9100 #define MLXSW_REG_MGPIR_LEN 0xA0
/* mgpir_devices_per_flash * Number of devices of device_type per flash (can be shared by few devices). * Access: RO
*/
MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8);
/* mgpir_num_of_devices * Number of devices of device_type. * Access: RO
*/
MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8);
/* max_modules_per_slot * Maximum number of modules that can be connected per slot. * Access: RO
*/
MLXSW_ITEM32(reg, mgpir, max_modules_per_slot, 0x04, 16, 8);
/* mgpir_num_of_slots * Number of slots in the system. * Access: RO
*/
MLXSW_ITEM32(reg, mgpir, num_of_slots, 0x04, 8, 8);
/* mgpir_num_of_modules * Number of modules. * Access: RO
*/
MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8);
staticinlinevoid
mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, enum mlxsw_reg_mgpir_device_type *device_type,
u8 *devices_per_flash, u8 *num_of_modules,
u8 *num_of_slots)
{ if (num_of_devices)
*num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); if (device_type)
*device_type = mlxsw_reg_mgpir_device_type_get(payload); if (devices_per_flash)
*devices_per_flash =
mlxsw_reg_mgpir_devices_per_flash_get(payload); if (num_of_modules)
*num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); if (num_of_slots)
*num_of_slots = mlxsw_reg_mgpir_num_of_slots_get(payload);
}
/* MBCT - Management Binary Code Transfer Register * ----------------------------------------------- * This register allows to transfer binary codes from the host to * the management FW by transferring it by chunks of maximum 1KB.
*/ #define MLXSW_REG_MBCT_ID 0x9120 #define MLXSW_REG_MBCT_LEN 0x420
/* reg_mbct_slot_index * Slot index. 0 is reserved. * Access: Index
*/
MLXSW_ITEM32(reg, mbct, slot_index, 0x00, 0, 4);
/* reg_mbct_data_size * Actual data field size in bytes for the current data transfer. * Access: WO
*/
MLXSW_ITEM32(reg, mbct, data_size, 0x04, 0, 11);
/* reg_mbct_last * Indicates that the current data field is the last chunk of the INI. * Access: WO
*/
MLXSW_ITEM32(reg, mbct, last, 0x08, 26, 1);
/* reg_mbct_oee * Opcode Event Enable. When set a BCTOE event will be sent once the opcode * was executed and the fsm_state has changed. * Access: WO
*/
MLXSW_ITEM32(reg, mbct, oee, 0x08, 25, 1);
enum mlxsw_reg_mbct_status { /* Partial data transfer completed successfully and ready for next * data transfer.
*/
MLXSW_REG_MBCT_STATUS_PART_DATA = 2,
MLXSW_REG_MBCT_STATUS_LAST_DATA,
MLXSW_REG_MBCT_STATUS_ERASE_COMPLETE, /* Error - trying to erase INI while it being used. */
MLXSW_REG_MBCT_STATUS_ERROR_INI_IN_USE, /* Last data transfer completed, applying magic pattern. */
MLXSW_REG_MBCT_STATUS_ERASE_FAILED = 7,
MLXSW_REG_MBCT_STATUS_INI_ERROR,
MLXSW_REG_MBCT_STATUS_ACTIVATION_FAILED,
MLXSW_REG_MBCT_STATUS_ILLEGAL_OPERATION = 11,
};
/* MDDQ - Management DownStream Device Query Register * -------------------------------------------------- * This register allows to query the DownStream device properties. The desired * information is chosen upon the query_type field and is delivered by 32B * of data blocks.
*/ #define MLXSW_REG_MDDQ_ID 0x9161 #define MLXSW_REG_MDDQ_LEN 0x30
/* reg_mddq_sie * Slot info event enable. * When set to '1', each change in the slot_info.provisioned / sr_valid / * active / ready will generate a DSDSC event. * Access: RW
*/
MLXSW_ITEM32(reg, mddq, sie, 0x00, 31, 1);
enum mlxsw_reg_mddq_query_type {
MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO = 1,
MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO, /* If there are no devices * on the slot, data_valid * will be '0'.
*/
MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME,
};
/* reg_mddq_slot_index * Slot index. 0 is reserved. * Access: Index
*/
MLXSW_ITEM32(reg, mddq, slot_index, 0x00, 0, 4);
/* reg_mddq_response_msg_seq * Response message sequential number. For a specific request, the response * message sequential number is the following one. In addition, the last * message should be 0. * Access: RO
*/
MLXSW_ITEM32(reg, mddq, response_msg_seq, 0x04, 16, 8);
/* reg_mddq_request_msg_seq * Request message sequential number. * The first message number should be 0. * Access: Index
*/
MLXSW_ITEM32(reg, mddq, request_msg_seq, 0x04, 0, 8);
/* reg_mddq_data_valid * If set, the data in the data field is valid and contain the information * for the queried index. * Access: RO
*/
MLXSW_ITEM32(reg, mddq, data_valid, 0x08, 31, 1);
/* reg_mddq_slot_info_provisioned * If set, the INI file is applied and the card is provisioned. * Access: RO
*/
MLXSW_ITEM32(reg, mddq, slot_info_provisioned, 0x10, 31, 1);
/* reg_mddq_slot_info_sr_valid * If set, Shift Register is valid (after being provisioned) and data * can be sent from the switch ASIC to the line-card CPLD over Shift-Register. * Access: RO
*/
MLXSW_ITEM32(reg, mddq, slot_info_sr_valid, 0x10, 30, 1);
/* reg_mddq_slot_info_lc_ready * If set, the LC is powered on, matching the INI version and a new FW * version can be burnt (if necessary). * Access: RO
*/
MLXSW_ITEM32(reg, mddq, slot_info_lc_ready, 0x10, 28, 2);
/* reg_mddq_slot_info_active * If set, the FW has completed the MDDC.device_enable command. * Access: RO
*/
MLXSW_ITEM32(reg, mddq, slot_info_active, 0x10, 27, 1);
/* reg_mddq_slot_info_hw_revision * Major user-configured version number of the current INI file. * Valid only when active or ready are '1'. * Access: RO
*/
MLXSW_ITEM32(reg, mddq, slot_info_hw_revision, 0x14, 16, 16);
/* reg_mddq_slot_info_ini_file_version * User-configured version number of the current INI file. * Valid only when active or lc_ready are '1'. * Access: RO
*/
MLXSW_ITEM32(reg, mddq, slot_info_ini_file_version, 0x14, 0, 16);
/* reg_mddq_device_info_flash_owner * If set, the device is the flash owner. Otherwise, a shared flash * is used by this device (another device is the flash owner). * Access: RO
*/
MLXSW_ITEM32(reg, mddq, device_info_flash_owner, 0x10, 30, 1);
/* reg_mddq_device_info_device_index * Device index. The first device should number 0. * Access: RO
*/
MLXSW_ITEM32(reg, mddq, device_info_device_index, 0x10, 0, 8);
/* reg_mddq_device_info_fw_major * Major FW version number. * Access: RO
*/
MLXSW_ITEM32(reg, mddq, device_info_fw_major, 0x14, 16, 16);
/* reg_mddq_device_info_fw_minor * Minor FW version number. * Access: RO
*/
MLXSW_ITEM32(reg, mddq, device_info_fw_minor, 0x18, 16, 16);
/* MDDC - Management DownStream Device Control Register * ---------------------------------------------------- * This register allows to control downstream devices and line cards.
*/ #define MLXSW_REG_MDDC_ID 0x9163 #define MLXSW_REG_MDDC_LEN 0x30
/* reg_mddc_device_enable * When set, FW is the manager and allowed to program the downstream device. * Access: RW
*/
MLXSW_ITEM32(reg, mddc, device_enable, 0x04, 28, 1);
/* reg_mfde_fw_assert_existptr * The instruction pointer when assert was triggered. * Access: RO
*/
MLXSW_ITEM32(reg, mfde, fw_assert_existptr, 0x24, 0, 32);
/* reg_mfde_fw_assert_callra * The return address after triggering assert. * Access: RO
*/
MLXSW_ITEM32(reg, mfde, fw_assert_callra, 0x28, 0, 32);
/* reg_mfde_fw_assert_oe * 0 - New event * 1 - Old event, occurred before MFGD activation. * Access: RO
*/
MLXSW_ITEM32(reg, mfde, fw_assert_oe, 0x2C, 24, 1);
/* reg_mfde_fw_assert_tile_v * 0: The assert was from main * 1: The assert was from a tile * Access: RO
*/
MLXSW_ITEM32(reg, mfde, fw_assert_tile_v, 0x2C, 23, 1);
/* reg_mfde_fw_assert_tile_index * When tile_v=1, the tile_index that caused the assert. * Access: RO
*/
MLXSW_ITEM32(reg, mfde, fw_assert_tile_index, 0x2C, 16, 6);
/* reg_mfde_fw_assert_ext_synd * A generated one-to-one identifier which is specific per-assert. * Access: RO
*/
MLXSW_ITEM32(reg, mfde, fw_assert_ext_synd, 0x2C, 0, 16);
/* reg_mfde_fatal_cause_tile_v * 0: The assert was from main * 1: The assert was from a tile * Access: RO
*/
MLXSW_ITEM32(reg, mfde, fatal_cause_tile_v, 0x14, 23, 1);
/* reg_mfde_fatal_cause_tile_index * When tile_v=1, the tile_index that caused the assert. * Access: RO
*/
MLXSW_ITEM32(reg, mfde, fatal_cause_tile_index, 0x14, 16, 6);
/* TNGCR - Tunneling NVE General Configuration Register * ---------------------------------------------------- * The TNGCR register is used for setting up the NVE Tunneling configuration.
*/ #define MLXSW_REG_TNGCR_ID 0xA001 #define MLXSW_REG_TNGCR_LEN 0x44
/* reg_tngcr_type * Tunnel type for encapsulation and decapsulation. The types are mutually * exclusive. * Note: For Spectrum the NVE parsing must be enabled in MPRS. * Access: RW
*/
MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4);
/* reg_tngcr_nve_valid * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. * Access: RW
*/
MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1);
enum { /* Do not copy flow label. Calculate flow label using nve_flh. */
MLXSW_REG_TNGCR_FL_NO_COPY, /* Copy flow label from inner packet if packet is IPv6 and * encapsulation is by IPv6. Otherwise, calculate flow label using * nve_flh.
*/
MLXSW_REG_TNGCR_FL_COPY,
};
enum { /* Flow label is static. In Spectrum this means '0'. Spectrum-2 * uses {nve_fl_prefix, nve_fl_suffix}.
*/
MLXSW_REG_TNGCR_FL_NO_HASH, /* 8 LSBs of the flow label are calculated from ECMP hash of the * inner packet. 12 MSBs are configured by nve_fl_prefix.
*/
MLXSW_REG_TNGCR_FL_HASH,
};
/* reg_tngcr_nve_fl_suffix * NVE flow label suffix. Constant 8 LSBs of the flow label. * Reserved when nve_flh=1 and for Spectrum. * Access: RW
*/
MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8);
enum { /* Source UDP port is fixed (default '0') */
MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, /* Source UDP port is calculated based on hash */
MLXSW_REG_TNGCR_UDP_SPORT_HASH,
};
/* reg_tngcr_nve_udp_sport_type * NVE UDP source port type. * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). * When the source UDP port is calculated based on hash, then the 8 LSBs * are calculated from hash the 8 MSBs are configured by * nve_udp_sport_prefix. * Access: RW
*/
MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1);
/* reg_tngcr_nve_udp_sport_prefix * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. * Reserved when NVE type is NVGRE. * Access: RW
*/
MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8);
/* reg_tngcr_nve_group_size_mc * The amount of sequential linked lists of MC entries. The first linked * list is configured by SFD.underlay_mc_ptr. * Valid values: 1, 2, 4, 8, 16, 32, 64 * The linked list are configured by TNUMT. * The hash is set by LAG hash. * Access: RW
*/
MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8);
/* reg_tngcr_nve_group_size_flood * The amount of sequential linked lists of flooding entries. The first * linked list is configured by SFMR.nve_tunnel_flood_ptr * Valid values: 1, 2, 4, 8, 16, 32, 64 * The linked list are configured by TNUMT. * The hash is set by LAG hash. * Access: RW
*/
MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8);
/* reg_tngcr_learn_enable * During decapsulation, whether to learn from NVE port. * Reserved when Spectrum-2. See TNPC. * Access: RW
*/
MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1);
/* reg_tngcr_underlay_rif * Underlay ingress router interface. RIF type should be loopback generic. * Reserved when Spectrum. * Access: RW
*/
MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16);
/* reg_tngcr_usipv4 * Underlay source IPv4 address of the NVE. * Access: RW
*/
MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32);
/* reg_tngcr_usipv6 * Underlay source IPv6 address of the NVE. For Spectrum, must not be * modified under traffic of NVE tunneling encapsulation. * Access: RW
*/
MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16);
/* TNUMT - Tunneling NVE Underlay Multicast Table Register * ------------------------------------------------------- * The TNUMT register is for building the underlay MC table. It is used * for MC, flooding and BC traffic into the NVE tunnel.
*/ #define MLXSW_REG_TNUMT_ID 0xA003 #define MLXSW_REG_TNUMT_LEN 0x20
/* reg_tnumt_underlay_mc_ptr * Index to the underlay multicast table. * For Spectrum the index is to the KVD linear. * Access: Index
*/
MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24);
/* reg_tnumt_vnext * The next_underlay_mc_ptr is valid. * Access: RW
*/
MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1);
/* reg_tnumt_next_underlay_mc_ptr * The next index to the underlay multicast table. * Access: RW
*/
MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24);
/* reg_tnumt_record_size * Number of IP addresses in the record. * Range is 1..cap_max_nve_mc_entries_ipv{4,6} * Access: RW
*/
MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3);
/* reg_tnumt_udip * The underlay IPv4 addresses. udip[i] is reserved if i >= size * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false);
/* reg_tnumt_udip_ptr * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if * i >= size. The IPv6 addresses are configured by RIPS. * Access: RW
*/
MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false);
/* TNQCR - Tunneling NVE QoS Configuration Register * ------------------------------------------------ * The TNQCR register configures how QoS is set in encapsulation into the * underlay network.
*/ #define MLXSW_REG_TNQCR_ID 0xA010 #define MLXSW_REG_TNQCR_LEN 0x0C
/* reg_tnqcr_enc_set_dscp * For encapsulation: How to set DSCP field: * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay * (outer) IP header. If there is no IP header, use TNQDR.dscp * 1 - Set the DSCP field as TNQDR.dscp * Access: RW
*/
MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1);
/* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register * -------------------------------------------------------- * The TNEEM register maps ECN of the IP header at the ingress to the * encapsulation to the ECN of the underlay network.
*/ #define MLXSW_REG_TNEEM_ID 0xA012 #define MLXSW_REG_TNEEM_LEN 0x0C
/* reg_tndem_underlay_ecn * ECN field of the IP header in the underlay network. * Access: Index
*/
MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2);
/* reg_tndem_overlay_ecn * ECN field of the IP header in the overlay network. * Access: Index
*/
MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2);
/* reg_tndem_eip_ecn * Egress IP ECN. ECN field of the IP header of the packet which goes out * from the decapsulation. * Access: RW
*/
MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2);
/* reg_tndem_trap_en * Trap enable: * 0 - No trap due to decap ECN * 1 - Trap enable with trap_id * Access: RW
*/
MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4);
/* reg_tndem_trap_id * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. * Reserved when trap_en is '0'. * Access: RW
*/
MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9);
/* TNPC - Tunnel Port Configuration Register * ----------------------------------------- * The TNPC register is used for tunnel port configuration. * Reserved when Spectrum.
*/ #define MLXSW_REG_TNPC_ID 0xA020 #define MLXSW_REG_TNPC_LEN 0x18
/* TIGCR - Tunneling IPinIP General Configuration Register * ------------------------------------------------------- * The TIGCR register is used for setting up the IPinIP Tunnel configuration.
*/ #define MLXSW_REG_TIGCR_ID 0xA801 #define MLXSW_REG_TIGCR_LEN 0x10
/* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register * ----------------------------------------------------------- * The TIEEM register maps ECN of the IP header at the ingress to the * encapsulation to the ECN of the underlay network.
*/ #define MLXSW_REG_TIEEM_ID 0xA812 #define MLXSW_REG_TIEEM_LEN 0x0C
/* reg_tidem_underlay_ecn * ECN field of the IP header in the underlay network. * Access: Index
*/
MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2);
/* reg_tidem_overlay_ecn * ECN field of the IP header in the overlay network. * Access: Index
*/
MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2);
/* reg_tidem_eip_ecn * Egress IP ECN. ECN field of the IP header of the packet which goes out * from the decapsulation. * Access: RW
*/
MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2);
/* reg_tidem_trap_en * Trap enable: * 0 - No trap due to decap ECN * 1 - Trap enable with trap_id * Access: RW
*/
MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4);
/* reg_tidem_trap_id * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. * Reserved when trap_en is '0'. * Access: RW
*/
MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9);
/* SBCM - Shared Buffer Class Management Register * ---------------------------------------------- * The SBCM register configures and retrieves the shared buffer allocation * and configuration according to Port-PG, including the binding to pool * and definition of the associated quota.
*/ #define MLXSW_REG_SBCM_ID 0xB002 #define MLXSW_REG_SBCM_LEN 0x28
/* reg_sbcm_local_port * Local port number. * For Ingress: excludes CPU port and Router port * For Egress: excludes IP Router * Access: Index
*/
MLXSW_ITEM32_LP(reg, sbcm, 0x00, 16, 0x00, 4);
/* reg_sbcm_pg_buff * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) * For PG buffer: range is 0..cap_max_pg_buffers - 1 * For traffic class: range is 0..cap_max_tclass - 1 * Note that when traffic class is in MC aware mode then the traffic * classes which are MC aware cannot be configured. * Access: Index
*/
MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
/* reg_sbcm_min_buff * Minimum buffer size for the limiter, in cells. * Access: RW
*/
MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
/* shared max_buff limits for dynamic threshold for SBCM, SBPM */ #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
/* reg_sbcm_infi_max * Max buffer is infinite. * Access: RW
*/
MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1);
/* reg_sbcm_max_buff * When the pool associated to the port-pg/tclass is configured to * static, Maximum buffer size for the limiter configured in cells. * When the pool associated to the port-pg/tclass is configured to * dynamic, the max_buff holds the "alpha" parameter, supporting * the following values: * 0: 0 * i: (1/128)*2^(i-1), for i=1..14 * 0xFF: Infinity * Reserved when infi_max = 1. * Access: RW
*/
MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
/* reg_sbcm_pool * Association of the port-priority to a pool. * Access: RW
*/
MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
/* SBPM - Shared Buffer Port Management Register * --------------------------------------------- * The SBPM register configures and retrieves the shared buffer allocation * and configuration according to Port-Pool, including the definition * of the associated quota.
*/ #define MLXSW_REG_SBPM_ID 0xB003 #define MLXSW_REG_SBPM_LEN 0x28
/* reg_sbpm_local_port * Local port number. * For Ingress: excludes CPU port and Router port * For Egress: excludes IP Router * Access: Index
*/
MLXSW_ITEM32_LP(reg, sbpm, 0x00, 16, 0x00, 12);
/* reg_sbpm_pool * The pool associated to quota counting on the local_port. * Access: Index
*/
MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
/* reg_sbpm_buff_occupancy * Current buffer occupancy in cells. * Access: RO
*/
MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
/* reg_sbpm_clr * Clear Max Buffer Occupancy * When this bit is set, max_buff_occupancy field is cleared (and a * new max value is tracked from the time the clear was performed). * Access: OP
*/
MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
/* reg_sbpm_max_buff_occupancy * Maximum value of buffer occupancy in cells monitored. Cleared by * writing to the clr field. * Access: RO
*/
MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
/* reg_sbpm_min_buff * Minimum buffer size for the limiter, in cells. * Access: RW
*/
MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
/* reg_sbpm_max_buff * When the pool associated to the port-pg/tclass is configured to * static, Maximum buffer size for the limiter configured in cells. * When the pool associated to the port-pg/tclass is configured to * dynamic, the max_buff holds the "alpha" parameter, supporting * the following values: * 0: 0 * i: (1/128)*2^(i-1), for i=1..14 * 0xFF: Infinity * Access: RW
*/
MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
/* SBMM - Shared Buffer Multicast Management Register * -------------------------------------------------- * The SBMM register configures and retrieves the shared buffer allocation * and configuration for MC packets according to Switch-Priority, including * the binding to pool and definition of the associated quota.
*/ #define MLXSW_REG_SBMM_ID 0xB004 #define MLXSW_REG_SBMM_LEN 0x28
/* reg_sbmm_min_buff * Minimum buffer size for the limiter, in cells. * Access: RW
*/
MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
/* reg_sbmm_max_buff * When the pool associated to the port-pg/tclass is configured to * static, Maximum buffer size for the limiter configured in cells. * When the pool associated to the port-pg/tclass is configured to * dynamic, the max_buff holds the "alpha" parameter, supporting * the following values: * 0: 0 * i: (1/128)*2^(i-1), for i=1..14 * 0xFF: Infinity * Access: RW
*/
MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
/* reg_sbmm_pool * Association of the port-priority to a pool. * Access: RW
*/
MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
/* SBSR - Shared Buffer Status Register * ------------------------------------ * The SBSR register retrieves the shared buffer occupancy according to * Port-Pool. Note that this register enables reading a large amount of data. * It is the user's responsibility to limit the amount of data to ensure the * response can match the maximum transfer unit. In case the response exceeds * the maximum transport unit, it will be truncated with no special notice.
*/ #define MLXSW_REG_SBSR_ID 0xB005 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \
MLXSW_REG_SBSR_REC_LEN * \
MLXSW_REG_SBSR_REC_MAX_COUNT)
/* reg_sbsr_clr * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy * field is cleared (and a new max value is tracked from the time the clear * was performed). * Access: OP
*/
MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
#define MLXSW_REG_SBSR_NUM_PORTS_IN_PAGE 256
/* reg_sbsr_port_page * Determines the range of the ports specified in the 'ingress_port_mask' * and 'egress_port_mask' bit masks. * {ingress,egress}_port_mask[x] is (256 * port_page) + x * Access: Index
*/
MLXSW_ITEM32(reg, sbsr, port_page, 0x04, 0, 4);
/* reg_sbsr_ingress_port_mask * Bit vector for all ingress network ports. * Indicates which of the ports (for which the relevant bit is set) * are affected by the set operation. Configuration of any other port * does not change. * Access: Index
*/
MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
/* reg_sbsr_pg_buff_mask * Bit vector for all switch priority groups. * Indicates which of the priorities (for which the relevant bit is set) * are affected by the set operation. Configuration of any other priority * does not change. * Range is 0..cap_max_pg_buffers - 1 * Access: Index
*/
MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
/* reg_sbsr_egress_port_mask * Bit vector for all egress network ports. * Indicates which of the ports (for which the relevant bit is set) * are affected by the set operation. Configuration of any other port * does not change. * Access: Index
*/
MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
/* reg_sbsr_tclass_mask * Bit vector for all traffic classes. * Indicates which of the traffic classes (for which the relevant bit is * set) are affected by the set operation. Configuration of any other * traffic class does not change. * Range is 0..cap_max_tclass - 1 * Access: Index
*/
MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
/* reg_sbsr_rec_max_buff_occupancy * Maximum value of buffer occupancy in cells monitored. Cleared by * writing to the clr field. * Access: RO
*/
MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
/* SBIB - Shared Buffer Internal Buffer Register * --------------------------------------------- * The SBIB register configures per port buffers for internal use. The internal * buffers consume memory on the port buffers (note that the port buffers are * used also by PBMC). * * For Spectrum this is used for egress mirroring.
*/ #define MLXSW_REG_SBIB_ID 0xB006 #define MLXSW_REG_SBIB_LEN 0x10
/* reg_sbib_local_port * Local port number * Not supported for CPU port and router port * Access: Index
*/
MLXSW_ITEM32_LP(reg, sbib, 0x00, 16, 0x00, 12);
/* reg_sbib_buff_size * Units represented in cells * Allowed range is 0 to (cap_max_headroom_size - 1) * Default is 0 * Access: RW
*/
MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
staticinlineconstchar *mlxsw_reg_id_str(u16 reg_id)
{ conststruct mlxsw_reg_info *reg_info; int i;
for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) {
reg_info = mlxsw_reg_infos[i]; if (reg_info->id == reg_id) return reg_info->name;
} return"*UNKNOWN*";
}
/* PUDE - Port Up / Down Event * --------------------------- * Reports the operational state change of a port.
*/ #define MLXSW_REG_PUDE_LEN 0x10
/* reg_pude_swid * Switch partition ID with which to associate the port. * Access: Index
*/
MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
/* reg_pude_local_port * Local port number. * Access: Index
*/
MLXSW_ITEM32_LP(reg, pude, 0x00, 16, 0x00, 12);
/* reg_pude_admin_status * Port administrative state (the desired state). * 1 - Up. * 2 - Down. * 3 - Up once. This means that in case of link failure, the port won't go * into polling mode, but will wait to be re-enabled by software. * 4 - Disabled by system. Can only be set by hardware. * Access: RO
*/
MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
/* reg_pude_oper_status * Port operatioanl state. * 1 - Up. * 2 - Down. * 3 - Down by port failure. This means that the device will not let the * port up again until explicitly specified by software. * Access: RO
*/
MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
#endif
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nach bestem Wissen sorgfältig zusammengestellt. Es wird jedoch weder Vollständigkeit, noch Richtigkeit,
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