/************************************************************************ * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC * Copyright(c) 2002-2010 Exar Corp.
* This software may be used and distributed according to the terms of * the GNU General Public License (GPL), incorporated herein by reference. * Drivers based on or derived from this code fall under the GPL and must * retain the authorship, copyright and license notice. This file is not * a complete program and may only be used when the entire operating * system is licensed under the GPL. * See the file COPYING in this distribution for more information.
************************************************************************/ #include <linux/io-64-nonatomic-lo-hi.h> #ifndef _S2IO_H #define _S2IO_H
/* Maintains Per FIFO related information. */ struct tx_fifo_config { #define MAX_AVAILABLE_TXDS 8192
u32 fifo_len; /* specifies len of FIFO up to 8192, ie no of TxDLs */ /* Priority definition */ #define TX_FIFO_PRI_0 0 /*Highest */ #define TX_FIFO_PRI_1 1 #define TX_FIFO_PRI_2 2 #define TX_FIFO_PRI_3 3 #define TX_FIFO_PRI_4 4 #define TX_FIFO_PRI_5 5 #define TX_FIFO_PRI_6 6 #define TX_FIFO_PRI_7 7 /*lowest */
u8 fifo_priority; /* specifies pointer level for FIFO */ /* user should not set twos fifos with same pri */
u8 f_no_snoop; #define NO_SNOOP_TXD 0x01 #define NO_SNOOP_TXD_BUFFER 0x02
};
/* Maintains per Ring related information */ struct rx_ring_config {
u32 num_rxd; /*No of RxDs per Rx Ring */ #define RX_RING_PRI_0 0 /* highest */ #define RX_RING_PRI_1 1 #define RX_RING_PRI_2 2 #define RX_RING_PRI_3 3 #define RX_RING_PRI_4 4 #define RX_RING_PRI_5 5 #define RX_RING_PRI_6 6 #define RX_RING_PRI_7 7 /* lowest */
u8 ring_priority; /*Specifies service priority of ring */ /* OSM should not set any two rings with same priority */
u8 ring_org; /*Organization of ring */ #define RING_ORG_BUFF1 0x01 #define RX_RING_ORG_BUFF3 0x03 #define RX_RING_ORG_BUFF5 0x05
/* This structure provides contains values of the tunable parameters * of the H/W
*/ struct config_param { /* Tx Side */
u32 tx_fifo_num; /*Number of Tx FIFOs */
/* Structure that represents the Rx descriptor block which contains * 128 Rx descriptors.
*/ struct RxD_block { #define MAX_RXDS_PER_BLOCK_1 127 struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
u64 reserved_0; #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
* Rxd in this blk */
u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch * the upper 32 bits should
* be 0 */
};
#define SIZE_OF_BLOCK 4096
#define RXD_MODE_1 0 /* One Buffer mode */ #define RXD_MODE_3B 1 /* Two Buffer mode */
/* Structure to hold virtual addresses of Buf0 and Buf1 in
* 2buf mode. */ struct buffAdd { void *ba_0_org; void *ba_1_org; void *ba_0; void *ba_1;
};
/* Structure which stores all the MAC control parameters */
/* This structure stores the offset of the RxD in the ring * from which the Rx Interrupt processor can start picking * up the RxDs for processing.
*/ struct rx_curr_get_info {
u32 block_index;
u32 offset;
u32 ring_len;
};
/* This structure stores the offset of the TxDl in the FIFO * from which the Tx Interrupt processor can start picking * up the TxDLs for send complete interrupt processing.
*/ struct tx_curr_get_info {
u32 offset;
u32 fifo_len;
};
/* Structure that holds the Phy and virt addresses of the Blocks */ struct rx_block_info { void *block_virt_addr;
dma_addr_t block_dma_addr; struct rxd_info *rxds;
};
/* Data structure to represent a LRO session */ struct lro { struct sk_buff *parent; struct sk_buff *last_frag;
u8 *l2h; struct iphdr *iph; struct tcphdr *tcph;
u32 tcp_next_seq;
__be32 tcp_ack; int total_len; int frags_len; int sg_num; int in_use;
__be16 window;
u16 vlan_tag;
u32 cur_tsval;
__be32 cur_tsecr;
u8 saw_ts;
} ____cacheline_aligned;
/* Ring specific structure */ struct ring_info { /* The ring number */ int ring_no;
/* Number of rxds per block for the rxd_mode */ int rxd_count;
/* copy of sp pointer */ struct s2io_nic *nic;
/* copy of sp->dev pointer */ struct net_device *dev;
/* copy of sp->pdev pointer */ struct pci_dev *pdev;
/* Per ring napi struct */ struct napi_struct napi;
unsignedlong interrupt_count;
/* * Place holders for the virtual and physical addresses of * all the Rx Blocks
*/ struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING]; int block_count; int pkt_cnt;
/* * Put pointer info which indictes which RxD has to be replenished * with a new buffer.
*/ struct rx_curr_put_info rx_curr_put_info;
/* * Get pointer info which indictes which is the last RxD that was * processed by the driver.
*/ struct rx_curr_get_info rx_curr_get_info;
/* Fifo specific structure */ struct fifo_info { /* FIFO number */ int fifo_no;
/* Maximum TxDs per TxDL */ int max_txds;
/* Place holder of all the TX List's Phy and Virt addresses. */ struct list_info_hold *list_info;
/* * Current offset within the tx FIFO where driver would write * new Tx frame
*/ struct tx_curr_put_info tx_curr_put_info;
/* * Current offset within tx FIFO from where the driver would start freeing * the buffers
*/ struct tx_curr_get_info tx_curr_get_info; #define FIFO_QUEUE_START 0 #define FIFO_QUEUE_STOP 1 int queue_state;
/* copy of sp->dev pointer */ struct net_device *dev;
/* copy of multiq status */
u8 multiq;
/* Per fifo lock */
spinlock_t tx_lock;
/* Per fifo UFO in band structure */
u64 *ufo_in_band_v;
struct s2io_nic *nic;
} ____cacheline_aligned;
/* Information related to the Tx and Rx FIFOs and Rings of Xena * is maintained in this structure.
*/ struct mac_info { /* tx side stuff */ /* logical pointer of start of each Tx FIFO */ struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
/* Fifo specific structure */ struct fifo_info fifos[MAX_TX_FIFOS];
/* Save virtual address of TxD page with zero DMA addr(if any) */ void *zerodma_virt_addr;
/* rx side stuff */ /* Ring specific structure */ struct ring_info rings[MAX_RX_RINGS];
void *stats_mem; /* orignal pointer to allocated mem */
dma_addr_t stats_mem_phy; /* Physical address of the stat block */
u32 stats_mem_sz; struct stat_block *stats_info; /* Logical address of the stat block */
};
/* Default Tunable parameters of the NIC. */ #define DEFAULT_FIFO_0_LEN 4096 #define DEFAULT_FIFO_1_7_LEN 512 #define SMALL_BLK_CNT 30 #define LARGE_BLK_CNT 100
/* * Structure to keep track of the MSI-X vectors and the corresponding * argument registered against each vector
*/ #define MAX_REQUESTED_MSI_X 9 struct s2io_msix_entry
{
u16 vector;
u16 entry; void *arg;
/* These flags represent the devices temporary state */ enum s2io_device_state_t
{
__S2IO_STATE_LINK_TASK=0,
__S2IO_STATE_CARD_UP
};
/* Structure representing one instance of the NIC */ struct s2io_nic { int rxd_mode; /* * Count of packets to be processed in a given iteration, it will be indicated * by the quota field of the device structure when NAPI is enabled.
*/ int pkts_to_process; struct net_device *dev; struct mac_info mac_control; struct config_param config; struct pci_dev *pdev; void __iomem *bar0; void __iomem *bar1; #define MAX_MAC_SUPPORTED 16 #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
struct mac_addr def_mac_addr[256];
struct net_device_stats stats; int device_enabled_once;
char name[60];
/* Timer that handles I/O errors/exceptions */ struct timer_list alarm_timer;
/* Space to back up the PCI config space */
u32 config_space[256 / sizeof(u32)];
/* Restart timer, used to restart NIC if the device is stuck and * a schedule task that will set the correct Link state once the * NIC's PHY has stabilized after a state change.
*/ struct work_struct rst_timer_task; struct work_struct set_link_task;
/* Flag that can be used to turn on or turn off the Rx checksum * offload feature.
*/ int rx_csum;
/* Below variables are used for fifo selection to transmit a packet */
u16 fifo_selector[MAX_TX_FIFOS];
/* Total fifos for tcp packets */
u8 total_tcp_fifos;
/* * Beginning index of udp for udp packets * Value will be equal to * (tx_fifo_num - FIFO_UDP_MAX_NUM - FIFO_OTHER_MAX_NUM)
*/
u8 udp_fifo_idx;
u8 total_udp_fifos;
/* * Beginning index of fifo for all other packets * Value will be equal to (tx_fifo_num - FIFO_OTHER_MAX_NUM)
*/
u8 other_fifo_idx;
struct napi_struct napi; /* after blink, the adapter must be restored with original * values.
*/
u64 adapt_ctrl_org;
/* Last known link state. */
u16 last_link_state; #define LINK_DOWN 1 #define LINK_UP 2
int task_flag; unsignedlonglong start_time; int vlan_strip_flag; #define MSIX_FLG 0xA5 int num_entries; struct msix_entry *entries; int msi_detected;
wait_queue_head_t msi_wait; struct s2io_msix_entry *s2io_entries; char desc[MAX_REQUESTED_MSI_X][25];
int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
/* * Some registers have to be written in a particular order to * expect correct hardware operation. The macro SPECIAL_REG_WRITE * is used to perform such ordered writes. Defines UF (Upper First) * and LF (Lower First) will be used to specify the required write order.
*/ #define UF 1 #define LF 2 staticinlinevoid SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
{ if (order == LF) {
writel((u32) (val), addr);
(void) readl(addr);
writel((u32) (val >> 32), (addr + 4));
(void) readl(addr + 4);
} else {
writel((u32) (val >> 32), (addr + 4));
(void) readl(addr + 4);
writel((u32) (val), addr);
(void) readl(addr);
}
}
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