/** * struct ionic_admin_cmd - General admin command format * @opcode: Opcode for the command * @rsvd: reserved byte(s) * @lif_index: LIF index * @cmd_data: Opcode-specific command bytes
*/ struct ionic_admin_cmd {
u8 opcode;
u8 rsvd;
__le16 lif_index;
u8 cmd_data[60];
};
/** * struct ionic_admin_comp - General admin command completion format * @status: Status of the command (enum ionic_status_code) * @rsvd: reserved byte(s) * @comp_index: Index in the descriptor ring for which this is the completion * @cmd_data: Command-specific bytes * @color: Color bit (Always 0 for commands issued to the * Device Cmd Registers)
*/ struct ionic_admin_comp {
u8 status;
u8 rsvd;
__le16 comp_index;
u8 cmd_data[11];
u8 color; #define IONIC_COMP_COLOR_MASK 0x80
};
/** * union ionic_drv_identity - driver identity information * @os_type: OS type (see enum ionic_os_type) * @os_dist: OS distribution, numeric format * @os_dist_str: OS distribution, string format * @kernel_ver: Kernel version, numeric format * @kernel_ver_str: Kernel version, string format * @driver_ver_str: Driver version, string format * @words: word access to struct contents
*/ union ionic_drv_identity { struct {
__le32 os_type;
__le32 os_dist; char os_dist_str[128];
__le32 kernel_ver; char kernel_ver_str[32]; char driver_ver_str[32];
};
__le32 words[478];
};
/** * union ionic_dev_identity - device identity information * @version: Version of device identify * @type: Identify type (0 for now) * @rsvd: reserved byte(s) * @nports: Number of ports provisioned * @rsvd2: reserved byte(s) * @nlifs: Number of LIFs provisioned * @nintrs: Number of interrupts provisioned * @ndbpgs_per_lif: Number of doorbell pages per LIF * @intr_coal_mult: Interrupt coalescing multiplication factor * Scale user-supplied interrupt coalescing * value in usecs to device units using: * device units = usecs * mult / div * @intr_coal_div: Interrupt coalescing division factor * Scale user-supplied interrupt coalescing * value in usecs to device units using: * device units = usecs * mult / div * @eq_count: Number of shared event queues * @hwstamp_mask: Bitmask for subtraction of hardware tick values. * @hwstamp_mult: Hardware tick to nanosecond multiplier. * @hwstamp_shift: Hardware tick to nanosecond divisor (power of two). * @capabilities: Device capabilities * @words: word access to struct contents
*/ union ionic_dev_identity { struct {
u8 version;
u8 type;
u8 rsvd[2];
u8 nports;
u8 rsvd2[3];
__le32 nlifs;
__le32 nintrs;
__le32 ndbpgs_per_lif;
__le32 intr_coal_mult;
__le32 intr_coal_div;
__le32 eq_count;
__le64 hwstamp_mask;
__le32 hwstamp_mult;
__le32 hwstamp_shift;
__le64 capabilities;
};
__le32 words[478];
};
/** * enum ionic_q_feature - Common Features for most queue types * * Common features use bits 0-15. Per-queue-type features use higher bits. * * @IONIC_QIDENT_F_CQ: Queue has completion ring * @IONIC_QIDENT_F_SG: Queue has scatter/gather ring * @IONIC_QIDENT_F_EQ: Queue can use event queue * @IONIC_QIDENT_F_CMB: Queue is in cmb bar * @IONIC_Q_F_2X_DESC: Double main descriptor size * @IONIC_Q_F_2X_CQ_DESC: Double cq descriptor size * @IONIC_Q_F_2X_SG_DESC: Double sg descriptor size * @IONIC_Q_F_4X_DESC: Quadruple main descriptor size * @IONIC_Q_F_4X_CQ_DESC: Quadruple cq descriptor size * @IONIC_Q_F_4X_SG_DESC: Quadruple sg descriptor size
*/ enum ionic_q_feature {
IONIC_QIDENT_F_CQ = BIT_ULL(0),
IONIC_QIDENT_F_SG = BIT_ULL(1),
IONIC_QIDENT_F_EQ = BIT_ULL(2),
IONIC_QIDENT_F_CMB = BIT_ULL(3),
IONIC_Q_F_2X_DESC = BIT_ULL(4),
IONIC_Q_F_2X_CQ_DESC = BIT_ULL(5),
IONIC_Q_F_2X_SG_DESC = BIT_ULL(6),
IONIC_Q_F_4X_DESC = BIT_ULL(7),
IONIC_Q_F_4X_CQ_DESC = BIT_ULL(8),
IONIC_Q_F_4X_SG_DESC = BIT_ULL(9),
};
/** * enum ionic_rxq_feature - RXQ-specific Features * * Per-queue-type features use bits 16 and higher. * * @IONIC_RXQ_F_HWSTAMP: Queue supports Hardware Timestamping
*/ enum ionic_rxq_feature {
IONIC_RXQ_F_HWSTAMP = BIT_ULL(16),
};
/** * enum ionic_txq_feature - TXQ-specific Features * * Per-queue-type features use bits 16 and higher. * * @IONIC_TXQ_F_HWSTAMP: Queue supports Hardware Timestamping
*/ enum ionic_txq_feature {
IONIC_TXQ_F_HWSTAMP = BIT(16),
};
/** * enum ionic_hwstamp_bits - Hardware timestamp decoding bits * @IONIC_HWSTAMP_INVALID: Invalid hardware timestamp value * @IONIC_HWSTAMP_CQ_NEGOFFSET: Timestamp field negative offset * from the base cq descriptor.
*/ enum ionic_hwstamp_bits {
IONIC_HWSTAMP_INVALID = ~0ull,
IONIC_HWSTAMP_CQ_NEGOFFSET = 8,
};
/** * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type * @qtype: Hardware Queue Type * @rsvd: reserved byte(s) * @qid_count: Number of Queue IDs of the logical type * @qid_base: Minimum Queue ID of the logical type
*/ struct ionic_lif_logical_qtype {
u8 qtype;
u8 rsvd[3];
__le32 qid_count;
__le32 qid_base;
};
/** * struct ionic_lif_init_comp - LIF init command completion * @status: Status of the command (enum ionic_status_code) * @rsvd: reserved byte(s) * @hw_index: Hardware index of the initialized LIF * @rsvd2: reserved byte(s)
*/ struct ionic_lif_init_comp {
u8 status;
u8 rsvd;
__le16 hw_index;
u8 rsvd2[12];
};
/** * struct ionic_q_identify_cmd - queue identify command * @opcode: opcode * @rsvd: reserved byte(s) * @lif_type: LIF type (enum ionic_lif_type) * @type: Logical queue type (enum ionic_logical_qtype) * @ver: Highest queue type version that the driver supports * @rsvd2: reserved byte(s)
*/ struct ionic_q_identify_cmd {
u8 opcode;
u8 rsvd;
__le16 lif_type;
u8 type;
u8 ver;
u8 rsvd2[58];
};
/** * struct ionic_q_identify_comp - queue identify command completion * @status: Status of the command (enum ionic_status_code) * @rsvd: reserved byte(s) * @comp_index: Index in the descriptor ring for which this is the completion * @ver: Queue type version that can be used with FW * @rsvd2: reserved byte(s)
*/ struct ionic_q_identify_comp {
u8 status;
u8 rsvd;
__le16 comp_index;
u8 ver;
u8 rsvd2[11];
};
/** * union ionic_q_identity - queue identity information * @version: Queue type version that can be used with FW * @supported: Bitfield of queue versions, first bit = ver 0 * @rsvd: reserved byte(s) * @features: Queue features (enum ionic_q_feature, etc) * @desc_sz: Descriptor size * @comp_sz: Completion descriptor size * @sg_desc_sz: Scatter/Gather descriptor size * @max_sg_elems: Maximum number of Scatter/Gather elements * @sg_desc_stride: Number of Scatter/Gather elements per descriptor * @words: word access to struct contents
*/ union ionic_q_identity { struct {
u8 version;
u8 supported;
u8 rsvd[6];
__le64 features;
__le16 desc_sz;
__le16 comp_sz;
__le16 sg_desc_sz;
__le16 max_sg_elems;
__le16 sg_desc_stride;
};
__le32 words[478];
};
/** * struct ionic_q_init_cmd - Queue init command * @opcode: opcode * @rsvd: reserved byte(s) * @type: Logical queue type * @ver: Queue type version * @rsvd1: reserved byte(s) * @lif_index: LIF index * @index: (LIF, qtype) relative admin queue index * @intr_index: Interrupt control register index, or Event queue index * @pid: Process ID * @flags: * IRQ: Interrupt requested on completion * ENA: Enable the queue. If ENA=0 the queue is initialized * but remains disabled, to be later enabled with the * Queue Enable command. If ENA=1, then queue is * initialized and then enabled. * SG: Enable Scatter-Gather on the queue. * in number of descs. The actual ring size is * (1 << ring_size). For example, to * select a ring size of 64 descriptors write * ring_size = 6. The minimum ring_size value is 2 * for a ring size of 4 descriptors. The maximum * ring_size value is 16 for a ring size of 64k * descriptors. Values of ring_size <2 and >16 are * reserved. * EQ: Enable the Event Queue * @cos: Class of service for this queue * @ring_size: Queue ring size, encoded as a log2(size) * @ring_base: Queue ring base address * @cq_ring_base: Completion queue ring base address * @sg_ring_base: Scatter/Gather ring base address * @rsvd2: reserved byte(s) * @features: Mask of queue features to enable, if not in the flags above.
*/ struct ionic_q_init_cmd {
u8 opcode;
u8 rsvd;
__le16 lif_index;
u8 type;
u8 ver;
u8 rsvd1[2];
__le32 index;
__le16 pid;
__le16 intr_index;
__le16 flags; #define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */ #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */ #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */ #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */ #define IONIC_QINIT_F_CMB 0x10 /* Enable cmb-based queue */ #define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */
u8 cos;
u8 ring_size;
__le64 ring_base;
__le64 cq_ring_base;
__le64 sg_ring_base;
u8 rsvd2[12];
__le64 features;
} __packed;
/** * struct ionic_q_init_comp - Queue init command completion * @status: Status of the command (enum ionic_status_code) * @rsvd: reserved byte(s) * @comp_index: Index in the descriptor ring for which this is the completion * @hw_index: Hardware Queue ID * @hw_type: Hardware Queue type * @rsvd2: reserved byte(s) * @color: Color
*/ struct ionic_q_init_comp {
u8 status;
u8 rsvd;
__le16 comp_index;
__le32 hw_index;
u8 hw_type;
u8 rsvd2[6];
u8 color;
};
/* the device's internal addressing uses up to 52 bits */ #define IONIC_ADDR_LEN 52 #define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
/** * struct ionic_txq_desc - Ethernet Tx queue descriptor format * @cmd: Tx operation, see IONIC_TXQ_DESC_OPCODE_*: * * IONIC_TXQ_DESC_OPCODE_CSUM_NONE: * Non-offload send. No segmentation, * fragmentation or checksum calc/insertion is * performed by device; packet is prepared * to send by software stack and requires * no further manipulation from device. * * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL: * Offload 16-bit L4 checksum * calculation/insertion. The device will * calculate the L4 checksum value and * insert the result in the packet's L4 * header checksum field. The L4 checksum * is calculated starting at @csum_start bytes * into the packet to the end of the packet. * The checksum insertion position is given * in @csum_offset, which is the offset from * @csum_start to the checksum field in the L4 * header. This feature is only applicable to * protocols such as TCP, UDP and ICMP where a * standard (i.e. the 'IP-style' checksum) * one's complement 16-bit checksum is used, * using an IP pseudo-header to seed the * calculation. Software will preload the L4 * checksum field with the IP pseudo-header * checksum. * * For tunnel encapsulation, @csum_start and * @csum_offset refer to the inner L4 * header. Supported tunnels encapsulations * are: IPIP, GRE, and UDP. If the @encap * is clear, no further processing by the * device is required; software will * calculate the outer header checksums. If * the @encap is set, the device will * offload the outer header checksums using * LCO (local checksum offload) (see * Documentation/networking/checksum-offloads.rst * for more info). * * IONIC_TXQ_DESC_OPCODE_CSUM_HW: * Offload 16-bit checksum computation to hardware. * If @csum_l3 is set then the packet's L3 checksum is * updated. Similarly, if @csum_l4 is set the L4 * checksum is updated. If @encap is set then encap header * checksums are also updated. * * IONIC_TXQ_DESC_OPCODE_TSO: * Device performs TCP segmentation offload * (TSO). @hdr_len is the number of bytes * to the end of TCP header (the offset to * the TCP payload). @mss is the desired * MSS, the TCP payload length for each * segment. The device will calculate/ * insert IP (IPv4 only) and TCP checksums * for each segment. In the first data * buffer containing the header template, * the driver will set IPv4 checksum to 0 * and preload TCP checksum with the IP * pseudo header calculated with IP length = 0. * * Supported tunnel encapsulations are IPIP, * layer-3 GRE, and UDP. @hdr_len includes * both outer and inner headers. The driver * will set IPv4 checksum to zero and * preload TCP checksum with IP pseudo * header on the inner header. * * TCP ECN offload is supported. The device * will set CWR flag in the first segment if * CWR is set in the template header, and * clear CWR in remaining segments. * flags: * vlan: * Insert an L2 VLAN header using @vlan_tci * encap: * Calculate encap header checksum * csum_l3: * Compute L3 header checksum * csum_l4: * Compute L4 header checksum * tso_sot: * TSO start * tso_eot: * TSO end * num_sg_elems: Number of scatter-gather elements in SG * descriptor * addr: First data buffer's DMA address * (Subsequent data buffers are on txq_sg_desc) * @len: First data buffer's length, in bytes * @vlan_tci: VLAN tag to insert in the packet (if requested * by @V-bit). Includes .1p and .1q tags * @hword0: half word padding * @hdr_len: Length of packet headers, including * encapsulating outer header, if applicable * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and * IONIC_TXQ_DESC_OPCODE_TSO. Should be set to zero for * all other modes. For * IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length * of headers up to inner-most L4 header. For * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to * inner-most L4 payload, so inclusive of * inner-most L4 header. * @hword1: half word padding * @mss: Desired MSS value for TSO; only applicable for * IONIC_TXQ_DESC_OPCODE_TSO * @csum_start: Offset from packet to first byte checked in L4 checksum * @csum_offset: Offset from csum_start to L4 checksum field * @hword2: half word padding
*/ struct ionic_txq_desc {
__le64 cmd; #define IONIC_TXQ_DESC_OPCODE_MASK 0xf #define IONIC_TXQ_DESC_OPCODE_SHIFT 4 #define IONIC_TXQ_DESC_FLAGS_MASK 0xf #define IONIC_TXQ_DESC_FLAGS_SHIFT 0 #define IONIC_TXQ_DESC_NSGE_MASK 0xf #define IONIC_TXQ_DESC_NSGE_SHIFT 8 #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) #define IONIC_TXQ_DESC_ADDR_SHIFT 12
/* common flags */ #define IONIC_TXQ_DESC_FLAG_VLAN 0x1 #define IONIC_TXQ_DESC_FLAG_ENCAP 0x2
/** * struct ionic_txq_comp - Ethernet transmit queue completion descriptor * @status: Status of the command (enum ionic_status_code) * @rsvd: reserved byte(s) * @comp_index: Index in the descriptor ring for which this is the completion * @rsvd2: reserved byte(s) * @color: Color bit
*/ struct ionic_txq_comp {
u8 status;
u8 rsvd;
__le16 comp_index;
u8 rsvd2[11];
u8 color;
};
/** * struct ionic_rxq_comp - Ethernet receive queue completion descriptor * @status: Status of the command (enum ionic_status_code) * @num_sg_elems: Number of SG elements used by this descriptor * @comp_index: Index in the descriptor ring for which this is the completion * @rss_hash: 32-bit RSS hash * @csum: 16-bit sum of the packet's L2 payload * If the packet's L2 payload is odd length, an extra * zero-value byte is included in the @csum calculation but * not included in @len. * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is * set. Includes .1p and .1q tags. * @len: Received packet length, in bytes. Excludes FCS. * @csum_calc L2 payload checksum is computed or not * @csum_flags: See IONIC_RXQ_COMP_CSUM_F_*: * * IONIC_RXQ_COMP_CSUM_F_TCP_OK: * The TCP checksum calculated by the device * matched the checksum in the receive packet's * TCP header. * * IONIC_RXQ_COMP_CSUM_F_TCP_BAD: * The TCP checksum calculated by the device did * not match the checksum in the receive packet's * TCP header. * * IONIC_RXQ_COMP_CSUM_F_UDP_OK: * The UDP checksum calculated by the device * matched the checksum in the receive packet's * UDP header * * IONIC_RXQ_COMP_CSUM_F_UDP_BAD: * The UDP checksum calculated by the device did * not match the checksum in the receive packet's * UDP header. * * IONIC_RXQ_COMP_CSUM_F_IP_OK: * The IPv4 checksum calculated by the device * matched the checksum in the receive packet's * first IPv4 header. If the receive packet * contains both a tunnel IPv4 header and a * transport IPv4 header, the device validates the * checksum for both IPv4 headers. * * IONIC_RXQ_COMP_CSUM_F_IP_BAD: * The IPv4 checksum calculated by the device did * not match the checksum in the receive packet's * first IPv4 header. If the receive packet * contains both a tunnel IPv4 header and a * transport IPv4 header, the device validates the * checksum for both IP headers. * * IONIC_RXQ_COMP_CSUM_F_VLAN: * The VLAN header was stripped and placed in @vlan_tci. * * IONIC_RXQ_COMP_CSUM_F_CALC: * The checksum was calculated by the device. * * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK
*/ struct ionic_rxq_comp {
u8 status;
u8 num_sg_elems;
__le16 comp_index;
__le32 rss_hash;
__le16 csum;
__le16 vlan_tci;
__le16 len;
u8 csum_flags; #define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01 #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02 #define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04 #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08 #define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10 #define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20 #define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40 #define IONIC_RXQ_COMP_CSUM_F_CALC 0x80
u8 pkt_type_color; #define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f
};
enum ionic_pkt_type {
IONIC_PKT_TYPE_NON_IP = 0x00,
IONIC_PKT_TYPE_IPV4 = 0x01,
IONIC_PKT_TYPE_IPV4_TCP = 0x03,
IONIC_PKT_TYPE_IPV4_UDP = 0x05,
IONIC_PKT_TYPE_IPV6 = 0x08,
IONIC_PKT_TYPE_IPV6_TCP = 0x18,
IONIC_PKT_TYPE_IPV6_UDP = 0x28, /* below types are only used if encap offloads are enabled on lif */
IONIC_PKT_TYPE_ENCAP_NON_IP = 0x40,
IONIC_PKT_TYPE_ENCAP_IPV4 = 0x41,
IONIC_PKT_TYPE_ENCAP_IPV4_TCP = 0x43,
IONIC_PKT_TYPE_ENCAP_IPV4_UDP = 0x45,
IONIC_PKT_TYPE_ENCAP_IPV6 = 0x48,
IONIC_PKT_TYPE_ENCAP_IPV6_TCP = 0x58,
IONIC_PKT_TYPE_ENCAP_IPV6_UDP = 0x68,
};
/** * enum ionic_port_type - Port types * @IONIC_PORT_TYPE_NONE: Port type not configured * @IONIC_PORT_TYPE_ETH: Port carries ethernet traffic (inband) * @IONIC_PORT_TYPE_MGMT: Port carries mgmt traffic (out-of-band)
*/ enum ionic_port_type {
IONIC_PORT_TYPE_NONE = 0,
IONIC_PORT_TYPE_ETH = 1,
IONIC_PORT_TYPE_MGMT = 2,
};
/** * enum ionic_port_admin_state - Port config state * @IONIC_PORT_ADMIN_STATE_NONE: Port admin state not configured * @IONIC_PORT_ADMIN_STATE_DOWN: Port admin disabled * @IONIC_PORT_ADMIN_STATE_UP: Port admin enabled
*/ enum ionic_port_admin_state {
IONIC_PORT_ADMIN_STATE_NONE = 0,
IONIC_PORT_ADMIN_STATE_DOWN = 1,
IONIC_PORT_ADMIN_STATE_UP = 2,
};
/** * enum ionic_port_oper_status - Port operational status * @IONIC_PORT_OPER_STATUS_NONE: Port disabled * @IONIC_PORT_OPER_STATUS_UP: Port link status up * @IONIC_PORT_OPER_STATUS_DOWN: Port link status down
*/ enum ionic_port_oper_status {
IONIC_PORT_OPER_STATUS_NONE = 0,
IONIC_PORT_OPER_STATUS_UP = 1,
IONIC_PORT_OPER_STATUS_DOWN = 2,
};
/** * struct ionic_xcvr_status - Transceiver Status information * @state: Transceiver status (enum ionic_xcvr_state) * @phy: Physical connection type (enum ionic_phy_type) * @pid: Transceiver link mode (enum ionic_xcvr_pid) * @sprom: Transceiver sprom contents
*/ struct ionic_xcvr_status {
u8 state;
u8 phy;
__le16 pid;
u8 sprom[256];
};
/** * union ionic_port_config - Port configuration * @speed: port speed (in Mbps) * @mtu: mtu * @state: port admin state (enum ionic_port_admin_state) * @an_enable: autoneg enable * @fec_type: fec type (enum ionic_port_fec_type) * @pause_type: pause type (enum ionic_port_pause_type) * @loopback_mode: loopback mode (enum ionic_port_loopback_mode) * @words: word access to struct contents
*/ union ionic_port_config { struct { #define IONIC_SPEED_400G 400000/* 400G in Mbps */ #define IONIC_SPEED_200G 200000/* 200G in Mbps */ #define IONIC_SPEED_100G 100000/* 100G in Mbps */ #define IONIC_SPEED_50G 50000/* 50G in Mbps */ #define IONIC_SPEED_40G 40000/* 40G in Mbps */ #define IONIC_SPEED_25G 25000/* 25G in Mbps */ #define IONIC_SPEED_10G 10000/* 10G in Mbps */ #define IONIC_SPEED_1G 1000/* 1G in Mbps */
__le32 speed;
__le32 mtu;
u8 state;
u8 an_enable;
u8 fec_type; #define IONIC_PAUSE_TYPE_MASK 0x0f #define IONIC_PAUSE_FLAGS_MASK 0xf0 #define IONIC_PAUSE_F_TX 0x10 #define IONIC_PAUSE_F_RX 0x20
u8 pause_type;
u8 loopback_mode;
};
__le32 words[64];
};
/** * struct ionic_port_status - Port Status information * @status: link status (enum ionic_port_oper_status) * @id: port id * @speed: link speed (in Mbps) * @link_down_count: number of times link went from up to down * @fec_type: fec type (enum ionic_port_fec_type) * @rsvd: reserved byte(s) * @xcvr: transceiver status
*/ struct ionic_port_status {
__le32 id;
__le32 speed;
u8 status;
__le16 link_down_count;
u8 fec_type;
u8 rsvd[48]; struct ionic_xcvr_status xcvr;
} __packed;
/** * struct ionic_port_identify_cmd - Port identify command * @opcode: opcode * @index: port index * @ver: Highest version of identify supported by driver * @rsvd: reserved byte(s)
*/ struct ionic_port_identify_cmd {
u8 opcode;
u8 index;
u8 ver;
u8 rsvd[61];
};
/** * struct ionic_port_identify_comp - Port identify command completion * @status: Status of the command (enum ionic_status_code) * @ver: Version of identify returned by device * @rsvd: reserved byte(s)
*/ struct ionic_port_identify_comp {
u8 status;
u8 ver;
u8 rsvd[14];
};
/** * struct ionic_port_init_cmd - Port initialization command * @opcode: opcode * @index: port index * @rsvd: reserved byte(s) * @info_pa: destination address for port info (struct ionic_port_info) * @rsvd2: reserved byte(s)
*/ struct ionic_port_init_cmd {
u8 opcode;
u8 index;
u8 rsvd[6];
__le64 info_pa;
u8 rsvd2[48];
};
/** * struct ionic_port_init_comp - Port initialization command completion * @status: Status of the command (enum ionic_status_code) * @rsvd: reserved byte(s)
*/ struct ionic_port_init_comp {
u8 status;
u8 rsvd[15];
};
/** * struct ionic_port_reset_cmd - Port reset command * @opcode: opcode * @index: port index * @rsvd: reserved byte(s)
*/ struct ionic_port_reset_cmd {
u8 opcode;
u8 index;
u8 rsvd[62];
};
/** * struct ionic_port_reset_comp - Port reset command completion * @status: Status of the command (enum ionic_status_code) * @rsvd: reserved byte(s)
*/ struct ionic_port_reset_comp {
u8 status;
u8 rsvd[15];
};
/** * enum ionic_stats_ctl_cmd - List of commands for stats control * @IONIC_STATS_CTL_RESET: Reset statistics
*/ enum ionic_stats_ctl_cmd {
IONIC_STATS_CTL_RESET = 0,
};
/** * enum ionic_port_attr - List of device attributes * @IONIC_PORT_ATTR_STATE: Port state attribute * @IONIC_PORT_ATTR_SPEED: Port speed attribute * @IONIC_PORT_ATTR_MTU: Port MTU attribute * @IONIC_PORT_ATTR_AUTONEG: Port autonegotiation attribute * @IONIC_PORT_ATTR_FEC: Port FEC attribute * @IONIC_PORT_ATTR_PAUSE: Port pause attribute * @IONIC_PORT_ATTR_LOOPBACK: Port loopback attribute * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute
*/ enum ionic_port_attr {
IONIC_PORT_ATTR_STATE = 0,
IONIC_PORT_ATTR_SPEED = 1,
IONIC_PORT_ATTR_MTU = 2,
IONIC_PORT_ATTR_AUTONEG = 3,
IONIC_PORT_ATTR_FEC = 4,
IONIC_PORT_ATTR_PAUSE = 5,
IONIC_PORT_ATTR_LOOPBACK = 6,
IONIC_PORT_ATTR_STATS_CTRL = 7,
};
/** * struct ionic_port_setattr_cmd - Set port attributes on the NIC * @opcode: Opcode * @index: Port index * @attr: Attribute type (enum ionic_port_attr) * @rsvd: reserved byte(s) * @state: Port state * @speed: Port speed * @mtu: Port MTU * @an_enable: Port autonegotiation setting * @fec_type: Port FEC type setting * @pause_type: Port pause type setting * @loopback_mode: Port loopback mode * @stats_ctl: Port stats setting * @rsvd2: reserved byte(s)
*/ struct ionic_port_setattr_cmd {
u8 opcode;
u8 index;
u8 attr;
u8 rsvd; union {
u8 state;
__le32 speed;
__le32 mtu;
u8 an_enable;
u8 fec_type;
u8 pause_type;
u8 loopback_mode;
u8 stats_ctl;
u8 rsvd2[60];
};
};
/** * struct ionic_port_setattr_comp - Port set attr command completion * @status: Status of the command (enum ionic_status_code) * @rsvd: reserved byte(s) * @color: Color bit
*/ struct ionic_port_setattr_comp {
u8 status;
u8 rsvd[14];
u8 color;
};
/** * struct ionic_port_getattr_cmd - Get port attributes from the NIC * @opcode: Opcode * @index: port index * @attr: Attribute type (enum ionic_port_attr) * @rsvd: reserved byte(s)
*/ struct ionic_port_getattr_cmd {
u8 opcode;
u8 index;
u8 attr;
u8 rsvd[61];
};
/** * struct ionic_port_getattr_comp - Port get attr command completion * @status: Status of the command (enum ionic_status_code) * @rsvd: reserved byte(s) * @state: Port state * @speed: Port speed * @mtu: Port MTU * @an_enable: Port autonegotiation setting * @fec_type: Port FEC type setting * @pause_type: Port pause type setting * @loopback_mode: Port loopback mode * @rsvd2: reserved byte(s) * @color: Color bit
*/ struct ionic_port_getattr_comp {
u8 status;
u8 rsvd[3]; union {
u8 state;
__le32 speed;
__le32 mtu;
u8 an_enable;
u8 fec_type;
u8 pause_type;
u8 loopback_mode;
u8 rsvd2[11];
} __packed;
u8 color;
};
/** * struct ionic_lif_status - LIF status register * @eid: most recent NotifyQ event id * @port_num: port the LIF is connected to * @rsvd: reserved byte(s) * @link_status: port status (enum ionic_port_oper_status) * @link_speed: speed of link in Mbps * @link_down_count: number of times link went from up to down * @rsvd2: reserved byte(s)
*/ struct ionic_lif_status {
__le64 eid;
u8 port_num;
u8 rsvd;
__le16 link_status;
__le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */
__le16 link_down_count;
u8 rsvd2[46];
};
/** * enum ionic_lif_attr - List of LIF attributes * @IONIC_LIF_ATTR_STATE: LIF state attribute * @IONIC_LIF_ATTR_NAME: LIF name attribute * @IONIC_LIF_ATTR_MTU: LIF MTU attribute * @IONIC_LIF_ATTR_MAC: LIF MAC attribute * @IONIC_LIF_ATTR_FEATURES: LIF features attribute * @IONIC_LIF_ATTR_RSS: LIF RSS attribute * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute * @IONIC_LIF_ATTR_TXSTAMP: LIF TX timestamping mode * @IONIC_LIF_ATTR_MAX: maximum attribute value
*/ enum ionic_lif_attr {
IONIC_LIF_ATTR_STATE = 0,
IONIC_LIF_ATTR_NAME = 1,
IONIC_LIF_ATTR_MTU = 2,
IONIC_LIF_ATTR_MAC = 3,
IONIC_LIF_ATTR_FEATURES = 4,
IONIC_LIF_ATTR_RSS = 5,
IONIC_LIF_ATTR_STATS_CTRL = 6,
IONIC_LIF_ATTR_TXSTAMP = 7,
IONIC_LIF_ATTR_MAX = 255,
};
/** * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC * @opcode: Opcode * @attr: Attribute type (enum ionic_lif_attr) * @index: LIF index * @state: LIF state (enum ionic_lif_state) * @name: The netdev name string, 0 terminated * @mtu: Mtu * @mac: Station mac * @features: Features (enum ionic_eth_hw_features) * @rss: RSS properties * @rss.types: The hash types to enable (see rss_hash_types) * @rss.key: The hash secret key * @rss.rsvd: reserved byte(s) * @rss.addr: Address for the indirection table shared memory * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd) * @txstamp_mode: TX Timestamping Mode (enum ionic_txstamp_mode) * @rsvd: reserved byte(s)
*/ struct ionic_lif_setattr_cmd {
u8 opcode;
u8 attr;
__le16 index; union {
u8 state; char name[IONIC_IFNAMSIZ];
__le32 mtu;
u8 mac[6];
__le64 features; struct {
__le16 types;
u8 key[IONIC_RSS_HASH_KEY_SIZE];
u8 rsvd[6];
__le64 addr;
} rss;
u8 stats_ctl;
__le16 txstamp_mode;
u8 rsvd[60];
} __packed;
};
/** * struct ionic_lif_setattr_comp - LIF set attr command completion * @status: Status of the command (enum ionic_status_code) * @rsvd: reserved byte(s) * @comp_index: Index in the descriptor ring for which this is the completion * @features: features (enum ionic_eth_hw_features) * @rsvd2: reserved byte(s) * @color: Color bit
*/ struct ionic_lif_setattr_comp {
u8 status;
u8 rsvd;
__le16 comp_index; union {
__le64 features;
u8 rsvd2[11];
} __packed;
u8 color;
};
/** * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC * @opcode: Opcode * @attr: Attribute type (enum ionic_lif_attr) * @index: LIF index * @rsvd: reserved byte(s)
*/ struct ionic_lif_getattr_cmd {
u8 opcode;
u8 attr;
__le16 index;
u8 rsvd[60];
};
/** * struct ionic_lif_getattr_comp - LIF get attr command completion * @status: Status of the command (enum ionic_status_code) * @rsvd: reserved byte(s) * @comp_index: Index in the descriptor ring for which this is the completion * @state: LIF state (enum ionic_lif_state) * @mtu: Mtu * @mac: Station mac * @features: Features (enum ionic_eth_hw_features) * @txstamp_mode: TX Timestamping Mode (enum ionic_txstamp_mode) * @rsvd2: reserved byte(s) * @color: Color bit
*/ struct ionic_lif_getattr_comp {
u8 status;
u8 rsvd;
__le16 comp_index; union {
u8 state;
__le32 mtu;
u8 mac[6];
__le64 features;
__le16 txstamp_mode;
u8 rsvd2[11];
} __packed;
u8 color;
};
/** * struct ionic_lif_setphc_cmd - Set LIF PTP Hardware Clock * @opcode: Opcode * @rsvd1: reserved byte(s) * @lif_index: LIF index * @rsvd2: reserved byte(s) * @tick: Hardware stamp tick of an instant in time. * @nsec: Nanosecond stamp of the same instant. * @frac: Fractional nanoseconds at the same instant. * @mult: Cycle to nanosecond multiplier. * @shift: Cycle to nanosecond divisor (power of two). * @rsvd3: reserved byte(s)
*/ struct ionic_lif_setphc_cmd {
u8 opcode;
u8 rsvd1;
__le16 lif_index;
u8 rsvd2[4];
__le64 tick;
__le64 nsec;
__le64 frac;
__le32 mult;
__le32 shift;
u8 rsvd3[24];
};
/** * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command * @opcode: opcode * @qtype: Queue type * @lif_index: LIF index * @qid: Queue ID * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx) * @vlan: VLAN filter * @vlan.vlan: VLAN ID * @mac: MAC filter * @mac.addr: MAC address (network-byte order) * @mac_vlan: MACVLAN filter * @mac_vlan.vlan: VLAN ID * @mac_vlan.addr: MAC address (network-byte order) * @pkt_class: Packet classification filter * @rsvd: reserved byte(s)
*/ struct ionic_rx_filter_add_cmd {
u8 opcode;
u8 qtype;
__le16 lif_index;
__le32 qid;
__le16 match; union { struct {
__le16 vlan;
} vlan; struct {
u8 addr[6];
} mac; struct {
__le16 vlan;
u8 addr[6];
} mac_vlan;
__le64 pkt_class;
u8 rsvd[54];
} __packed;
};
/** * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion * @status: Status of the command (enum ionic_status_code) * @rsvd: reserved byte(s) * @comp_index: Index in the descriptor ring for which this is the completion * @filter_id: Filter ID * @rsvd2: reserved byte(s) * @color: Color bit
*/ struct ionic_rx_filter_add_comp {
u8 status;
u8 rsvd;
__le16 comp_index;
__le32 filter_id;
u8 rsvd2[7];
u8 color;
};
/** * enum ionic_vf_link_status - Virtual Function link status * @IONIC_VF_LINK_STATUS_AUTO: Use link state of the uplink * @IONIC_VF_LINK_STATUS_UP: Link always up * @IONIC_VF_LINK_STATUS_DOWN: Link always down
*/ enum ionic_vf_link_status {
IONIC_VF_LINK_STATUS_AUTO = 0,
IONIC_VF_LINK_STATUS_UP = 1,
IONIC_VF_LINK_STATUS_DOWN = 2,
};
/** * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC * @opcode: Opcode * @attr: Attribute type (enum ionic_vf_attr) * @vf_index: VF index * @macaddr: mac address * @vlanid: vlan ID * @maxrate: max Tx rate in Mbps * @spoofchk: enable address spoof checking * @trust: enable VF trust * @linkstate: set link up or down * @stats_pa: set DMA address for VF stats * @pad: reserved byte(s)
*/ struct ionic_vf_setattr_cmd {
u8 opcode;
u8 attr;
__le16 vf_index; union {
u8 macaddr[6];
__le16 vlanid;
__le32 maxrate;
u8 spoofchk;
u8 trust;
u8 linkstate;
__le64 stats_pa;
u8 pad[60];
} __packed;
};
/** * struct ionic_vf_ctrl_cmd - VF control command * @opcode: Opcode for the command * @ctrl_opcode: VF control operation type * @vf_index: VF Index. It is unused if op START_ALL is used.
*/ struct ionic_vf_ctrl_cmd {
u8 opcode;
u8 ctrl_opcode;
__le16 vf_index; /* private: */
u8 rsvd1[60];
};
/** * struct ionic_vf_ctrl_comp - VF_CTRL command completion. * @status: Status of the command (enum ionic_status_code)
*/ struct ionic_vf_ctrl_comp {
u8 status; /* private: */
u8 rsvd[15];
};
/** * union ionic_qos_config - QoS configuration structure * @flags: Configuration flags * IONIC_QOS_CONFIG_F_ENABLE enable * IONIC_QOS_CONFIG_F_NO_DROP drop/nodrop * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite * IONIC_QOS_CONFIG_F_NON_DISRUPTIVE Non-disruptive TC update * @sched_type: QoS class scheduling type (enum ionic_qos_sched_type) * @class_type: QoS class type (enum ionic_qos_class_type) * @pause_type: QoS pause type (enum ionic_qos_pause_type) * @name: QoS class name * @mtu: MTU of the class * @pfc_cos: Priority-Flow Control class of service * @dwrr_weight: QoS class scheduling weight * @strict_rlmt: Rate limit for strict priority scheduling * @rw_dot1q_pcp: Rewrite dot1q pcp to value (valid iff F_RW_DOT1Q_PCP) * @rw_ip_dscp: Rewrite ip dscp to value (valid iff F_RW_IP_DSCP) * @dot1q_pcp: Dot1q pcp value * @ndscp: Number of valid dscp values in the ip_dscp field * @ip_dscp: IP dscp values * @words: word access to struct contents
*/ union ionic_qos_config { struct { #define IONIC_QOS_CONFIG_F_ENABLE BIT(0) #define IONIC_QOS_CONFIG_F_NO_DROP BIT(1) /* Used to rewrite PCP or DSCP value. */ #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2) #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3) /* Non-disruptive TC update */ #define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE BIT(4)
u8 flags;
u8 sched_type;
u8 class_type;
u8 pause_type; char name[IONIC_QOS_CLASS_NAME_SZ];
__le32 mtu; /* flow control */
u8 pfc_cos; /* scheduler */ union {
u8 dwrr_weight;
__le64 strict_rlmt;
}; /* marking */ /* Used to rewrite PCP or DSCP value. */ union {
u8 rw_dot1q_pcp;
u8 rw_ip_dscp;
}; /* classification */ union {
u8 dot1q_pcp; struct {
u8 ndscp;
u8 ip_dscp[IONIC_QOS_DSCP_MAX];
};
};
};
__le32 words[64];
};
/** * union ionic_qos_identity - QoS identity structure * @version: Version of the identify structure * @type: QoS system type * @rsvd: reserved byte(s) * @config: Current configuration of classes * @words: word access to struct contents
*/ union ionic_qos_identity { struct {
u8 version;
u8 type;
u8 rsvd[62]; union ionic_qos_config config[IONIC_QOS_CLASS_MAX];
};
__le32 words[478];
};
/** * struct ionic_fw_control_comp - Firmware control copletion * @status: Status of the command (enum ionic_status_code) * @rsvd: reserved byte(s) * @comp_index: Index in the descriptor ring for which this is the completion * @slot: Slot where the firmware was installed * @rsvd1: reserved byte(s) * @color: Color bit
*/ struct ionic_fw_control_comp {
u8 status;
u8 rsvd;
__le16 comp_index;
u8 slot;
u8 rsvd1[10];
u8 color;
};
/** * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd * @opcode: opcode * @rsvd: reserved byte(s) * @lif_index: LIF index * @rsvd2: reserved byte(s) * * There is no RDMA specific dev command completion struct. Completion uses * the common struct ionic_admin_comp. Only the status is indicated. * Nonzero status means the LIF does not support RDMA.
**/ struct ionic_rdma_reset_cmd {
u8 opcode;
u8 rsvd;
__le16 lif_index;
u8 rsvd2[60];
};
/** * struct ionic_rdma_queue_cmd - Create RDMA Queue command * @opcode: opcode, 52, 53 * @rsvd: reserved byte(s) * @lif_index: LIF index * @qid_ver: (qid | (RDMA version << 24)) * @cid: intr, eq_id, or cq_id * @dbid: doorbell page id * @depth_log2: log base two of queue depth * @stride_log2: log base two of queue stride * @dma_addr: address of the queue memory * @rsvd2: reserved byte(s) * * The same command struct is used to create an RDMA event queue, completion * queue, or RDMA admin queue. The cid is an interrupt number for an event * queue, an event queue id for a completion queue, or a completion queue id * for an RDMA admin queue. * * The queue created via a dev command must be contiguous in dma space. * * The dev commands are intended only to be used during driver initialization, * to create queues supporting the RDMA admin queue. Other queues, and other * types of RDMA resources like memory regions, will be created and registered * via the RDMA admin queue, and will support a more complete interface * providing scatter gather lists for larger, scattered queue buffers and * memory registration. * * There is no RDMA specific dev command completion struct. Completion uses * the common struct ionic_admin_comp. Only the status is indicated.
**/ struct ionic_rdma_queue_cmd {
u8 opcode;
u8 rsvd;
__le16 lif_index;
__le32 qid_ver;
__le32 cid;
__le16 dbid;
u8 depth_log2;
u8 stride_log2;
__le64 dma_addr;
u8 rsvd2[40];
};
/** * struct ionic_notifyq_event - Generic event reporting structure * @eid: event number * @ecode: event code * @data: unspecified data about the event * * This is the generic event report struct from which the other * actual events will be formed.
*/ struct ionic_notifyq_event {
__le64 eid;
__le16 ecode;
u8 data[54];
};
/** * struct ionic_link_change_event - Link change event notification * @eid: event number * @ecode: event code = IONIC_EVENT_LINK_CHANGE * @link_status: link up/down, with error bits (enum ionic_port_status) * @link_speed: speed of the network link * @rsvd: reserved byte(s) * * Sent when the network link state changes between UP and DOWN
*/ struct ionic_link_change_event {
__le64 eid;
__le16 ecode;
__le16 link_status;
__le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */
u8 rsvd[48];
};
/** * struct ionic_reset_event - Reset event notification * @eid: event number * @ecode: event code = IONIC_EVENT_RESET * @reset_code: reset type * @state: 0=pending, 1=complete, 2=error * @rsvd: reserved byte(s) * * Sent when the NIC or some subsystem is going to be or * has been reset.
*/ struct ionic_reset_event {
__le64 eid;
__le16 ecode;
u8 reset_code;
u8 state;
u8 rsvd[52];
};
/** * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health * @eid: event number * @ecode: event code = IONIC_EVENT_HEARTBEAT * @rsvd: reserved byte(s)
*/ struct ionic_heartbeat_event {
__le64 eid;
__le16 ecode;
u8 rsvd[54];
};
/** * struct ionic_log_event - Sent to notify the driver of an internal error * @eid: event number * @ecode: event code = IONIC_EVENT_LOG * @data: log data
*/ struct ionic_log_event {
__le64 eid;
__le16 ecode;
u8 data[54];
};
/** * struct ionic_hwstamp_regs - Hardware current timestamp registers * @tick_low: Low 32 bits of hardware timestamp * @tick_high: High 32 bits of hardware timestamp
*/ struct ionic_hwstamp_regs {
u32 tick_low;
u32 tick_high;
};
/** * union ionic_dev_info_regs - Device info register format (read-only) * @signature: Signature value of 0x44455649 ('DEVI') * @version: Current version of info * @asic_type: Asic type * @asic_rev: Asic revision * @fw_status: Firmware status * bit 0 - 1 = fw running * bit 4-7 - 4 bit generation number, changes on fw restart * @fw_heartbeat: Firmware heartbeat counter * @serial_num: Serial number * @rsvd_pad1024: reserved byte(s) * @fw_version: Firmware version * @hwstamp: Hardware current timestamp registers * @words: word access to struct contents
*/ union ionic_dev_info_regs { #define IONIC_DEVINFO_FWVERS_BUFLEN 32 #define IONIC_DEVINFO_SERIAL_BUFLEN 32 struct {
u32 signature;
u8 version;
u8 asic_type;
u8 asic_rev; #define IONIC_FW_STS_F_RUNNING 0x01 #define IONIC_FW_STS_F_GENERATION 0xF0
u8 fw_status;
u32 fw_heartbeat; char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN]; char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN];
u8 rsvd_pad1024[948]; struct ionic_hwstamp_regs hwstamp;
};
u32 words[512];
};
/** * union ionic_dev_cmd_regs - Device command register format (read-write) * @doorbell: Device Cmd Doorbell, write-only * Write a 1 to signal device to process cmd, * poll done for completion. * @done: Done indicator, bit 0 == 1 when command is complete * @cmd: Opcode-specific command bytes * @comp: Opcode-specific response bytes * @rsvd: reserved byte(s) * @data: Opcode-specific side-data * @words: word access to struct contents
*/ union ionic_dev_cmd_regs { struct {
u32 doorbell;
u32 done; union ionic_dev_cmd cmd; union ionic_dev_cmd_comp comp;
u8 rsvd[48];
u32 data[478];
} __packed;
u32 words[512];
};
/** * union ionic_dev_regs - Device register format for bar 0 page 0 * @info: Device info registers * @devcmd: Device command registers * @words: word access to struct contents
*/ union ionic_dev_regs { struct { union ionic_dev_info_regs info; union ionic_dev_cmd_regs devcmd;
} __packed;
__le32 words[1024];
};
/* Deprecate */ struct ionic_identity { union ionic_drv_identity drv; union ionic_dev_identity dev; union ionic_lif_identity lif; union ionic_port_identity port; union ionic_qos_identity qos; union ionic_q_identity txq;
};
#endif/* _IONIC_IF_H_ */
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