// SPDX-License-Identifier: GPL-2.0-only /* * r8169.c: RealTek 8169/8168/8101 ethernet driver. * * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> * Copyright (c) a lot of people too. Please respect their work. * * See MAINTAINERS file for support contact information. #include <linux/module.h>#include <linux/pci.h>#include <linux/netdevice.h>#include <linux/etherdevice.h>#include <linux/clk.h>#include <linux/delay.h>#include <linux/ethtool.h>#include <linux/phy.h>#include <linux/if_vlan.h>#include <linux/in.h>#include <linux/io.h>#include <linux/ip.h>#include <linux/tcp.h>#include <linux/interrupt.h>#include <linux/dma-mapping.h>#include <linux/pm_runtime.h>#include <linux/bitfield.h>#include <linux/prefetch.h>#include <linux/ipv6.h>#include <linux/unaligned.h>#include <net/ip6_checksum.h>#include <net/netdev_queues.h>#include "r8169.h" #include "r8169_firmware.h" #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" #define FIRMWARE_8125D_1 "rtl_nic/rtl8125d-1.fw" #define FIRMWARE_8125D_2 "rtl_nic/rtl8125d-2.fw" #define FIRMWARE_8125BP_2 "rtl_nic/rtl8125bp-2.fw" #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw" #define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw" #define FIRMWARE_8127A_1 "rtl_nic/rtl8127a-1.fw" #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ #define R8169_REGS_SIZE 256#define R8169_RX_BUF_SIZE (SZ_16K - 1)#define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof (struct TxDesc))#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof (struct RxDesc))#define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1)#define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS)#define OCP_STD_PHY_BASE 0xa400#define RTL_CFG_NO_GBIT 1/* write/read MMIO register */ #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))#define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)#define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)#define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)#define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)#define JUMBO_16K (SZ_16K - VLAN_ETH_HLEN - ETH_FCS_LEN)static const struct rtl_chip_info {enum mac_version mac_version;const char *name;const char *fw_name;/* 8127A family. */ "RTL8127A" , FIRMWARE_8127A_1 },/* 8126A family. */ "RTL8126A" , FIRMWARE_8126A_3 },"RTL8126A" , FIRMWARE_8126A_2 },/* 8125BP family. */ "RTL8125BP" , FIRMWARE_8125BP_2 },/* 8125D family. */ "RTL8125D" , FIRMWARE_8125D_2 },"RTL8125D" , FIRMWARE_8125D_1 },/* 8125B family. */ "RTL8125B" , FIRMWARE_8125B_2 },/* 8125A family. */ "RTL8125A" , FIRMWARE_8125A_3 },/* RTL8117 */ "RTL8168fp/RTL8117" },"RTL8168fp/RTL8117" ,/* 8168EP family. */ "RTL8168ep/8111ep" },/* 8168H family. */ "RTL8168h/8111h" ,/* Realtek calls it RTL8168M, but it's handled like RTL8168H */ "RTL8168M" , FIRMWARE_8168H_2 },/* 8168G family. */ "RTL8411b" , FIRMWARE_8411_2 },"RTL8168gu/8111gu" ,"RTL8168g/8111g" ,/* 8168F family. */ "RTL8411" , FIRMWARE_8411_1 },"RTL8168f/8111f" ,"RTL8168f/8111f" ,/* 8168E family. */ "RTL8168evl/8111evl" ,"RTL8168e/8111e" ,"RTL8168e/8111e" ,/* 8168D family. */ "RTL8168d/8111d" ,"RTL8168d/8111d" ,/* 8168DP family. */ "RTL8168dp/8111dp" },"RTL8168dp/8111dp" },/* 8168C family. */ "RTL8168cp/8111cp" },"RTL8168cp/8111cp" },"RTL8168cp/8111cp" },"RTL8168c/8111c" },"RTL8168c/8111c" },"RTL8168c/8111c" },"RTL8168c/8111c" },/* 8168B family. */ "RTL8168b/8111b" },/* This one is very old and rare, support has been removed. * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11, "RTL8168b/8111b" }, /* 8101 family. */ "RTL8106e" , FIRMWARE_8106E_1 },"RTL8402" , FIRMWARE_8402_1 },"RTL8105e" , FIRMWARE_8105E_1 },"RTL8105e" , FIRMWARE_8105E_1 },"RTL8102e" },"RTL8102e" },"RTL8102e" },"RTL8102e" },"RTL8401" },"RTL8102e/RTL8103e" },"RTL8102e/RTL8103e" },"RTL8101e/RTL8100e" },/* 8110 family. */ "RTL8169sc/8110sc" },"RTL8169sc/8110sc" },"RTL8169sb/8110sb" },"RTL8110s" },"RTL8169s" },/* Catch-all */ static const struct pci_device_id rtl8169_pci_tbl[] = {enum rtl_registers {/* Ethernet hardware address. */ /* Multicast filter. */ #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ #define RX128_INT_EN (1 << 15) /* 8111c and later */ #define RX_MULTI_EN (1 << 14) /* 8111c only */ #define RXCFG_FIFO_SHIFT 13/* No threshold before first PCI xfer */ #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)#define RX_EARLY_OFF (1 << 11)#define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ #define RXCFG_DMA_SHIFT 8/* Unlimited maximum PCI burst. */ #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)#define PME_SIGNAL (1 << 5) /* 8168c and later */ #define RTL_COALESCE_TX_USECS GENMASK(15, 12)#define RTL_COALESCE_TX_FRAMES GENMASK(11, 8)#define RTL_COALESCE_RX_USECS GENMASK(7, 4)#define RTL_COALESCE_RX_FRAMES GENMASK(3, 0)#define RTL_COALESCE_T_MAX 0x0fU#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4)/* 8169. Unit of 32 bytes. */ #define NoEarlyTx 0x3f /* Max value : no early transmit. */ /* 8101/8168. Unit of 128 bytes. */ #define TxPacketMax (8064 >> 7)#define EarlySize 0x27enum rtl8168_8101_registers {#define CSIAR_FLAG 0x80000000#define CSIAR_WRITE_CMD 0x80000000#define CSIAR_BYTE_ENABLE 0x0000f000#define CSIAR_ADDR_MASK 0x00000fff#define D3COLD_NO_PLL_DOWN BIT(7)#define D3HOT_NO_PLL_DOWN BIT(6)#define D3_NO_PLL_DOWN (BIT(7) | BIT(6))#define EPHYAR_FLAG 0x80000000#define EPHYAR_WRITE_CMD 0x80000000#define EPHYAR_REG_MASK 0x1f#define EPHYAR_REG_SHIFT 16#define EPHYAR_DATA_MASK 0xffff#define PFM_EN (1 << 6)#define TX_10M_PS_EN (1 << 7)#define FIX_NAK_1 (1 << 4)#define FIX_NAK_2 (1 << 3)#define NOW_IS_OOB (1 << 7)#define TX_EMPTY (1 << 5)#define RX_EMPTY (1 << 4)#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)#define EN_NDP (1 << 3)#define EN_OOB_RESET (1 << 2)#define LINK_LIST_RDY (1 << 1)#define EFUSEAR_FLAG 0x80000000#define EFUSEAR_WRITE_CMD 0x80000000#define EFUSEAR_READ_CMD 0x00000000#define EFUSEAR_REG_MASK 0x03ff#define EFUSEAR_REG_SHIFT 8#define EFUSEAR_DATA_MASK 0xff#define PFM_D3COLD_EN (1 << 6)enum rtl8168_registers {#define ERIAR_FLAG 0x80000000#define ERIAR_WRITE_CMD 0x80000000#define ERIAR_READ_CMD 0x00000000#define ERIAR_ADDR_BYTE_ALIGN 4#define ERIAR_TYPE_SHIFT 16#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)#define ERIAR_MASK_SHIFT 12#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)/* OCP GPHY access */ #define OCPDR_WRITE_CMD 0x80000000#define OCPDR_READ_CMD 0x00000000#define OCPDR_REG_MASK 0x7f#define OCPDR_GPHY_REG_SHIFT 16#define OCPDR_DATA_MASK 0xffff#define OCPAR_FLAG 0x80000000#define OCPAR_GPHY_WRITE_CMD 0x8000f060#define OCPAR_GPHY_READ_CMD 0x0000f060/* 8168c only. Undocumented on 8168dp */ /* 8168e only. */ #define TXPLA_RST (1 << 29)#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ #define PWM_EN (1 << 22)#define RXDV_GATED_EN (1 << 19)#define EARLY_TALLY_EN (1 << 16)enum rtl8125_registers {#define INT_CFG0_ENABLE_8125 BIT(0)#define INT_CFG0_CLKREQEN BIT(3)#define LEDSEL_MASK_8125 0x23f#define RX_VLAN_INNER_8125 BIT(22)#define RX_VLAN_OUTER_8125 BIT(23)#define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)#define RX_FETCH_DFLT_8125 (8 << 27)enum rtl_register_content {/* InterruptStatusBits */ /* RxStatusDesc */ /* ChipCmdBits */ /* TXPoll register p.5 */ /* Poll cmd on the high prio queue */ /* Poll cmd on the low prio queue */ /* Forced software interrupt */ /* Cfg9346Bits */ /* rx_mode_bits */ #define RX_CONFIG_ACCEPT_ERR_MASK 0x30#define RX_CONFIG_ACCEPT_OK_MASK 0x0f#define RX_CONFIG_ACCEPT_MASK 0x3f/* TxConfigBits */ /* DMA burst value (0-7) is shift this many bits */ /* Config1 register p.24 */ /* Power Management Enable */ /* Config2 register p. 25 */ /* Clock Request Enable */ /* 8169 only. Reserved in the 8168. */ /* Config3 register p.25 */ /* Wake up when receives a Magic Packet */ /* Wake up when the cable connection is re-established */ /* 8168 only. Reserved in the 8168b */ /* L23 Enable */ /* 8168 only. Reserved in the 8168b */ /* Config4 register */ /* 8168 only. Reserved in the 8168b */ /* Config5 register p.27 */ /* Accept Broadcast wakeup frame */ /* Accept Multicast wakeup frame */ /* Accept Unicast wakeup frame */ /* LanWake enable/disable */ /* PME status can be reset by PCI RST# */ /* ASPM enable */ /* CPlusCmd p.31 */ // 8168 8101 // 8168 8101 // 8169 // unused // 8168 8101 // 8168 8101 // 8168 8101 // 8168 8101 // 8168 8101 // 8168 8101 // 8168 #define INTT_MASK GENMASK(1, 0)#define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)/* rtl8169_PHYstatus */ /* ResetCounterCommand */ /* DumpCounterCommand */ /* magic enable v2 */ /* Wake up when receives a Magic Packet */ enum rtl_desc_bit {/* First doubleword. */ /* Descriptor is owned by NIC */ /* End of descriptor ring */ /* First segment of a packet */ /* Final segment of a packet */ /* Generic case. */ enum rtl_tx_desc_bit {/* First doubleword. */ /* Large Send Offload */ #define TD_MSS_MAX 0x07ffu /* MSS value */ /* Second doubleword. */ /* Add VLAN tag */ /* 8169, 8168b and 810x except 8102e. */ enum rtl_tx_desc_bit_0 {/* First doubleword. */ #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ /* Calculate TCP/IP checksum */ /* Calculate UDP/IP checksum */ /* Calculate IP checksum */ /* 8102e, 8168c and beyond. */ enum rtl_tx_desc_bit_1 {/* First doubleword. */ /* Giant Send for IPv4 */ /* Giant Send for IPv6 */ #define GTTCPHO_SHIFT 18#define GTTCPHO_MAX 0x7f/* Second doubleword. */ #define TCPHO_SHIFT 18#define TCPHO_MAX 0x3ff#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ /* Calculate IPv6 checksum */ /* Calculate IPv4 checksum */ /* Calculate TCP/IP checksum */ /* Calculate UDP/IP checksum */ enum rtl_rx_desc_bit {/* Rx private */ /* Protocol ID bit 1/2 */ /* Protocol ID bit 0/2 */ #define RxProtoUDP (PID1)#define RxProtoTCP (PID0)#define RxProtoIP (PID1 | PID0)#define RxProtoMask RxProtoIP/* IP checksum failed */ /* UDP/IP checksum failed */ /* TCP/IP checksum failed */ #define RxCSFailMask (IPFail | UDPFail | TCPFail)/* VLAN tag available */ #define RTL_GSO_MAX_SIZE_V1 32000#define RTL_GSO_MAX_SEGS_V1 24#define RTL_GSO_MAX_SIZE_V2 64000#define RTL_GSO_MAX_SEGS_V2 64struct TxDesc {struct RxDesc {struct ring_info {struct sk_buff *skb;struct rtl8169_counters {/* new since RTL8125 */ struct rtl8169_tc_offsets {bool inited;enum rtl_flag {enum rtl_dash_type {struct rtl8169_private {void __iomem *mmio_addr; /* memory map physical address */ struct pci_dev *pci_dev;struct net_device *dev;struct phy_device *phydev;struct napi_struct napi;enum mac_version mac_version;enum rtl_dash_type dash_type;/* Index into the Rx descriptor buffer of next Rx pkt. */ /* Index into the Tx descriptor buffer of next Rx pkt. */ struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ int irq;struct clk *clk;struct {struct work_struct work;struct mutex led_lock; /* serialize LED ctrl RMW access */ unsigned supports_gmii:1;unsigned aspm_manageable:1;unsigned dash_enabled:1;struct rtl8169_counters *counters;struct rtl8169_tc_offsets tc_offset;const char *fw_name;struct rtl_fw *rtl_fw;struct r8169_led_classdev *leds;typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);"Realtek and the Linux r8169 crew " );"RealTek RTL-8169 Gigabit Ethernet driver" );"pre: realtek" );"GPL" );static inline struct device *tp_to_dev(struct rtl8169_private *tp)return &tp->pci_dev->dev;static void rtl_lock_config_regs(struct rtl8169_private *tp)static void rtl_unlock_config_regs(struct rtl8169_private *tp)static void rtl_pci_commit(struct rtl8169_private *tp)/* Read an arbitrary register to commit a preceding PCI write */ static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set)static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set)static void r8169_mod_reg8_cond(struct rtl8169_private *tp, int reg,bool cond)if (cond)else if (val != old_val)static bool rtl_is_8125(struct rtl8169_private *tp)return tp->mac_version >= RTL_GIGA_MAC_VER_61;static bool rtl_is_8168evl_up(struct rtl8169_private *tp)return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&static bool rtl_supports_eee(struct rtl8169_private *tp)return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)int i;for (i = 0; i < ETH_ALEN; i++)struct rtl_cond {bool (*check)(struct rtl8169_private *);const char *msg;static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,unsigned long usecs, int n, bool high)int i;for (i = 0; i < n; i++) {if (c->check(tp) == high)return true ;if (net_ratelimit())"%s == %d (loop: %d, delay: %lu).\n" ,return false ;static bool rtl_loop_wait_high(struct rtl8169_private *tp,const struct rtl_cond *c,unsigned long d, int n)return rtl_loop_wait(tp, c, d, n, true );static bool rtl_loop_wait_low(struct rtl8169_private *tp,const struct rtl_cond *c,unsigned long d, int n)return rtl_loop_wait(tp, c, d, n, false );#define DECLARE_RTL_COND(name) \static bool name ## _check(struct rtl8169_private *); \static const struct rtl_cond name = { \## _check, \#name \static bool name ## _check(struct rtl8169_private *tp)int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val)struct device *dev = tp_to_dev(tp);int ret;if (ret < 0)return ret;return 0;int rtl8168_get_led_mode(struct rtl8169_private *tp)struct device *dev = tp_to_dev(tp);int ret;if (ret < 0)return ret;return ret;static int rtl8125_get_led_reg(int index)static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 };return led_regs[index];int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode)int reg = rtl8125_get_led_reg(index);struct device *dev = tp_to_dev(tp);int ret;if (ret < 0)return ret;return 0;int rtl8125_get_led_mode(struct rtl8169_private *tp, int index)int reg = rtl8125_get_led_reg(index);struct device *dev = tp_to_dev(tp);int ret;if (ret < 0)return ret;return ret;void r8169_get_led_name(struct rtl8169_private *tp, int idx,char *buf, int buf_len)struct pci_dev *pdev = tp->pci_dev;char pdom[8], pfun[8];int domain;if (domain)sizeof (pdom), "P%d" , domain);else '\0' ;if (pdev->multifunction)sizeof (pfun), "f%d" , PCI_FUNC(pdev->devfn));else '\0' ;"en%sp%ds%d%s-%d::lan" , pdom, pdev->bus->number,static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)/* based on RTL8168FP_OOBMAC_BASE in vendor driver */ if (type == ERIAR_OOB && tp->mac_version == RTL_GIGA_MAC_VER_52)return RTL_R32(tp, ERIAR) & ERIAR_FLAG;static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,int type)if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n" , addr, mask))return ;static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)static bool rtl_ocp_reg_failure(u32 reg)return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n" , reg);return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)if (rtl_ocp_reg_failure(reg))return ;static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)if (rtl_ocp_reg_failure(reg))return 0;return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)if (rtl_ocp_reg_failure(reg))return ;static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)unsigned long flags;static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)if (rtl_ocp_reg_failure(reg))return 0;return RTL_R32(tp, OCPDR);static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)unsigned long flags;return val;static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,unsigned long flags;/* Work around a hw issue with RTL8168g PHY, the quirk disables * PHY MCU interrupts before PHY power-down. static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)switch (tp->mac_version) {case RTL_GIGA_MAC_VER_40:if (value & BMCR_RESET || !(value & BMCR_PDOWN))else break ;default :break ;static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)if (reg == 0x1f) {return ;if (tp->ocp_base != OCP_STD_PHY_BASE)if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)if (reg == 0x1f)return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;if (tp->ocp_base != OCP_STD_PHY_BASE)return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)if (reg == 0x1f) {return ;static int mac_mcu_read(struct rtl8169_private *tp, int reg)return r8168_mac_ocp_read(tp, tp->ocp_base + reg);return RTL_R32(tp, PHYAR) & 0x80000000;static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)/* * According to hardware specs a 20us delay is required after write * complete indication, but before sending next command. static int r8169_mdio_read(struct rtl8169_private *tp, int reg)int value;/* * According to hardware specs a 20us delay is required after read * complete indication, but before sending next command. return value;return RTL_R32(tp, OCPAR) & OCPAR_FLAG;#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000static void r8168dp_2_mdio_start(struct rtl8169_private *tp)static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)int value;/* Work around issue with chip reporting wrong PHY ID */ if (reg == MII_PHYSID2)return 0xc912;return value;static void rtl_writephy(struct rtl8169_private *tp, int location, int val)switch (tp->mac_version) {case RTL_GIGA_MAC_VER_28:case RTL_GIGA_MAC_VER_31:break ;case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST:break ;default :break ;static int rtl_readphy(struct rtl8169_private *tp, int location)switch (tp->mac_version) {case RTL_GIGA_MAC_VER_28:case RTL_GIGA_MAC_VER_31:return r8168dp_2_mdio_read(tp, location);case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST:return r8168g_mdio_read(tp, location);default :return r8169_mdio_read(tp, location);return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)return _rtl_eri_read(tp, reg, ERIAR_OOB);static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)#define OOB_CMD_RESET 0x00#define OOB_CMD_DRIVER_START 0x05#define OOB_CMD_DRIVER_STOP 0x06static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;return r8168dp_ocp_read(tp, reg) & 0x00000800;return r8168ep_ocp_read(tp, 0x124) & 0x00000001;return RTL_R8(tp, IBISR0) & 0x20;static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)static void rtl8168dp_driver_start(struct rtl8169_private *tp)if (tp->dash_enabled)static void rtl8168ep_driver_start(struct rtl8169_private *tp)if (tp->dash_enabled)static void rtl8125bp_driver_start(struct rtl8169_private *tp)static void rtl8168_driver_start(struct rtl8169_private *tp)if (tp->dash_type == RTL_DASH_DP)else if (tp->dash_type == RTL_DASH_25_BP)else static void rtl8168dp_driver_stop(struct rtl8169_private *tp)if (tp->dash_enabled)static void rtl8168ep_driver_stop(struct rtl8169_private *tp)if (tp->dash_enabled)static void rtl8125bp_driver_stop(struct rtl8169_private *tp)static void rtl8168_driver_stop(struct rtl8169_private *tp)if (tp->dash_type == RTL_DASH_DP)else if (tp->dash_type == RTL_DASH_25_BP)else static bool r8168dp_check_dash(struct rtl8169_private *tp)return r8168dp_ocp_read(tp, reg) & BIT(15);static bool r8168ep_check_dash(struct rtl8169_private *tp)return r8168ep_ocp_read(tp, 0x128) & BIT(0);static bool rtl_dash_is_enabled(struct rtl8169_private *tp)switch (tp->dash_type) {case RTL_DASH_DP:return r8168dp_check_dash(tp);case RTL_DASH_EP:case RTL_DASH_25_BP:return r8168ep_check_dash(tp);default :return false ;static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp)switch (tp->mac_version) {case RTL_GIGA_MAC_VER_28:case RTL_GIGA_MAC_VER_31:return RTL_DASH_DP;case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_52:return RTL_DASH_EP;case RTL_GIGA_MAC_VER_66:return RTL_DASH_25_BP;default :return RTL_DASH_NONE;static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)if (tp->mac_version >= RTL_GIGA_MAC_VER_25 &&static void rtl_reset_packet_filter(struct rtl8169_private *tp)return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;struct rtl8169_private *tp, int reg_addr)return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?static u32 rtl_get_events(struct rtl8169_private *tp)if (rtl_is_8125(tp))return RTL_R32(tp, IntrStatus_8125);else return RTL_R16(tp, IntrStatus);static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)if (rtl_is_8125(tp))else static void rtl_irq_disable(struct rtl8169_private *tp)if (rtl_is_8125(tp))else static void rtl_irq_enable(struct rtl8169_private *tp)if (rtl_is_8125(tp))else static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)static void rtl_link_chg_patch(struct rtl8169_private *tp)struct phy_device *phydev = tp->phydev;if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||if (phydev->speed == SPEED_1000) {else if (phydev->speed == SPEED_100) {else {else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||if (phydev->speed == SPEED_1000) {else {else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {if (phydev->speed == SPEED_10) {else {#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)struct rtl8169_private *tp = netdev_priv(dev);static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)if (rtl_is_8168evl_up(tp)) {if (wolopts & WAKE_MAGIC)else else if (rtl_is_8125(tp)) {if (wolopts & WAKE_MAGIC)else else {if (rtl_is_8125(tp))switch (tp->mac_version) {case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:break ;case RTL_GIGA_MAC_VER_34:case RTL_GIGA_MAC_VER_37:case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_LAST:break ;default :break ;if (!tp->dash_enabled) {static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)struct rtl8169_private *tp = netdev_priv(dev);if (wol->wolopts & ~WAKE_ANY)return -EINVAL;return 0;static void rtl8169_get_drvinfo(struct net_device *dev,struct ethtool_drvinfo *info)struct rtl8169_private *tp = netdev_priv(dev);struct rtl_fw *rtl_fw = tp->rtl_fw;sizeof (info->driver));sizeof (info->bus_info));sizeof (info->fw_version) < sizeof (rtl_fw->version));if (rtl_fw)sizeof (info->fw_version));static int rtl8169_get_regs_len(struct net_device *dev)return R8169_REGS_SIZE;static netdev_features_t rtl8169_fix_features(struct net_device *dev,struct rtl8169_private *tp = netdev_priv(dev);if (dev->mtu > TD_MSS_MAX)if (dev->mtu > ETH_DATA_LEN &&return features;static void rtl_set_rx_config_features(struct rtl8169_private *tp,if (features & NETIF_F_RXALL)else if (rtl_is_8125(tp)) {if (features & NETIF_F_HW_VLAN_CTAG_RX)else static int rtl8169_set_features(struct net_device *dev,struct rtl8169_private *tp = netdev_priv(dev);if (features & NETIF_F_RXCSUM)else if (!rtl_is_8125(tp)) {if (features & NETIF_F_HW_VLAN_CTAG_RX)else return 0;static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)return (skb_vlan_tag_present(skb)) ?static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)if (opts2 & RxVlanTag)static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,void *p)struct rtl8169_private *tp = netdev_priv(dev);int i;for (i = 0; i < R8169_REGS_SIZE; i += 4)static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {"tx_packets" ,"rx_packets" ,"tx_errors" ,"rx_errors" ,"rx_missed" ,"align_errors" ,"tx_single_collisions" ,"tx_multi_collisions" ,"unicast" ,"broadcast" ,"multicast" ,"tx_aborted" ,"tx_underrun" ,static int rtl8169_get_sset_count(struct net_device *dev, int sset)switch (sset) {case ETH_SS_STATS:return ARRAY_SIZE(rtl8169_gstrings);default :return -EOPNOTSUPP;return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)static void rtl8169_update_counters(struct rtl8169_private *tp)/* * Some chips are unable to dump tally counters when the receiver * is disabled. If 0xff chip may be in a PCI power-save state. if (val & CmdRxEnb && val != 0xff)static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)struct rtl8169_counters *counters = tp->counters;/* * rtl8169_init_counter_offsets is called from rtl_open. On chip * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only * reset by a power cycle, while the counter values collected by the * driver are reset at every driver unload/load cycle. * * To make sure the HW values returned by @get_stats64 match the SW * values, we collect the initial values at first open(*) and use them * as offsets to normalize the values returned by @get_stats64. * * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one * for the reason stated in rtl8169_update_counters; CmdRxEnb is only * set at open time by rtl_hw_start. if (tp->tc_offset.inited)return ;if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {else {true ;static void rtl8169_get_ethtool_stats(struct net_device *dev,struct ethtool_stats *stats, u64 *data)struct rtl8169_private *tp = netdev_priv(dev);struct rtl8169_counters *counters;static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)switch (stringset) {case ETH_SS_STATS:sizeof (rtl8169_gstrings));break ;/* * Interrupt coalescing * * > 1 - the availability of the IntrMitigate (0xe2) register through the * > 8169, 8168 and 810x line of chipsets * * 8169, 8168, and 8136(810x) serial chipsets support it. * * > 2 - the Tx timer unit at gigabit speed * * The unit of the timer depends on both the speed and the setting of CPlusCmd * (0xe0) bit 1 and bit 0. * * For 8169 * bit[1:0] \ speed 1000M 100M 10M * 0 0 320ns 2.56us 40.96us * 0 1 2.56us 20.48us 327.7us * 1 0 5.12us 40.96us 655.4us * 1 1 10.24us 81.92us 1.31ms * * For the other * bit[1:0] \ speed 1000M 100M 10M * 0 0 5us 2.56us 40.96us * 0 1 40us 20.48us 327.7us * 1 0 80us 40.96us 655.4us * 1 1 160us 81.92us 1.31ms /* rx/tx scale factors for all CPlusCmd[0:1] cases */ struct rtl_coalesce_info {/* produce array with base delay *1, *8, *8*2, *8*2*2 */ #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {#undef COALESCE_DELAY/* get rx/tx scale vector corresponding to current speed */ static const struct rtl_coalesce_info *struct rtl8169_private *tp)const struct rtl_coalesce_info *ci;if (tp->mac_version <= RTL_GIGA_MAC_VER_06)else /* if speed is unknown assume highest one */ if (tp->phydev->speed == SPEED_UNKNOWN)return ci;for (; ci->speed; ci++) {if (tp->phydev->speed == ci->speed)return ci;return ERR_PTR(-ELNRNG);static int rtl_get_coalesce(struct net_device *dev,struct ethtool_coalesce *ec,struct kernel_ethtool_coalesce *kernel_coal,struct netlink_ext_ack *extack)struct rtl8169_private *tp = netdev_priv(dev);const struct rtl_coalesce_info *ci;if (rtl_is_8125(tp))return -EOPNOTSUPP;sizeof (*ec));/* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ if (IS_ERR(ci))return PTR_ERR(ci);/* ethtool_coalesce states usecs and max_frames must not both be 0 */ return 0;/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,const struct rtl_coalesce_info *ci;if (IS_ERR(ci))return PTR_ERR(ci);for (i = 0; i < 4; i++) {if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {return ci->scale_nsecs[i];return -ERANGE;static int rtl_set_coalesce(struct net_device *dev,struct ethtool_coalesce *ec,struct kernel_ethtool_coalesce *kernel_coal,struct netlink_ext_ack *extack)struct rtl8169_private *tp = netdev_priv(dev);int scale;if (rtl_is_8125(tp))return -EOPNOTSUPP;if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)return -ERANGE;if (scale < 0)return scale;/* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it * not only when usecs=0 because of e.g. the following scenario: * * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 * - then user does `ethtool -C eth0 rx-usecs 100` * * Since ethtool sends to kernel whole ethtool_coalesce settings, * if we want to ignore rx_frames then it has to be set to 0. if (rx_fr == 1)if (tx_fr == 1)/* HW requires time limit to be set if frame limit is set */ if ((tx_fr && !ec->tx_coalesce_usecs) ||return -EINVAL;/* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ if (rtl_is_8168evl_up(tp)) {if (!rx_fr && !tx_fr)/* disable packet counter */ else return 0;static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp)unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20;switch (tp->mac_version) {case RTL_GIGA_MAC_VER_46:case RTL_GIGA_MAC_VER_48:break ;case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST:break ;default :break ;static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp)unsigned int speed = tp->phydev->speed;unsigned int timer = tp->tx_lpi_timer;if (!timer || speed == SPEED_UNKNOWN)return 0;/* tx_lpi_timer value is in bytes */ return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed);static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data)struct rtl8169_private *tp = netdev_priv(dev);int ret;if (!rtl_supports_eee(tp))return -EOPNOTSUPP;if (ret)return ret;return 0;static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data)struct rtl8169_private *tp = netdev_priv(dev);if (!rtl_supports_eee(tp))return -EOPNOTSUPP;return phy_ethtool_set_eee(tp->phydev, data);static void rtl8169_get_ringparam(struct net_device *dev,struct ethtool_ringparam *data,struct kernel_ethtool_ringparam *kernel_data,struct netlink_ext_ack *extack)static void rtl8169_get_pause_stats(struct net_device *dev,struct ethtool_pause_stats *pause_stats)struct rtl8169_private *tp = netdev_priv(dev);if (!rtl_is_8125(tp))return ;static void rtl8169_get_pauseparam(struct net_device *dev,struct ethtool_pauseparam *data)struct rtl8169_private *tp = netdev_priv(dev);bool tx_pause, rx_pause;static int rtl8169_set_pauseparam(struct net_device *dev,struct ethtool_pauseparam *data)struct rtl8169_private *tp = netdev_priv(dev);if (dev->mtu > ETH_DATA_LEN)return -EOPNOTSUPP;return 0;static void rtl8169_get_eth_mac_stats(struct net_device *dev,struct ethtool_eth_mac_stats *mac_stats)struct rtl8169_private *tp = netdev_priv(dev);if (!rtl_is_8125(tp))return ;static void rtl8169_get_eth_ctrl_stats(struct net_device *dev,struct ethtool_eth_ctrl_stats *ctrl_stats)struct rtl8169_private *tp = netdev_priv(dev);if (!rtl_is_8125(tp))return ;static const struct ethtool_ops rtl8169_ethtool_ops = {static const struct rtl_chip_info *rtl8169_get_chip_version(u16 xid, bool gmii)/* Chips combining a 1Gbps MAC with a 100Mbps PHY */ static const struct rtl_chip_info rtl8106eus_info = {"RTL8106eus" ,static const struct rtl_chip_info rtl8107e_info = {"RTL8107e" ,const struct rtl_chip_info *p = rtl_chip_infos;while ((xid & p->mask) != p->val)if (p->mac_version == RTL_GIGA_MAC_VER_42 && !gmii)return &rtl8106eus_info;if (p->mac_version == RTL_GIGA_MAC_VER_46 && !gmii)return &rtl8107e_info;return p;static void rtl_release_firmware(struct rtl8169_private *tp)if (tp->rtl_fw) {void r8169_apply_firmware(struct rtl8169_private *tp)int val;/* TODO: release firmware if rtl_fw_write_firmware signals failure. */ if (tp->rtl_fw) {/* At least one firmware doesn't reset tp->ocp_base. */ /* PHY soft reset may still be in progress */ true );static void rtl8168_config_eee_mac(struct rtl8169_private *tp)/* Adjust EEE LED frequency */ if (tp->mac_version != RTL_GIGA_MAC_VER_38)static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)struct rtl8169_private *tp)if (data1 & BIT(7))return ioffset;static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
Messung V0.5 C=95 H=95 G=94
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