/* SPDX-License-Identifier: GPL-2.0-only */ /**************************************************************************** * Driver for Solarflare network controllers and boards * Copyright 2009-2018 Solarflare Communications Inc. * Copyright 2019-2020 Xilinx Inc.
*/
#ifndef MCDI_PCOL_H #define MCDI_PCOL_H
/* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ /* Power-on reset state */ #define MC_FW_STATE_POR (1) /* If this is set in MC_RESET_STATE_REG then it should be
* possible to jump into IMEM without loading code from flash. */ #define MC_FW_WARM_BOOT_OK (2) /* The MC main image has started to boot. */ #define MC_FW_STATE_BOOTING (4) /* The Scheduler has started. */ #define MC_FW_STATE_SCHED (8) /* If this is set in MC_RESET_STATE_REG then it should be * possible to jump into IMEM without loading code from flash. * Unlike a warm boot, assume DMEM has been reloaded, so that
* the MC persistent data must be reinitialised. */ #define MC_FW_TEPID_BOOT_OK (16) /* We have entered the main firmware via recovery mode. This * means that MC persistent data must be reinitialised, but that
* we shouldn't touch PCIe config. */ #define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32) /* BIST state has been initialized */ #define MC_FW_BIST_INIT_OK (128)
/* Siena MC shared memmory offsets */ /* The 'doorbell' addresses are hard-wired to alert the MC when written */ #define MC_SMEM_P0_DOORBELL_OFST 0x000 #define MC_SMEM_P1_DOORBELL_OFST 0x004 /* The rest of these are firmware-defined */ #define MC_SMEM_P0_PDU_OFST 0x008 #define MC_SMEM_P1_PDU_OFST 0x108 #define MC_SMEM_PDU_LEN 0x100 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 #define MC_SMEM_P0_STATUS_OFST 0x7f8 #define MC_SMEM_P1_STATUS_OFST 0x7fc
/* Values to be written to the per-port status dword in shared
* memory on reboot and assert */ #define MC_STATUS_DWORD_REBOOT (0xb007b007) #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
/* Check whether an mcfw version (in host order) belongs to a bootloader */ #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007)
/* The current version of the MCDI protocol. * * Note that the ROM burnt into the card only talks V0, so at the very * least every driver must support version 0 and MCDI_PCOL_VERSION
*/ #define MCDI_PCOL_VERSION 2
/* Unused commands: 0x23, 0x27, 0x30, 0x31 */
/* MCDI version 1 * * Each MCDI request starts with an MCDI_HEADER, which is a 32bit * structure, filled in by the client. * * 0 7 8 16 20 22 23 24 31 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | * | | | * | | \--- Response * | \------- Error * \------------------------------ Resync (always set) * * The client writes it's request into MC shared memory, and rings the * doorbell. Each request is completed by either by the MC writing * back into shared memory, or by writing out an event. * * All MCDI commands support completion by shared memory response. Each * request may also contain additional data (accounted for by HEADER.LEN), * and some response's may also contain additional data (again, accounted * for by HEADER.LEN). * * Some MCDI commands support completion by event, in which any associated * response data is included in the event. * * The protocol requires one response to be delivered for every request, a * request should not be sent unless the response for the previous request * has been received (either by polling shared memory, or by receiving * an event).
*/
/* The MC can generate events for two reasons: * - To advance a shared memory request if XFLAGS_EVREQ was set * - As a notification (link state, i2c event), controlled * via MC_CMD_LOG_CTRL * * Both events share a common structure: * * 0 32 33 36 44 52 60 * | Data | Cont | Level | Src | Code | Rsvd | * | * \ There is another event pending in this notification * * If Code==CMDDONE, then the fields are further interpreted as: * * - LEVEL==INFO Command succeeded * - LEVEL==ERR Command failed * * 0 8 16 24 32 * | Seq | Datalen | Errno | Rsvd | * * These fields are taken directly out of the standard MCDI header, i.e., * LEVEL==ERR, Datalen == 0 => Reboot * * Events can be squirted out of the UART (using LOG_CTRL) without a * MCDI header. An event can be distinguished from a MCDI response by * examining the first byte which is 0xc0. This corresponds to the * non-existent MCDI command MC_CMD_DEBUG_LOG. * * 0 7 8 * | command | Resync | = 0xc0 * * Since the event is written in big-endian byte order, this works * providing bits 56-63 of the event are 0xc0. * * 56 60 63 * | Rsvd | Code | = 0xc0 * * Which means for convenience the event code is 0xc for all MC * generated events.
*/ #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
/* Operation not permitted. */ #define MC_CMD_ERR_EPERM 1 /* Non-existent command target */ #define MC_CMD_ERR_ENOENT 2 /* assert() has killed the MC */ #define MC_CMD_ERR_EINTR 4 /* I/O failure */ #define MC_CMD_ERR_EIO 5 /* Already exists */ #define MC_CMD_ERR_EEXIST 6 /* Try again */ #define MC_CMD_ERR_EAGAIN 11 /* Out of memory */ #define MC_CMD_ERR_ENOMEM 12 /* Caller does not hold required locks */ #define MC_CMD_ERR_EACCES 13 /* Resource is currently unavailable (e.g. lock contention) */ #define MC_CMD_ERR_EBUSY 16 /* No such device */ #define MC_CMD_ERR_ENODEV 19 /* Invalid argument to target */ #define MC_CMD_ERR_EINVAL 22 /* Broken pipe */ #define MC_CMD_ERR_EPIPE 32 /* Read-only */ #define MC_CMD_ERR_EROFS 30 /* Out of range */ #define MC_CMD_ERR_ERANGE 34 /* Non-recursive resource is already acquired */ #define MC_CMD_ERR_EDEADLK 35 /* Operation not implemented */ #define MC_CMD_ERR_ENOSYS 38 /* Operation timed out */ #define MC_CMD_ERR_ETIME 62 /* Link has been severed */ #define MC_CMD_ERR_ENOLINK 67 /* Protocol error */ #define MC_CMD_ERR_EPROTO 71 /* Operation not supported */ #define MC_CMD_ERR_ENOTSUP 95 /* Address not available */ #define MC_CMD_ERR_EADDRNOTAVAIL 99 /* Not connected */ #define MC_CMD_ERR_ENOTCONN 107 /* Operation already in progress */ #define MC_CMD_ERR_EALREADY 114
/* Resource allocation failed. */ #define MC_CMD_ERR_ALLOC_FAIL 0x1000 /* V-adaptor not found. */ #define MC_CMD_ERR_NO_VADAPTOR 0x1001 /* EVB port not found. */ #define MC_CMD_ERR_NO_EVB_PORT 0x1002 /* V-switch not found. */ #define MC_CMD_ERR_NO_VSWITCH 0x1003 /* Too many VLAN tags. */ #define MC_CMD_ERR_VLAN_LIMIT 0x1004 /* Bad PCI function number. */ #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 /* Invalid VLAN mode. */ #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 /* Invalid v-switch type. */ #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 /* Invalid v-port type. */ #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 /* MAC address exists. */ #define MC_CMD_ERR_MAC_EXIST 0x1009 /* Slave core not present */ #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a /* The datapath is disabled. */ #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b /* The requesting client is not a function */ #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c /* The requested operation might require the command to be passed between MCs, and the transport doesn't support that. Should
only ever been seen over the UART. */ #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d /* VLAN tag(s) exists */ #define MC_CMD_ERR_VLAN_EXIST 0x100e /* No MAC address assigned to an EVB port */ #define MC_CMD_ERR_NO_MAC_ADDR 0x100f /* Notifies the driver that the request has been relayed * to an admin function for authorization. The driver should * wait for a PROXY_RESPONSE event and then resend its request. * This error code is followed by a 32-bit handle that
* helps matching it with the respective PROXY_RESPONSE event. */ #define MC_CMD_ERR_PROXY_PENDING 0x1010 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4 /* The request cannot be passed for authorization because * another request from the same function is currently being
* authorized. The drvier should try again later. */ #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011 /* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function * that has enabled proxying or BLOCK_INDEX points to a function that
* doesn't await an authorization. */ #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012 /* This code is currently only used internally in FW. Its meaning is that * an operation failed due to lack of SR-IOV privilege. * Normally it is translated to EPERM by send_cmd_err(), * but it may also be used to trigger some special mechanism * for handling such case, e.g. to relay the failed request
* to a designated admin function for authorization. */ #define MC_CMD_ERR_NO_PRIVILEGE 0x1013 /* Workaround 26807 could not be turned on/off because some functions * have already installed filters. See the comment at * MC_CMD_WORKAROUND_BUG26807.
* May also returned for other operations such as sub-variant switching. */ #define MC_CMD_ERR_FILTERS_PRESENT 0x1014 /* The clock whose frequency you've attempted to set
* doesn't exist on this NIC */ #define MC_CMD_ERR_NO_CLOCK 0x1015 /* Returned by MC_CMD_TESTASSERT if the action that should
* have caused an assertion failed to do so. */ #define MC_CMD_ERR_UNREACHABLE 0x1016 /* This command needs to be processed in the background but there were no
* resources to do so. Send it again after a command has completed. */ #define MC_CMD_ERR_QUEUE_FULL 0x1017 /* The operation could not be completed because the PCIe link has gone * away. This error code is never expected to be returned over the TLP
* transport. */ #define MC_CMD_ERR_NO_PCIE 0x1018 /* The operation could not be completed because the datapath has gone * away. This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the
* datapath absence may be temporary*/ #define MC_CMD_ERR_NO_DATAPATH 0x1019 /* The operation could not complete because some VIs are allocated */ #define MC_CMD_ERR_VIS_PRESENT 0x101a /* The operation could not complete because some PIO buffers are allocated */ #define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b
#define MC_CMD_ERR_CODE_OFST 0
/* We define 8 "escape" commands to allow
for command number space extension */
/* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default * stack ID (which must be in the range 1-255) along with an EVB port ID.
*/ #define EVB_STACK_ID(n) (((n) & 0xff) << 16)
/* Version 2 adds an optional argument to error returns: the errno value * may be followed by the (0-based) number of the first argument that * could not be processed.
*/ #define MC_CMD_ERR_ARG_OFST 4
/* No space */ #define MC_CMD_ERR_ENOSPC 28
/* MCDI_EVENT structuredef */ #define MCDI_EVENT_LEN 8 #define MCDI_EVENT_CONT_LBN 32 #define MCDI_EVENT_CONT_WIDTH 1 #define MCDI_EVENT_LEVEL_LBN 33 #define MCDI_EVENT_LEVEL_WIDTH 3 /* enum: Info. */ #define MCDI_EVENT_LEVEL_INFO 0x0 /* enum: Warning. */ #define MCDI_EVENT_LEVEL_WARN 0x1 /* enum: Error. */ #define MCDI_EVENT_LEVEL_ERR 0x2 /* enum: Fatal. */ #define MCDI_EVENT_LEVEL_FATAL 0x3 #define MCDI_EVENT_DATA_OFST 0 #define MCDI_EVENT_DATA_LEN 4 #define MCDI_EVENT_CMDDONE_SEQ_OFST 0 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 #define MCDI_EVENT_CMDDONE_DATALEN_OFST 0 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 #define MCDI_EVENT_CMDDONE_ERRNO_OFST 0 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 #define MCDI_EVENT_LINKCHANGE_LP_CAP_OFST 0 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 #define MCDI_EVENT_LINKCHANGE_SPEED_OFST 0 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 /* enum: Link is down or link speed could not be determined */ #define MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0 /* enum: 100Mbs */ #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 /* enum: 1Gbs */ #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 /* enum: 10Gbs */ #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 /* enum: 40Gbs */ #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 /* enum: 25Gbs */ #define MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5 /* enum: 50Gbs */ #define MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6 /* enum: 100Gbs */ #define MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7 #define MCDI_EVENT_LINKCHANGE_FCNTL_OFST 0 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_OFST 0 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 #define MCDI_EVENT_SENSOREVT_MONITOR_OFST 0 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 #define MCDI_EVENT_SENSOREVT_STATE_OFST 0 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 #define MCDI_EVENT_SENSOREVT_VALUE_OFST 0 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 #define MCDI_EVENT_FWALERT_DATA_OFST 0 #define MCDI_EVENT_FWALERT_DATA_LBN 8 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 #define MCDI_EVENT_FWALERT_REASON_OFST 0 #define MCDI_EVENT_FWALERT_REASON_LBN 0 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 /* enum: SRAM Access. */ #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 #define MCDI_EVENT_FLR_VF_OFST 0 #define MCDI_EVENT_FLR_VF_LBN 0 #define MCDI_EVENT_FLR_VF_WIDTH 8 #define MCDI_EVENT_TX_ERR_TXQ_OFST 0 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 #define MCDI_EVENT_TX_ERR_TYPE_OFST 0 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 /* enum: Descriptor loader reported failure */ #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 /* enum: Descriptor ring empty and no EOP seen for packet */ #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 /* enum: Overlength packet */ #define MCDI_EVENT_TX_ERR_2BIG 0x3 /* enum: Malformed option descriptor */ #define MCDI_EVENT_TX_BAD_OPTDESC 0x5 /* enum: Option descriptor part way through a packet */ #define MCDI_EVENT_TX_OPT_IN_PKT 0x8 /* enum: DMA or PIO data access error */ #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 #define MCDI_EVENT_TX_ERR_INFO_OFST 0 #define MCDI_EVENT_TX_ERR_INFO_LBN 16 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_OFST 0 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 #define MCDI_EVENT_TX_FLUSH_TXQ_OFST 0 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 #define MCDI_EVENT_PTP_ERR_TYPE_OFST 0 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 /* enum: PLL lost lock */ #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 /* enum: Filter overflow (PDMA) */ #define MCDI_EVENT_PTP_ERR_FILTER 0x2 /* enum: FIFO overflow (FPGA) */ #define MCDI_EVENT_PTP_ERR_FIFO 0x3 /* enum: Merge queue overflow */ #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 #define MCDI_EVENT_AOE_ERR_TYPE_OFST 0 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 /* enum: AOE failed to load - no valid image? */ #define MCDI_EVENT_AOE_NO_LOAD 0x1 /* enum: AOE FC reported an exception */ #define MCDI_EVENT_AOE_FC_ASSERT 0x2 /* enum: AOE FC watchdogged */ #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 /* enum: AOE FC failed to start */ #define MCDI_EVENT_AOE_FC_NO_START 0x4 /* enum: Generic AOE fault - likely to have been reported via other means too * but intended for use by aoex driver.
*/ #define MCDI_EVENT_AOE_FAULT 0x5 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 /* enum: AOE loaded successfully */ #define MCDI_EVENT_AOE_LOAD 0x7 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ #define MCDI_EVENT_AOE_DMA 0x8 /* enum: AOE byteblaster connected/disconnected (Connection status in * AOE_ERR_DATA)
*/ #define MCDI_EVENT_AOE_BYTEBLASTER 0x9 /* enum: DDR ECC status update */ #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa /* enum: PTP status update */ #define MCDI_EVENT_AOE_PTP_STATUS 0xb /* enum: FPGA header incorrect */ #define MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc /* enum: FPGA Powered Off due to error in powering up FPGA */ #define MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd /* enum: AOE FPGA load failed due to MC to MUM communication failure */ #define MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe /* enum: Notify that invalid flash type detected */ #define MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf /* enum: Notify that the attempt to run FPGA Controller firmware timedout */ #define MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10 /* enum: Failure to probe one or more FPGA boot flash chips */ #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11 /* enum: FPGA boot-flash contains an invalid image header */ #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12 /* enum: Failed to program clocks required by the FPGA */ #define MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13 /* enum: Notify that FPGA Controller is alive to serve MCDI requests */ #define MCDI_EVENT_AOE_FC_RUNNING 0x14 #define MCDI_EVENT_AOE_ERR_DATA_OFST 0 #define MCDI_EVENT_AOE_ERR_DATA_LBN 8 #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_OFST 0 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_LBN 8 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_WIDTH 8 /* enum: FC Assert happened, but the register information is not available */ #define MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0 /* enum: The register information for FC Assert is ready for readinng by driver
*/ #define MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_OFST 0 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8 /* enum: Reading from NV failed */ #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0 /* enum: Invalid Magic Number if FPGA header */ #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1 /* enum: Invalid Silicon type detected in header */ #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2 /* enum: Unsupported VRatio */ #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3 /* enum: Unsupported DDR Type */ #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4 /* enum: DDR Voltage out of supported range */ #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5 /* enum: Unsupported DDR speed */ #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6 /* enum: Unsupported DDR size */ #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7 /* enum: Unsupported DDR rank */ #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_OFST 0 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 8 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 8 /* enum: Primary boot flash */ #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0 /* enum: Secondary boot flash */ #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_OFST 0 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 8 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 8 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_OFST 0 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 8 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 8 #define MCDI_EVENT_RX_ERR_RXQ_OFST 0 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0 #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 #define MCDI_EVENT_RX_ERR_TYPE_OFST 0 #define MCDI_EVENT_RX_ERR_TYPE_LBN 12 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 #define MCDI_EVENT_RX_ERR_INFO_OFST 0 #define MCDI_EVENT_RX_ERR_INFO_LBN 16 #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_OFST 0 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 #define MCDI_EVENT_RX_FLUSH_RXQ_OFST 0 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 #define MCDI_EVENT_MC_REBOOT_COUNT_OFST 0 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 #define MCDI_EVENT_MUM_ERR_TYPE_OFST 0 #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0 #define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8 /* enum: MUM failed to load - no valid image? */ #define MCDI_EVENT_MUM_NO_LOAD 0x1 /* enum: MUM f/w reported an exception */ #define MCDI_EVENT_MUM_ASSERT 0x2 /* enum: MUM not kicking watchdog */ #define MCDI_EVENT_MUM_WATCHDOG 0x3 #define MCDI_EVENT_MUM_ERR_DATA_OFST 0 #define MCDI_EVENT_MUM_ERR_DATA_LBN 8 #define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8 #define MCDI_EVENT_DBRET_SEQ_OFST 0 #define MCDI_EVENT_DBRET_SEQ_LBN 0 #define MCDI_EVENT_DBRET_SEQ_WIDTH 8 #define MCDI_EVENT_SUC_ERR_TYPE_OFST 0 #define MCDI_EVENT_SUC_ERR_TYPE_LBN 0 #define MCDI_EVENT_SUC_ERR_TYPE_WIDTH 8 /* enum: Corrupted or bad SUC application. */ #define MCDI_EVENT_SUC_BAD_APP 0x1 /* enum: SUC application reported an assert. */ #define MCDI_EVENT_SUC_ASSERT 0x2 /* enum: SUC application reported an exception. */ #define MCDI_EVENT_SUC_EXCEPTION 0x3 /* enum: SUC watchdog timer expired. */ #define MCDI_EVENT_SUC_WATCHDOG 0x4 #define MCDI_EVENT_SUC_ERR_ADDRESS_OFST 0 #define MCDI_EVENT_SUC_ERR_ADDRESS_LBN 8 #define MCDI_EVENT_SUC_ERR_ADDRESS_WIDTH 24 #define MCDI_EVENT_SUC_ERR_DATA_OFST 0 #define MCDI_EVENT_SUC_ERR_DATA_LBN 8 #define MCDI_EVENT_SUC_ERR_DATA_WIDTH 24 #define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_OFST 0 #define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_LBN 0 #define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_WIDTH 24 #define MCDI_EVENT_LINKCHANGE_V2_SPEED_OFST 0 #define MCDI_EVENT_LINKCHANGE_V2_SPEED_LBN 24 #define MCDI_EVENT_LINKCHANGE_V2_SPEED_WIDTH 4 /* Enum values, see field(s): */ /* MCDI_EVENT/LINKCHANGE_SPEED */ #define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_OFST 0 #define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_LBN 28 #define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_WIDTH 1 #define MCDI_EVENT_LINKCHANGE_V2_FCNTL_OFST 0 #define MCDI_EVENT_LINKCHANGE_V2_FCNTL_LBN 29 #define MCDI_EVENT_LINKCHANGE_V2_FCNTL_WIDTH 3 /* Enum values, see field(s): */ /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ #define MCDI_EVENT_MODULECHANGE_LD_CAP_OFST 0 #define MCDI_EVENT_MODULECHANGE_LD_CAP_LBN 0 #define MCDI_EVENT_MODULECHANGE_LD_CAP_WIDTH 30 #define MCDI_EVENT_MODULECHANGE_SEQ_OFST 0 #define MCDI_EVENT_MODULECHANGE_SEQ_LBN 30 #define MCDI_EVENT_MODULECHANGE_SEQ_WIDTH 2 #define MCDI_EVENT_DATA_LBN 0 #define MCDI_EVENT_DATA_WIDTH 32 /* Alias for PTP_DATA. */ #define MCDI_EVENT_SRC_LBN 36 #define MCDI_EVENT_SRC_WIDTH 8 /* Data associated with PTP events which doesn't fit into the main DATA field
*/ #define MCDI_EVENT_PTP_DATA_LBN 36 #define MCDI_EVENT_PTP_DATA_WIDTH 8 /* EF100 specific. Defined by QDMA. The phase bit, changes each time round the * event ring
*/ #define MCDI_EVENT_EV_EVQ_PHASE_LBN 59 #define MCDI_EVENT_EV_EVQ_PHASE_WIDTH 1 #define MCDI_EVENT_EV_CODE_LBN 60 #define MCDI_EVENT_EV_CODE_WIDTH 4 #define MCDI_EVENT_CODE_LBN 44 #define MCDI_EVENT_CODE_WIDTH 8 /* enum: Event generated by host software */ #define MCDI_EVENT_SW_EVENT 0x0 /* enum: Bad assert. */ #define MCDI_EVENT_CODE_BADSSERT 0x1 /* enum: PM Notice. */ #define MCDI_EVENT_CODE_PMNOTICE 0x2 /* enum: Command done. */ #define MCDI_EVENT_CODE_CMDDONE 0x3 /* enum: Link change. */ #define MCDI_EVENT_CODE_LINKCHANGE 0x4 /* enum: Sensor Event. */ #define MCDI_EVENT_CODE_SENSOREVT 0x5 /* enum: Schedule error. */ #define MCDI_EVENT_CODE_SCHEDERR 0x6 /* enum: Reboot. */ #define MCDI_EVENT_CODE_REBOOT 0x7 /* enum: Mac stats DMA. */ #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 /* enum: Firmware alert. */ #define MCDI_EVENT_CODE_FWALERT 0x9 /* enum: Function level reset. */ #define MCDI_EVENT_CODE_FLR 0xa /* enum: Transmit error */ #define MCDI_EVENT_CODE_TX_ERR 0xb /* enum: Tx flush has completed */ #define MCDI_EVENT_CODE_TX_FLUSH 0xc /* enum: PTP packet received timestamp */ #define MCDI_EVENT_CODE_PTP_RX 0xd /* enum: PTP NIC failure */ #define MCDI_EVENT_CODE_PTP_FAULT 0xe /* enum: PTP PPS event */ #define MCDI_EVENT_CODE_PTP_PPS 0xf /* enum: Rx flush has completed */ #define MCDI_EVENT_CODE_RX_FLUSH 0x10 /* enum: Receive error */ #define MCDI_EVENT_CODE_RX_ERR 0x11 /* enum: AOE fault */ #define MCDI_EVENT_CODE_AOE 0x12 /* enum: Network port calibration failed (VCAL). */ #define MCDI_EVENT_CODE_VCAL_FAIL 0x13 /* enum: HW PPS event */ #define MCDI_EVENT_CODE_HW_PPS 0x14 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and * a different format)
*/ #define MCDI_EVENT_CODE_MC_REBOOT 0x15 /* enum: the MC has detected a parity error */ #define MCDI_EVENT_CODE_PAR_ERR 0x16 /* enum: the MC has detected a correctable error */ #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 /* enum: the MC has detected an uncorrectable error */ #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 /* enum: The MC has entered offline BIST mode */ #define MCDI_EVENT_CODE_MC_BIST 0x19 /* enum: PTP tick event providing current NIC time */ #define MCDI_EVENT_CODE_PTP_TIME 0x1a /* enum: MUM fault */ #define MCDI_EVENT_CODE_MUM 0x1b /* enum: notify the designated PF of a new authorization request */ #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c /* enum: notify a function that awaits an authorization that its request has * been processed and it may now resend the command
*/ #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d /* enum: MCDI command accepted. New commands can be issued but this command is * not done yet.
*/ #define MCDI_EVENT_CODE_DBRET 0x1e /* enum: The MC has detected a fault on the SUC */ #define MCDI_EVENT_CODE_SUC 0x1f /* enum: Link change. This event is sent instead of LINKCHANGE if * WANT_V2_LINKCHANGES was set on driver attach.
*/ #define MCDI_EVENT_CODE_LINKCHANGE_V2 0x20 /* enum: This event is sent if WANT_V2_LINKCHANGES was set on driver attach * when the local device capabilities changes. This will usually correspond to * a module change.
*/ #define MCDI_EVENT_CODE_MODULECHANGE 0x21 /* enum: Notification that the sensors have been added and/or removed from the * sensor table. This event includes the new sensor table generation count, if * this does not match the driver's local copy it is expected to call * DYNAMIC_SENSORS_LIST to refresh it.
*/ #define MCDI_EVENT_CODE_DYNAMIC_SENSORS_CHANGE 0x22 /* enum: Notification that a sensor has changed state as a result of a reading * crossing a threshold. This is sent as two events, the first event contains * the handle and the sensor's state (in the SRC field), and the second * contains the value.
*/ #define MCDI_EVENT_CODE_DYNAMIC_SENSORS_STATE_CHANGE 0x23 /* enum: Notification that a descriptor proxy function configuration has been * pushed to "live" status (visible to host). SRC field contains the handle of * the affected descriptor proxy function. DATA field contains the generation * count of configuration set applied. See MC_CMD_DESC_PROXY_FUNC_CONFIG_SET / * MC_CMD_DESC_PROXY_FUNC_CONFIG_COMMIT and SF-122927-TC for details.
*/ #define MCDI_EVENT_CODE_DESC_PROXY_FUNC_CONFIG_COMMITTED 0x24 /* enum: Notification that a descriptor proxy function has been reset. SRC * field contains the handle of the affected descriptor proxy function. See * SF-122927-TC for details.
*/ #define MCDI_EVENT_CODE_DESC_PROXY_FUNC_RESET 0x25 /* enum: Notification that a driver attached to a descriptor proxy function. * SRC field contains the handle of the affected descriptor proxy function. For * Virtio proxy functions this message consists of two MCDI events, where the * first event's (CONT=1) DATA field carries negotiated virtio feature bits 0 * to 31 and the second (CONT=0) carries bits 32 to 63. For EF100 proxy * functions event length and meaning of DATA field is not yet defined. See * SF-122927-TC for details.
*/ #define MCDI_EVENT_CODE_DESC_PROXY_FUNC_DRIVER_ATTACH 0x26 /* enum: Artificial event generated by host and posted via MC for test * purposes.
*/ #define MCDI_EVENT_CODE_TESTGEN 0xfa #define MCDI_EVENT_CMDDONE_DATA_OFST 0 #define MCDI_EVENT_CMDDONE_DATA_LEN 4 #define MCDI_EVENT_CMDDONE_DATA_LBN 0 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 #define MCDI_EVENT_LINKCHANGE_DATA_LEN 4 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 #define MCDI_EVENT_SENSOREVT_DATA_LEN 4 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 4 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 #define MCDI_EVENT_TX_ERR_DATA_OFST 0 #define MCDI_EVENT_TX_ERR_DATA_LEN 4 #define MCDI_EVENT_TX_ERR_DATA_LBN 0 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of * timestamp
*/ #define MCDI_EVENT_PTP_SECONDS_OFST 0 #define MCDI_EVENT_PTP_SECONDS_LEN 4 #define MCDI_EVENT_PTP_SECONDS_LBN 0 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of * timestamp
*/ #define MCDI_EVENT_PTP_MAJOR_OFST 0 #define MCDI_EVENT_PTP_MAJOR_LEN 4 #define MCDI_EVENT_PTP_MAJOR_LBN 0 #define MCDI_EVENT_PTP_MAJOR_WIDTH 32 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field * of timestamp
*/ #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 #define MCDI_EVENT_PTP_NANOSECONDS_LEN 4 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of * timestamp
*/ #define MCDI_EVENT_PTP_MINOR_OFST 0 #define MCDI_EVENT_PTP_MINOR_LEN 4 #define MCDI_EVENT_PTP_MINOR_LBN 0 #define MCDI_EVENT_PTP_MINOR_WIDTH 32 /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet
*/ #define MCDI_EVENT_PTP_UUID_OFST 0 #define MCDI_EVENT_PTP_UUID_LEN 4 #define MCDI_EVENT_PTP_UUID_LBN 0 #define MCDI_EVENT_PTP_UUID_WIDTH 32 #define MCDI_EVENT_RX_ERR_DATA_OFST 0 #define MCDI_EVENT_RX_ERR_DATA_LEN 4 #define MCDI_EVENT_RX_ERR_DATA_LBN 0 #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0 #define MCDI_EVENT_PAR_ERR_DATA_LEN 4 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0 #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LEN 4 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 4 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 /* For CODE_PTP_TIME events, the major value of the PTP clock */ #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0 #define MCDI_EVENT_PTP_TIME_MAJOR_LEN 4 #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0 #define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */ #define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8 /* For CODE_PTP_TIME events, most significant bits of the minor value of the * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_19.
*/ #define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_LBN 36 #define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_WIDTH 8 /* For CODE_PTP_TIME events where report sync status is enabled, indicates * whether the NIC clock has ever been set
*/ #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1 /* For CODE_PTP_TIME events where report sync status is enabled, indicates * whether the NIC and System clocks are in sync
*/ #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of * the minor value of the PTP clock
*/ #define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6 /* For CODE_PTP_TIME events, most significant bits of the minor value of the * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_21.
*/ #define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_LBN 38 #define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_WIDTH 6 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 4 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 4 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32 /* Zero means that the request has been completed or authorized, and the driver * should resend it. A non-zero value means that the authorization has been * denied, and gives the reason. Typically it will be EPERM.
*/ #define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36 #define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8 #define MCDI_EVENT_DBRET_DATA_OFST 0 #define MCDI_EVENT_DBRET_DATA_LEN 4 #define MCDI_EVENT_DBRET_DATA_LBN 0 #define MCDI_EVENT_DBRET_DATA_WIDTH 32 #define MCDI_EVENT_LINKCHANGE_V2_DATA_OFST 0 #define MCDI_EVENT_LINKCHANGE_V2_DATA_LEN 4 #define MCDI_EVENT_LINKCHANGE_V2_DATA_LBN 0 #define MCDI_EVENT_LINKCHANGE_V2_DATA_WIDTH 32 #define MCDI_EVENT_MODULECHANGE_DATA_OFST 0 #define MCDI_EVENT_MODULECHANGE_DATA_LEN 4 #define MCDI_EVENT_MODULECHANGE_DATA_LBN 0 #define MCDI_EVENT_MODULECHANGE_DATA_WIDTH 32 /* The new generation count after a sensor has been added or deleted. */ #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_OFST 0 #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LEN 4 #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LBN 0 #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_WIDTH 32 /* The handle of a dynamic sensor. */ #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_OFST 0 #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LEN 4 #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LBN 0 #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_WIDTH 32 /* The current values of a sensor. */ #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_OFST 0 #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LEN 4 #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LBN 0 #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_WIDTH 32 /* The current state of a sensor. */ #define MCDI_EVENT_DYNAMIC_SENSORS_STATE_LBN 36 #define MCDI_EVENT_DYNAMIC_SENSORS_STATE_WIDTH 8 #define MCDI_EVENT_DESC_PROXY_DATA_OFST 0 #define MCDI_EVENT_DESC_PROXY_DATA_LEN 4 #define MCDI_EVENT_DESC_PROXY_DATA_LBN 0 #define MCDI_EVENT_DESC_PROXY_DATA_WIDTH 32 /* Generation count of applied configuration set */ #define MCDI_EVENT_DESC_PROXY_GENERATION_OFST 0 #define MCDI_EVENT_DESC_PROXY_GENERATION_LEN 4 #define MCDI_EVENT_DESC_PROXY_GENERATION_LBN 0 #define MCDI_EVENT_DESC_PROXY_GENERATION_WIDTH 32 /* Virtio features negotiated with the host driver. First event (CONT=1) * carries bits 0 to 31. Second event (CONT=0) carries bits 32 to 63.
*/ #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_OFST 0 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LEN 4 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LBN 0 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_WIDTH 32
/* FCDI_EVENT structuredef */ #define FCDI_EVENT_LEN 8 #define FCDI_EVENT_CONT_LBN 32 #define FCDI_EVENT_CONT_WIDTH 1 #define FCDI_EVENT_LEVEL_LBN 33 #define FCDI_EVENT_LEVEL_WIDTH 3 /* enum: Info. */ #define FCDI_EVENT_LEVEL_INFO 0x0 /* enum: Warning. */ #define FCDI_EVENT_LEVEL_WARN 0x1 /* enum: Error. */ #define FCDI_EVENT_LEVEL_ERR 0x2 /* enum: Fatal. */ #define FCDI_EVENT_LEVEL_FATAL 0x3 #define FCDI_EVENT_DATA_OFST 0 #define FCDI_EVENT_DATA_LEN 4 #define FCDI_EVENT_LINK_STATE_STATUS_OFST 0 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ #define FCDI_EVENT_LINK_UP 0x1 /* enum */ #define FCDI_EVENT_DATA_LBN 0 #define FCDI_EVENT_DATA_WIDTH 32 #define FCDI_EVENT_SRC_LBN 36 #define FCDI_EVENT_SRC_WIDTH 8 #define FCDI_EVENT_EV_CODE_LBN 60 #define FCDI_EVENT_EV_CODE_WIDTH 4 #define FCDI_EVENT_CODE_LBN 44 #define FCDI_EVENT_CODE_WIDTH 8 /* enum: The FC was rebooted. */ #define FCDI_EVENT_CODE_REBOOT 0x1 /* enum: Bad assert. */ #define FCDI_EVENT_CODE_ASSERT 0x2 /* enum: DDR3 test result. */ #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 /* enum: Link status. */ #define FCDI_EVENT_CODE_LINK_STATE 0x4 /* enum: A timed read is ready to be serviced. */ #define FCDI_EVENT_CODE_TIMED_READ 0x5 /* enum: One or more PPS IN events */ #define FCDI_EVENT_CODE_PPS_IN 0x6 /* enum: Tick event from PTP clock */ #define FCDI_EVENT_CODE_PTP_TICK 0x7 /* enum: ECC error counters */ #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 /* enum: Current status of PTP */ #define FCDI_EVENT_CODE_PTP_STATUS 0x9 /* enum: Port id config to map MC-FC port idx */ #define FCDI_EVENT_CODE_PORT_CONFIG 0xa /* enum: Boot result or error code */ #define FCDI_EVENT_CODE_BOOT_RESULT 0xb #define FCDI_EVENT_REBOOT_SRC_LBN 36 #define FCDI_EVENT_REBOOT_SRC_WIDTH 8 #define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */ #define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */ #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LEN 4 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 #define FCDI_EVENT_ASSERT_TYPE_LBN 36 #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LEN 4 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 #define FCDI_EVENT_LINK_STATE_DATA_LEN 4 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 #define FCDI_EVENT_PTP_STATE_OFST 0 #define FCDI_EVENT_PTP_STATE_LEN 4 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */ #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */ #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */ #define FCDI_EVENT_PTP_STATE_LBN 0 #define FCDI_EVENT_PTP_STATE_WIDTH 32 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LEN 4 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 /* Index of MC port being referred to */ #define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36 #define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8 /* FC Port index that matches the MC port index in SRC */ #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0 #define FCDI_EVENT_PORT_CONFIG_DATA_LEN 4 #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0 #define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32 #define FCDI_EVENT_BOOT_RESULT_OFST 0 #define FCDI_EVENT_BOOT_RESULT_LEN 4 /* Enum values, see field(s): */ /* MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */ #define FCDI_EVENT_BOOT_RESULT_LBN 0 #define FCDI_EVENT_BOOT_RESULT_WIDTH 32
/* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events * to the MC. Note that this structure | is overlayed over a normal FCDI event * such that bits 32-63 containing | event code, level, source etc remain the * same. In this case the data | field of the header is defined to be the * number of timestamps
*/ #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 #define FCDI_EXTENDED_EVENT_PPS_LENMAX_MCDI2 1016 #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_NUM(len) (((len)-8)/8) /* Number of timestamps following */ #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 4 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 /* Seconds field of a timestamp record */ #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LEN 4 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 /* Nanoseconds field of a timestamp record */ #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LEN 4 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 /* Timestamp records comprising the event */ #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM_MCDI2 126 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64
/***********************************/ /* MC_CMD_READ32 * Read multiple 32byte words from MC memory. Note - this command really * belongs to INSECURE category but is required by shmboot. The command handler * has additional checks to reject insecure calls.
*/ #define MC_CMD_READ32 0x1 #undef MC_CMD_0x1_PRIVILEGE_CTG
/***********************************/ /* MC_CMD_COPYCODE * Copy MC code between two locations and jump. Note - this command really * belongs to INSECURE category but is required by shmboot. The command handler * has additional checks to reject insecure calls.
*/ #define MC_CMD_COPYCODE 0x3 #undef MC_CMD_0x3_PRIVILEGE_CTG
#define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN
/* MC_CMD_COPYCODE_IN msgrequest */ #define MC_CMD_COPYCODE_IN_LEN 16 /* Source address * * The main image should be entered via a copy of a single word from and to a * magic address, which controls various aspects of the boot. The magic address * is a bitfield, with each bit as documented below.
*/ #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 #define MC_CMD_COPYCODE_IN_SRC_ADDR_LEN 4 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */ #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below)
*/ #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT, * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see * below)
*/ #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_OFST 0 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_OFST 0 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_OFST 0 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_OFST 0 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_OFST 0 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_OFST 0 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 6 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1 /* Destination address */ #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 #define MC_CMD_COPYCODE_IN_DEST_ADDR_LEN 4 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 #define MC_CMD_COPYCODE_IN_NUMWORDS_LEN 4 /* Address of where to jump after copy. */ #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 #define MC_CMD_COPYCODE_IN_JUMP_LEN 4 /* enum: Control should return to the caller rather than jumping */ #define MC_CMD_COPYCODE_JUMP_NONE 0x1
/***********************************/ /* MC_CMD_GET_BOOT_STATUS * Get the instruction address from which the MC booted.
*/ #define MC_CMD_GET_BOOT_STATUS 0x5 #undef MC_CMD_0x5_PRIVILEGE_CTG
/***********************************/ /* MC_CMD_GET_ASSERTS * Get (and optionally clear) the current assertion status. Only * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS
*/ #define MC_CMD_GET_ASSERTS 0x6 #undef MC_CMD_0x6_PRIVILEGE_CTG
#define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
/* MC_CMD_GET_ASSERTS_IN msgrequest */ #define MC_CMD_GET_ASSERTS_IN_LEN 4 /* Set to clear assertion */ #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 #define MC_CMD_GET_ASSERTS_IN_CLEAR_LEN 4
/* MC_CMD_GET_ASSERTS_OUT msgresponse */ #define MC_CMD_GET_ASSERTS_OUT_LEN 140 /* Assertion status flag. */ #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 4 /* enum: No assertions have failed. */ #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 /* enum: A system-level assertion has failed. */ #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 /* enum: A thread-level assertion has failed. */ #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 /* enum: The system was reset by the watchdog. */ #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 /* enum: An illegal address trap stopped the system (huntington and later) */ #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 /* Failing PC value */ #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 4 /* Saved GP regs */ #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 /* enum: A magic value hinting that the value in this register at the time of * the failure has likely been lost.
*/ #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 /* Failing thread address */ #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 4 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4
/* MC_CMD_GET_ASSERTS_OUT_V2 msgresponse: Extended response for MicroBlaze CPUs * found on Riverhead designs
*/ #define MC_CMD_GET_ASSERTS_OUT_V2_LEN 240 /* Assertion status flag. */ #define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_OFST 0 #define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_LEN 4 /* enum: No assertions have failed. */ /* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */ /* enum: A system-level assertion has failed. */ /* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */ /* enum: A thread-level assertion has failed. */ /* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */ /* enum: The system was reset by the watchdog. */ /* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */ /* enum: An illegal address trap stopped the system (huntington and later) */ /* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */ /* Failing PC value */ #define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_OFST 4 #define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_LEN 4 /* Saved GP regs */ #define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_OFST 8 #define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_LEN 4 #define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_NUM 31 /* enum: A magic value hinting that the value in this register at the time of * the failure has likely been lost.
*/ /* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */ /* Failing thread address */ #define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_OFST 132 #define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_LEN 4 #define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_OFST 136 #define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_LEN 4 /* Saved Special Function Registers */ #define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_OFST 136 #define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_LEN 4 #define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_NUM 26
/* MC_CMD_GET_ASSERTS_OUT_V3 msgresponse: Extended response with asserted * firmware version information
*/ #define MC_CMD_GET_ASSERTS_OUT_V3_LEN 360 /* Assertion status flag. */ #define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_OFST 0 #define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_LEN 4 /* enum: No assertions have failed. */ /* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */ /* enum: A system-level assertion has failed. */ /* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */ /* enum: A thread-level assertion has failed. */ /* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */ /* enum: The system was reset by the watchdog. */ /* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */ /* enum: An illegal address trap stopped the system (huntington and later) */ /* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */ /* Failing PC value */ #define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_OFST 4 #define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_LEN 4 /* Saved GP regs */ #define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_OFST 8 #define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_LEN 4 #define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_NUM 31 /* enum: A magic value hinting that the value in this register at the time of * the failure has likely been lost.
*/ /* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */ /* Failing thread address */ #define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_OFST 132 #define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_LEN 4 #define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_OFST 136 #define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_LEN 4 /* Saved Special Function Registers */ #define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_OFST 136 #define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_LEN 4 #define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_NUM 26 /* MC firmware unique build ID (as binary SHA-1 value) */ #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_ID_OFST 240 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_ID_LEN 20 /* MC firmware build date (as Unix timestamp) */ #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_OFST 260 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LEN 8 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_OFST 260 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_OFST 264 /* MC firmware version number */ #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_OFST 268 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LEN 8 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_OFST 268 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_OFST 272 /* MC firmware security level */ #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_OFST 276 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_LEN 4 /* MC firmware extra version info (as null-terminated US-ASCII string) */ #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_EXTRA_INFO_OFST 280 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_EXTRA_INFO_LEN 16 /* MC firmware build name (as null-terminated US-ASCII string) */ #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_NAME_OFST 296 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_NAME_LEN 64
/***********************************/ /* MC_CMD_LOG_CTRL * Configure the output stream for log events such as link state changes, * sensor notifications and MCDI completions
*/ #define MC_CMD_LOG_CTRL 0x7 #undef MC_CMD_0x7_PRIVILEGE_CTG
/***********************************/ /* MC_CMD_GET_VERSION * Get version information about adapter components.
*/ #define MC_CMD_GET_VERSION 0x8 #undef MC_CMD_0x8_PRIVILEGE_CTG
/* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ #define MC_CMD_GET_VERSION_EXT_IN_LEN 4 /* placeholder, set to 0 */ #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 4
/* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 /* enum: Reserved version number to indicate "any" version. */ #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff /* enum: Bootrom version value for Siena. */ #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 /* enum: Bootrom version value for Huntington. */ #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 /* enum: Bootrom version value for Medford2. */ #define MC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb0070002
/* MC_CMD_PTP_IN msgrequest */ #define MC_CMD_PTP_IN_LEN 1 /* PTP operation code */ #define MC_CMD_PTP_IN_OP_OFST 0 #define MC_CMD_PTP_IN_OP_LEN 1 /* enum: Enable PTP packet timestamping operation. */ #define MC_CMD_PTP_OP_ENABLE 0x1 /* enum: Disable PTP packet timestamping operation. */ #define MC_CMD_PTP_OP_DISABLE 0x2 /* enum: Send a PTP packet. This operation is used on Siena and Huntington. * From Medford onwards it is not supported: on those platforms PTP transmit * timestamping is done using the fast path.
*/ #define MC_CMD_PTP_OP_TRANSMIT 0x3 /* enum: Read the current NIC time. */ #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 /* enum: Get the current PTP status. Note that the clock frequency returned (in * Hz) is rounded to the nearest MHz (e.g. 666000000 for 666666666).
*/ #define MC_CMD_PTP_OP_STATUS 0x5 /* enum: Adjust the PTP NIC's time. */ #define MC_CMD_PTP_OP_ADJUST 0x6 /* enum: Synchronize host and NIC time. */ #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 /* enum: Basic manufacturing tests. Siena PTP adapters only. */ #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 /* enum: Packet based manufacturing tests. Siena PTP adapters only. */ #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 /* enum: Reset some of the PTP related statistics */ #define MC_CMD_PTP_OP_RESET_STATS 0xa /* enum: Debug operations to MC. */ #define MC_CMD_PTP_OP_DEBUG 0xb /* enum: Read an FPGA register. Siena PTP adapters only. */ #define MC_CMD_PTP_OP_FPGAREAD 0xc /* enum: Write an FPGA register. Siena PTP adapters only. */ #define MC_CMD_PTP_OP_FPGAWRITE 0xd /* enum: Apply an offset to the NIC clock */ #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe /* enum: Change the frequency correction applied to the NIC clock */ #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf /* enum: Set the MC packet filter VLAN tags for received PTP packets. * Deprecated for Huntington onwards.
*/ #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 /* enum: Set the MC packet filter UUID for received PTP packets. Deprecated for * Huntington onwards.
*/ #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 /* enum: Set the MC packet filter Domain for received PTP packets. Deprecated * for Huntington onwards.
*/ #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 /* enum: Set the clock source. Required for snapper tests on Huntington and * Medford. Not implemented for Siena or Medford2.
*/ #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 /* enum: Reset value of Timer Reg. Not implemented. */ #define MC_CMD_PTP_OP_RST_CLK 0x14 /* enum: Enable the forwarding of PPS events to the host */ #define MC_CMD_PTP_OP_PPS_ENABLE 0x15 /* enum: Get the time format used by this NIC for PTP operations */ #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16 /* enum: Get the clock attributes. NOTE- extended version of * MC_CMD_PTP_OP_GET_TIME_FORMAT
*/ #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16 /* enum: Get corrections that should be applied to the various different * timestamps
*/ #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17 /* enum: Subscribe to receive periodic time events indicating the current NIC * time
*/ #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18 /* enum: Unsubscribe to stop receiving time events */ #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19 /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS * input on the same NIC. Siena PTP adapters only.
*/ #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a /* enum: Set the PTP sync status. Status is used by firmware to report to event * subscribers.
*/ #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b /* enum: Above this for future use. */ #define MC_CMD_PTP_OP_MAX 0x1c
/* MC_CMD_PTP_IN_ENABLE msgrequest */ #define MC_CMD_PTP_IN_ENABLE_LEN 16 #define MC_CMD_PTP_IN_CMD_OFST 0 #define MC_CMD_PTP_IN_CMD_LEN 4 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 #define MC_CMD_PTP_IN_PERIPH_ID_LEN 4 /* Not used. Events are always sent to function relative queue 0. */ #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 #define MC_CMD_PTP_IN_ENABLE_QUEUE_LEN 4 /* PTP timestamping mode. Not used from Huntington onwards. */ #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 #define MC_CMD_PTP_IN_ENABLE_MODE_LEN 4 /* enum: PTP, version 1 */ #define MC_CMD_PTP_MODE_V1 0x0 /* enum: PTP, version 1, with VLAN headers - deprecated */ #define MC_CMD_PTP_MODE_V1_VLAN 0x1 /* enum: PTP, version 2 */ #define MC_CMD_PTP_MODE_V2 0x2 /* enum: PTP, version 2, with VLAN headers - deprecated */ #define MC_CMD_PTP_MODE_V2_VLAN 0x3 /* enum: PTP, version 2, with improved UUID filtering */ #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 /* enum: FCoE (seconds and microseconds) */ #define MC_CMD_PTP_MODE_FCOE 0x5
/* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */ #define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24 /* MC_CMD_PTP_IN_CMD_OFST 0 */ /* MC_CMD_PTP_IN_CMD_LEN 4 */ /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ /* NIC - Host System Clock Synchronization status */ #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 4 /* enum: Host System clock and NIC clock are not in sync */ #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0 /* enum: Host System clock and NIC clock are synchronized */ #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1 /* If synchronized, number of seconds until clocks should be considered to be * no longer in sync.
*/ #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 4 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 4 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 4
/* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 /* Value of seconds timestamp */ #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 4 /* Timestamp major value */ #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 4 /* Value of nanoseconds timestamp */ #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 4 /* Timestamp minor value */ #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 4
/* MC_CMD_PTP_OUT_READ_NIC_TIME_V2 msgresponse */ #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_LEN 12 /* Value of seconds timestamp */ #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 0 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 4 /* Timestamp major value */ #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 0 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 4 /* Value of nanoseconds timestamp */ #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 4 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 4 /* Timestamp minor value */ #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 4 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 4 /* Upper 32bits of major timestamp value */ #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_OFST 8 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 4
/* MC_CMD_PTP_OUT_STATUS msgresponse */ #define MC_CMD_PTP_OUT_STATUS_LEN 64 /* Frequency of NIC's hardware clock */ #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 4 /* Number of packets transmitted and timestamped */ #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 4 /* Number of packets received and timestamped */ #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 4 /* Number of packets timestamped by the FPGA */ #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 4 /* Number of packets filter matched */ #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 4 /* Number of packets not filter matched */ #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 4 /* Number of PPS overflows (noise on input?) */ #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 4 /* Number of PPS bad periods */ #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 4 /* Minimum period of PPS pulse in nanoseconds */ #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 4 /* Maximum period of PPS pulse in nanoseconds */ #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 4 /* Last period of PPS pulse in nanoseconds */ #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 4 /* Mean period of PPS pulse in nanoseconds */ #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 4 /* Minimum offset of PPS pulse in nanoseconds (signed) */ #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 4 /* Maximum offset of PPS pulse in nanoseconds (signed) */ #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 4 /* Last offset of PPS pulse in nanoseconds (signed) */ #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 4 /* Mean offset of PPS pulse in nanoseconds (signed) */ #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 4
/* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX_MCDI2 1020 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_NUM(len) (((len)-0)/20) /* A set of host and NIC times */ #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM_MCDI2 51 /* Host time immediately before NIC's hardware clock read */ #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 4 /* Value of seconds timestamp */ #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 4 /* Timestamp major value */ #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 4 /* Value of nanoseconds timestamp */ #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 4 /* Timestamp minor value */ #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 4 /* Host time immediately after NIC's hardware clock read */ #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 4 /* Number of nanoseconds waited after reading NIC's hardware clock */ #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 4
/* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 /* Results of testing */ #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 4 /* enum: Successful test */ #define MC_CMD_PTP_MANF_SUCCESS 0x0 /* enum: FPGA load failed */ #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 /* enum: FPGA version invalid */ #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 /* enum: FPGA registers incorrect */ #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 /* enum: Oscillator possibly not working? */ #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 /* enum: Timestamps not increasing */ #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 /* enum: Mismatched packet count */ #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 /* enum: Mismatched packet count (Siena filter and FPGA) */ #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 /* enum: Not enough packets to perform timestamp check */ #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 /* enum: Timestamp trigger GPIO not working */ #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 /* enum: Insufficient PPS events to perform checks */ #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa /* enum: PPS time event period not sufficiently close to 1s. */ #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb /* enum: PPS time event nS reading not sufficiently close to zero. */ #define MC_CMD_PTP_MANF_PPS_NS 0xc /* enum: PTP peripheral registers incorrect */ #define MC_CMD_PTP_MANF_REGISTERS 0xd /* enum: Failed to read time from PTP peripheral */ #define MC_CMD_PTP_MANF_CLOCK_READ 0xe /* Presence of external oscillator */ #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 4
/* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 /* Results of testing */ #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 4 /* Number of packets received by FPGA */ #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 4 /* Number of packets received by Siena filters */ #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 4
/* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */ #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4 /* Time format required/used by for this NIC. Applies to all PTP MCDI * operations that pass times between the host and firmware. If this operation * is not supported (older firmware) a format of seconds and nanoseconds should * be assumed. Note this enum is deprecated. Do not add to it- use the * TIME_FORMAT field in MC_CMD_PTP_OUT_GET_ATTRIBUTES instead.
*/ #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 4 /* enum: Times are in seconds and nanoseconds */ #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1 /* enum: Major register has units of seconds, minor 2^-27s per tick */ #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2
/* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */ #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24 /* Time format required/used by for this NIC. Applies to all PTP MCDI * operations that pass times between the host and firmware. If this operation * is not supported (older firmware) a format of seconds and nanoseconds should * be assumed.
*/ #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 4 /* enum: Times are in seconds and nanoseconds */ #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1 /* enum: Major register has units of seconds, minor 2^-27s per tick */ #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2 /* enum: Major register units are seconds, minor units are quarter nanoseconds
*/ #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x3 /* Minimum acceptable value for a corrected synchronization timeset. When * comparing host and NIC clock times, the MC returns a set of samples that * contain the host start and end time, the MC time when the host start was * detected and the time the MC waited between reading the time and detecting * the host end. The corrected sync window is the difference between the host * end and start times minus the time that the MC waited for host end.
*/ #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 4 /* Various PTP capabilities */ #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_OFST 8 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_OFST 8 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_OFST 8 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_LBN 2 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_WIDTH 1 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_OFST 8 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_LBN 3 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_WIDTH 1 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 4 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 4 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 4
/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 4 /* Uncorrected error on PTP receive timestamps in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 4 /* Uncorrected error on PPS output in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 4 /* Uncorrected error on PPS input in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 4
/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 4 /* Uncorrected error on PTP receive timestamps in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 4 /* Uncorrected error on PPS output in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 4 /* Uncorrected error on PPS input in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 4 /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 4 /* Uncorrected error on non-PTP receive timestamps in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 4
/***********************************/ /* MC_CMD_HP * These commands are used for HP related features. They are grouped under one * MCDI command to avoid creating too many MCDI commands.
*/ #define MC_CMD_HP 0x54 #undef MC_CMD_0x54_PRIVILEGE_CTG
#define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN
/* MC_CMD_HP_IN msgrequest */ #define MC_CMD_HP_IN_LEN 16 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at * the specified address with the specified interval.When address is NULL, * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current * state / 2: (debug) Show temperature reported by one of the supported * sensors.
*/ #define MC_CMD_HP_IN_SUBCMD_OFST 0 #define MC_CMD_HP_IN_SUBCMD_LEN 4 /* enum: OCSD (Option Card Sensor Data) sub-command. */ #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 /* enum: Last known valid HP sub-command. */ #define MC_CMD_HP_IN_LAST_SUBCMD 0x0 /* The address to the array of sensor fields. (Or NULL to use a sub-command.)
*/ #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 /* The requested update interval, in seconds. (Or the sub-command if ADDR is * NULL.)
*/ #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 #define MC_CMD_HP_IN_OCSD_INTERVAL_LEN 4
/* MC_CMD_HP_OUT msgresponse */ #define MC_CMD_HP_OUT_LEN 4 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 #define MC_CMD_HP_OUT_OCSD_STATUS_LEN 4 /* enum: OCSD stopped for this card. */ #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 /* enum: OCSD was successfully started with the address provided. */ #define MC_CMD_HP_OUT_OCSD_STARTED 0x2 /* enum: OCSD was already started for this card. */ #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3
/* MC_CMD_MDIO_READ_IN msgrequest */ #define MC_CMD_MDIO_READ_IN_LEN 16 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for * external devices.
*/ #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 #define MC_CMD_MDIO_READ_IN_BUS_LEN 4 /* enum: Internal. */ #define MC_CMD_MDIO_BUS_INTERNAL 0x0 /* enum: External. */ #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 /* Port address */ #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 #define MC_CMD_MDIO_READ_IN_PRTAD_LEN 4 /* Device Address or clause 22. */ #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 #define MC_CMD_MDIO_READ_IN_DEVAD_LEN 4 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
*/ #define MC_CMD_MDIO_CLAUSE22 0x20 /* Address */ #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 #define MC_CMD_MDIO_READ_IN_ADDR_LEN 4
/* MC_CMD_MDIO_READ_OUT msgresponse */ #define MC_CMD_MDIO_READ_OUT_LEN 8 /* Value */ #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 #define MC_CMD_MDIO_READ_OUT_VALUE_LEN 4 /* Status the MDIO commands return the raw status bits from the MDIO block. A * "good" transaction should have the DONE bit set and all other bits clear.
*/ #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 #define MC_CMD_MDIO_READ_OUT_STATUS_LEN 4 /* enum: Good. */ #define MC_CMD_MDIO_STATUS_GOOD 0x8
/* MC_CMD_MDIO_WRITE_IN msgrequest */ #define MC_CMD_MDIO_WRITE_IN_LEN 20 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for * external devices.
*/ #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 #define MC_CMD_MDIO_WRITE_IN_BUS_LEN 4 /* enum: Internal. */ /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ /* enum: External. */ /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ /* Port address */ #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 #define MC_CMD_MDIO_WRITE_IN_PRTAD_LEN 4 /* Device Address or clause 22. */ #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 #define MC_CMD_MDIO_WRITE_IN_DEVAD_LEN 4 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
*/ /* MC_CMD_MDIO_CLAUSE22 0x20 */ /* Address */ #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 #define MC_CMD_MDIO_WRITE_IN_ADDR_LEN 4 /* Value */ #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 #define MC_CMD_MDIO_WRITE_IN_VALUE_LEN 4
/* MC_CMD_MDIO_WRITE_OUT msgresponse */ #define MC_CMD_MDIO_WRITE_OUT_LEN 4 /* Status; the MDIO commands return the raw status bits from the MDIO block. A * "good" transaction should have the DONE bit set and all other bits clear.
*/ #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 #define MC_CMD_MDIO_WRITE_OUT_STATUS_LEN 4 /* enum: Good. */ /* MC_CMD_MDIO_STATUS_GOOD 0x8 */
/***********************************/ /* MC_CMD_PORT_READ32 * Read a 32-bit register from the indirect port register map. The port to * access is implied by the Shared memory channel used.
*/ #define MC_CMD_PORT_READ32 0x14
/***********************************/ /* MC_CMD_PORT_WRITE32 * Write a 32-bit register to the indirect port register map. The port to * access is implied by the Shared memory channel used.
*/ #define MC_CMD_PORT_WRITE32 0x15
/***********************************/ /* MC_CMD_PORT_READ128 * Read a 128-bit register from the indirect port register map. The port to * access is implied by the Shared memory channel used.
*/ #define MC_CMD_PORT_READ128 0x16
/***********************************/ /* MC_CMD_PORT_WRITE128 * Write a 128-bit register to the indirect port register map. The port to * access is implied by the Shared memory channel used.
*/ #define MC_CMD_PORT_WRITE128 0x17
/* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX_MCDI2 136 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_NUM(len) (((len)-72)/2) #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 /* Capabilities for Siena Port0 (see struct MC_CMD_CAPABILITIES). Unused on * EF10 and later (use MC_CMD_GET_CAPABILITIES).
*/ #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4 /* Capabilities for Siena Port1 (see struct MC_CMD_CAPABILITIES). Unused on * EF10 and later (use MC_CMD_GET_CAPABILITIES).
*/ #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4 /* Base MAC address for Siena Port0. Unused on EF10 and later (use * MC_CMD_GET_MAC_ADDRESSES).
*/ #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 /* Base MAC address for Siena Port1. Unused on EF10 and later (use * MC_CMD_GET_MAC_ADDRESSES).
*/ #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 /* Size of MAC address pool for Siena Port0. Unused on EF10 and later (use * MC_CMD_GET_MAC_ADDRESSES).
*/ #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4 /* Size of MAC address pool for Siena Port1. Unused on EF10 and later (use * MC_CMD_GET_MAC_ADDRESSES).
*/ #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4 /* Increment between addresses in MAC address pool for Siena Port0. Unused on * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).
*/ #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4 /* Increment between addresses in MAC address pool for Siena Port1. Unused on * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).
*/ #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4 /* Siena only. This field contains a 16-bit value for each of the types of * NVRAM area. The values are defined in the firmware/mc/platform/.c file for a * specific board type, but otherwise have no meaning to the MC; they are used * by the driver to manage selection of appropriate firmware updates. Unused on * EF10 and later (use MC_CMD_NVRAM_METADATA).
*/ #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM_MCDI2 32
/***********************************/ /* MC_CMD_SET_RAND_SEED * Set the 16byte seed for the MC pseudo-random generator.
*/ #define MC_CMD_SET_RAND_SEED 0x1a #undef MC_CMD_0x1a_PRIVILEGE_CTG
/***********************************/ /* MC_CMD_LTSSM_HIST * Retrieve the history of the LTSSM, if the build supports it.
*/ #define MC_CMD_LTSSM_HIST 0x1b
/* MC_CMD_LTSSM_HIST_OUT msgresponse */ #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 #define MC_CMD_LTSSM_HIST_OUT_LENMAX_MCDI2 1020 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) #define MC_CMD_LTSSM_HIST_OUT_DATA_NUM(len) (((len)-0)/4) /* variable number of LTSSM values, as bytes. The history is read-to-clear. */ #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM_MCDI2 255
/***********************************/ /* MC_CMD_DRV_ATTACH * Inform MCPU that this port is managed on the host (i.e. driver active). For * Huntington, also request the preferred datapath firmware to use if possible * (it may not be possible for this request to be fulfilled; the driver must * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which * features are actually available). The FIRMWARE_ID field is ignored by older * platforms.
*/ #define MC_CMD_DRV_ATTACH 0x1c #undef MC_CMD_0x1c_PRIVILEGE_CTG
/* MC_CMD_DRV_ATTACH_IN msgrequest */ #define MC_CMD_DRV_ATTACH_IN_LEN 12 /* new state to set if UPDATE=1 */ #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4 #define MC_CMD_DRV_ATTACH_OFST 0 #define MC_CMD_DRV_ATTACH_LBN 0 #define MC_CMD_DRV_ATTACH_WIDTH 1 #define MC_CMD_DRV_ATTACH_IN_ATTACH_OFST 0 #define MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 0 #define MC_CMD_DRV_ATTACH_IN_ATTACH_WIDTH 1 #define MC_CMD_DRV_PREBOOT_OFST 0 #define MC_CMD_DRV_PREBOOT_LBN 1 #define MC_CMD_DRV_PREBOOT_WIDTH 1 #define MC_CMD_DRV_ATTACH_IN_PREBOOT_OFST 0 #define MC_CMD_DRV_ATTACH_IN_PREBOOT_LBN 1 #define MC_CMD_DRV_ATTACH_IN_PREBOOT_WIDTH 1 #define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_OFST 0 #define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_LBN 2 #define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_WIDTH 1 #define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_OFST 0 #define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_LBN 3 #define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_WIDTH 1 #define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_OFST 0 #define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_LBN 4 #define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_WIDTH 1 #define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_OFST 0 #define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_LBN 5 #define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1 #define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_OFST 0 #define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_LBN 5 #define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_WIDTH 1 /* 1 to set new state, or 0 to just report the existing state */ #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 #define MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4 /* preferred datapath firmware (for Huntington; ignored for Siena) */ #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 4 /* enum: Prefer to use full featured firmware */ #define MC_CMD_FW_FULL_FEATURED 0x0 /* enum: Prefer to use firmware with fewer features but lower latency */ #define MC_CMD_FW_LOW_LATENCY 0x1 /* enum: Prefer to use firmware for SolarCapture packed stream mode */ #define MC_CMD_FW_PACKED_STREAM 0x2 /* enum: Prefer to use firmware with fewer features and simpler TX event * batching but higher TX packet rate
*/ #define MC_CMD_FW_HIGH_TX_RATE 0x3 /* enum: Reserved value */ #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 /* enum: Prefer to use firmware with additional "rules engine" filtering * support
*/ #define MC_CMD_FW_RULES_ENGINE 0x5 /* enum: Prefer to use firmware with additional DPDK support */ #define MC_CMD_FW_DPDK 0x6 /* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and * bug69716)
*/ #define MC_CMD_FW_L3XUDP 0x7 /* enum: Requests that the MC keep whatever datapath firmware is currently * running. It's used for test purposes, where we want to be able to shmboot * special test firmware variants. This option is only recognised in eftest * (i.e. non-production) builds.
*/ #define MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe /* enum: Only this option is allowed for non-admin functions */ #define MC_CMD_FW_DONT_CARE 0xffffffff
/* MC_CMD_DRV_ATTACH_IN_V2 msgrequest: Updated DRV_ATTACH to include driver * version
*/ #define MC_CMD_DRV_ATTACH_IN_V2_LEN 32 /* new state to set if UPDATE=1 */ #define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_OFST 0 #define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_LEN 4 /* MC_CMD_DRV_ATTACH_OFST 0 */ /* MC_CMD_DRV_ATTACH_LBN 0 */ /* MC_CMD_DRV_ATTACH_WIDTH 1 */ #define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_OFST 0 #define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_LBN 0 #define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_WIDTH 1 /* MC_CMD_DRV_PREBOOT_OFST 0 */ /* MC_CMD_DRV_PREBOOT_LBN 1 */ /* MC_CMD_DRV_PREBOOT_WIDTH 1 */ #define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_OFST 0 #define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_LBN 1 #define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_WIDTH 1 #define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_OFST 0 #define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_LBN 2 #define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_WIDTH 1 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_OFST 0 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_LBN 3 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_WIDTH 1 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_OFST 0 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_LBN 4 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_WIDTH 1 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_OFST 0 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_LBN 5 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_OFST 0 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_LBN 5 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_WIDTH 1 /* 1 to set new state, or 0 to just report the existing state */ #define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_OFST 4 #define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_LEN 4 /* preferred datapath firmware (for Huntington; ignored for Siena) */ #define MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_OFST 8 #define MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_LEN 4 /* enum: Prefer to use full featured firmware */ /* MC_CMD_FW_FULL_FEATURED 0x0 */ /* enum: Prefer to use firmware with fewer features but lower latency */ /* MC_CMD_FW_LOW_LATENCY 0x1 */ /* enum: Prefer to use firmware for SolarCapture packed stream mode */ /* MC_CMD_FW_PACKED_STREAM 0x2 */ /* enum: Prefer to use firmware with fewer features and simpler TX event * batching but higher TX packet rate
*/ /* MC_CMD_FW_HIGH_TX_RATE 0x3 */ /* enum: Reserved value */ /* MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 */ /* enum: Prefer to use firmware with additional "rules engine" filtering * support
*/ /* MC_CMD_FW_RULES_ENGINE 0x5 */ /* enum: Prefer to use firmware with additional DPDK support */ /* MC_CMD_FW_DPDK 0x6 */ /* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and * bug69716)
*/ /* MC_CMD_FW_L3XUDP 0x7 */ /* enum: Requests that the MC keep whatever datapath firmware is currently * running. It's used for test purposes, where we want to be able to shmboot * special test firmware variants. This option is only recognised in eftest * (i.e. non-production) builds.
*/ /* MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe */ /* enum: Only this option is allowed for non-admin functions */ /* MC_CMD_FW_DONT_CARE 0xffffffff */ /* Version of the driver to be reported by management protocols (e.g. NC-SI) * handled by the NIC. This is a zero-terminated ASCII string.
*/ #define MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_OFST 12 #define MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_LEN 20
/* MC_CMD_DRV_ATTACH_OUT msgresponse */ #define MC_CMD_DRV_ATTACH_OUT_LEN 4 /* previous or existing state, see the bitmask at NEW_STATE */ #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 4
/* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 /* previous or existing state, see the bitmask at NEW_STATE */ #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 4 /* Flags associated with this function */ #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 4 /* enum: Labels the lowest-numbered function visible to the OS */ #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 /* enum: The function can control the link state of the physical port it is * bound to.
*/ #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 /* enum: The function can perform privileged operations */ #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 /* enum: The function does not have an active port associated with it. The port * refers to the Sorrento external FPGA port.
*/ #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3 /* enum: If set, indicates that VI spreading is currently enabled. Will always * indicate the current state, regardless of the value in the WANT_VI_SPREADING * input.
*/ #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x4 /* enum: Used during development only. Should no longer be used. */ #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_RX_VI_SPREADING_INHIBITED 0x5 /* enum: If set, indicates that TX only spreading is enabled. Even-numbered * TXQs will use one engine, and odd-numbered TXQs will use the other. This * also has the effect that only even-numbered RXQs will receive traffic.
*/ #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TX_ONLY_VI_SPREADING_ENABLED 0x5
/***********************************/ /* MC_CMD_SHMUART * Route UART output to circular buffer in shared memory instead.
*/ #define MC_CMD_SHMUART 0x1f
/***********************************/ /* MC_CMD_ENTITY_RESET * Generic per-resource reset. There is no equivalent for per-board reset. * Locks required: None; Return code: 0, ETIME. NOTE: This command is an * extended version of the deprecated MC_CMD_PORT_RESET with added fields.
*/ #define MC_CMD_ENTITY_RESET 0x20 /* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */
/***********************************/ /* MC_CMD_PUTS * Copy the given ASCII string out onto UART and/or out of the network port.
*/ #define MC_CMD_PUTS 0x23 #undef MC_CMD_0x23_PRIVILEGE_CTG
/***********************************/ /* MC_CMD_GET_PHY_CFG * Report PHY configuration. This guarantees to succeed even if the PHY is in a * 'zombie' state. Locks required: None
*/ #define MC_CMD_GET_PHY_CFG 0x24 #undef MC_CMD_0x24_PRIVILEGE_CTG
/***********************************/ /* MC_CMD_START_BIST * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
*/ #define MC_CMD_START_BIST 0x25 #undef MC_CMD_0x25_PRIVILEGE_CTG
#define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN
/* MC_CMD_START_BIST_IN msgrequest */ #define MC_CMD_START_BIST_IN_LEN 4 /* Type of test. */ #define MC_CMD_START_BIST_IN_TYPE_OFST 0 #define MC_CMD_START_BIST_IN_TYPE_LEN 4 /* enum: Run the PHY's short cable BIST. */ #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 /* enum: Run the PHY's long cable BIST. */ #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ #define MC_CMD_BPX_SERDES_BIST 0x3 /* enum: Run the MC loopback tests. */ #define MC_CMD_MC_LOOPBACK_BIST 0x4 /* enum: Run the PHY's standard BIST. */ #define MC_CMD_PHY_BIST 0x5 /* enum: Run MC RAM test. */ #define MC_CMD_MC_MEM_BIST 0x6 /* enum: Run Port RAM test. */ #define MC_CMD_PORT_MEM_BIST 0x7 /* enum: Run register test. */ #define MC_CMD_REG_BIST 0x8
/***********************************/ /* MC_CMD_POLL_BIST * Poll for BIST completion. Returns a single status code, and optionally some * PHY specific bist output. The driver should only consume the BIST output * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't * successfully parse the BIST output, it should still respect the pass/Fail in * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, * EACCES (if PHY_LOCK is not held).
*/ #define MC_CMD_POLL_BIST 0x26 #undef MC_CMD_0x26_PRIVILEGE_CTG
/***********************************/ /* MC_CMD_FLUSH_RX_QUEUES * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ * flushes should be initiated via this MCDI operation, rather than via * directly writing FLUSH_CMD. * * The flush is completed (either done/fail) asynchronously (after this command * returns). The driver must still wait for flush done/failure events as usual.
*/ #define MC_CMD_FLUSH_RX_QUEUES 0x27
/***********************************/ /* MC_CMD_GET_LOOPBACK_MODES * Returns a bitmask of loopback modes available at each speed.
*/ #define MC_CMD_GET_LOOPBACK_MODES 0x28 #undef MC_CMD_0x28_PRIVILEGE_CTG
/* MC_CMD_SET_MAC_V2_OUT msgresponse */ #define MC_CMD_SET_MAC_V2_OUT_LEN 4 /* MTU as configured after processing the request. See comment at * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL * to 0.
*/ #define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0 #define MC_CMD_SET_MAC_V2_OUT_MTU_LEN 4
/***********************************/ /* MC_CMD_PHY_STATS * Get generic PHY statistics. This call returns the statistics for a generic * PHY in a sparse array (indexed by the enumerate). Each value is represented * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the * statistics may be read from the message response. If DMA_ADDR != 0, then the * statistics are dmad to that (page-aligned location). Locks required: None. * Returns: 0, ETIME
*/ #define MC_CMD_PHY_STATS 0x2d #undef MC_CMD_0x2d_PRIVILEGE_CTG
/***********************************/ /* MC_CMD_MAC_STATS * Get generic MAC statistics. This call returns unified statistics maintained * by the MC as it switches between the GMAC and XMAC. The MC will write out * all supported stats. The driver should zero initialise the buffer to * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is * performed, and the statistics may be read from the message response. If * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). * Locks required: None. The PERIODIC_CLEAR option is not used and now has no * effect. Returns: 0, ETIME
*/ #define MC_CMD_MAC_STATS 0x2e #undef MC_CMD_0x2e_PRIVILEGE_CTG
/* MC_CMD_MAC_STATS_V2_OUT_NO_DMA msgresponse */ #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V2*64))>>3) #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LEN 8 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2 /* enum: Start of FEC stats buffer space, Medford2 and up */ #define MC_CMD_MAC_FEC_DMABUF_START 0x61 /* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2)
*/ #define MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61 /* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2)
*/ #define MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62 /* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */ #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63 /* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */ #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64 /* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */ #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65 /* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */ #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66 /* enum: This includes the space at offset 103 which is the final * GENERATION_END in a MAC_STATS_V2 response and otherwise unused.
*/ #define MC_CMD_MAC_NSTATS_V2 0x68 /* Other enum values, see field(s): */ /* MC_CMD_MAC_STATS_OUT_NO_DMA/STATISTICS */
/* MC_CMD_MAC_STATS_V3_OUT_NO_DMA msgresponse */ #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V3*64))>>3) #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 0 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LEN 8 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 0 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V3 /* enum: Start of CTPIO stats buffer space, Medford2 and up */ #define MC_CMD_MAC_CTPIO_DMABUF_START 0x68 /* enum: Number of CTPIO fallbacks because a DMA packet was in progress on the * target VI
*/ #define MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x68 /* enum: Number of times a CTPIO send wrote beyond frame end (informational * only)
*/ #define MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x69 /* enum: Number of CTPIO failures because the TX doorbell was written before * the end of the frame data
*/ #define MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a /* enum: Number of CTPIO failures because the internal FIFO overflowed */ #define MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b /* enum: Number of CTPIO failures because the host did not deliver data fast * enough to avoid MAC underflow
*/ #define MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c /* enum: Number of CTPIO failures because the host did not deliver all the * frame data within the timeout
*/ #define MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d /* enum: Number of CTPIO failures because the frame data arrived out of order * or with gaps
*/ #define MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e /* enum: Number of CTPIO failures because the host started a new frame before * completing the previous one
*/ #define MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f /* enum: Number of CTPIO failures because a write was not a multiple of 32 bits * or not 32-bit aligned
*/ #define MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x70 /* enum: Number of CTPIO fallbacks because another VI on the same port was * sending a CTPIO frame
*/ #define MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x71 /* enum: Number of CTPIO fallbacks because target VI did not have CTPIO enabled
*/ #define MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x72 /* enum: Number of CTPIO fallbacks because length in header was less than 29 * bytes
*/ #define MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x73 /* enum: Total number of successful CTPIO sends on this port */ #define MC_CMD_MAC_CTPIO_SUCCESS 0x74 /* enum: Total number of CTPIO fallbacks on this port */ #define MC_CMD_MAC_CTPIO_FALLBACK 0x75 /* enum: Total number of CTPIO poisoned frames on this port, whether erased or * not
*/ #define MC_CMD_MAC_CTPIO_POISON 0x76 /* enum: Total number of CTPIO erased frames on this port */ #define MC_CMD_MAC_CTPIO_ERASE 0x77 /* enum: This includes the space at offset 120 which is the final * GENERATION_END in a MAC_STATS_V3 response and otherwise unused.
*/ #define MC_CMD_MAC_NSTATS_V3 0x79 /* Other enum values, see field(s): */ /* MC_CMD_MAC_STATS_V2_OUT_NO_DMA/STATISTICS */
/* MC_CMD_MAC_STATS_V4_OUT_NO_DMA msgresponse */ #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V4*64))>>3) #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_OFST 0 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LEN 8 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_OFST 0 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_OFST 4 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V4 /* enum: Start of V4 stats buffer space */ #define MC_CMD_MAC_V4_DMABUF_START 0x79 /* enum: RXDP counter: Number of packets truncated because scattering was * disabled.
*/ #define MC_CMD_MAC_RXDP_SCATTER_DISABLED_TRUNC 0x79 /* enum: RXDP counter: Number of times the RXDP head of line blocked waiting * for descriptors. Will be zero unless RXDP_HLB_IDLE capability is set.
*/ #define MC_CMD_MAC_RXDP_HLB_IDLE 0x7a /* enum: RXDP counter: Number of times the RXDP timed out while head of line * blocking. Will be zero unless RXDP_HLB_IDLE capability is set.
*/ #define MC_CMD_MAC_RXDP_HLB_TIMEOUT 0x7b /* enum: This includes the space at offset 124 which is the final * GENERATION_END in a MAC_STATS_V4 response and otherwise unused.
*/ #define MC_CMD_MAC_NSTATS_V4 0x7d /* Other enum values, see field(s): */ /* MC_CMD_MAC_STATS_V3_OUT_NO_DMA/STATISTICS */
/***********************************/ /* MC_CMD_SRIOV * to be documented
*/ #define MC_CMD_SRIOV 0x30
/***********************************/ /* MC_CMD_MEMCPY * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data * embedded directly in the command. * * A common pattern is for a client to use generation counts to signal a dma * update of a datastructure. To facilitate this, this MCDI operation can * contain multiple requests which are executed in strict order. Requests take * the form of duplicating the entire MCDI request continuously (including the * requests record, which is ignored in all but the first structure) * * The source data can either come from a DMA from the host, or it can be * embedded within the request directly, thereby eliminating a DMA read. To * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and * ADDR_LO=offset, and inserts the data at %offset from the start of the * payload. It's the callers responsibility to ensure that the embedded data * doesn't overlap the records. * * Returns: 0, EINVAL (invalid RID)
*/ #define MC_CMD_MEMCPY 0x31
/***********************************/ /* MC_CMD_WOL_FILTER_SET * Set a WoL filter.
*/ #define MC_CMD_WOL_FILTER_SET 0x32 #undef MC_CMD_0x32_PRIVILEGE_CTG
#define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK
/* MC_CMD_WOL_FILTER_SET_IN msgrequest */ #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ /* A type value of 1 is unused. */ #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 /* enum: Magic */ #define MC_CMD_WOL_TYPE_MAGIC 0x0 /* enum: MS Windows Magic */ #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 /* enum: IPv4 Syn */ #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 /* enum: IPv6 Syn */ #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 /* enum: Bitmap */ #define MC_CMD_WOL_TYPE_BITMAP 0x5 /* enum: Link */ #define MC_CMD_WOL_TYPE_LINK 0x6 /* enum: (Above this for future use) */ #define MC_CMD_WOL_TYPE_MAX 0x7 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46
/***********************************/ /* MC_CMD_SET_MCAST_HASH * Set the MCAST hash value without otherwise reconfiguring the MAC
*/ #define MC_CMD_SET_MCAST_HASH 0x35
/***********************************/ /* MC_CMD_NVRAM_UPDATE_START * Start a group of update operations on a virtual NVRAM partition. Locks * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if * PHY_LOCK required and not held). In an adapter bound to a TSA controller, * MC_CMD_NVRAM_UPDATE_START can only be used on a subset of partition types * i.e. static config, dynamic config and expansion ROM config. Attempting to * perform this operation on a restricted partition will return the error * EPERM.
*/ #define MC_CMD_NVRAM_UPDATE_START 0x38 #undef MC_CMD_0x38_PRIVILEGE_CTG
#define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN
/* MC_CMD_NVRAM_UPDATE_START_IN msgrequest: Legacy NVRAM_UPDATE_START request. * Use NVRAM_UPDATE_START_V2_IN in new code
*/ #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 4 /* Enum values, see field(s): */ /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
/* MC_CMD_NVRAM_UPDATE_START_V2_IN msgrequest: Extended NVRAM_UPDATE_START * request with additional flags indicating version of command in use. See * MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended functionality. Use * paired up with NVRAM_UPDATE_FINISH_V2_IN.
*/ #define MC_CMD_NVRAM_UPDATE_START_V2_IN_LEN 8 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 4 /* Enum values, see field(s): */ /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 4 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
/* MC_CMD_NVRAM_READ_IN_V2 msgrequest */ #define MC_CMD_NVRAM_READ_IN_V2_LEN 16 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 4 /* Enum values, see field(s): */ /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 4 /* amount to read in bytes */ #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 4 /* Optional control info. If a partition is stored with an A/B versioning * scheme (i.e. in more than one physical partition in NVRAM) the host can set * this to control which underlying physical partition is used to read data * from. This allows it to perform a read-modify-write-verify with the write * lock continuously held by calling NVRAM_UPDATE_START, reading the old * contents using MODE=TARGET_CURRENT, overwriting the old partition and then * verifying by reading with MODE=TARGET_BACKUP.
*/ #define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12 #define MC_CMD_NVRAM_READ_IN_V2_MODE_LEN 4 /* enum: Same as omitting MODE: caller sees data in current partition unless it * holds the write lock in which case it sees data in the partition it is * updating.
*/ #define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0 /* enum: Read from the current partition of an A/B pair, even if holding the * write lock.
*/ #define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B * pair
*/ #define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2
/***********************************/ /* MC_CMD_NVRAM_UPDATE_FINISH * Finish a group of update operations on a virtual NVRAM partition. Locks * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type/offset/ * length), EACCES (if PHY_LOCK required and not held). In an adapter bound to * a TSA controller, MC_CMD_NVRAM_UPDATE_FINISH can only be used on a subset of * partition types i.e. static config, dynamic config and expansion ROM config. * Attempting to perform this operation on a restricted partition will return * the error EPERM.
*/ #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c #undef MC_CMD_0x3c_PRIVILEGE_CTG
#define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
/* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest: Legacy NVRAM_UPDATE_FINISH * request. Use NVRAM_UPDATE_FINISH_V2_IN in new code
*/ #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 4 /* Enum values, see field(s): */ /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 4
/* MC_CMD_NVRAM_UPDATE_FINISH_V2_IN msgrequest: Extended NVRAM_UPDATE_FINISH * request with additional flags indicating version of NVRAM_UPDATE commands in * use. See MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended * functionality. Use paired up with NVRAM_UPDATE_START_V2_IN.
*/ #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN 12 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 4 /* Enum values, see field(s): */ /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 8 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 8 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_OFST 8 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_LBN 1 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_WIDTH 1 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_OFST 8 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_LBN 2 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_WIDTH 1
/* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code
*/ #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0
/* MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT msgresponse: * * Extended NVRAM_UPDATE_FINISH response that communicates the result of secure * firmware validation where applicable back to the host. * * Medford only: For signed firmware images, such as those for medford, the MC * firmware verifies the signature before marking the firmware image as valid. * This process takes a few seconds to complete. So is likely to take more than * the MCDI timeout. Hence signature verification is initiated when * MC_CMD_NVRAM_UPDATE_FINISH_V2_IN is received by the firmware, however, the * MCDI command is run in a background MCDI processing thread. This response * payload includes the results of the signature verification. Note that the * per-partition nvram lock in firmware is only released after the verification * has completed.
*/ #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4 /* Result of nvram update completion processing. Result codes that indicate an * internal build failure and therefore not expected to be seen by customers in * the field are marked with a prefix 'Internal-error'.
*/ #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4 /* enum: Invalid return code; only non-zero values are defined. Defined as * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT.
*/ #define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0 /* enum: Verify succeeded without any errors. */ #define MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1 /* enum: CMS format verification failed due to an internal error. */ #define MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2 /* enum: Invalid CMS format in image metadata. */ #define MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3 /* enum: Message digest verification failed due to an internal error. */ #define MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4 /* enum: Error in message digest calculated over the reflash-header, payload * and reflash-trailer.
*/ #define MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5 /* enum: Signature verification failed due to an internal error. */ #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6 /* enum: There are no valid signatures in the image. */ #define MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7 /* enum: Trusted approvers verification failed due to an internal error. */ #define MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8 /* enum: The Trusted approver's list is empty. */ #define MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9 /* enum: Signature chain verification failed due to an internal error. */ #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa /* enum: The signers of the signatures in the image are not listed in the * Trusted approver's list.
*/ #define MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb /* enum: The image contains a test-signed certificate, but the adapter accepts * only production signed images.
*/ #define MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc /* enum: The image has a lower security level than the current firmware. */ #define MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd /* enum: Internal-error. The signed image is missing the 'contents' section, * where the 'contents' section holds the actual image payload to be applied.
*/ #define MC_CMD_NVRAM_VERIFY_RC_CONTENT_NOT_FOUND 0xe /* enum: Internal-error. The bundle header is invalid. */ #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_CONTENT_HEADER_INVALID 0xf /* enum: Internal-error. The bundle does not have a valid reflash image layout.
*/ #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_REFLASH_IMAGE_INVALID 0x10 /* enum: Internal-error. The bundle has an inconsistent layout of components or * incorrect checksum.
*/ #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_IMAGE_LAYOUT_INVALID 0x11 /* enum: Internal-error. The bundle manifest is inconsistent with components in * the bundle.
*/ #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_INVALID 0x12 /* enum: Internal-error. The number of components in a bundle do not match the * number of components advertised by the bundle manifest.
*/ #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_NUM_COMPONENTS_MISMATCH 0x13 /* enum: Internal-error. The bundle contains too many components for the MC * firmware to process
*/ #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_TOO_MANY_COMPONENTS 0x14 /* enum: Internal-error. The bundle manifest has an invalid/inconsistent * component.
*/ #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_INVALID 0x15 /* enum: Internal-error. The hash of a component does not match the hash stored * in the bundle manifest.
*/ #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_MISMATCH 0x16 /* enum: Internal-error. Component hash calculation failed. */ #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_FAILED 0x17 /* enum: Internal-error. The component does not have a valid reflash image * layout.
*/ #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_REFLASH_IMAGE_INVALID 0x18 /* enum: The bundle processing code failed to copy a component to its target * partition.
*/ #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_COPY_FAILED 0x19 /* enum: The update operation is in-progress. */ #define MC_CMD_NVRAM_VERIFY_RC_PENDING 0x1a
/***********************************/ /* MC_CMD_REBOOT * Reboot the MC. * * The AFTER_ASSERTION flag is intended to be used when the driver notices an * assertion failure (at which point it is expected to perform a complete tear * down and reinitialise), to allow both ports to reset the MC once in an * atomic fashion. * * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, * which means that they will automatically reboot out of the assertion * handler, so this is in practise an optional operation. It is still * recommended that drivers execute this to support custom firmwares with * REBOOT_ON_ASSERT=0. * * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, * DATALEN=0
*/ #define MC_CMD_REBOOT 0x3d #undef MC_CMD_0x3d_PRIVILEGE_CTG
/***********************************/ /* MC_CMD_SCHEDINFO * Request scheduler info. Locks required: NONE. Returns: An array of * (timeslice,maximum overrun), one for each thread, in ascending order of * thread address.
*/ #define MC_CMD_SCHEDINFO 0x3e #undef MC_CMD_0x3e_PRIVILEGE_CTG
/***********************************/ /* MC_CMD_REBOOT_MODE * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot * mode to the specified value. Returns the old mode.
*/ #define MC_CMD_REBOOT_MODE 0x3f #undef MC_CMD_0x3f_PRIVILEGE_CTG
/***********************************/ /* MC_CMD_SENSOR_INFO * Returns information about every available sensor. * * Each sensor has a single (16bit) value, and a corresponding state. The * mapping between value and state is nominally determined by the MC, but may * be implemented using up to 2 ranges per sensor. * * This call returns a mask (32bit) of the sensors that are supported by this * platform, then an array of sensor information structures, in order of sensor * type (but without gaps for unimplemented sensors). Each structure defines * the ranges for the corresponding sensor. An unused range is indicated by * equal limit values. If one range is used, a value outside that range results * in STATE_FATAL. If two ranges are used, a value outside the second range * results in STATE_FATAL while a value outside the first and inside the second * range results in STATE_WARNING. * * Sensor masks and sensor information arrays are organised into pages. For * backward compatibility, older host software can only use sensors in page 0. * Bit 32 in the sensor mask was previously unused, and is no reserved for use * as the next page flag. * * If the request does not contain a PAGE value then firmware will only return * page 0 of sensor information, with bit 31 in the sensor mask cleared. * * If the request contains a PAGE value then firmware responds with the sensor * mask and sensor information array for that page of sensors. In this case bit * 31 in the mask is set if another page exists. * * Locks required: None Returns: 0
*/ #define MC_CMD_SENSOR_INFO 0x41 #undef MC_CMD_0x41_PRIVILEGE_CTG
/* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 /* Which page of sensors to report. * * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). * * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
*/ #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 4
/* MC_CMD_SENSOR_INFO_EXT_IN_V2 msgrequest */ #define MC_CMD_SENSOR_INFO_EXT_IN_V2_LEN 8 /* Which page of sensors to report. * * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). * * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
*/ #define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_OFST 0 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_LEN 4 /* Flags controlling information retrieved */ #define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_OFST 4 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_LEN 4 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_OFST 4 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_LBN 0 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_WIDTH 1
/* MC_CMD_SENSOR_INFO_OUT msgresponse */ #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 #define MC_CMD_SENSOR_INFO_OUT_LENMAX_MCDI2 1020 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) #define MC_CMD_SENSOR_INFO_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8) #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 #define MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4 /* enum: Controller temperature: degC */ #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 /* enum: Phy common temperature: degC */ #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 /* enum: Controller cooling: bool */ #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 /* enum: Phy 0 temperature: degC */ #define MC_CMD_SENSOR_PHY0_TEMP 0x3 /* enum: Phy 0 cooling: bool */ #define MC_CMD_SENSOR_PHY0_COOLING 0x4 /* enum: Phy 1 temperature: degC */ #define MC_CMD_SENSOR_PHY1_TEMP 0x5 /* enum: Phy 1 cooling: bool */ #define MC_CMD_SENSOR_PHY1_COOLING 0x6 /* enum: 1.0v power: mV */ #define MC_CMD_SENSOR_IN_1V0 0x7 /* enum: 1.2v power: mV */ #define MC_CMD_SENSOR_IN_1V2 0x8 /* enum: 1.8v power: mV */ #define MC_CMD_SENSOR_IN_1V8 0x9 /* enum: 2.5v power: mV */ #define MC_CMD_SENSOR_IN_2V5 0xa /* enum: 3.3v power: mV */ #define MC_CMD_SENSOR_IN_3V3 0xb /* enum: 12v power: mV */ #define MC_CMD_SENSOR_IN_12V0 0xc /* enum: 1.2v analogue power: mV */ #define MC_CMD_SENSOR_IN_1V2A 0xd /* enum: reference voltage: mV */ #define MC_CMD_SENSOR_IN_VREF 0xe /* enum: AOE FPGA power: mV */ #define MC_CMD_SENSOR_OUT_VAOE 0xf /* enum: AOE FPGA temperature: degC */ #define MC_CMD_SENSOR_AOE_TEMP 0x10 /* enum: AOE FPGA PSU temperature: degC */ #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 /* enum: AOE PSU temperature: degC */ #define MC_CMD_SENSOR_PSU_TEMP 0x12 /* enum: Fan 0 speed: RPM */ #define MC_CMD_SENSOR_FAN_0 0x13 /* enum: Fan 1 speed: RPM */ #define MC_CMD_SENSOR_FAN_1 0x14 /* enum: Fan 2 speed: RPM */ #define MC_CMD_SENSOR_FAN_2 0x15 /* enum: Fan 3 speed: RPM */ #define MC_CMD_SENSOR_FAN_3 0x16 /* enum: Fan 4 speed: RPM */ #define MC_CMD_SENSOR_FAN_4 0x17 /* enum: AOE FPGA input power: mV */ #define MC_CMD_SENSOR_IN_VAOE 0x18 /* enum: AOE FPGA current: mA */ #define MC_CMD_SENSOR_OUT_IAOE 0x19 /* enum: AOE FPGA input current: mA */ #define MC_CMD_SENSOR_IN_IAOE 0x1a /* enum: NIC power consumption: W */ #define MC_CMD_SENSOR_NIC_POWER 0x1b /* enum: 0.9v power voltage: mV */ #define MC_CMD_SENSOR_IN_0V9 0x1c /* enum: 0.9v power current: mA */ #define MC_CMD_SENSOR_IN_I0V9 0x1d /* enum: 1.2v power current: mA */ #define MC_CMD_SENSOR_IN_I1V2 0x1e /* enum: Not a sensor: reserved for the next page flag */ #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f /* enum: 0.9v power voltage (at ADC): mV */ #define MC_CMD_SENSOR_IN_0V9_ADC 0x20 /* enum: Controller temperature 2: degC */ #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 /* enum: Voltage regulator internal temperature: degC */ #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 /* enum: 0.9V voltage regulator temperature: degC */ #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 /* enum: 1.2V voltage regulator temperature: degC */ #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 /* enum: controller internal temperature sensor voltage (internal ADC): mV */ #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 /* enum: controller internal temperature (internal ADC): degC */ #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 /* enum: controller internal temperature sensor voltage (external ADC): mV */ #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 /* enum: controller internal temperature (external ADC): degC */ #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 /* enum: ambient temperature: degC */ #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 /* enum: air flow: bool */ #define MC_CMD_SENSOR_AIRFLOW 0x2a /* enum: voltage between VSS08D and VSS08D at CSR: mV */ #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c /* enum: Hotpoint temperature: degC */ #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d /* enum: Port 0 PHY power switch over-current: bool */ #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e /* enum: Port 1 PHY power switch over-current: bool */ #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f /* enum: Mop-up microcontroller reference voltage: mV */ #define MC_CMD_SENSOR_MUM_VCC 0x30 /* enum: 0.9v power phase A voltage: mV */ #define MC_CMD_SENSOR_IN_0V9_A 0x31 /* enum: 0.9v power phase A current: mA */ #define MC_CMD_SENSOR_IN_I0V9_A 0x32 /* enum: 0.9V voltage regulator phase A temperature: degC */ #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33 /* enum: 0.9v power phase B voltage: mV */ #define MC_CMD_SENSOR_IN_0V9_B 0x34 /* enum: 0.9v power phase B current: mA */ #define MC_CMD_SENSOR_IN_I0V9_B 0x35 /* enum: 0.9V voltage regulator phase B temperature: degC */ #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36 /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */ #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37 /* enum: CCOM AVREG 1v2 supply (external ADC): mV */ #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38 /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */ #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */ #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a /* enum: CCOM RTS temperature: degC */ #define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b /* enum: Not a sensor: reserved for the next page flag */ #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f /* enum: controller internal temperature sensor voltage on master core * (internal ADC): mV
*/ #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40 /* enum: controller internal temperature on master core (internal ADC): degC */ #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41 /* enum: controller internal temperature sensor voltage on master core * (external ADC): mV
*/ #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42 /* enum: controller internal temperature on master core (external ADC): degC */ #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43 /* enum: controller internal temperature on slave core sensor voltage (internal * ADC): mV
*/ #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44 /* enum: controller internal temperature on slave core (internal ADC): degC */ #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45 /* enum: controller internal temperature on slave core sensor voltage (external * ADC): mV
*/ #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46 /* enum: controller internal temperature on slave core (external ADC): degC */ #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47 /* enum: Voltage supplied to the SODIMMs from their power supply: mV */ #define MC_CMD_SENSOR_SODIMM_VOUT 0x49 /* enum: Temperature of SODIMM 0 (if installed): degC */ #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a /* enum: Temperature of SODIMM 1 (if installed): degC */ #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */ #define MC_CMD_SENSOR_PHY0_VCC 0x4c /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */ #define MC_CMD_SENSOR_PHY1_VCC 0x4d /* enum: Controller die temperature (TDIODE): degC */ #define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e /* enum: Board temperature (front): degC */ #define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f /* enum: Board temperature (back): degC */ #define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50 /* enum: 1.8v power current: mA */ #define MC_CMD_SENSOR_IN_I1V8 0x51 /* enum: 2.5v power current: mA */ #define MC_CMD_SENSOR_IN_I2V5 0x52 /* enum: 3.3v power current: mA */ #define MC_CMD_SENSOR_IN_I3V3 0x53 /* enum: 12v power current: mA */ #define MC_CMD_SENSOR_IN_I12V0 0x54 /* enum: 1.3v power: mV */ #define MC_CMD_SENSOR_IN_1V3 0x55 /* enum: 1.3v power current: mA */ #define MC_CMD_SENSOR_IN_I1V3 0x56 /* enum: Engineering sensor 1 */ #define MC_CMD_SENSOR_ENGINEERING_1 0x57 /* enum: Engineering sensor 2 */ #define MC_CMD_SENSOR_ENGINEERING_2 0x58 /* enum: Engineering sensor 3 */ #define MC_CMD_SENSOR_ENGINEERING_3 0x59 /* enum: Engineering sensor 4 */ #define MC_CMD_SENSOR_ENGINEERING_4 0x5a /* enum: Engineering sensor 5 */ #define MC_CMD_SENSOR_ENGINEERING_5 0x5b /* enum: Engineering sensor 6 */ #define MC_CMD_SENSOR_ENGINEERING_6 0x5c /* enum: Engineering sensor 7 */ #define MC_CMD_SENSOR_ENGINEERING_7 0x5d /* enum: Engineering sensor 8 */ #define MC_CMD_SENSOR_ENGINEERING_8 0x5e /* enum: Not a sensor: reserved for the next page flag */ #define MC_CMD_SENSOR_PAGE2_NEXT 0x5f /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ #define MC_CMD_SENSOR_ENTRY_OFST 4 #define MC_CMD_SENSOR_ENTRY_LEN 8 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 #define MC_CMD_SENSOR_ENTRY_MINNUM 0 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 #define MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127
/***********************************/ /* MC_CMD_READ_SENSORS * Returns the current reading from each sensor. DMAs an array of sensor * readings, in order of sensor type (but without gaps for unimplemented * sensors), into host memory. Each array element is a * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. * * If the request does not contain the LENGTH field then only sensors 0 to 30 * are reported, to avoid DMA buffer overflow in older host software. If the * sensor reading require more space than the LENGTH allows, then return * EINVAL. * * The MC will send a SENSOREVT event every time any sensor changes state. The * driver is responsible for ensuring that it doesn't miss any events. The * board will function normally if all sensors are in STATE_OK or * STATE_WARNING. Otherwise the board should not be expected to function.
*/ #define MC_CMD_READ_SENSORS 0x42 #undef MC_CMD_0x42_PRIVILEGE_CTG
/* MC_CMD_READ_SENSORS_IN msgrequest */ #define MC_CMD_READ_SENSORS_IN_LEN 8 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). * * If the address is 0xffffffffffffffff send the readings in the response (used * by cmdclient).
*/ #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
/* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). * * If the address is 0xffffffffffffffff send the readings in the response (used * by cmdclient).
*/ #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 /* Size in bytes of host buffer. */ #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4
/* MC_CMD_READ_SENSORS_EXT_IN_V2 msgrequest */ #define MC_CMD_READ_SENSORS_EXT_IN_V2_LEN 16 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). * * If the address is 0xffffffffffffffff send the readings in the response (used * by cmdclient).
*/ #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_OFST 0 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LEN 8 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_OFST 0 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_OFST 4 /* Size in bytes of host buffer. */ #define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_OFST 8 #define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_LEN 4 /* Flags controlling information retrieved */ #define MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_OFST 12 #define MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_LEN 4 #define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_OFST 12 #define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_LBN 0 #define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_WIDTH 1
/***********************************/ /* MC_CMD_GET_PHY_STATE * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot * (e.g. due to missing or corrupted firmware). Locks required: None. Return * code: 0
*/ #define MC_CMD_GET_PHY_STATE 0x43 #undef MC_CMD_0x43_PRIVILEGE_CTG
/***********************************/ /* MC_CMD_SETUP_8021QBB * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to * disable 802.Qbb for a given priority.
*/ #define MC_CMD_SETUP_8021QBB 0x44
/* MC_CMD_TESTASSERT_V2_IN msgrequest */ #define MC_CMD_TESTASSERT_V2_IN_LEN 4 /* How to provoke the assertion */ #define MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0 #define MC_CMD_TESTASSERT_V2_IN_TYPE_LEN 4 /* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless * you're testing firmware, this is what you want.
*/ #define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0 /* enum: Assert using assert(0); */ #define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1 /* enum: Deliberately trigger a watchdog */ #define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2 /* enum: Deliberately trigger a trap by loading from an invalid address */ #define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3 /* enum: Deliberately trigger a trap by storing to an invalid address */ #define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4 /* enum: Jump to an invalid address */ #define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5
/***********************************/ /* MC_CMD_WORKAROUND * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't * understand the given workaround number - which should not be treated as a * hard error by client code. This op does not imply any semantics about each * workaround, that's between the driver and the mcfw on a per-workaround * basis. Locks required: None. Returns: 0, EINVAL .
*/ #define MC_CMD_WORKAROUND 0x4a #undef MC_CMD_0x4a_PRIVILEGE_CTG
#define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
/* MC_CMD_WORKAROUND_IN msgrequest */ #define MC_CMD_WORKAROUND_IN_LEN 8 /* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */ #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 #define MC_CMD_WORKAROUND_IN_TYPE_LEN 4 /* enum: Bug 17230 work around. */ #define MC_CMD_WORKAROUND_BUG17230 0x1 /* enum: Bug 35388 work around (unsafe EVQ writes). */ #define MC_CMD_WORKAROUND_BUG35388 0x2 /* enum: Bug35017 workaround (A64 tables must be identity map) */ #define MC_CMD_WORKAROUND_BUG35017 0x3 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ #define MC_CMD_WORKAROUND_BUG41750 0x4 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution * - before adding code that queries this workaround, remember that there's * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, * and will hence (incorrectly) report that the bug doesn't exist.
*/ #define MC_CMD_WORKAROUND_BUG42008 0x5 /* enum: Bug 26807 features present in firmware (multicast filter chaining) * This feature cannot be turned on/off while there are any filters already * present. The behaviour in such case depends on the acting client's privilege * level. If the client has the admin privilege, then all functions that have * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise * the command will fail with MC_CMD_ERR_FILTERS_PRESENT.
*/ #define MC_CMD_WORKAROUND_BUG26807 0x6 /* enum: Bug 61265 work around (broken EVQ TMR writes). */ #define MC_CMD_WORKAROUND_BUG61265 0x7 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable * the workaround
*/ #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 #define MC_CMD_WORKAROUND_IN_ENABLED_LEN 4
/* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used * when (TYPE == MC_CMD_WORKAROUND_BUG26807)
*/ #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_OFST 0 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1
/***********************************/ /* MC_CMD_GET_PHY_MEDIA_INFO * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. * Anything else: currently undefined. Locks required: None. Return code: 0.
*/ #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b #undef MC_CMD_0x4b_PRIVILEGE_CTG
/***********************************/ /* MC_CMD_NVRAM_TEST * Test a particular NVRAM partition for valid contents (where "valid" depends * on the type of partition).
*/ #define MC_CMD_NVRAM_TEST 0x4c #undef MC_CMD_0x4c_PRIVILEGE_CTG
/***********************************/ /* MC_CMD_MRSFP_TWEAK * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. * I2C I/O expander bits are always read; if equaliser parameters are supplied, * they are configured first. Locks required: None. Return code: 0, EINVAL.
*/ #define MC_CMD_MRSFP_TWEAK 0x4d
/***********************************/ /* MC_CMD_SENSOR_SET_LIMS * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: * ENOENT if the sensor specified does not exist, EINVAL if the limits are out * of range.
*/ #define MC_CMD_SENSOR_SET_LIMS 0x4e #undef MC_CMD_0x4e_PRIVILEGE_CTG
/* MC_CMD_NVRAM_METADATA_IN msgrequest */ #define MC_CMD_NVRAM_METADATA_IN_LEN 4 /* Partition type ID code */ #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0 #define MC_CMD_NVRAM_METADATA_IN_TYPE_LEN 4
/* MC_CMD_NVRAM_METADATA_OUT msgresponse */ #define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20 #define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252 #define MC_CMD_NVRAM_METADATA_OUT_LENMAX_MCDI2 1020 #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num)) #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_NUM(len) (((len)-20)/1) /* Partition type ID code */ #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_OFST 4 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_OFST 4 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_OFST 4 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1 /* Subtype ID code for content of this partition */ #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 4 /* 1st component of W.X.Y.Z version number for content of this partition */ #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2 /* 2nd component of W.X.Y.Z version number for content of this partition */ #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2 /* 3rd component of W.X.Y.Z version number for content of this partition */ #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2 /* 4th component of W.X.Y.Z version number for content of this partition */ #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2 /* Zero-terminated string describing the content of this partition */ #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM_MCDI2 1000
/***********************************/ /* MC_CMD_GET_MAC_ADDRESSES * Returns the base MAC, count and stride for the requesting function
*/ #define MC_CMD_GET_MAC_ADDRESSES 0x55 #undef MC_CMD_0x55_PRIVILEGE_CTG
/* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */ #define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16 /* Base MAC address */ #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6 /* Padding */ #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2 /* Number of allocated MAC addresses */ #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 4 /* Spacing of allocated MAC addresses */ #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4
/***********************************/ /* MC_CMD_CLP * Perform a CLP related operation, see SF-110495-PS for details of CLP * processing. This command has been extended to accomodate the requirements of * different manufacturers which are to be found in SF-119187-TC, SF-119186-TC, * SF-120509-TC and SF-117282-PS.
*/ #define MC_CMD_CLP 0x56 #undef MC_CMD_0x56_PRIVILEGE_CTG
#define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN
/* MC_CMD_CLP_IN msgrequest */ #define MC_CMD_CLP_IN_LEN 4 /* Sub operation */ #define MC_CMD_CLP_IN_OP_OFST 0 #define MC_CMD_CLP_IN_OP_LEN 4 /* enum: Return to factory default settings */ #define MC_CMD_CLP_OP_DEFAULT 0x1 /* enum: Set MAC address */ #define MC_CMD_CLP_OP_SET_MAC 0x2 /* enum: Get MAC address */ #define MC_CMD_CLP_OP_GET_MAC 0x3 /* enum: Set UEFI/GPXE boot mode */ #define MC_CMD_CLP_OP_SET_BOOT 0x4 /* enum: Get UEFI/GPXE boot mode */ #define MC_CMD_CLP_OP_GET_BOOT 0x5
/* MC_CMD_CLP_IN_SET_MAC msgrequest */ #define MC_CMD_CLP_IN_SET_MAC_LEN 12 /* MC_CMD_CLP_IN_OP_OFST 0 */ /* MC_CMD_CLP_IN_OP_LEN 4 */ /* The MAC address assigned to port. A zero MAC address of 00:00:00:00:00:00 * restores the permanent (factory-programmed) MAC address associated with the * port. A non-zero MAC address persists until a PCIe reset or a power cycle.
*/ #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4 #define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6 /* Padding */ #define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2
/* MC_CMD_CLP_IN_SET_MAC_V2 msgrequest */ #define MC_CMD_CLP_IN_SET_MAC_V2_LEN 16 /* MC_CMD_CLP_IN_OP_OFST 0 */ /* MC_CMD_CLP_IN_OP_LEN 4 */ /* The MAC address assigned to port. A zero MAC address of 00:00:00:00:00:00 * restores the permanent (factory-programmed) MAC address associated with the * port. A non-zero MAC address persists until a PCIe reset or a power cycle.
*/ #define MC_CMD_CLP_IN_SET_MAC_V2_ADDR_OFST 4 #define MC_CMD_CLP_IN_SET_MAC_V2_ADDR_LEN 6 /* Padding */ #define MC_CMD_CLP_IN_SET_MAC_V2_RESERVED_OFST 10 #define MC_CMD_CLP_IN_SET_MAC_V2_RESERVED_LEN 2 #define MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_OFST 12 #define MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_LEN 4 #define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_OFST 12 #define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_LBN 0 #define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_WIDTH 1
/* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */ #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16 /* MC_CMD_MUM_IN_CMD_OFST 0 */ /* MC_CMD_MUM_IN_CMD_LEN 4 */ #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_LEN 4 /* The first 32-bit word to be written to the GPIO OUT register. */ #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_LEN 4 /* The second 32-bit word to be written to the GPIO OUT register. */ #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_LEN 4
/* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */ #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16 /* MC_CMD_MUM_IN_CMD_OFST 0 */ /* MC_CMD_MUM_IN_CMD_LEN 4 */ #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_LEN 4 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */ #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_LEN 4 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */ #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_LEN 4
/* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */ #define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8 /* The first 32-bit word read from the GPIO IN register. */ #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_LEN 4 /* The second 32-bit word read from the GPIO IN register. */ #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_LEN 4
/* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */ #define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8 /* The first 32-bit word read from the GPIO OUT register. */ #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_LEN 4 /* The second 32-bit word read from the GPIO OUT register. */ #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_LEN 4
/* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */ #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX_MCDI2 1016 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num)) #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_NUM(len) (((len)-8)/8) /* Discrete (soldered) DDR resistor strap info */ #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_OFST 0 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_OFST 0 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16 /* Number of SODIMM info records */ #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_LEN 4 /* Array of SODIMM info records */ #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM_MCDI2 126 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_OFST 8 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8 /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */ #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0 /* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */ #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1 /* enum: Total number of SODIMM banks */ #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_OFST 8 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_OFST 8 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_OFST 8 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */ #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */ #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */ #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */ /* enum: Values 5-15 are reserved for future usage */ #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_OFST 8 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_OFST 8 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_OFST 8 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4 /* enum: No module present */ #define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0 /* enum: Module present supported and powered on */ #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1 /* enum: Module present but bad type */ #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2 /* enum: Module present but incompatible voltage */ #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3 /* enum: Module present but unknown SPD */ #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4 /* enum: Module present but slot cannot support it */ #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5 /* enum: Modules may or may not be present, but cannot establish contact by I2C
*/ #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_OFST 8 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12
/* MC_CMD_DYNAMIC_SENSORS_LIMITS structuredef: Set of sensor limits. This * should match the equivalent structure in the sensor_query SPHINX service.
*/ #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LEN 24 /* A value below this will trigger a warning event. */ #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_OFST 0 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LEN 4 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LBN 0 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_WIDTH 32 /* A value below this will trigger a critical event. */ #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_OFST 4 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LEN 4 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LBN 32 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_WIDTH 32 /* A value below this will shut down the card. */ #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_OFST 8 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LEN 4 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LBN 64 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_WIDTH 32 /* A value above this will trigger a warning event. */ #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_OFST 12 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LEN 4 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LBN 96 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_WIDTH 32 /* A value above this will trigger a critical event. */ #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_OFST 16 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LEN 4 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LBN 128 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_WIDTH 32 /* A value above this will shut down the card. */ #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_OFST 20 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LEN 4 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LBN 160 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_WIDTH 32
/* MC_CMD_DYNAMIC_SENSORS_DESCRIPTION structuredef: Description of a sensor. * This should match the equivalent structure in the sensor_query SPHINX * service.
*/ #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LEN 64 /* The handle used to identify the sensor in calls to * MC_CMD_DYNAMIC_SENSORS_GET_VALUES
*/ #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_OFST 0 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LEN 4 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LBN 0 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_WIDTH 32 /* A human-readable name for the sensor (zero terminated string, max 32 bytes)
*/ #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_OFST 4 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_LEN 32 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_LBN 32 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_WIDTH 256 /* The type of the sensor device, and by implication the unit of that the * values will be reported in
*/ #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_OFST 36 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LEN 4 /* enum: A voltage sensor. Unit is mV */ #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_VOLTAGE 0x0 /* enum: A current sensor. Unit is mA */ #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_CURRENT 0x1 /* enum: A power sensor. Unit is mW */ #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_POWER 0x2 /* enum: A temperature sensor. Unit is Celsius */ #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TEMPERATURE 0x3 /* enum: A cooling fan sensor. Unit is RPM */ #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_FAN 0x4 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LBN 288 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_WIDTH 32 /* A single MC_CMD_DYNAMIC_SENSORS_LIMITS structure */ #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_OFST 40 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_LEN 24 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_LBN 320 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_WIDTH 192
/* MC_CMD_DYNAMIC_SENSORS_READING structuredef: State and value of a sensor. * This should match the equivalent structure in the sensor_query SPHINX * service.
*/ #define MC_CMD_DYNAMIC_SENSORS_READING_LEN 12 /* The handle used to identify the sensor */ #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_OFST 0 #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LEN 4 #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LBN 0 #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_WIDTH 32 /* The current value of the sensor */ #define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_OFST 4 #define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LEN 4 #define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LBN 32 #define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_WIDTH 32 /* The sensor's condition, e.g. good, broken or removed */ #define MC_CMD_DYNAMIC_SENSORS_READING_STATE_OFST 8 #define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LEN 4 /* enum: Sensor working normally within limits */ #define MC_CMD_DYNAMIC_SENSORS_READING_OK 0x0 /* enum: Warning threshold breached */ #define MC_CMD_DYNAMIC_SENSORS_READING_WARNING 0x1 /* enum: Critical threshold breached */ #define MC_CMD_DYNAMIC_SENSORS_READING_CRITICAL 0x2 /* enum: Fatal threshold breached */ #define MC_CMD_DYNAMIC_SENSORS_READING_FATAL 0x3 /* enum: Sensor not working */ #define MC_CMD_DYNAMIC_SENSORS_READING_BROKEN 0x4 /* enum: Sensor working but no reading available */ #define MC_CMD_DYNAMIC_SENSORS_READING_NO_READING 0x5 /* enum: Sensor initialization failed */ #define MC_CMD_DYNAMIC_SENSORS_READING_INIT_FAILED 0x6 #define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LBN 64 #define MC_CMD_DYNAMIC_SENSORS_READING_STATE_WIDTH 32
/***********************************/ /* MC_CMD_DYNAMIC_SENSORS_LIST * Return a complete list of handles for sensors currently managed by the MC, * and a generation count for this version of the sensor table. On systems * advertising the DYNAMIC_SENSORS capability bit, this replaces the * MC_CMD_READ_SENSORS command. On multi-MC systems this may include sensors * added by the NMC. * * Sensor handles are persistent for the lifetime of the sensor and are used to * identify sensors in MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS and * MC_CMD_DYNAMIC_SENSORS_GET_VALUES. * * The generation count is maintained by the MC, is persistent across reboots * and will be incremented each time the sensor table is modified. When the * table is modified, a CODE_DYNAMIC_SENSORS_CHANGE event will be generated * containing the new generation count. The driver should compare this against * the current generation count, and if it is different, call * MC_CMD_DYNAMIC_SENSORS_LIST again to update it's copy of the sensor table. * * The sensor count is provided to allow a future path to supporting more than * MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM_MCDI2 sensors, i.e. * the maximum number that will fit in a single response. As this is a fairly * large number (253) it is not anticipated that this will be needed in the * near future, so can currently be ignored. * * On Riverhead this command is implemented as a wrapper for `list` in the * sensor_query SPHINX service.
*/ #define MC_CMD_DYNAMIC_SENSORS_LIST 0x66 #undef MC_CMD_0x66_PRIVILEGE_CTG
/* MC_CMD_DYNAMIC_SENSORS_LIST_OUT msgresponse */ #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMIN 8 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMAX 252 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMAX_MCDI2 1020 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LEN(num) (8+4*(num)) #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_NUM(len) (((len)-8)/4) /* Generation count, which will be updated each time a sensor is added to or * removed from the MC sensor table.
*/ #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_OFST 0 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_LEN 4 /* Number of sensors managed by the MC. Note that in principle, this can be * larger than the size of the HANDLES array.
*/ #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_OFST 4 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_LEN 4 /* Array of sensor handles */ #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_OFST 8 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_LEN 4 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MINNUM 0 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MAXNUM 61 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MAXNUM_MCDI2 253
/***********************************/ /* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS * Get descriptions for a set of sensors, specified as an array of sensor * handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST * * Any handles which do not correspond to a sensor currently managed by the MC * will be dropped from the response. This may happen when a sensor table * update is in progress, and effectively means the set of usable sensors is * the intersection between the sets of sensors known to the driver and the MC. * * On Riverhead this command is implemented as a wrapper for * `get_descriptions` in the sensor_query SPHINX service.
*/ #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 0x67 #undef MC_CMD_0x67_PRIVILEGE_CTG
/***********************************/ /* MC_CMD_DYNAMIC_SENSORS_GET_READINGS * Read the state and value for a set of sensors, specified as an array of * sensor handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST. * * In the case of a broken sensor, then the state of the response's * MC_CMD_DYNAMIC_SENSORS_VALUE entry will be set to BROKEN, and any value * provided should be treated as erroneous. * * Any handles which do not correspond to a sensor currently managed by the MC * will be dropped from the response. This may happen when a sensor table * update is in progress, and effectively means the set of usable sensors is * the intersection between the sets of sensors known to the driver and the MC. * * On Riverhead this command is implemented as a wrapper for `get_readings` * in the sensor_query SPHINX service.
*/ #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS 0x68 #undef MC_CMD_0x68_PRIVILEGE_CTG
/* TX_TIMESTAMP_EVENT structuredef */ #define TX_TIMESTAMP_EVENT_LEN 6 /* lower 16 bits of timestamp data */ #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16 /* Type of TX event, ordinary TX completion, low or high part of TX timestamp
*/ #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1 /* enum: This is a TX completion event, not a timestamp */ #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0 /* enum: This is a TX completion event for a CTPIO transmit. The event format * is the same as for TX_EV_COMPLETION.
*/ #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x11 /* enum: This is the low part of a TX timestamp for a CTPIO transmission. The * event format is the same as for TX_EV_TSTAMP_LO
*/ #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x12 /* enum: This is the high part of a TX timestamp for a CTPIO transmission. The * event format is the same as for TX_EV_TSTAMP_HI
*/ #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x13 /* enum: This is the low part of a TX timestamp event */ #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51 /* enum: This is the high part of a TX timestamp event */ #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8 /* upper 16 bits of timestamp data */ #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16
/* RSS_MODE structuredef */ #define RSS_MODE_LEN 1 /* The RSS mode for a particular packet type is a value from 0 - 15 which can * be considered as 4 bits selecting which fields are included in the hash. (A * value 0 effectively disables RSS spreading for the packet type.) The YAML * generation tools require this structure to be a whole number of bytes wide, * but only 4 bits are relevant.
*/ #define RSS_MODE_HASH_SELECTOR_OFST 0 #define RSS_MODE_HASH_SELECTOR_LEN 1 #define RSS_MODE_HASH_SRC_ADDR_OFST 0 #define RSS_MODE_HASH_SRC_ADDR_LBN 0 #define RSS_MODE_HASH_SRC_ADDR_WIDTH 1 #define RSS_MODE_HASH_DST_ADDR_OFST 0 #define RSS_MODE_HASH_DST_ADDR_LBN 1 #define RSS_MODE_HASH_DST_ADDR_WIDTH 1 #define RSS_MODE_HASH_SRC_PORT_OFST 0 #define RSS_MODE_HASH_SRC_PORT_LBN 2 #define RSS_MODE_HASH_SRC_PORT_WIDTH 1 #define RSS_MODE_HASH_DST_PORT_OFST 0 #define RSS_MODE_HASH_DST_PORT_LBN 3 #define RSS_MODE_HASH_DST_PORT_WIDTH 1 #define RSS_MODE_HASH_SELECTOR_LBN 0 #define RSS_MODE_HASH_SELECTOR_WIDTH 8
/* CTPIO_STATS_MAP structuredef */ #define CTPIO_STATS_MAP_LEN 4 /* The (function relative) VI number */ #define CTPIO_STATS_MAP_VI_OFST 0 #define CTPIO_STATS_MAP_VI_LEN 2 #define CTPIO_STATS_MAP_VI_LBN 0 #define CTPIO_STATS_MAP_VI_WIDTH 16 /* The target bucket for the VI */ #define CTPIO_STATS_MAP_BUCKET_OFST 2 #define CTPIO_STATS_MAP_BUCKET_LEN 2 #define CTPIO_STATS_MAP_BUCKET_LBN 16 #define CTPIO_STATS_MAP_BUCKET_WIDTH 16
/***********************************/ /* MC_CMD_READ_REGS * Get a dump of the MCPU registers
*/ #define MC_CMD_READ_REGS 0x50 #undef MC_CMD_0x50_PRIVILEGE_CTG
/* MC_CMD_READ_REGS_OUT msgresponse */ #define MC_CMD_READ_REGS_OUT_LEN 308 /* Whether the corresponding register entry contains a valid value */ #define MC_CMD_READ_REGS_OUT_MASK_OFST 0 #define MC_CMD_READ_REGS_OUT_MASK_LEN 16 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, * fir, fp)
*/ #define MC_CMD_READ_REGS_OUT_REGS_OFST 16 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4 #define MC_CMD_READ_REGS_OUT_REGS_NUM 73
/***********************************/ /* MC_CMD_INIT_EVQ * Set up an event queue according to the supplied parameters. The IN arguments * end with an address for each 4k of host memory required to back the EVQ.
*/ #define MC_CMD_INIT_EVQ 0x80 #undef MC_CMD_0x80_PRIVILEGE_CTG
/***********************************/ /* MC_CMD_INIT_RXQ * set up a receive queue according to the supplied parameters. The IN * arguments end with an address for each 4k of host memory required to back * the RXQ.
*/ #define MC_CMD_INIT_RXQ 0x81 #undef MC_CMD_0x81_PRIVILEGE_CTG
/* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version * in new code.
*/ #define MC_CMD_INIT_RXQ_IN_LENMIN 36 #define MC_CMD_INIT_RXQ_IN_LENMAX 252 #define MC_CMD_INIT_RXQ_IN_LENMAX_MCDI2 1020 #define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num)) #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8) /* Size, in entries */ #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 #define MC_CMD_INIT_RXQ_IN_SIZE_LEN 4 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ
*/ #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_LEN 4 /* The value to put in the event data. Check hardware spec. for valid range. */ #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 #define MC_CMD_INIT_RXQ_IN_LABEL_LEN 4 /* Desired instance. Must be set to a specific instance, which is a function * local queue index.
*/ #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 #define MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4 /* There will be more flags here. */ #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 #define MC_CMD_INIT_RXQ_IN_FLAGS_LEN 4 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_OFST 16 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_OFST 16 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_OFST 16 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_OFST 16 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_OFST 16 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_OFST 16 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_OFST 16 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1 #define MC_CMD_INIT_RXQ_IN_UNUSED_OFST 16 #define MC_CMD_INIT_RXQ_IN_UNUSED_LBN 10 #define MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1 /* Owner ID to use if in buffer mode (zero if physical) */ #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_LEN 4 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ #define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24 #define MC_CMD_INIT_RXQ_IN_PORT_ID_LEN 4 /* 64-bit address of 4k of 4k-aligned host memory buffer */ #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM_MCDI2 124
/* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode * flags
*/ #define MC_CMD_INIT_RXQ_EXT_IN_LEN 544 /* Size, in entries */ #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 4 /* The EVQ to send events to. This is an index originally specified to * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
*/ #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4 /* The value to put in the event data. Check hardware spec. for valid range. * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE * == PACKED_STREAM.
*/ #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4 /* Desired instance. Must be set to a specific instance, which is a function * local queue index.
*/ #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4 /* There will be more flags here. */ #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 4 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_OFST 16 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_OFST 16 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_OFST 16 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_OFST 16 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_OFST 16 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_OFST 16 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_OFST 16 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_OFST 16 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4 /* enum: One packet per descriptor (for normal networking) */ #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1 /* enum: Pack multiple packets into large descriptors using the format designed * to maximise packet rate. This mode uses 1 "bucket" per descriptor with * multiple fixed-size packet buffers within each bucket. For a full * description see SF-119419-TC. This mode is only supported by "dpdk" datapath * firmware.
*/ #define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2 /* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */ #define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x2 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_OFST 16 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_OFST 16 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */ #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */ #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */ #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */ #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */ #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_OFST 16 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_OFST 16 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_OFST 16 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_LBN 20 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_WIDTH 1 /* Owner ID to use if in buffer mode (zero if physical) */ #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_LEN 4 /* 64-bit address of 4k of 4k-aligned host memory buffer */ #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 4
/* MC_CMD_INIT_RXQ_V3_IN msgrequest */ #define MC_CMD_INIT_RXQ_V3_IN_LEN 560 /* Size, in entries */ #define MC_CMD_INIT_RXQ_V3_IN_SIZE_OFST 0 #define MC_CMD_INIT_RXQ_V3_IN_SIZE_LEN 4 /* The EVQ to send events to. This is an index originally specified to * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
*/ #define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_OFST 4 #define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_LEN 4 /* The value to put in the event data. Check hardware spec. for valid range. * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE * == PACKED_STREAM.
*/ #define MC_CMD_INIT_RXQ_V3_IN_LABEL_OFST 8 #define MC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 4 /* Desired instance. Must be set to a specific instance, which is a function * local queue index.
*/ #define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_OFST 12 #define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 4 /* There will be more flags here. */ #define MC_CMD_INIT_RXQ_V3_IN_FLAGS_OFST 16 #define MC_CMD_INIT_RXQ_V3_IN_FLAGS_LEN 4 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_OFST 16 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_LBN 0 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_WIDTH 1 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_OFST 16 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_LBN 1 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_WIDTH 1 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_OFST 16 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_LBN 2 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_WIDTH 1 #define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_OFST 16 #define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_LBN 3 #define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_WIDTH 4 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_OFST 16 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_LBN 7 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_WIDTH 1 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_OFST 16 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_LBN 8 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_WIDTH 1 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_OFST 16 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_LBN 9 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_WIDTH 1 #define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_OFST 16 #define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_LBN 10 #define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 4 /* enum: One packet per descriptor (for normal networking) */ #define MC_CMD_INIT_RXQ_V3_IN_SINGLE_PACKET 0x0 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ #define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM 0x1 /* enum: Pack multiple packets into large descriptors using the format designed * to maximise packet rate. This mode uses 1 "bucket" per descriptor with * multiple fixed-size packet buffers within each bucket. For a full * description see SF-119419-TC. This mode is only supported by "dpdk" datapath * firmware.
*/ #define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2 /* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */ #define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x2 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_OFST 16 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_LBN 14 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 #define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_OFST 16 #define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 #define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */ #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */ #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */ #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */ #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */ #define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_OFST 16 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_OFST 16 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_LBN 19 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_OFST 16 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_LBN 20 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_WIDTH 1 /* Owner ID to use if in buffer mode (zero if physical) */ #define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_OFST 20 #define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 4 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ #define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_OFST 24 #define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_LEN 4 /* 64-bit address of 4k of 4k-aligned host memory buffer */ #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_OFST 28 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LEN 8 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_OFST 28 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_OFST 32 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_NUM 64 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ #define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_OFST 540 #define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_LEN 4 /* The number of packet buffers that will be contained within each * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
*/ #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544 #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4 /* The length in bytes of the area in each packet buffer that can be written to * by the adapter. This is used to store the packet prefix and the packet * payload. This length does not include any end padding added by the driver. * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
*/ #define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_OFST 548 #define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_LEN 4 /* The length in bytes of a single packet buffer within a * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
*/ #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_OFST 552 #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_LEN 4 /* The maximum time in nanoseconds that the datapath will be backpressured if * there are no RX descriptors available. If the timeout is reached and there * are still no descriptors then the packet will be dropped. A timeout of 0 * means the datapath will never be blocked. This field is ignored unless * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
*/ #define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556 #define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
/* MC_CMD_INIT_RXQ_V4_IN msgrequest: INIT_RXQ request with new field required * for systems with a QDMA (currently, Riverhead)
*/ #define MC_CMD_INIT_RXQ_V4_IN_LEN 564 /* Size, in entries */ #define MC_CMD_INIT_RXQ_V4_IN_SIZE_OFST 0 #define MC_CMD_INIT_RXQ_V4_IN_SIZE_LEN 4 /* The EVQ to send events to. This is an index originally specified to * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
*/ #define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_OFST 4 #define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_LEN 4 /* The value to put in the event data. Check hardware spec. for valid range. * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE * == PACKED_STREAM.
*/ #define MC_CMD_INIT_RXQ_V4_IN_LABEL_OFST 8 #define MC_CMD_INIT_RXQ_V4_IN_LABEL_LEN 4 /* Desired instance. Must be set to a specific instance, which is a function * local queue index.
*/ #define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_OFST 12 #define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_LEN 4 /* There will be more flags here. */ #define MC_CMD_INIT_RXQ_V4_IN_FLAGS_OFST 16 #define MC_CMD_INIT_RXQ_V4_IN_FLAGS_LEN 4 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_OFST 16 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_LBN 0 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_WIDTH 1 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_OFST 16 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_LBN 1 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_WIDTH 1 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_OFST 16 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_LBN 2 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_WIDTH 1 #define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_OFST 16 #define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_LBN 3 #define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_WIDTH 4 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_OFST 16 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_LBN 7 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_WIDTH 1 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_OFST 16 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_LBN 8 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_WIDTH 1 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_OFST 16 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_LBN 9 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_WIDTH 1 #define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_OFST 16 #define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_LBN 10 #define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_WIDTH 4 /* enum: One packet per descriptor (for normal networking) */ #define MC_CMD_INIT_RXQ_V4_IN_SINGLE_PACKET 0x0 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ #define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM 0x1 /* enum: Pack multiple packets into large descriptors using the format designed * to maximise packet rate. This mode uses 1 "bucket" per descriptor with * multiple fixed-size packet buffers within each bucket. For a full * description see SF-119419-TC. This mode is only supported by "dpdk" datapath * firmware.
*/ #define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2 /* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */ #define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_PACKED_STREAM 0x2 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_OFST 16 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_LBN 14 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 #define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_OFST 16 #define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 #define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_1M 0x0 /* enum */ #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_512K 0x1 /* enum */ #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_256K 0x2 /* enum */ #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_128K 0x3 /* enum */ #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_64K 0x4 /* enum */ #define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_OFST 16 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_OFST 16 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_LBN 19 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_OFST 16 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_LBN 20 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_WIDTH 1 /* Owner ID to use if in buffer mode (zero if physical) */ #define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_OFST 20 #define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_LEN 4 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ #define MC_CMD_INIT_RXQ_V4_IN_PORT_ID_OFST 24 #define MC_CMD_INIT_RXQ_V4_IN_PORT_ID_LEN 4 /* 64-bit address of 4k of 4k-aligned host memory buffer */ #define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_OFST 28 #define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LEN 8 #define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_OFST 28 #define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_OFST 32 #define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_NUM 64 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ #define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_OFST 540 #define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_LEN 4 /* The number of packet buffers that will be contained within each * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
*/ #define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544 #define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4 /* The length in bytes of the area in each packet buffer that can be written to * by the adapter. This is used to store the packet prefix and the packet * payload. This length does not include any end padding added by the driver. * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
*/ #define MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_OFST 548 #define MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_LEN 4 /* The length in bytes of a single packet buffer within a * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
*/ #define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_OFST 552 #define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_LEN 4 /* The maximum time in nanoseconds that the datapath will be backpressured if * there are no RX descriptors available. If the timeout is reached and there * are still no descriptors then the packet will be dropped. A timeout of 0 * means the datapath will never be blocked. This field is ignored unless * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
*/ #define MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556 #define MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4 /* V4 message data */ #define MC_CMD_INIT_RXQ_V4_IN_V4_DATA_OFST 560 #define MC_CMD_INIT_RXQ_V4_IN_V4_DATA_LEN 4 /* Size in bytes of buffers attached to descriptors posted to this queue. Set * to zero if using this message on non-QDMA based platforms. Currently in * Riverhead there is a global limit of eight different buffer sizes across all * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a * request for a different buffer size will fail if there are already eight * other buffer sizes in use. In future Riverhead this limit will go away and * any size will be accepted.
*/ #define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_OFST 560 #define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_LEN 4
/* MC_CMD_INIT_RXQ_V5_IN msgrequest: INIT_RXQ request with ability to request a * different RX packet prefix
*/ #define MC_CMD_INIT_RXQ_V5_IN_LEN 568 /* Size, in entries */ #define MC_CMD_INIT_RXQ_V5_IN_SIZE_OFST 0 #define MC_CMD_INIT_RXQ_V5_IN_SIZE_LEN 4 /* The EVQ to send events to. This is an index originally specified to * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
*/ #define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_OFST 4 #define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_LEN 4 /* The value to put in the event data. Check hardware spec. for valid range. * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE * == PACKED_STREAM.
*/ #define MC_CMD_INIT_RXQ_V5_IN_LABEL_OFST 8 #define MC_CMD_INIT_RXQ_V5_IN_LABEL_LEN 4 /* Desired instance. Must be set to a specific instance, which is a function * local queue index.
*/ #define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_OFST 12 #define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_LEN 4 /* There will be more flags here. */ #define MC_CMD_INIT_RXQ_V5_IN_FLAGS_OFST 16 #define MC_CMD_INIT_RXQ_V5_IN_FLAGS_LEN 4 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_OFST 16 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_LBN 0 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_WIDTH 1 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_OFST 16 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_LBN 1 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_WIDTH 1 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_OFST 16 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_LBN 2 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_WIDTH 1 #define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_OFST 16 #define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_LBN 3 #define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_WIDTH 4 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_OFST 16 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_LBN 7 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_WIDTH 1 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_OFST 16 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_LBN 8 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_WIDTH 1 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_OFST 16 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_LBN 9 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_WIDTH 1 #define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_OFST 16 #define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_LBN 10 #define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_WIDTH 4 /* enum: One packet per descriptor (for normal networking) */ #define MC_CMD_INIT_RXQ_V5_IN_SINGLE_PACKET 0x0 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ #define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM 0x1 /* enum: Pack multiple packets into large descriptors using the format designed * to maximise packet rate. This mode uses 1 "bucket" per descriptor with * multiple fixed-size packet buffers within each bucket. For a full * description see SF-119419-TC. This mode is only supported by "dpdk" datapath * firmware.
*/ #define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2 /* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */ #define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_PACKED_STREAM 0x2 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_OFST 16 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_LBN 14 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 #define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_OFST 16 #define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 #define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_1M 0x0 /* enum */ #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_512K 0x1 /* enum */ #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_256K 0x2 /* enum */ #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_128K 0x3 /* enum */ #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_64K 0x4 /* enum */ #define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_OFST 16 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_OFST 16 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_LBN 19 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_OFST 16 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_LBN 20 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_WIDTH 1 /* Owner ID to use if in buffer mode (zero if physical) */ #define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_OFST 20 #define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_LEN 4 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ #define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_OFST 24 #define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_LEN 4 /* 64-bit address of 4k of 4k-aligned host memory buffer */ #define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_OFST 28 #define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LEN 8 #define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_OFST 28 #define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_OFST 32 #define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_NUM 64 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ #define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_OFST 540 #define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_LEN 4 /* The number of packet buffers that will be contained within each * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
*/ #define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544 #define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4 /* The length in bytes of the area in each packet buffer that can be written to * by the adapter. This is used to store the packet prefix and the packet * payload. This length does not include any end padding added by the driver. * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
*/ #define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_OFST 548 #define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_LEN 4 /* The length in bytes of a single packet buffer within a * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
*/ #define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_OFST 552 #define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_LEN 4 /* The maximum time in nanoseconds that the datapath will be backpressured if * there are no RX descriptors available. If the timeout is reached and there * are still no descriptors then the packet will be dropped. A timeout of 0 * means the datapath will never be blocked. This field is ignored unless * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
*/ #define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556 #define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4 /* V4 message data */ #define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_OFST 560 #define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_LEN 4 /* Size in bytes of buffers attached to descriptors posted to this queue. Set * to zero if using this message on non-QDMA based platforms. Currently in * Riverhead there is a global limit of eight different buffer sizes across all * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a * request for a different buffer size will fail if there are already eight * other buffer sizes in use. In future Riverhead this limit will go away and * any size will be accepted.
*/ #define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_OFST 560 #define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_LEN 4 /* Prefix id for the RX prefix format to use on packets delivered this queue. * Zero is always a valid prefix id and means the default prefix format * documented for the platform. Other prefix ids can be obtained by calling * MC_CMD_GET_RX_PREFIX_ID with a requested set of prefix fields.
*/ #define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_OFST 564 #define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_LEN 4
/***********************************/ /* MC_CMD_FINI_EVQ * Teardown an EVQ. * * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first * or the operation will fail with EBUSY
*/ #define MC_CMD_FINI_EVQ 0x83 #undef MC_CMD_0x83_PRIVILEGE_CTG
/* MC_CMD_FINI_EVQ_IN msgrequest */ #define MC_CMD_FINI_EVQ_IN_LEN 4 /* Instance of EVQ to destroy. Should be the same instance as that previously * passed to INIT_EVQ
*/ #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 #define MC_CMD_FINI_EVQ_IN_INSTANCE_LEN 4
/***********************************/ /* MC_CMD_DRIVER_EVENT * Generate an event on an EVQ belonging to the function issuing the command.
*/ #define MC_CMD_DRIVER_EVENT 0x86 #undef MC_CMD_0x86_PRIVILEGE_CTG
/***********************************/ /* MC_CMD_ALLOC_BUFTBL_CHUNK * Allocate a set of buffer table entries using the specified owner ID. This * operation allocates the required buffer table entries (and fails if it * cannot do so). The buffer table entries will initially be zeroed.
*/ #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 #undef MC_CMD_0x87_PRIVILEGE_CTG
/* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 /* Owner ID to use */ #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_LEN 4 /* Size of buffer table pages to use, in bytes (note that only a few values are * legal on any specific hardware).
*/ #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_LEN 4
/***********************************/ /* MC_CMD_PROGRAM_BUFTBL_ENTRIES * Reprogram a set of buffer table entries in the specified chunk.
*/ #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 #undef MC_CMD_0x88_PRIVILEGE_CTG
/* MC_CMD_FILTER_OP_IN msgrequest */ #define MC_CMD_FILTER_OP_IN_LEN 108 /* identifies the type of operation requested */ #define MC_CMD_FILTER_OP_IN_OP_OFST 0 #define MC_CMD_FILTER_OP_IN_OP_LEN 4 /* enum: single-recipient filter insert */ #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 /* enum: single-recipient filter remove */ #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 /* enum: multi-recipient filter subscribe */ #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 /* enum: multi-recipient filter unsubscribe */ #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 /* enum: replace one recipient with another (warning - the filter handle may * change)
*/ #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4 /* filter handle (for remove / unsubscribe operations) */ #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 #define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4 #define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8 /* The port ID associated with the v-adaptor which should contain this filter.
*/ #define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12 #define MC_CMD_FILTER_OP_IN_PORT_ID_LEN 4 /* fields to include in match criteria */ #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 4 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_OFST 16 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_OFST 16 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_OFST 16 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_OFST 16 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_OFST 16 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_OFST 16 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_OFST 16 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_OFST 16 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_OFST 16 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_OFST 16 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_OFST 16 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_OFST 16 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 /* receive destination */ #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20 #define MC_CMD_FILTER_OP_IN_RX_DEST_LEN 4 /* enum: drop packets */ #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 /* enum: receive to host */ #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 /* enum: receive to MC */ #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 /* enum: loop back to TXDP 0 */ #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 /* enum: loop back to TXDP 1 */ #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 /* receive queue handle (for multiple queue modes, this is the base queue) */ #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 4 /* receive mode */ #define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28 #define MC_CMD_FILTER_OP_IN_RX_MODE_LEN 4 /* enum: receive to just the specified queue */ #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0 /* enum: receive to multiple queues using RSS context */ #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1 /* enum: receive to multiple queues using .1p mapping */ #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2 /* enum: install a filter entry that will never match; for test purposes only
*/ #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or * MC_CMD_DOT1P_MAPPING_ALLOC.
*/ #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_LEN 4 /* transmit domain (reserved; set to 0) */ #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_LEN 4 /* transmit destination (either set the MAC and/or PM bits for explicit * control, or set this field to TX_DEST_DEFAULT for sensible default * behaviour)
*/ #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40 #define MC_CMD_FILTER_OP_IN_TX_DEST_LEN 4 /* enum: request default behaviour (based on filter type) */ #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_OFST 40 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_OFST 40 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 /* source MAC address to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44 #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 /* source port to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50 #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 /* destination MAC address to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52 #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 /* destination port to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58 #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 /* Ethernet type to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 /* Inner VLAN tag to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 /* Outer VLAN tag to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 /* IP protocol to match (in low byte; set high byte to 0) */ #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66 #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 /* Firmware defined register 0 to match (reserved; set to 0) */ #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68 #define MC_CMD_FILTER_OP_IN_FWDEF0_LEN 4 /* Firmware defined register 1 to match (reserved; set to 0) */ #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72 #define MC_CMD_FILTER_OP_IN_FWDEF1_LEN 4 /* source IP address to match (as bytes in network order; set last 12 bytes to * 0 for IPv4 address)
*/ #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76 #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 /* destination IP address to match (as bytes in network order; set last 12 * bytes to 0 for IPv4 address)
*/ #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92 #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16
/* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to * include handling of VXLAN/NVGRE encapsulated frame filtering (which is * supported on Medford only).
*/ #define MC_CMD_FILTER_OP_EXT_IN_LEN 172 /* identifies the type of operation requested */ #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0 #define MC_CMD_FILTER_OP_EXT_IN_OP_LEN 4 /* Enum values, see field(s): */ /* MC_CMD_FILTER_OP_IN/OP */ /* filter handle (for remove / unsubscribe operations) */ #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8 /* The port ID associated with the v-adaptor which should contain this filter.
*/ #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_LEN 4 /* fields to include in match criteria */ #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 4 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 /* receive destination */ #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 4 /* enum: drop packets */ #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0 /* enum: receive to host */ #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1 /* enum: receive to MC */ #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2 /* enum: loop back to TXDP 0 */ #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3 /* enum: loop back to TXDP 1 */ #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4 /* receive queue handle (for multiple queue modes, this is the base queue) */ #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 4 /* receive mode */ #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 4 /* enum: receive to just the specified queue */ #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0 /* enum: receive to multiple queues using RSS context */ #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1 /* enum: receive to multiple queues using .1p mapping */ #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2 /* enum: install a filter entry that will never match; for test purposes only
*/ #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or * MC_CMD_DOT1P_MAPPING_ALLOC.
*/ #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_LEN 4 /* transmit domain (reserved; set to 0) */ #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_LEN 4 /* transmit destination (either set the MAC and/or PM bits for explicit * control, or set this field to TX_DEST_DEFAULT for sensible default * behaviour)
*/ #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4 /* enum: request default behaviour (based on filter type) */ #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_OFST 40 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_OFST 40 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1 /* source MAC address to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6 /* source port to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2 /* destination MAC address to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6 /* destination port to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2 /* Ethernet type to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2 /* Inner VLAN tag to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2 /* Outer VLAN tag to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2 /* IP protocol to match (in low byte; set high byte to 0) */ #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2 /* Firmware defined register 0 to match (reserved; set to 0) */ #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_LEN 4 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP * protocol is GRE) to match (as bytes in network order; set last byte to 0 for * VXLAN/NVGRE, or 1 for Geneve)
*/ #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 4 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_OFST 72 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_OFST 72 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8 /* enum: Match VXLAN traffic with this VNI */ #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0 /* enum: Match Geneve traffic with this VNI */ #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1 /* enum: Reserved for experimental development use */ #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_OFST 72 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_OFST 72 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8 /* enum: Match NVGRE traffic with this VSID */ #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0 /* source IP address to match (as bytes in network order; set last 12 bytes to * 0 for IPv4 address)
*/ #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16 /* destination IP address to match (as bytes in network order; set last 12 * bytes to 0 for IPv4 address)
*/ #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network * order)
*/ #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in * network order)
*/ #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network * order)
*/ #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)
*/ #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)
*/ #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)
*/ #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to * 0)
*/ #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set * to 0)
*/ #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_LEN 4 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set * to 0)
*/ #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_LEN 4 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network * order; set last 12 bytes to 0 for IPv4 address)
*/ #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network * order; set last 12 bytes to 0 for IPv4 address)
*/ #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16
/* MC_CMD_FILTER_OP_V3_IN msgrequest: FILTER_OP extension to support additional * filter actions for Intel's DPDK (Data Plane Development Kit, dpdk.org) via * its rte_flow API. This extension is only useful with the sfc_efx driver * included as part of DPDK, used in conjunction with the dpdk datapath * firmware variant.
*/ #define MC_CMD_FILTER_OP_V3_IN_LEN 180 /* identifies the type of operation requested */ #define MC_CMD_FILTER_OP_V3_IN_OP_OFST 0 #define MC_CMD_FILTER_OP_V3_IN_OP_LEN 4 /* Enum values, see field(s): */ /* MC_CMD_FILTER_OP_IN/OP */ /* filter handle (for remove / unsubscribe operations) */ #define MC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 4 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_LEN 8 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 4 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_OFST 8 /* The port ID associated with the v-adaptor which should contain this filter.
*/ #define MC_CMD_FILTER_OP_V3_IN_PORT_ID_OFST 12 #define MC_CMD_FILTER_OP_V3_IN_PORT_ID_LEN 4 /* fields to include in match criteria */ #define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_LEN 4 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_LBN 0 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_LBN 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_LBN 2 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_LBN 3 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_LBN 4 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_LBN 5 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_LBN 6 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_LBN 7 #define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_LBN 8 #define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_LBN 9 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_LBN 10 #define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_LBN 11 #define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_LBN 12 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_LBN 13 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_LBN 14 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_LBN 15 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_LBN 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_LBN 17 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_LBN 18 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_LBN 19 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_LBN 20 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_LBN 21 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_LBN 22 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_LBN 23 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 /* receive destination */ #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_OFST 20 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_LEN 4 /* enum: drop packets */ #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_DROP 0x0 /* enum: receive to host */ #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_HOST 0x1 /* enum: receive to MC */ #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_MC 0x2 /* enum: loop back to TXDP 0 */ #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX0 0x3 /* enum: loop back to TXDP 1 */ #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX1 0x4 /* receive queue handle (for multiple queue modes, this is the base queue) */ #define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_OFST 24 #define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_LEN 4 /* receive mode */ #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_OFST 28 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_LEN 4 /* enum: receive to just the specified queue */ #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_SIMPLE 0x0 /* enum: receive to multiple queues using RSS context */ #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_RSS 0x1 /* enum: receive to multiple queues using .1p mapping */ #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_DOT1P_MAPPING 0x2 /* enum: install a filter entry that will never match; for test purposes only
*/ #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or * MC_CMD_DOT1P_MAPPING_ALLOC.
*/ #define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_OFST 32 #define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_LEN 4 /* transmit domain (reserved; set to 0) */ #define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_OFST 36 #define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_LEN 4 /* transmit destination (either set the MAC and/or PM bits for explicit * control, or set this field to TX_DEST_DEFAULT for sensible default * behaviour)
*/ #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_OFST 40 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 4 /* enum: request default behaviour (based on filter type) */ #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_OFST 40 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 0 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_WIDTH 1 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_OFST 40 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_LBN 1 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_WIDTH 1 /* source MAC address to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_V3_IN_SRC_MAC_OFST 44 #define MC_CMD_FILTER_OP_V3_IN_SRC_MAC_LEN 6 /* source port to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_V3_IN_SRC_PORT_OFST 50 #define MC_CMD_FILTER_OP_V3_IN_SRC_PORT_LEN 2 /* destination MAC address to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_V3_IN_DST_MAC_OFST 52 #define MC_CMD_FILTER_OP_V3_IN_DST_MAC_LEN 6 /* destination port to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_V3_IN_DST_PORT_OFST 58 #define MC_CMD_FILTER_OP_V3_IN_DST_PORT_LEN 2 /* Ethernet type to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_OFST 60 #define MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_LEN 2 /* Inner VLAN tag to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_OFST 62 #define MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_LEN 2 /* Outer VLAN tag to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_OFST 64 #define MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_LEN 2 /* IP protocol to match (in low byte; set high byte to 0) */ #define MC_CMD_FILTER_OP_V3_IN_IP_PROTO_OFST 66 #define MC_CMD_FILTER_OP_V3_IN_IP_PROTO_LEN 2 /* Firmware defined register 0 to match (reserved; set to 0) */ #define MC_CMD_FILTER_OP_V3_IN_FWDEF0_OFST 68 #define MC_CMD_FILTER_OP_V3_IN_FWDEF0_LEN 4 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP * protocol is GRE) to match (as bytes in network order; set last byte to 0 for * VXLAN/NVGRE, or 1 for Geneve)
*/ #define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_OFST 72 #define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_LEN 4 #define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_OFST 72 #define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_LBN 0 #define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_WIDTH 24 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_OFST 72 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_LBN 24 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_WIDTH 8 /* enum: Match VXLAN traffic with this VNI */ #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_VXLAN 0x0 /* enum: Match Geneve traffic with this VNI */ #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x1 /* enum: Reserved for experimental development use */ #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe #define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_OFST 72 #define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 0 #define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_WIDTH 24 #define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_OFST 72 #define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_LBN 24 #define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_WIDTH 8 /* enum: Match NVGRE traffic with this VSID */ #define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_NVGRE 0x0 /* source IP address to match (as bytes in network order; set last 12 bytes to * 0 for IPv4 address)
*/ #define MC_CMD_FILTER_OP_V3_IN_SRC_IP_OFST 76 #define MC_CMD_FILTER_OP_V3_IN_SRC_IP_LEN 16 /* destination IP address to match (as bytes in network order; set last 12 * bytes to 0 for IPv4 address)
*/ #define MC_CMD_FILTER_OP_V3_IN_DST_IP_OFST 92 #define MC_CMD_FILTER_OP_V3_IN_DST_IP_LEN 16 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network * order)
*/ #define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_OFST 108 #define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_LEN 6 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */ #define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_OFST 114 #define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_LEN 2 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in * network order)
*/ #define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_OFST 116 #define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_LEN 6 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network * order)
*/ #define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_OFST 122 #define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_LEN 2 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)
*/ #define MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_OFST 124 #define MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_LEN 2 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)
*/ #define MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_OFST 126 #define MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_LEN 2 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)
*/ #define MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_OFST 128 #define MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_LEN 2 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to * 0)
*/ #define MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_OFST 130 #define MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_LEN 2 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set * to 0)
*/ #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_OFST 132 #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_LEN 4 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set * to 0)
*/ #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_OFST 136 #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_LEN 4 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network * order; set last 12 bytes to 0 for IPv4 address)
*/ #define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_OFST 140 #define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_LEN 16 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network * order; set last 12 bytes to 0 for IPv4 address)
*/ #define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_OFST 156 #define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_LEN 16 /* Set an action for all packets matching this filter. The DPDK driver and dpdk * f/w variant use their own specific delivery structures, which are documented * in the DPDK Firmware Driver Interface (SF-119419-TC). Requesting anything * other than MATCH_ACTION_NONE when the NIC is running another f/w variant * will cause the filter insertion to fail with ENOTSUP.
*/ #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_OFST 172 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_LEN 4 /* enum: do nothing extra */ #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_NONE 0x0 /* enum: Set the match flag in the packet prefix for packets matching the * filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to * support the DPDK rte_flow "FLAG" action.
*/ #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAG 0x1 /* enum: Insert MATCH_MARK_VALUE into the packet prefix for packets matching * the filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to * support the DPDK rte_flow "MARK" action.
*/ #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x2 /* the mark value for MATCH_ACTION_MARK. Requesting a value larger than the * maximum (obtained from MC_CMD_GET_CAPABILITIES_V5/FILTER_ACTION_MARK_MAX) * will cause the filter insertion to fail with EINVAL.
*/ #define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_OFST 176 #define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_LEN 4
/* MC_CMD_FILTER_OP_OUT msgresponse */ #define MC_CMD_FILTER_OP_OUT_LEN 12 /* identifies the type of operation requested */ #define MC_CMD_FILTER_OP_OUT_OP_OFST 0 #define MC_CMD_FILTER_OP_OUT_OP_LEN 4 /* Enum values, see field(s): */ /* MC_CMD_FILTER_OP_IN/OP */ /* Returned filter handle (for insert / subscribe operations). Note that these * handles should be considered opaque to the host, although a value of * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
*/ #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 #define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8 /* enum: guaranteed invalid filter handle (low 32 bits) */ #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff /* enum: guaranteed invalid filter handle (high 32 bits) */ #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff
/* MC_CMD_FILTER_OP_EXT_OUT msgresponse */ #define MC_CMD_FILTER_OP_EXT_OUT_LEN 12 /* identifies the type of operation requested */ #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0 #define MC_CMD_FILTER_OP_EXT_OUT_OP_LEN 4 /* Enum values, see field(s): */ /* MC_CMD_FILTER_OP_EXT_IN/OP */ /* Returned filter handle (for insert / subscribe operations). Note that these * handles should be considered opaque to the host, although a value of * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
*/ #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8 /* Enum values, see field(s): */ /* MC_CMD_FILTER_OP_OUT/HANDLE */
/***********************************/ /* MC_CMD_GET_PARSER_DISP_INFO * Get information related to the parser-dispatcher subsystem
*/ #define MC_CMD_GET_PARSER_DISP_INFO 0xe4 #undef MC_CMD_0xe4_PRIVILEGE_CTG
/* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */ #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4 /* identifies the type of operation requested */ #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 4 /* enum: read the list of supported RX filter matches */ #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1 /* enum: read flags indicating restrictions on filter insertion for the calling * client
*/ #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2 /* enum: read properties relating to security rules (Medford-only; for use by * SolarSecure apps, not directly by drivers. See SF-114946-SW.)
*/ #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3 /* enum: read the list of supported RX filter matches for VXLAN/NVGRE * encapsulated frames, which follow a different match sequence to normal * frames (Medford only)
*/ #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4 /* enum: read the list of supported matches for the encapsulation detection * rules inserted by MC_CMD_VNIC_ENCAP_RULE_ADD. (ef100 and later)
*/ #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES 0x5
/* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX_MCDI2 1020 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num)) #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4) /* identifies the type of operation requested */ #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 4 /* Enum values, see field(s): */ /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ /* number of supported match types */ #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_LEN 4 /* array of supported match types (valid MATCH_FIELDS values for * MC_CMD_FILTER_OP) sorted in decreasing priority order
*/ #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM_MCDI2 253
/* MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT msgresponse: This response is * returned if a MC_CMD_GET_PARSER_DISP_INFO_IN request is sent with OP value * OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES. It contains information about the * supported match types that can be used in the encapsulation detection rules * inserted by MC_CMD_VNIC_ENCAP_RULE_ADD.
*/ #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMIN 8 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMAX 252 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMAX_MCDI2 1020 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LEN(num) (8+4*(num)) #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4) /* The op code OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES is returned. */ #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_OFST 0 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_LEN 4 /* Enum values, see field(s): */ /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ /* number of supported match types */ #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_OFST 4 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_LEN 4 /* array of supported match types (valid MATCH_FLAGS values for * MC_CMD_VNIC_ENCAP_RULE_ADD) sorted in decreasing priority order
*/ #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_OFST 8 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_LEN 4 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MINNUM 0 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MAXNUM 61 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MAXNUM_MCDI2 253
/***********************************/ /* MC_CMD_GET_PORT_ASSIGNMENT * Get port assignment for current PCI function.
*/ #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8 #undef MC_CMD_0xb8_PRIVILEGE_CTG
/* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 /* Identifies the port assignment for this function. */ #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4
/***********************************/ /* MC_CMD_SET_PORT_ASSIGNMENT * Set port assignment for current PCI function.
*/ #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 #undef MC_CMD_0xb9_PRIVILEGE_CTG
#define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN
/* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 /* Identifies the port assignment for this function. */ #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_LEN 4
/* MC_CMD_ALLOC_VIS_IN msgrequest */ #define MC_CMD_ALLOC_VIS_IN_LEN 8 /* The minimum number of VIs that is acceptable */ #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_LEN 4 /* The maximum number of VIs that would be useful */ #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_LEN 4
/* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request. * Use extended version in new code.
*/ #define MC_CMD_ALLOC_VIS_OUT_LEN 8 /* The number of VIs allocated on this function */ #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_LEN 4 /* The base absolute VI number allocated to this function. Required to * correctly interpret wakeup events.
*/ #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_LEN 4
/* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */ #define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12 /* The number of VIs allocated on this function */ #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_LEN 4 /* The base absolute VI number allocated to this function. Required to * correctly interpret wakeup events.
*/ #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_LEN 4 /* Function's port vi_shift value (always 0 on Huntington) */ #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 4
/***********************************/ /* MC_CMD_FREE_VIS * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, * but not freed.
*/ #define MC_CMD_FREE_VIS 0x8c #undef MC_CMD_0x8c_PRIVILEGE_CTG
/* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 /* Number of VFs currently enabled. */ #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_LEN 4 /* Max number of VFs before sriov stride and offset may need to be changed. */ #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 4 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 4 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_OFST 8 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 /* RID offset of first VF from PF. */ #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_LEN 4 /* RID offset of each subsequent VF from the previous. */ #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 4
/***********************************/ /* MC_CMD_SET_SRIOV_CFG * Set SRIOV config for this PF.
*/ #define MC_CMD_SET_SRIOV_CFG 0xbb #undef MC_CMD_0xbb_PRIVILEGE_CTG
#define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
/* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 /* Number of VFs currently enabled. */ #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_LEN 4 /* Max number of VFs before sriov stride and offset may need to be changed. */ #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 4 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 4 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_OFST 8 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 /* RID offset of first VF from PF, or 0 for no change, or * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset.
*/ #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_LEN 4 /* RID offset of each subsequent VF from the previous, 0 for no change, or * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride.
*/ #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_LEN 4
/***********************************/ /* MC_CMD_GET_VI_ALLOC_INFO * Get information about number of VI's and base VI number allocated to this * function.
*/ #define MC_CMD_GET_VI_ALLOC_INFO 0x8d #undef MC_CMD_0x8d_PRIVILEGE_CTG
/* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12 /* The number of VIs allocated on this function */ #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_LEN 4 /* The base absolute VI number allocated to this function. Required to * correctly interpret wakeup events.
*/ #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_LEN 4 /* Function's port vi_shift value (always 0 on Huntington) */ #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_LEN 4
/***********************************/ /* MC_CMD_DUMP_VI_STATE * For CmdClient use. Dump pertinent information on a specific absolute VI.
*/ #define MC_CMD_DUMP_VI_STATE 0x8e #undef MC_CMD_0x8e_PRIVILEGE_CTG
/* MC_CMD_DUMP_VI_STATE_IN msgrequest */ #define MC_CMD_DUMP_VI_STATE_IN_LEN 4 /* The VI number to query. */ #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4
/* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ #define MC_CMD_DUMP_VI_STATE_OUT_LEN 96 /* The PF part of the function owning this VI. */ #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 /* The VF part of the function owning this VI. */ #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 /* Base of VIs allocated to this function. */ #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 /* Count of VIs allocated to the owner function. */ #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 /* Base interrupt vector allocated to this function. */ #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 /* Number of interrupt vectors allocated to this function. */ #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 /* Raw evq ptr table data. */ #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 /* Raw evq timer table data. */ #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 /* Combined metadata field. */ #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_OFST 28 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_OFST 28 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_OFST 28 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 /* TXDPCPU raw table data for queue. */ #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 /* TXDPCPU raw table data for queue. */ #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 /* TXDPCPU raw table data for queue. */ #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 /* Combined metadata field. */ #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_OFST 56 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_OFST 56 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_OFST 56 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_OFST 56 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_OFST 56 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 /* RXDPCPU raw table data for queue. */ #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 /* RXDPCPU raw table data for queue. */ #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 /* Reserved, currently 0. */ #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 /* Combined metadata field. */ #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_OFST 88 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_OFST 88 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_OFST 88 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_OFST 88 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8
/***********************************/ /* MC_CMD_ALLOC_PIOBUF * Allocate a push I/O buffer for later use with a tx queue.
*/ #define MC_CMD_ALLOC_PIOBUF 0x8f #undef MC_CMD_0x8f_PRIVILEGE_CTG
/***********************************/ /* MC_CMD_GET_CAPABILITIES * Get device capabilities. * * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to * reference inherent device capabilities as opposed to current NVRAM config.
*/ #define MC_CMD_GET_CAPABILITIES 0xbe #undef MC_CMD_0xbe_PRIVILEGE_CTG
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