/* SPDX-License-Identifier: GPL-2.0-or-later */ /*------------------------------------------------------------------------ . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device. . . Copyright (C) 1996 by Erik Stahlman . Copyright (C) 2001 Standard Microsystems Corporation . Developed by Simple Network Magic Corporation . Copyright (C) 2003 Monta Vista Software, Inc. . Unified SMC91x driver by Nicolas Pitre . . . Information contained in this file was obtained from the LAN91C111 . manual from SMC. To get a copy, if you really want one, you can find . information under www.smsc.com. . . Authors . Erik Stahlman <erik@vt.edu> . Daris A Nevil <dnevil@snmc.com> . Nicolas Pitre <nico@fluxnic.net> .
---------------------------------------------------------------------------*/ #ifndef _SMC91X_H_ #define _SMC91X_H_
/* * Any 16-bit access is performed with two 8-bit accesses if the hardware * can't do it directly. Most registers are 16-bit so those are mandatory.
*/ #define SMC_outw_b(x, a, r) \ do { \ unsignedint __val16 = (x); \ unsignedint __reg = (r); \
SMC_outb(__val16, a, __reg); \
SMC_outb(__val16 >> 8, a, __reg + (1 << SMC_IO_SHIFT)); \
} while (0)
/* * Define your architecture specific bus configuration parameters here.
*/
#ifdefined(CONFIG_ARM)
#include <asm/mach-types.h>
/* Now the bus width is specified in the platform data * pretend here to support all I/O access types
*/ #define SMC_CAN_USE_8BIT 1 #define SMC_CAN_USE_16BIT 1 #define SMC_CAN_USE_32BIT 1 #define SMC_NOWAIT 1
/* store this information for the driver.. */ struct smc_local { /* * If I have to wait until memory is available to send a * packet, I will store the skbuff here, until I get the * desired memory. Then, I'll send it out and free it.
*/ struct sk_buff *pending_tx_skb; struct tasklet_struct tx_task;
/* work queue */ struct work_struct phy_configure; struct net_device *dev; int work_pending;
spinlock_t lock;
#ifdef CONFIG_ARCH_PXA /* DMA needs the physical address of the chip */
u_long physaddr; struct device *device; #endif struct dma_chan *dma_chan; void __iomem *base; void __iomem *datacs;
/* the low address lines on some platforms aren't connected... */ int io_shift; /* on some platforms a u16 write must be 4-bytes aligned */ bool half_word_align4;
#ifdef CONFIG_ARCH_PXA /* * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is * always happening in irq context so no need to worry about races. TX is * different and probably not worth it for that reason, and not as critical * as RX which can overrun memory and lose packets.
*/ #include <linux/dma-mapping.h>
len *= 2;
smc_pxa_dma_inpump(lp, buf, len);
} #endif
#endif/* CONFIG_ARCH_PXA */
/* * Everything a particular hardware setup needs should have been defined * at this point. Add stubs for the undefined cases, mainly to avoid * compilation warnings since they'll be optimized away, or to prevent buggy * use of them.
*/
/* Because of bank switching, the LAN91x uses only 16 I/O ports */ #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT) #define SMC_DATA_EXTENT (4)
/* . Bank Select Register: . . yyyy yyyy 0000 00xx . xx = bank number . yyyy yyyy = 0x33, for identification purposes.
*/ #define BANK_SELECT (14 << SMC_IO_SHIFT)
// Transmit Control Register /* BANK 0 */ #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0) #define TCR_ENABLE 0x0001 // When 1 we can transmit #define TCR_LOOP 0x0002 // Controls output pin LBK #define TCR_FORCOL 0x0004 // When 1 will force a collision #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
#define TCR_CLEAR 0 /* do NOTHING */ /* the default settings for the TCR register : */ #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
// EPH Status Register /* BANK 0 */ #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0) #define ES_TX_SUC 0x0001 // Last TX was successful #define ES_SNGL_COL 0x0002 // Single collision detected for last tx #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx #define ES_LTX_MULT 0x0008 // Last tx was a multicast #define ES_16COL 0x0010 // 16 Collisions Reached #define ES_SQET 0x0020 // Signal Quality Error Test #define ES_LTXBRD 0x0040 // Last tx was a broadcast #define ES_TXDEFR 0x0080 // Transmit Deferred #define ES_LATCOL 0x0200 // Late collision detected on last tx #define ES_LOSTCARR 0x0400 // Lost Carrier Sense #define ES_EXC_DEF 0x0800 // Excessive Deferral #define ES_CTR_ROL 0x1000 // Counter Roll Over indication #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin #define ES_TXUNRN 0x8000 // Tx Underrun
// Receive Control Register /* BANK 0 */ #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0) #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted #define RCR_PRMS 0x0002 // Enable promiscuous mode #define RCR_ALMUL 0x0004 // When set accepts all multicast frames #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier #define RCR_SOFTRST 0x8000 // resets the chip
/* the normal settings for the RCR register : */ #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) #define RCR_CLEAR 0x0 // set it to a base state
// Memory Information Register /* BANK 0 */ #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
// Receive/Phy Control Register /* BANK 0 */ #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0) #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
// Bank Select Register /* All Banks */ #define BSR_REG 0x000E
// Configuration Reg /* BANK 1 */ #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1) #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
// Base Address Register /* BANK 1 */ #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
// General Purpose Register /* BANK 1 */ #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
// Control Register /* BANK 1 */ #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1) #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers #define CTL_STORE 0x0001 // When set stores registers into EEPROM
// MMU Command Register /* BANK 2 */ #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2) #define MC_BUSY 1 // When 1 the last release has not completed #define MC_NOP (0<<5) // No Op #define MC_ALLOC (1<<5) // OR with number of 256 byte packets #define MC_RESET (2<<5) // Reset MMU to initial state #define MC_REMOVE (3<<5) // Remove the current rx packet #define MC_RELEASE (4<<5) // Remove and release the current rx packet #define MC_FREEPKT (5<<5) // Release packet in PNR register #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
// Packet Number Register /* BANK 2 */ #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
// Allocation Result Register /* BANK 2 */ #define AR_REG(lp) SMC_REG(lp, 0x0003, 2) #define AR_FAILED 0x80 // Alocation Failed
// Pointer Register /* BANK 2 */ #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2) #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access #define PTR_READ 0x2000 // When 1 the operation is a read
// Data Register /* BANK 2 */ #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
// Early RCV Register /* BANK 3 */ /* this is NOT on SMC9192 */ #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3) #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
/* * PHY Register Addresses (LAN91C111 Internal PHY) * * Generic PHY registers can be found in <linux/mii.h> * * These phy registers are specific to our on-board phy.
*/
/* * Macros to abstract register access according to the data bus * capabilities. Please use those and not the in/out primitives. * Note: the following macros do *not* select the bank -- this must * be done separately as needed in the main code. The SMC_REG() macro * only uses the bank argument for debugging purposes (when enabled). * * Note: despite inline functions being safer, everything leading to this * should preferably be macros to let BUG() display the line number in * the core source code since we're interested in the top call site * not in any inline function location.
*/
/* * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not * aligned to a 32 bit boundary. I tell you that does exist! * Fortunately the affected register accesses can be easily worked around * since we can write zeroes to the preceding 16 bits without adverse * effects and use a 32-bit access. * * Enforce it on any 32-bit capable setup for now.
*/ #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
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