// SPDX-License-Identifier: GPL-2.0-or-later /* Copyright ( C ) 2010 Willow Garage < http : //www.willowgarage.com> Copyright ( C ) 2010 Ivo van Doorn < IvDoorn @ gmail . com > Copyright ( C ) 2009 Bartlomiej Zolnierkiewicz < bzolnier @ gmail . com > Copyright ( C ) 2009 Gertjan van Wingerde < gwingerde @ gmail . com > Based on the original rt2800pci . c and rt2800usb . c . Copyright ( C ) 2009 Alban Browaeys < prahal @ yahoo . com > Copyright ( C ) 2009 Felix Fietkau < nbd @ openwrt . org > Copyright ( C ) 2009 Luis Correia < luis . f . correia @ gmail . com > Copyright ( C ) 2009 Mattias Nissler < mattias . nissler @ gmx . de > Copyright ( C ) 2009 Mark Asselstine < asselsm @ gmail . com > Copyright ( C ) 2009 Xose Vazquez Perez < xose . vazquez @ gmail . com > < http : //rt2x00.serialmonkey.com> /* Module : rt2800lib Abstract : rt2800 generic device routines . #include <linux/crc-ccitt.h>#include <linux/kernel.h>#include <linux/module.h>#include <linux/slab.h>#include "rt2x00.h" #include "rt2800lib.h" #include "rt2800.h" static unsigned int modparam_watchdog = RT2800_WATCHDOG_DMA_BUSY;0444 );"Enable watchdog to recover tx/rx hangs.\n" "\t\t(0=disabled, 1=hang watchdog, 2=DMA watchdog(default), 3=both)" );/* * Register access . * All access to the CSR registers will go through the methods * rt2800_register_read and rt2800_register_write . * BBP and RF register require indirect register access , * and use the CSR registers BBPCSR and RFCSR to achieve this . * These indirect registers work with busy bits , * and we will try maximal REGISTER_BUSY_COUNT times to access * the register while taking a REGISTER_BUSY_DELAY us delay * between each attampt . When the busy bit is still set at that time , * the access attempt is considered to have failed , * and we will print an error . * The _ lock versions must be used if you already hold the csr_mutex #define WAIT_FOR_BBP(__dev, __reg) \#define WAIT_FOR_RFCSR(__dev, __reg) \#define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \#define WAIT_FOR_RF(__dev, __reg) \#define WAIT_FOR_MCU(__dev, __reg) \static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)/* check for rt2872 on SoC */ if (!rt2x00_is_soc(rt2x00dev) ||return false ;/* we know for sure that these rf chipsets are used on rt305x boards */ if (rt2x00_rf(rt2x00dev, RF3020) ||return true ;"Unknown RF chipset on rt305x\n" );return false ;static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,const unsigned int word, const u8 value)/* * Wait until the BBP becomes available , afterwards we * can safely write the new data into the register . if (WAIT_FOR_BBP(rt2x00dev, ®)) {0 ;1 );0 );1 );static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word)/* * Wait until the BBP becomes available , afterwards we * can safely write the read request into the register . * After the data has been written , we wait until hardware * returns the correct value , if at any time the register * doesn ' t become available in time , reg will be 0 xffffffff * which means we return 0 xff to the caller . if (WAIT_FOR_BBP(rt2x00dev, ®)) {0 ;1 );1 );1 );return value;static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,const unsigned int word, const u8 value)/* * Wait until the RFCSR becomes available , afterwards we * can safely write the new data into the register . switch (rt2x00dev->chip.rt) {case RT6352:if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) {0 ;1 );1 );break ;default :if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {0 ;1 );1 );break ;static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,const unsigned int reg, const u8 value)6 )), value);static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,const unsigned int reg, const u8 value)4 , reg, value);6 , reg, value);static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,const unsigned int reg, const u8 value)5 , reg, value);7 , reg, value);static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,const u8 reg, const u8 value)158 , reg);159 , value);static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg)158 , reg);return rt2800_bbp_read(rt2x00dev, 159 );static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,const u8 reg, const u8 value)195 , reg);196 , value);static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,const unsigned int word)/* * Wait until the RFCSR becomes available , afterwards we * can safely write the read request into the register . * After the data has been written , we wait until hardware * returns the correct value , if at any time the register * doesn ' t become available in time , reg will be 0 xffffffff * which means we return 0 xff to the caller . switch (rt2x00dev->chip.rt) {case RT6352:if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) {0 ;0 );1 );break ;default :if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {0 ;0 );1 );break ;return value;static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,const unsigned int reg)return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6 )));static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,const unsigned int word, const u32 value)/* * Wait until the RF becomes available , afterwards we * can safely write the new data into the register . if (WAIT_FOR_RF(rt2x00dev, ®)) {0 ;0 );0 );1 );static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {0 x0000,0 x0001,0 x0002,0 x0003,0 x0004,0 x001a,0 x001b,0 x001d,0 x001e,0 x001f,0 x0020,0 x0021,0 x0022,0 x0023,0 x0024,0 x0024, /* overlaps with RSSI_BG2 */ 0 x0025,0 x0026,0 x0026, /* overlaps with RSSI_A2 */ 0 x0027,0 x0028,0 x0029,0 x0030,0 x0037,0 x0038,0 x0039,0 x003a,0 x003b,0 x003c,0 x0053,0 x0068,0 x006a,0 x006b,0 x006c,0 x006d,0 x006e,0 x006f,0 x0078,static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {0 x0000,0 x0001,0 x0002,0 x0003,0 x0004,0 x001a,0 x001b,0 x001c,0 x0020,0 x0022,0 x0023,0 x0024,0 x0025,0 x0026,0 x0027,0 x0028,0 x0029,0 x002a,0 x002b,0 x0030,0 x0037,0 x003e,0 x0045,0 x0046,0 x0047,0 x0048,0 x0049,0 x004b,0 x0065,0 x007f,0 x009a,0 x009b,0 x009c,0 x009d,0 x009e,0 x00a0,static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,const enum rt2800_eeprom_word word)const unsigned int *map;unsigned int index;if (WARN_ONCE(word >= EEPROM_WORD_COUNT,"%s: invalid EEPROM word %d\n" ,return 0 ;if (rt2x00_rt(rt2x00dev, RT3593) ||else /* Index 0 is valid only for EEPROM_CHIP_ID. * Otherwise it means that the offset of the * given word is not initialized in the map , * or that the field is not usable on the * actual chipset . 0 ,"%s: invalid access of EEPROM word %d\n" ,return index;static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,const enum rt2800_eeprom_word word)unsigned int index;return rt2x00_eeprom_addr(rt2x00dev, index);static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,const enum rt2800_eeprom_word word)unsigned int index;return rt2x00_eeprom_read(rt2x00dev, index);static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,const enum rt2800_eeprom_word word, u16 data)unsigned int index;static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,const enum rt2800_eeprom_word array,unsigned int offset)unsigned int index;return rt2x00_eeprom_read(rt2x00dev, index + offset);static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)int i, count;0 xff);1 );0 );1 );0 ;do {/* * Check PLL_LD & XTAL_RDY . for (i = 0 ; i < REGISTER_BUSY_COUNT; i++) {if (rt2x00_get_field32(reg, PLL_LD) &&break ;if (i >= REGISTER_BUSY_COUNT) {if (count >= 10 )return -EIO;0 x58, 0 x018);0 x58, 0 x418);0 x58, 0 x618);else {0 ;0 );1 );1 );10 );0 );10 );0 x7fffffff);while (count != 0 );return 0 ;void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,const u8 command, const u8 token,const u8 arg0, const u8 arg1)/* * SOC devices don ' t support MCU requests . if (rt2x00_is_soc(rt2x00dev))return ;/* * Wait until the MCU becomes available , afterwards we * can safely write the new data into the register . if (WAIT_FOR_MCU(rt2x00dev, ®)) {1 );0 ;int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)unsigned int i = 0 ;for (i = 0 ; i < REGISTER_BUSY_COUNT; i++) {if (reg && reg != ~0 )return 0 ;1 );"Unstable hardware\n" );return -EBUSY;int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)unsigned int i;/* * Some devices are really slow to respond here . Wait a whole second * before timing out . for (i = 0 ; i < REGISTER_BUSY_COUNT; i++) {if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&return 0 ;10 );"WPDMA TX/RX busy [0x%08x]\n" , reg);return -EACCES;void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)0 );0 );0 );0 );1 );void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,unsigned short *txwi_size,unsigned short *rxwi_size)switch (rt2x00dev->chip.rt) {case RT3593:case RT3883:break ;case RT5592:case RT6352:break ;default :break ;static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)/* * The last 2 bytes in the firmware array are the crc checksum itself , * this means that we should never pass those 2 bytes to the crc * algorithm . 2 ] << 8 | data[len - 1 ]);/* * Use the crc ccitt algorithm . * This will return the same value as the legacy driver which * used bit ordering reversion on both the firmware bytes * before input input as well as on the final output . * Obviously using crc ccitt directly is much more efficient . 0 , data, len - 2 );/* * There is a small difference between the crc - itu - t + bitrev and * the crc - ccitt crc calculation . In the latter method the 2 bytes * will be swapped , use swab16 to convert the crc to the correct * value . return fw_crc == crc;int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,const u8 *data, const size_t len)0 ;bool multiple;/* * PCI ( e ) & SOC devices require firmware with a length * of 8 kb . USB devices require firmware files with a length * of 4 kb . Certain USB chipsets however require different firmware , * which Ralink only provides attached to the original firmware * file . Thus for USB devices , firmware files have a length * which is a multiple of 4 kb . The firmware for rt3290 chip also * have a length which is a multiple of 4 kb . if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))4096 ;else 8192 ;true ;/* * Validate the firmware length if (len != fw_len && (!multiple || (len % fw_len) != 0 ))return FW_BAD_LENGTH;/* * Check if the chipset requires one of the upper parts * of the firmware . if (rt2x00_is_usb(rt2x00dev) &&1 ))return FW_BAD_VERSION;/* * 8 kb firmware files must be checked as if it were * 2 separate firmware files . while (offset < len) {if (!rt2800_check_firmware_crc(data + offset, fw_len))return FW_BAD_CRC;return FW_OK;int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,const u8 *data, const size_t len)unsigned int i;int retval;if (rt2x00_rt(rt2x00dev, RT3290)) {if (retval)return -EBUSY;/* * If driver doesn ' t wake up firmware here , * rt2800_load_firmware will hang forever when interface is up again . 0 x00000000);/* * Wait for stable hardware . if (rt2800_wait_csr_ready(rt2x00dev))return -EBUSY;if (rt2x00_is_pci(rt2x00dev)) {if (rt2x00_rt(rt2x00dev, RT3290) ||1 );1 );0 x00000002);/* * Write firmware to the device . /* * Wait for device to stabilize . for (i = 0 ; i < REGISTER_BUSY_COUNT; i++) {if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))break ;1 );if (i == REGISTER_BUSY_COUNT) {"PBF system register not ready\n" );return -EBUSY;/* * Disable DMA , will be reenabled later when enabling * the radio . /* * Initialize firmware . 0 );0 );if (rt2x00_is_usb(rt2x00dev)) {0 );0 , 0 , 0 );1 );return 0 ;void rt2800_write_tx_data(struct queue_entry *entry,struct txentry_desc *txdesc)int i;/* * Initialize TX Info descriptor 0 );0 );0 , word);1 );3 ) + 1 );1 , word);/* * Always write 0 to IV / EIV fields ( word 2 and 3 ) , hardware will insert * the IV from the IVEIV register when TXD_W3_WIV is set to 0 . * When TXD_W3_WIV is set to 1 it will use the IV data * from the descriptor . The TXWI_W1_WIRELESS_CLI_ID indicates which * crypto entry in the registers should be used to encrypt the frame . * * Nulify all remaining words as well , we don ' t know how to program them . for (i = 2 ; i < entry->queue->winfo_size / sizeof (__le32); i++)0 );static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)2 : -12 ;if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {else {/* * Convert the value from the descriptor into the RSSI value * If the value in the descriptor is 0 , it is considered invalid * and the default ( extremely low ) rssi value is assumed 128 ;128 ;128 ;/* * mac80211 only accepts a single RSSI value . Calculating the * average doesn ' t deliver a fair answer either since - 60 : - 60 would * be considered equally good as - 50 : - 70 while the second is the one * which gives less energy . . . return (int )max(rssi0, rssi2);void rt2800_process_rxwi(struct queue_entry *entry,struct rxdone_entry_desc *rxdesc)0 );1 );if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))if (rt2x00_get_field32(word, RXWI_W1_BW))/* * Detect RX rate , always use MCS as signal type . /* * Mask of 0 x8 bit to remove the short preamble flag . if (rxdesc->rate_mode == RATE_MODE_CCK)0 x8;2 );/* * Convert descriptor AGC value to RSSI value . /* * Remove RXWI descriptor from start of the buffer . static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc,enum nl80211_band band)0 ;switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) {case RATE_MODE_HT_GREENFIELD:case RATE_MODE_HT_MIX:break ;case RATE_MODE_OFDM:if (band == NL80211_BAND_2GHZ)4 ;break ;case RATE_MODE_CCK:if (idx >= 8 )8 ;break ;if (rt2x00_get_field32(status, TX_STA_FIFO_BW))if (rt2x00_get_field32(status, TX_STA_FIFO_SGI))static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)int wcid, ack, pid;int tx_wcid, tx_ack, tx_pid, is_agg;/* * This frames has returned with an IO error , * so the status report is not intended for this * frame . if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags))return false ;/* * Validate if this TX status report is intended for * this entry by comparing the WCID / ACK / PID fields . 1 );if (wcid != tx_wcid || ack != tx_ack || (!is_agg && pid != tx_pid)) {"TX status report missed for queue %d entry %d\n" ,return false ;return true ;void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi,bool match)struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);struct txdone_entry_desc txdesc;int aggr, ampdu, wcid, ack_req;/* * Obtain the status about this packet . 0 ;0 );/* * If a frame was meant to be sent as a single non - aggregated MPDU * but ended up in an aggregate the used tx rate doesn ' t correlate * with the one specified in the TXWI as the whole aggregate is sent * with the same rate . * * For example : two frames are sent to rt2x00 , the first one sets * AMPDU = 1 and requests MCS7 whereas the second frame sets AMDPU = 0 * and requests MCS15 . If the hw aggregates both frames into one * AMDPU the tx status for both frames will contain MCS7 although * the frame was sent successfully . * * Hence , replace the requested rate with the real tx rate to not * confuse the rate control algortihm by providing clearly wrong * data . * * FIXME : if we do not find matching entry , we tell that frame was * posted without any retries . We need to find a way to fix that * and provide retry count . if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) {if (aggr == 1 || ampdu == 1 )if (!ack_req)/* * Ralink has a retry mechanism using a global fallback * table . We setup this fallback table to try the immediate * lower rate for all rates . In the TX_STA_FIFO , the MCS field * always contains the MCS used for the last transmission , be * it successful or not . if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {/* * Transmission succeeded . The number of retries is * mcs - real_mcs 0 );else {/* * Transmission failed . The number of retries is * always 7 in this case ( for a total number of 8 * frames sent ) . /* * the frame was retried at least once * - > hw used fallback rates if (txdesc.retry)if (!match) {/* RCU assures non-null sta will not be freed by mac80211. */ if (likely(wcid >= WCID_START && wcid <= WCID_END))else else {void rt2800_txdone(struct rt2x00_dev *rt2x00dev, unsigned int quota)struct data_queue *queue;struct queue_entry *entry;bool match;while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, ®)) {/* * TX_STA_FIFO_PID_QUEUE is a 2 - bit field , thus qid is * guaranteed to be one of the TX QIDs . if (unlikely(rt2x00queue_empty(queue))) {"Got TX status for an empty queue %u, dropping\n" ,break ;if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||"Data pending for entry %u in queue %u\n" ,break ;static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev,struct queue_entry *entry)bool ret;unsigned long tout;if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))return false ;if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags))50 );else 2000 );if (unlikely(ret))"TX status timeout for entry %d in queue %d\n" ,return ret;bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev)struct data_queue *queue;struct queue_entry *entry;if (rt2800_entry_txstatus_timeout(rt2x00dev, entry))return true ;return false ;/* * test if there is an entry in any TX queue for which DMA is done * but the TX status has not been returned yet bool rt2800_txstatus_pending(struct rt2x00_dev *rt2x00dev)struct data_queue *queue;if (rt2x00queue_get_entry(queue, Q_INDEX_DMA_DONE) !=return true ;return false ;void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev)struct data_queue *queue;struct queue_entry *entry;/* * Process any trailing TX status reports for IO failures , * we loop until we find the first non - IO error entry . This * can either be a frame which is free , is being uploaded , * or has completed the upload but didn ' t have an entry * in the TX_STAT_FIFO register yet . while (!rt2x00queue_empty(queue)) {if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||break ;if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) ||else break ;static bool rt2800_check_hung(struct data_queue *queue)unsigned int cur_idx = rt2800_drv_get_dma_done(queue);if (queue->wd_idx != cur_idx) {0 ;else return queue->wd_count > 16 ;static void rt2800_update_survey(struct rt2x00_dev *rt2x00dev)struct ieee80211_channel *chan = rt2x00dev->hw->conf.chandef.chan;struct rt2x00_chan_survey *chan_survey =static bool rt2800_watchdog_hung(struct rt2x00_dev *rt2x00dev)struct data_queue *queue;bool hung_tx = false ;bool hung_rx = false ;switch (queue->qid) {case QID_AC_VO:case QID_AC_VI:case QID_AC_BE:case QID_AC_BK:case QID_MGMT:if (rt2x00queue_empty(queue))continue ;break ;case QID_RX:/* For station mode we should reactive at least * beacons . TODO : need to find good way detect * RX hung for AP mode . if (rt2x00dev->intf_sta_count == 0 )continue ;break ;default :break ;if (!hung_tx && !hung_rx)return false ;if (hung_tx)"Watchdog TX hung detected\n" );if (hung_rx)"Watchdog RX hung detected\n" );0 ;return true ;static bool rt2800_watchdog_dma_busy(struct rt2x00_dev *rt2x00dev)bool busy_rx, busy_tx;if (rt2x00_get_field32(reg_cfg, WPDMA_GLO_CFG_RX_DMA_BUSY) &&else 0 ;if (rt2x00_get_field32(reg_cfg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&else 0 ;30 ;30 ;if (!busy_rx && !busy_tx)return false ;if (busy_rx)"Watchdog RX DMA busy detected\n" );if (busy_tx)"Watchdog TX DMA busy detected\n" );0 ;0 ;return true ;void rt2800_watchdog(struct rt2x00_dev *rt2x00dev)bool reset = false ;if (test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags))return ;if (rt2x00dev->link.watchdog & RT2800_WATCHDOG_DMA_BUSY)if (rt2x00dev->link.watchdog & RT2800_WATCHDOG_HANG)if (reset)static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,unsigned int index)return HW_BEACON_BASE(index);static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,unsigned int index)return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)struct data_queue *queue = rt2x00dev->bcn;struct queue_entry *entry;int i, bcn_num = 0 ;0 ;/* * Setup offsets of all active beacons in BCN_OFFSET { 0 , 1 } registers . for (i = 0 ; i < queue->limit; i++) {if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))continue ;8 * bcn_num);32 ));/* * H / W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons . 0 ? bcn_num - 1 : 0 );void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);unsigned int beacon_base;unsigned int padding_len;const int txwi_desc_size = entry->queue->winfo_size;/* * Disable beaconing while we are reloading the beacon data , * otherwise we might be sending out invalid data . 0 );/* * Add space for the TXWI in front of the skb . 0 , txwi_desc_size);/* * Register descriptor details in skb frame descriptor . /* * Add the TXWI for the beacon to the skb . /* * Dump beacon to userspace through debugfs . /* * Write entire beacon with TXWI and padding to register . 4 ) - entry->skb->len;if (padding_len && skb_pad(entry->skb, padding_len)) {"Failure padding beacon, aborting\n" );/* skb freed by skb_pad() on failure */ return ;/* * Change global beacons settings . /* * Restore beaconing state . /* * Clean up beacon skb . static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,unsigned int index)int i;const int txwi_desc_size = rt2x00dev->bcn->winfo_size;unsigned int beacon_base;/* * For the Beacon base registers we only need to clear * the whole TXWI which ( when set to 0 ) will invalidate * the entire beacon . for (i = 0 ; i < txwi_desc_size; i += sizeof (__le32))0 );void rt2800_clear_beacon(struct queue_entry *entry)struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;/* * Disable beaconing while we are reloading the beacon data , * otherwise we might be sending out invalid data . 0 );/* * Clear beacon . /* * Change global beacons settings . /* * Restore beaconing state . #ifdef CONFIG_RT2X00_LIB_DEBUGFSconst struct rt2x00debug rt2800_rt2x00debug = {sizeof (u32),sizeof (u32),/* NOTE: The local EEPROM access functions can't * be used here , use the generic versions instead . sizeof (u16),sizeof (u16),sizeof (u8),sizeof (u8),sizeof (u32),sizeof (u32),sizeof (u8),sizeof (u8),#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)if (rt2x00_rt(rt2x00dev, RT3290)) {return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);else {return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);#ifdef CONFIG_RT2X00_LIB_LEDSstatic void rt2800_brightness_set(struct led_classdev *led_cdev,enum led_brightness brightness)struct rt2x00_led *led =struct rt2x00_led, led_dev);unsigned int enabled = brightness != LED_OFF;unsigned int bg_mode =unsigned int polarity =unsigned int ledmode =/* Check for SoC (SOC devices don't support MCU requests) */ if (rt2x00_is_soc(led->rt2x00dev)) {/* Set LED Polarity */ /* Set LED Mode */ if (led->type == LED_TYPE_RADIO) {3 : 0 );else if (led->type == LED_TYPE_ASSOC) {3 : 0 );else if (led->type == LED_TYPE_QUALITY) {3 : 0 );else {if (led->type == LED_TYPE_RADIO) {0 xff, ledmode,0 x20 : 0 );else if (led->type == LED_TYPE_ASSOC) {0 xff, ledmode,0 x60 : 0 xa0) : 0 x20);else if (led->type == LED_TYPE_QUALITY) {/* * The brightness is divided into 6 levels ( 0 - 5 ) , * The specs tell us the following levels : * 0 , 1 , 3 , 7 , 15 , 31 * to determine the level in a simple way we can simply * work with bitshifting : * ( 1 < < level ) - 1 0 xff,1 << brightness / (LED_FULL / 6 )) - 1 ,static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,struct rt2x00_led *led, enum led_type type)#endif /* CONFIG_RT2X00_LIB_LEDS */ /* * Configuration handlers . static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,const u8 *address,int wcid)struct mac_wcid_entry wcid_entry;0 xff, sizeof (wcid_entry));if (address)sizeof (wcid_entry));static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)0 );static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,int wcid, u32 bssidx)/* * The BSS Idx numbers is split in a main value of 3 bits , * and a extended field for adding one additional bit to the value . 0 x7));0 x8) >> 3 );static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,struct rt2x00lib_crypto *crypto,struct ieee80211_key_conf *key)struct mac_iveiv_entry iveiv_entry;if (crypto->cmd == SET_KEY) {/* * Both the cipher as the BSS Idx numbers are split in a main * value of 3 bits , and a extended field for adding one additional * bit to the value . 0 x7));0 x8) >> 3 );else {/* Delete the cipher without touching the bssidx */ 0 );0 );0 );0 );if (test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags))return ;0 , sizeof (iveiv_entry));if ((crypto->cipher == CIPHER_TKIP) ||3 ] |= 0 x20;3 ] |= key->keyidx << 6 ;sizeof (iveiv_entry));int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,struct rt2x00lib_crypto *crypto,struct ieee80211_key_conf *key)struct hw_key_entry key_entry;struct rt2x00_field32 field;if (crypto->cmd == SET_KEY) {4 * crypto->bssidx) + key->keyidx;sizeof (key_entry.key));sizeof (key_entry.tx_mic));sizeof (key_entry.rx_mic));sizeof (key_entry));/* * The cipher types are stored over multiple registers * starting with SHARED_KEY_MODE_BASE each word will have * 32 bits and contains the cipher types for 2 bssidx each . * Using the correct defines correctly will cause overhead , * so just calculate the correct offset . 4 * (key->hw_key_idx % 8 );0 x7 << field.bit_offset;8 );/* * Update WCID information return 0 ;int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,struct rt2x00lib_crypto *crypto,struct ieee80211_key_conf *key)struct hw_key_entry key_entry;if (crypto->cmd == SET_KEY) {/* * Allow key configuration only for STAs that are * known by the hw . if (crypto->wcid > WCID_END)return -ENOSPC;sizeof (key_entry.key));sizeof (key_entry.tx_mic));sizeof (key_entry.rx_mic));sizeof (key_entry));/* * Update WCID information return 0 ;static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev)struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;for (i = 0 ; i < 3 ; i++)if (drv_data->ampdu_factor_cnt[i] > 0 )break ;int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,struct ieee80211_sta *sta)struct rt2x00_dev *rt2x00dev = hw->priv;struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);int wcid;/* * Limit global maximum TX AMPDU length to smallest value of all * connected stations . In AP mode this can be suboptimal , but we * do not have a choice if some connected STA is not capable to * receive the same amount of data like the others . if (sta->deflink.ht_cap.ht_supported) {3 ]++;/* * Search for the first free WCID entry and return the corresponding * index . /* * Store selected wcid even if it is invalid so that we can * later decide if the STA is uploaded into the hw . /* * No space left in the device , however , we can still communicate * with the STA - > No error . if (wcid > WCID_END)return 0 ;/* * Clean up WCID attributes and write STA address to the device . return 0 ;int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,struct ieee80211_sta *sta)struct rt2x00_dev *rt2x00dev = hw->priv;struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);int wcid = sta_priv->wcid;if (sta->deflink.ht_cap.ht_supported) {3 ]--;if (wcid > WCID_END)return 0 ;/* * Remove WCID entry , no need to clean the attributes as they will * get renewed when the WCID is reused . return 0 ;void rt2800_pre_reset_hw(struct rt2x00_dev *rt2x00dev)struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;struct data_queue *queue = rt2x00dev->bcn;struct queue_entry *entry;int i, wcid;for (wcid = WCID_START; wcid < WCID_END; wcid++) {for (i = 0 ; i < queue->limit; i++) {void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,const unsigned int filter_flags)/* * Start configuration steps . * Note that the version error will always be dropped * and broadcast frames will always be accepted since * there is no filter for it at this time . 0 );1 );0 );1 );0 );void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,struct rt2x00intf_conf *conf, const unsigned int flags)bool update_bssid = false ;if (flags & CONFIG_UPDATE_TYPE) {/* * Enable synchronisation . if (conf->sync == TSF_SYNC_AP_NONE) {/* * Tune beacon queue transmit parameters for AP mode 0 );1 );32 );0 );else {4 );2 );32 );16 );if (flags & CONFIG_UPDATE_MAC) {if (flags & CONFIG_UPDATE_TYPE &&/* * The BSSID register has to be set to our own mac * address in AP mode . sizeof (conf->mac));true ;if (!is_zero_ether_addr((const u8 *)conf->mac)) {1 ]);0 xff);1 ] = cpu_to_le32(reg);sizeof (conf->mac));if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {if (!is_zero_ether_addr((const u8 *)conf->bssid)) {1 ]);3 );0 );1 ] = cpu_to_le32(reg);sizeof (conf->bssid));static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,struct rt2x00lib_erp *erp)bool any_sta_nongf = !!(erp->ht_opmode &/* default protection rate for HT20: OFDM 24M */ 0 x4004;/* default protection rate for HT40: duplicate OFDM 24M */ 0 x4084;switch (protection) {case IEEE80211_HT_OP_MODE_PROTECTION_NONE:/* * All STAs in this BSS are HT20 / 40 but there might be * STAs not supporting greenfield mode . * = > Disable protection for HT transmissions . 0 ;break ;case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:/* * All STAs in this BSS are HT20 or HT20 / 40 but there * might be STAs not supporting greenfield mode . * = > Protect all HT40 transmissions . 0 ;1 ;break ;case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:/* * Nonmember protection : * According to 802 . 11 n we _ should_ protect all * HT transmissions ( but we don ' t have to ) . * * But if cts_protection is enabled we _ shall_ protect * all HT transmissions using a CCK rate . * * And if any station is non GF we _ shall_ protect * GF transmissions . * * We decide to protect everything * - > fall through to mixed mode . case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:/* * Legacy STAs are present * = > Protect all HT transmissions . 1 ;/* * If erp protection is needed we have to protect HT * transmissions with CCK 11 M long preamble . if (erp->cts_protection) {/* don't duplicate RTS/CTS in CCK mode */ 0 x0003;0 x0003;break ;/* check for STAs not supporting greenfield mode */ if (any_sta_nongf)1 ;/* Update HT protection config */ void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,if (changed & BSS_CHANGED_ERP_PREAMBLE) {if (changed & BSS_CHANGED_ERP_CTS_PROT) {2 : 0 );if (changed & BSS_CHANGED_BASIC_RATES) {0 xff0 | erp->basic_rates);0 x00008003);if (changed & BSS_CHANGED_ERP_SLOT) {if (changed & BSS_CHANGED_BEACON_INT) {16 );if (changed & BSS_CHANGED_HT)static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev,const struct rt2x00_field32 mask)unsigned int i;for (i = 0 ; i < REGISTER_BUSY_COUNT; i++) {if (!rt2x00_get_field32(reg, mask))return 0 ;"BBP/RF register access failed, aborting\n" );return -EACCES;static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)unsigned int i;/* * BBP was enabled after firmware was loaded , * but we need to reactivate it now . 0 );0 );1 );for (i = 0 ; i < REGISTER_BUSY_COUNT; i++) {0 );if ((value != 0 xff) && (value != 0 x00))return 0 ;"BBP register access failed, aborting\n" );return -EACCES;static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {1 );1 );else {0 );0 );3 : 0 ;0 : 3 ;if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||if (led_ctrl == 0 || led_ctrl > 0 x40) {else {0 xff,2 ) | led_r_mode, 1 );static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,enum antenna ant)1 : 0 ;0 : 1 ;if (rt2x00_is_pci(rt2x00dev)) {else if (rt2x00_is_usb(rt2x00dev))0 xff,0 );0 );void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)1 );3 );if (rt2x00_rt(rt2x00dev, RT3572) &&/* * Configure the TX antenna . switch (ant->tx_chain_num) {case 1 :0 );break ;case 2 :if (rt2x00_rt(rt2x00dev, RT3572) &&1 );else 2 );break ;case 3 :2 );break ;/* * Configure the RX antenna . switch (ant->rx_chain_num) {case 1 :if (rt2x00_rt(rt2x00dev, RT3070) ||if (rt2x00_get_field16(eeprom,0 );break ;case 2 :if (rt2x00_rt(rt2x00dev, RT3572) &&1 );else {1 );break ;case 3 :2 );break ;3 , r3);1 , r1);if (rt2x00_rt(rt2x00dev, RT3593) ||if (ant->rx_chain_num == 1 )86 , 0 x00);else 86 , 0 x46);static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,struct rt2x00lib_conf *libconf)short lna_gain;if (libconf->rf.channel <= 14 ) {else if (libconf->rf.channel <= 64 ) {else if (libconf->rf.channel <= 128 ) {if (rt2x00_rt(rt2x00dev, RT3593) ||else {else {if (rt2x00_rt(rt2x00dev, RT3593) ||else {static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev)return clk_get_rate(rt2x00dev->clk) == 20000000 ;#define FREQ_OFFSET_BOUND 0 x5fstatic void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev)17 );if (rfcsr == prev_rfcsr)return ;if (rt2x00_is_usb(rt2x00dev)) {0 xff,return ;while (prev_freq_offset != freq_offset) {if (prev_freq_offset < freq_offset)else 17 , rfcsr);1000 , 1500 );static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,struct ieee80211_conf *conf,struct rf_channel *rf,struct channel_info *info)if (rt2x00dev->default_ant.tx_chain_num == 1 )1 );if (rt2x00dev->default_ant.rx_chain_num == 1 ) {1 );1 );else if (rt2x00dev->default_ant.rx_chain_num == 2 )1 );if (rf->channel > 14 ) {/* * When TX power is below 0 , we should increase it by 7 to * make it a positive value ( Minimum value is - 7 ) . * However this means that values between 0 and 7 have * double meaning , and we should set a 7 DBm boost flag . 0 ));if (info->default_power1 < 0 )7 ;0 ));if (info->default_power2 < 0 )7 ;else {1 , rf->rf1);2 , rf->rf2);3 , rf->rf3 & ~0 x00000004);4 , rf->rf4);200 );1 , rf->rf1);2 , rf->rf2);3 , rf->rf3 | 0 x00000004);4 , rf->rf4);200 );1 , rf->rf1);2 , rf->rf2);3 , rf->rf3 & ~0 x00000004);4 , rf->rf4);static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,struct ieee80211_conf *conf,struct rf_channel *rf,struct channel_info *info)struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;2 , rf->rf1);3 );3 , rfcsr);6 );6 , rfcsr);12 );12 , rfcsr);13 );13 , rfcsr);1 );0 );1 );2 );0 );1 );2 );1 , rfcsr);23 );23 , rfcsr);if (rt2x00_rt(rt2x00dev, RT3390)) {0 x68 : 0 x4f;0 x6f : 0 x4f;else {if (conf_is_ht40(conf)) {else {24 );24 , rfcsr);31 );31 , rfcsr);7 );1 );7 , rfcsr);30 );1 );30 , rfcsr);1000 , 1500 );0 );30 , rfcsr);static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,struct ieee80211_conf *conf,struct rf_channel *rf,struct channel_info *info)struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;if (rf->channel <= 14 ) {25 , drv_data->bbp25);26 , drv_data->bbp26);else {25 , 0 x09);26 , 0 xff);2 , rf->rf1);3 , rf->rf3);6 );if (rf->channel <= 14 )2 );else 1 );6 , rfcsr);5 );if (rf->channel <= 14 )1 );else 2 );5 , rfcsr);12 );if (rf->channel <= 14 ) {3 );else {7 );0 x3) |0 xC) << 1 ));12 , rfcsr);13 );if (rf->channel <= 14 ) {3 );else {7 );0 x3) |0 xC) << 1 ));13 , rfcsr);1 );0 );0 );0 );0 );0 );0 );if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {if (rf->channel <= 14 ) {1 );1 );1 );1 );else {switch (rt2x00dev->default_ant.tx_chain_num) {case 1 :1 );case 2 :1 );break ;switch (rt2x00dev->default_ant.rx_chain_num) {case 1 :1 );case 2 :1 );break ;1 , rfcsr);23 );23 , rfcsr);if (conf_is_ht40(conf)) {24 , drv_data->calibration_bw40);31 , drv_data->calibration_bw40);else {24 , drv_data->calibration_bw20);31 , drv_data->calibration_bw20);if (rf->channel <= 14 ) {7 , 0 xd8);9 , 0 xc3);10 , 0 xf1);11 , 0 xb9);15 , 0 x53);0 x4c;16 , rfcsr);17 , 0 x23);19 , 0 x93);20 , 0 xb3);25 , 0 x15);26 , 0 x85);27 , 0 x00);29 , 0 x9b);else {7 );1 );0 );1 );0 );7 , rfcsr);9 , 0 xc0);10 , 0 xf1);11 , 0 x00);15 , 0 x43);0 x7a;16 , rfcsr);17 , 0 x23);if (rf->channel <= 64 ) {19 , 0 xb7);20 , 0 xf6);25 , 0 x3d);else if (rf->channel <= 128 ) {19 , 0 x74);20 , 0 xf4);25 , 0 x01);else {19 , 0 x72);20 , 0 xf3);25 , 0 x01);26 , 0 x87);27 , 0 x01);29 , 0 x9f);0 );if (rf->channel <= 14 )1 );else 0 );7 );1 );7 , rfcsr);static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,struct ieee80211_conf *conf,struct rf_channel *rf,struct channel_info *info)struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;const bool txbf_enabled = false ; /* TODO */ /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */ 109 );0 );0 );109 , bbp);110 );0 );110 , bbp);if (rf->channel <= 14 ) {/* Restore BBP 25 & 26 for 2.4 GHz */ 25 , drv_data->bbp25);26 , drv_data->bbp26);else {/* Hard code BBP 25 & 26 for 5GHz */ /* Enable IQ Phase correction */ 25 , 0 x09);/* Setup IQ Phase correction value */ 26 , 0 xff);8 , rf->rf1);9 , rf->rf3 & 0 xf);11 );0 x3));11 , rfcsr);11 );1 );if (rf->channel <= 14 )1 );else 2 );11 , rfcsr);53 );if (rf->channel <= 14 ) {0 ;0 x1f);else {if (rt2x00_is_usb(rt2x00dev))0 x40;0 x18) << 1 ) |7 ));53 , rfcsr);55 );if (rf->channel <= 14 ) {0 ;0 x1f);else {if (rt2x00_is_usb(rt2x00dev))0 x40;0 x18) << 1 ) |7 ));55 , rfcsr);54 );if (rf->channel <= 14 ) {0 ;0 x1f);else {if (rt2x00_is_usb(rt2x00dev))0 x40;0 x18) << 1 ) |7 ));54 , rfcsr);1 );0 );0 );0 );0 );0 );0 );1 );1 );switch (rt2x00dev->default_ant.tx_chain_num) {case 3 :1 );case 2 :1 );case 1 :1 );break ;switch (rt2x00dev->default_ant.rx_chain_num) {case 3 :1 );case 2 :1 );case 1 :1 );break ;1 , rfcsr);if (conf_is_ht40(conf)) {else {/* NOTE: the reference driver does not writes the new value * back to RFCSR 32 32 );if (rf->channel <= 14 )0 xa0;else 0 x80;31 , rfcsr);30 );30 , rfcsr);/* Band selection */ 36 );if (rf->channel <= 14 )1 );else 0 );36 , rfcsr);34 );if (rf->channel <= 14 )0 x3c;else 0 x20;34 , rfcsr);12 );if (rf->channel <= 14 )0 x1a;else 0 x12;12 , rfcsr);6 );if (rf->channel >= 1 && rf->channel <= 14 )1 );else if (rf->channel >= 36 && rf->channel <= 64 )2 );else if (rf->channel >= 100 && rf->channel <= 128 )2 );else 1 );6 , rfcsr);30 );2 );30 , rfcsr);46 , 0 x60);if (rf->channel <= 14 ) {10 , 0 xd3);13 , 0 x12);else {10 , 0 xd8);13 , 0 x23);51 );1 );51 , rfcsr);51 );if (rf->channel <= 14 ) {5 );3 );else {4 );2 );51 , rfcsr);49 );if (rf->channel <= 14 )3 );else 2 );if (txbf_enabled)1 );49 , rfcsr);50 );0 );50 , rfcsr);57 );if (rf->channel <= 14 )0 x1b);else 0 x0f);57 , rfcsr);if (rf->channel <= 14 ) {44 , 0 x93);52 , 0 x45);else {44 , 0 x9b);52 , 0 x05);/* Initiate VCO calibration */ 3 );if (rf->channel <= 14 ) {1 );else {1 );1 );1 );1 );1 );1 );3 , rfcsr);if (rf->channel >= 1 && rf->channel <= 14 ) {0 x23;if (txbf_enabled)1 );39 , rfcsr);45 , 0 xbb);else if (rf->channel >= 36 && rf->channel <= 64 ) {0 x36;if (txbf_enabled)1 );39 , 0 x36);45 , 0 xeb);else if (rf->channel >= 100 && rf->channel <= 128 ) {0 x32;if (txbf_enabled)1 );39 , rfcsr);45 , 0 xb3);else {0 x30;if (txbf_enabled)1 );39 , rfcsr);45 , 0 x9b);static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev,struct ieee80211_conf *conf,struct rf_channel *rf,struct channel_info *info)const bool txbf_enabled = false ; /* TODO */ /* TODO: add band selection */ if (rf->channel <= 14 )6 , 0 x40);else if (rf->channel < 132 )6 , 0 x80);else 6 , 0 x40);8 , rf->rf1);9 , rf->rf3);if (rf->channel <= 14 )11 , 0 x46);else 11 , 0 x48);if (rf->channel <= 14 )12 , 0 x1a);else 12 , 0 x52);13 , 0 x12);1 );0 );0 );0 );0 );0 );0 );1 );1 );switch (rt2x00dev->default_ant.tx_chain_num) {case 3 :1 );case 2 :1 );case 1 :1 );break ;switch (rt2x00dev->default_ant.rx_chain_num) {case 3 :1 );case 2 :1 );case 1 :1 );break ;1 , rfcsr);30 );if (!conf_is_ht40(conf))0 x06);else 0 x06;30 , rfcsr);if (rf->channel <= 14 )31 , 0 xa0);else 31 , 0 x80);if (conf_is_ht40(conf))32 , 0 x80);else 32 , 0 xd8);if (rf->channel <= 14 )34 , 0 x3c);else 34 , 0 x20);/* loopback RF_BS */ 36 );if (rf->channel <= 14 )1 );else 0 );36 , rfcsr);if (rf->channel <= 14 )0 x23;else if (rf->channel < 100 )0 x36;else if (rf->channel < 132 )0 x32;else 0 x30;if (txbf_enabled)0 x40;39 , rfcsr);if (rf->channel <= 14 )44 , 0 x93);else 44 , 0 x9b);if (rf->channel <= 14 )0 xbb;else if (rf->channel < 100 )0 xeb;else if (rf->channel < 132 )0 xb3;else 0 x9b;45 , rfcsr);if (rf->channel <= 14 )0 x8e;else 0 x8a;if (txbf_enabled)0 x20;49 , rfcsr);50 , 0 x86);51 );if (rf->channel <= 14 )51 , 0 x75);else 51 , 0 x51);52 );if (rf->channel <= 14 )52 , 0 x45);else 52 , 0 x05);if (rf->channel <= 14 ) {0 x1f;0 x1f;0 x1f;else {0 x48 | ((info->default_power1 & 0 x18) << 1 ) |0 x7);0 x48 | ((info->default_power2 & 0 x18) << 1 ) |0 x7);0 x48 | ((info->default_power3 & 0 x18) << 1 ) |0 x7);53 , pwr1);54 , pwr2);55 , pwr3);"Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n" ,5 ) |0 xe0) >> 1 );109 , bbp);110 );0 x0f;0 xe0) >> 1 ;110 , bbp);57 );if (rf->channel <= 14 )57 , 0 x6e);else 57 , 0 x3e);/* Enable RF tuning */ 3 );1 );3 , rfcsr);2000 );49 );/* clear update flag */ 49 , bbp & 0 xfe);49 , bbp);/* TODO: add calibration for TxBF */ #define POWER_BOUND 0 x27#define POWER_BOUND_5G 0 x2bstatic void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,struct ieee80211_conf *conf,struct rf_channel *rf,struct channel_info *info)8 , rf->rf1);9 , rf->rf3);11 );11 , rfcsr);49 );if (info->default_power1 > POWER_BOUND)else 49 , rfcsr);if (rf->channel <= 14 ) {if (rf->channel == 6 )68 , 0 x0c);else 68 , 0 x0b);if (rf->channel >= 1 && rf->channel <= 6 )59 , 0 x0f);else if (rf->channel >= 7 && rf->channel <= 11 )59 , 0 x0e);else if (rf->channel >= 12 && rf->channel <= 14 )59 , 0 x0d);static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,struct ieee80211_conf *conf,struct rf_channel *rf,struct channel_info *info)8 , rf->rf1);9 , rf->rf3);11 , 0 x42);12 , 0 x1c);13 , 0 x00);if (info->default_power1 > POWER_BOUND)47 , POWER_BOUND);else 47 , info->default_power1);if (info->default_power2 > POWER_BOUND)48 , POWER_BOUND);else 48 , info->default_power2);1 );1 );1 );if ( rt2x00dev->default_ant.tx_chain_num == 2 )1 );else 0 );if ( rt2x00dev->default_ant.rx_chain_num == 2 )1 );else 0 );0 );0 );1 , rfcsr);31 , 80 );static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,struct ieee80211_conf *conf,struct rf_channel *rf,struct channel_info *info)int idx = rf->channel-1 ;8 , rf->rf1);9 , rf->rf3);11 );11 , rfcsr);49 );if (info->default_power1 > POWER_BOUND)else 49 , rfcsr);if (rt2x00_rt(rt2x00dev, RT5392)) {50 );if (info->default_power2 > POWER_BOUND)else 50 , rfcsr);1 );if (rt2x00_rt(rt2x00dev, RT5392)) {1 );1 );1 );1 );1 );1 );1 , rfcsr);if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {/* r55/r59 value array of channel 1~14 */ static const u8 r55_bt_rev[] = {0 x83, 0 x83,0 x83, 0 x73, 0 x73, 0 x63, 0 x53, 0 x53,0 x53, 0 x43, 0 x43, 0 x43, 0 x43, 0 x43};static const u8 r59_bt_rev[] = {0 x0e, 0 x0e,0 x0e, 0 x0e, 0 x0e, 0 x0b, 0 x0a, 0 x09,0 x07, 0 x07, 0 x07, 0 x07, 0 x07, 0 x07};55 ,59 ,else {static const u8 r59_bt[] = {0 x8b, 0 x8b, 0 x8b,0 x8b, 0 x8b, 0 x8b, 0 x8b, 0 x8a, 0 x89,0 x88, 0 x88, 0 x86, 0 x85, 0 x84};59 , r59_bt[idx]);else {if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {static const u8 r55_nonbt_rev[] = {0 x23, 0 x23,0 x23, 0 x23, 0 x13, 0 x13, 0 x03, 0 x03,0 x03, 0 x03, 0 x03, 0 x03, 0 x03, 0 x03};static const u8 r59_nonbt_rev[] = {0 x07, 0 x07,0 x07, 0 x07, 0 x07, 0 x07, 0 x07, 0 x07,0 x07, 0 x07, 0 x06, 0 x05, 0 x04, 0 x04};55 ,59 ,else if (rt2x00_rt(rt2x00dev, RT5390) ||static const u8 r59_non_bt[] = {0 x8f, 0 x8f,0 x8f, 0 x8f, 0 x8f, 0 x8f, 0 x8f, 0 x8d,0 x8a, 0 x88, 0 x88, 0 x87, 0 x87, 0 x86};59 ,else if (rt2x00_rt(rt2x00dev, RT5350)) {static const u8 r59_non_bt[] = {0 x0b, 0 x0b,0 x0b, 0 x0b, 0 x0b, 0 x0b, 0 x0b, 0 x0a,0 x0a, 0 x09, 0 x08, 0 x07, 0 x07, 0 x06};59 ,static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,struct ieee80211_conf *conf,struct rf_channel *rf,struct channel_info *info)int power_bound;/* TODO */ const bool is_11b = false ;const bool is_type_ep = false ;14 || conf_is_ht40(conf)) ? 5 : 0 );/* Order of values on rf_channel entry: N, K, mod, R */ 8 , rf->rf1 & 0 xff);9 );0 xf);0 x100) >> 8 );8 ) & 0 x4) >> 2 );9 , rfcsr);11 ;1 );8 ) & 0 x3);14 {ength 42/* FIXME: RF11 owerwrite ? */ char [java.lang.StringIndexOutOfBoundsException: Range [29, 28) out of bounds for length 3013 , 0 x42);22 , 0 x40);24 , 0 x4A);25 , 0 x80); out of bounds for length 2th 170 )38 , 0 x890 rfcsr_write(rt2x00dev, 39 , 0 x1B);40 x);41 , 0 x9B);42 ,0 xD5;46 , 0 x6B)java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42return 0 48 ;57 , 0 x00);58 , 0 x39);60 , 0 x45);61 , 0 x91);62 , 0 x39);/* TODO RF27 <- tssi */ 10 ? 0 x07 : 0 x06;23 , rfcsr);59 , rfcsr);if (is_11b) {/* CCK */ 31 , 0 xF8);32 , 0 xC0);if (is_type_ep)55 , 0 x06);else 55 , 0 x47);else {/* OFDM */ if (is_type_ep)55 , 0 x03);else 55 , 0 x43);0 x2;else {10 , 0 x97);/* FIMXE: RF11 overwrite */ 11 , 0 x40);25 , 0 xBF);27 , 0 x42);36 , 0 x00);37 , 0 x04);38 , 0 x85);40 , 0 x42);41 , 0 xBB);42 , 0 xD7);45 , 0 x41);48 , 0 x00);57 , 0 x77);60 , 0 x05);61 , 0 x01);/* TODO RF27 <- tssi */ if (rf->channel >= 36 && rf->channel <= 64 ) {12 , 0 x2E);13 , 0 x22);22 , 0 x60);23 , 0 x7F);if (rf->channel <= 50 )24 , 0 x09);else if (rf->channel >= 52 )24 , 0 x07);39 , 0 x1C);43 , 0 x5B);44 , 0 X40);46 , 0 X00);51 , 0 xFE);52 , 0 x0C);54 , 0 xF8);if (rf->channel <= 50 ) {55 , 0 x06);56 , 0 xD3);else if (rf->channel >= 52 ) {55 , 0 x04);56 , 0 xBB);58 , 0 x15);59 , 0 x7F);62 , 0 x15);else if (rf->channel >= 100 && rf->channel <= 165 ) {12 , 0 x0E);13 , 0 x42);22 , 0 x40);if (rf->channel <= 153 ) {23 , 0 x3C);24 , 0 x06);else if (rf->channel >= 155 ) {23 , 0 x38);24 , 0 x05);if (rf->channel <= 138 ) {39 , 0 x1A);43 , 0 x3B);44 , 0 x20);46 , 0 x18);else if (rf->channel >= 140 ) {39 , 0 x18);43 , 0 x1B);44 , 0 x10);46 , 0 X08);if (rf->channel <= 124 )51 , 0 xFC);else if (rf->channel >= 126 )51 , 0 xEC);if (rf->channel <= 138 )52 , 0 x06);else if (rf->channel >= 140 )52 , 0 x06);54 , 0 xEB);if (rf->channel <= 138 )55 , 0 x01);else if (rf->channel >= 140 )55 , 0 x00);if (rf->channel <= 128 )56 , 0 xBB);else if (rf->channel >= 130 )56 , 0 xAB);if (rf->channel <= 116 )58 , 0 x1D);else if (rf->channel >= 118 )58 , 0 x15);if (rf->channel <= 138 )59 , 0 x3F);else if (rf->channel >= 140 )59 , 0 x7C);if (rf->channel <= 116 )62 , 0 x1D);else if (rf->channel >= 118 )62 , 0 x15);0 x3;49 );if (info->default_power1 > power_bound)else if (is_type_ep)49 , rfcsr);50 );if (info->default_power2 > power_bound)else if (is_type_ep)50 , rfcsr);1 );1 );1 );1 );2 );0 );1 );2 );0 );1 , rfcsr);6 , 0 xe4);if (conf_is_ht40(conf))30 , 0 x16);else 30 , 0 x10);if (!is_11b) {31 , 0 x80);32 , 0 x80);/* TODO proper frequency adjustment */ /* TODO merge with others */ 3 );1 );3 , rfcsr);/* BBP settings */ 62 , 0 x37 - rt2x00dev->lna_gain);63 , 0 x37 - rt2x00dev->lna_gain);64 , 0 x37 - rt2x00dev->lna_gain);79 , (rf->channel <= 14 ) ? 0 x1C : 0 x18);80 , (rf->channel <= 14 ) ? 0 x0E : 0 x08);81 , (rf->channel <= 14 ) ? 0 x3A : 0 x38);82 , (rf->channel <= 14 ) ? 0 x62 : 0 x92);/* GLRT band configuration */ 195 , 128 );196 , (rf->channel <= 14 ) ? 0 xE0 : 0 xF0);195 , 129 );196 , (rf->channel <= 14 ) ? 0 x1F : 0 x1E);195 , 130 );196 , (rf->channel <= 14 ) ? 0 x38 : 0 x28);195 , 131 );196 , (rf->channel <= 14 ) ? 0 x32 : 0 x20);195 , 133 );196 , (rf->channel <= 14 ) ? 0 x28 : 0 x7F);195 , 124 );196 , (rf->channel <= 14 ) ? 0 x19 : 0 x7F);static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,struct ieee80211_conf *conf,struct rf_channel *rf,struct channel_info *info)struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;/* Frequeny plan setting */ /* Rdiv setting (set 0x03 if Xtal==20) * R13 [ 1 : 0 ] 13 );3 : 0 );13 , rfcsr);/* N setting * R20 [ 7 : 0 ] in rf - > rf1 * R21 [ 0 ] always 0 20 );0 x00ff);20 , rfcsr);21 );0 );21 , rfcsr);/* K setting (always 0) * R16 [ 3 : 0 ] ( RF PLL freq selection ) 16 );0 );16 , rfcsr);/* D setting (always 0) * R22 [ 2 : 0 ] ( D = 15 , R22 [ 2 : 0 ] = < 111 > ) 22 );0 );22 , rfcsr);/* Ksd setting * Ksd : R17 < 7 : 0 > in rf - > rf2 * R18 < 7 : 0 > in rf - > rf3 * R19 < 1 : 0 > in rf - > rf4 17 );17 , rfcsr);18 );18 , rfcsr);19 );19 , rfcsr);/* Default: XO=20MHz , SDM mode */ 16 );0 x80);16 , rfcsr);21 );1 );21 , rfcsr);1 );1 );1 , rfcsr);2 );1 );1 );2 , rfcsr);42 );1 );42 , rfcsr);/* RF for DC Cal BW */ if (conf_is_ht40(conf)) {6 , 0 x10);7 , 0 x10);8 , 0 x04);58 , 0 x10);59 , 0 x10);else {6 , 0 x20);7 , 0 x20);8 , 0 x00);58 , 0 x20);59 , 0 x20);if (conf_is_ht40(conf)) {58 , 0 x08);59 , 0 x08);else {58 , 0 x28);59 , 0 x28);28 );11 ));28 , rfcsr);if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {if (conf_is_ht40(conf)) {else {5 , 6 );0 x3F);5 , 6 , rfcsr);5 , 7 );0 x3F);5 , 7 , rfcsr);7 , 6 );0 x3F);7 , 6 , rfcsr);7 , 7 );0 x3F);7 , 7 , rfcsr);5 , 58 );0 x3F);5 , 58 , rfcsr);5 , 59 );0 x3F);5 , 59 , rfcsr);7 , 58 );0 x3F);7 , 58 , rfcsr);7 , 59 );0 x3F);7 , 59 , rfcsr);static void rt2800_config_alc_rt6352(struct rt2x00_dev *rt2x00dev,struct ieee80211_channel *chan,int power_level)int cur_channel = rt2x00dev->rf_channel;2 ];2 ];if (WARN_ON(cur_channel < 1 || cur_channel > 14 ))return ;/* get per chain power, 2 chains in total, unit is 0.5dBm */ 3 ) * 2 ;/* We can't get the accurate TX power. Based on some tests, the real * TX power is approximately equal to channel_power + ( max ) rate_power . * Usually max rate_power is the gain of the OFDM 6 M rate . The antenna * gain and externel PA gain are not included as we are unable to * obtain these values . 1 );0 x3f;if (power_level < 1 )1 ;0 ] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);1 ] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);for (cnt = 0 ; cnt < 2 ; cnt++) {1 ];if (chan_power >= 0 x20 || chan_power == 0 )0 x10;0 ]);1 ]);0 x2f);0 x2f);if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {/* init base power by eeprom target power */ 0 );/* Save MAC SYS CTRL registers */ /* Disable Tx/Rx */ 0 );/* Check MAC Tx/Rx idle */ if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))"RF busy while configuring ALC\n" );if (chan->center_freq > 2457 ) {30 );0 x40;30 , bbp);39 , 0 );if (rt2x00_has_cap_external_lna_bg(rt2x00dev))42 , 0 xfb);else 42 , 0 x7b);else {30 );0 x1f;30 , bbp);39 , 0 x80);if (rt2x00_has_cap_external_lna_bg(rt2x00dev))42 , 0 xdb);else 42 , 0 x5b);static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,const unsigned int word,const u8 value)for (chain = 0 ; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {27 );27 , reg);static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)/* TX0 IQ Gain */ 158 , 0 x2c);if (channel <= 14 )else if (channel >= 36 && channel <= 64 )else if (channel >= 100 && channel <= 138 )else if (channel >= 140 && channel <= 165 )else 0 ;159 , cal);/* TX0 IQ Phase */ 158 , 0 x2d);if (channel <= 14 )else if (channel >= 36 && channel <= 64 )else if (channel >= 100 && channel <= 138 )else if (channel >= 140 && channel <= 165 )else 0 ;159 , cal);/* TX1 IQ Gain */ 158 , 0 x4a);if (channel <= 14 )else if (channel >= 36 && channel <= 64 )else if (channel >= 100 && channel <= 138 )else if (channel >= 140 && channel <= 165 )else 0 ;159 , cal);/* TX1 IQ Phase */ 158 , 0 x4b);if (channel <= 14 )else if (channel >= 36 && channel <= 64 )else if (channel >= 100 && channel <= 138 )else if (channel >= 140 && channel <= 165 )else 0 ;159 , cal);/* FIXME: possible RX0, RX1 callibration ? */ /* RF IQ compensation control */ 158 , 0 x04);159 , cal != 0 xff ? cal : 0 );/* RF IQ imbalance compensation control */ 158 , 0 x03);159 , cal != 0 xff ? cal : 0 );static s8 rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,unsigned int channel,if (rt2x00_rt(rt2x00dev, RT3593) ||if (channel <= 14 )return clamp_t(s8, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);if (rt2x00_rt(rt2x00dev, RT3593) ||return clamp_t(s8, txpower, MIN_A_TXPOWER_3593,else return clamp_t(s8, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev,struct rf_channel *rf)14 ) ? 0 x48 : 0 x38;66 , bbp);69 , 0 x12);if (rf->channel <= 14 ) {70 , 0 x0a);else {/* Disable CCK packet detection */ 70 , 0 x00);73 , 0 x10);if (rf->channel > 14 ) {62 , 0 x1d);63 , 0 x1d);64 , 0 x1d);else {62 , 0 x2d);63 , 0 x2d);64 , 0 x2d);static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,struct ieee80211_conf *conf,struct rf_channel *rf,struct channel_info *info)if (rt2x00dev->default_ant.tx_chain_num > 2 )switch (rt2x00dev->chip.rt) {case RT3883:break ;switch (rt2x00dev->chip.rf) {case RF2020:case RF3020:case RF3021:case RF3022:case RF3320:break ;case RF3052:break ;case RF3053:break ;case RF3290:break ;case RF3322:break ;case RF3853:break ;case RF3070:case RF5350:case RF5360:case RF5362:case RF5370:case RF5372:case RF5390:case RF5392:break ;case RF5592:break ;case RF7620:break ;default :if (rt2x00_rf(rt2x00dev, RF3070) ||30 );if (rt2x00_rf(rt2x00dev, RF3322)) {else {30 , rfcsr);3 );1 );3 , rfcsr);/* * Change BBP settings if (rt2x00_rt(rt2x00dev, RT3352)) {62 , 0 x37 - rt2x00dev->lna_gain);63 , 0 x37 - rt2x00dev->lna_gain);64 , 0 x37 - rt2x00dev->lna_gain);27 , 0 x0);66 , 0 x26 + rt2x00dev->lna_gain);27 , 0 x20);66 , 0 x26 + rt2x00dev->lna_gain);86 , 0 x38);83 , 0 x6a);else if (rt2x00_rt(rt2x00dev, RT3593)) {if (rf->channel > 14 ) {/* Disable CCK Packet detection on 5GHz */ 70 , 0 x00);else {70 , 0 x0a);if (conf_is_ht40(conf))105 , 0 x04);else 105 , 0 x34);62 , 0 x37 - rt2x00dev->lna_gain);63 , 0 x37 - rt2x00dev->lna_gain);64 , 0 x37 - rt2x00dev->lna_gain);77 , 0 x98);else if (rt2x00_rt(rt2x00dev, RT3883)) {62 , 0 x37 - rt2x00dev->lna_gain);63 , 0 x37 - rt2x00dev->lna_gain);64 , 0 x37 - rt2x00dev->lna_gain);if (rt2x00dev->default_ant.rx_chain_num > 1 )86 , 0 x46);else 86 , 0 );else {62 , 0 x37 - rt2x00dev->lna_gain);63 , 0 x37 - rt2x00dev->lna_gain);64 , 0 x37 - rt2x00dev->lna_gain);if (rt2x00_rt(rt2x00dev, RT6352))86 , 0 x38);else 86 , 0 );if (rf->channel <= 14 ) {if (!rt2x00_rt(rt2x00dev, RT5390) &&if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {82 , 0 x62);82 , 0 x62);75 , 0 x46);else {if (rt2x00_rt(rt2x00dev, RT3593))82 , 0 x62);else 82 , 0 x84);75 , 0 x50);if (rt2x00_rt(rt2x00dev, RT3593) ||83 , 0 x8a);else {if (rt2x00_rt(rt2x00dev, RT3572))82 , 0 x94);else if (rt2x00_rt(rt2x00dev, RT3593) ||82 , 0 x82);else if (!rt2x00_rt(rt2x00dev, RT6352))82 , 0 xf2);if (rt2x00_rt(rt2x00dev, RT3593) ||83 , 0 x9a);if (rt2x00_has_cap_external_lna_a(rt2x00dev))75 , 0 x46);else 75 , 0 x50);14 );14 );if (rt2x00_rt(rt2x00dev, RT3572))8 , 0 );if (rt2x00_rt(rt2x00dev, RT6352)) {1 );else {0 ;switch (rt2x00dev->default_ant.tx_chain_num) {case 3 :/* Turn on tertiary PAs */ 14 );14 );case 2 :/* Turn on secondary PAs */ 14 );14 );case 1 :/* Turn on primary PAs */ 14 );if (rt2x00_has_cap_bt_coexist(rt2x00dev))1 );else 14 );break ;switch (rt2x00dev->default_ant.rx_chain_num) {case 3 :/* Turn on tertiary LNAs */ 1 );1 );case 2 :/* Turn on secondary LNAs */ 1 );1 );case 1 :/* Turn on primary LNAs */ 1 );1 );break ;1 );1 );if (rt2x00_rt(rt2x00dev, RT3572)) {8 , 0 x80);/* AGC init */ if (rf->channel <= 14 )0 x1c + (2 * rt2x00dev->lna_gain);else 0 x22 + ((rt2x00dev->lna_gain * 5 ) / 3 );66 , reg);if (rt2x00_rt(rt2x00dev, RT3593)) {/* Band selection */ if (rt2x00_is_usb(rt2x00dev) ||/* GPIO #8 controls all paths */ 0 );if (rf->channel <= 14 )1 );else 0 );/* LNA PE control. */ if (rt2x00_is_usb(rt2x00dev)) {/* GPIO #4 controls PE0 and PE1, * GPIO # 7 controls PE2 0 );0 );1 );1 );else if (rt2x00_is_pcie(rt2x00dev)) {/* GPIO #4 controls PE0, PE1 and PE2 */ 0 );1 );/* AGC init */ if (rf->channel <= 14 )0 x1c + 2 * rt2x00dev->lna_gain;else 0 x22 + ((rt2x00dev->lna_gain * 5 ) / 3 );66 , reg);1000 , 1500 );if (rt2x00_rt(rt2x00dev, RT3883)) {if (!conf_is_ht40(conf))105 , 0 x34);else 105 , 0 x04);/* AGC init */ if (rf->channel <= 14 )0 x2e + rt2x00dev->lna_gain;else 0 x20 + ((rt2x00dev->lna_gain * 5 ) / 3 );66 , reg);1000 , 1500 );if (rt2x00_rt(rt2x00dev, RT5592)) {0 x10 : 0 x1a;141 , bbp);14 ? 0 x1c : 0 x24) + 2 * rt2x00dev->lna_gain;66 , bbp);if (rt2x00_rt(rt2x00dev, RT6352)) {/* BBP for GLRT BW */ 0 x10 : rt2x00_has_cap_external_lna_bg(rt2x00dev) ?0 x15 : 0 x1a;141 , bbp);0 x2f : 0 x40;157 , bbp);if (rt2x00dev->default_ant.rx_chain_num == 1 ) {91 , 0 x07);95 , 0 x1a);128 , 0 xa0);170 , 0 x12);171 , 0 x10);else {91 , 0 x06);95 , 0 x9a);128 , 0 xe0);170 , 0 x30);171 , 0 x30);/* AGC init */ 14 ? 0 x04 + 2 * rt2x00dev->lna_gain : 0 ;66 , bbp);1000 , 1500 );4 );2 * conf_is_ht40(conf));4 , bbp);3 );3 , bbp);if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {if (conf_is_ht40(conf)) {69 , 0 x1a);70 , 0 x0a);73 , 0 x16);else {69 , 0 x16);70 , 0 x08);73 , 0 x11);1000 , 1500 );/* * Clear channel statistic counters /* * Clear update flag if (rt2x00_rt(rt2x00dev, RT3352) ||49 );0 );49 , bbp);static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)9 ];int i;/* * First check if temperature compensation is supported . if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))return 0 ;/* * Read TSSI boundaries for temperature compensation from * the EEPROM . * * Array idx 0 1 2 3 4 5 6 7 8 * Matching Delta value - 4 - 3 - 2 - 1 0 + 1 + 2 + 3 + 4 * Example TSSI bounds 0 xF0 0 xD0 0 xB5 0 xA0 0 x88 0 x45 0 x25 0 x15 0 x00 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {0 ] = rt2x00_get_field16(eeprom,1 ] = rt2x00_get_field16(eeprom,2 ] = rt2x00_get_field16(eeprom,3 ] = rt2x00_get_field16(eeprom,4 ] = rt2x00_get_field16(eeprom,5 ] = rt2x00_get_field16(eeprom,6 ] = rt2x00_get_field16(eeprom,7 ] = rt2x00_get_field16(eeprom,8 ] = rt2x00_get_field16(eeprom,else {0 ] = rt2x00_get_field16(eeprom,1 ] = rt2x00_get_field16(eeprom,2 ] = rt2x00_get_field16(eeprom,3 ] = rt2x00_get_field16(eeprom,4 ] = rt2x00_get_field16(eeprom,5 ] = rt2x00_get_field16(eeprom,6 ] = rt2x00_get_field16(eeprom,7 ] = rt2x00_get_field16(eeprom,8 ] = rt2x00_get_field16(eeprom,/* * Check if temperature compensation is supported . if (tssi_bounds[4 ] == 0 xff || step == 0 xff)return 0 ;/* * Read current TSSI ( BBP 49 ) . 49 );/* * Compare TSSI value ( BBP49 ) with the compensation boundaries * from the EEPROM and increase or decrease tx power . for (i = 0 ; i <= 3 ; i++) {if (current_tssi > tssi_bounds[i])break ;if (i == 4 ) {for (i = 8 ; i >= 5 ; i--) {if (current_tssi < tssi_bounds[i])break ;return (i - 4 ) * step;static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,enum nl80211_band band)int comp_value = 0 ;/* * HT40 compensation not required . if (eeprom == 0 xffff ||return 0 ;if (band == NL80211_BAND_2GHZ) {if (comp_en) {if (!comp_type)else {if (comp_en) {if (!comp_type)return comp_value;static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,int power_level, int max_power)int delta;if (rt2x00_has_cap_power_limit(rt2x00dev))return 0 ;/* * XXX : We don ' t know the maximum transmit power of our hardware since * the EEPROM doesn ' t expose it . We only know that we are calibrated * to 100 % tx power . * * Hence , we assume the regulatory limit that cfg80211 calulated for * the current channel is our maximum and if we are requested to lower * the value we just reduce our tx power accordingly . return min(delta, 0 );static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,enum nl80211_band band, int power_level,int delta)if (rt2x00_rt(rt2x00dev, RT3593))return min_t(u8, txpower, 0 xc);if (rt2x00_rt(rt2x00dev, RT3883))return min_t(u8, txpower, 0 xf);if (rt2x00_has_cap_power_limit(rt2x00dev)) {/* * Check if eirp txpower exceed txpower_limit . * We use OFDM 6 M as criterion and its eirp txpower * is stored at EEPROM_EIRP_MAX_TX_POWER . * . 11 b data rate need add additional 4 dbm * when calculating eirp txpower . 1 );if (band == NL80211_BAND_2GHZ)else 4 : 0 ) + delta;0 ;else 0 ;0 , txpower + delta - reg_limit);return min_t(u8, txpower, 0 xc);enum {static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,struct ieee80211_channel *chan,int power_level)unsigned int offset;enum nl80211_band band = chan->band;int delta;int i;'\0' , sizeof (regs));/* TODO: adapt TX power reduction from the rt28xx code */ /* calculate temperature compensation delta */ if (band == NL80211_BAND_5GHZ)16 ;else 0 ;if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))8 ;/* read the next four txpower values */ /* CCK 1MBS,2MBS */ 1 , band, power_level,/* CCK 5.5MBS,11MBS */ 1 , band, power_level,/* OFDM 6MBS,9MBS */ 0 , band, power_level,/* OFDM 12MBS,18MBS */ 0 , band, power_level,/* read the next four txpower values */ 1 );/* OFDM 24MBS,36MBS */ 0 , band, power_level,/* OFDM 48MBS */ 0 , band, power_level,/* OFDM 54MBS */ 0 , band, power_level,/* read the next four txpower values */ 2 );/* MCS 0,1 */ 0 , band, power_level,/* MCS 2,3 */ 0 , band, power_level,/* MCS 4,5 */ 0 , band, power_level,/* MCS 6 */ 0 , band, power_level,/* read the next four txpower values */ 3 );/* MCS 7 */ 0 , band, power_level,/* MCS 8,9 */ 0 , band, power_level,/* MCS 10,11 */ 0 , band, power_level,/* MCS 12,13 */ 0 , band, power_level,/* read the next four txpower values */ 4 );/* MCS 14 */ 0 , band, power_level,/* MCS 15 */ 0 , band, power_level,/* MCS 16,17 */ 0 , band, power_level,/* MCS 18,19 */ 0 , band, power_level,/* read the next four txpower values */ 5 );/* MCS 20,21 */ 0 , band, power_level,/* MCS 22 */ 0 , band, power_level,/* MCS 23 */ 0 , band, power_level,/* read the next four txpower values */ 6 );/* STBC, MCS 0,1 */ 0 , band, power_level,/* STBC, MCS 2,3 */ 0 , band, power_level,/* STBC, MCS 4,5 */ 0 , band, power_level,/* STBC, MCS 6 */ 0 , band, power_level,/* read the next four txpower values */ 7 );/* STBC, MCS 7 */ 0 , band, power_level,for (i = 0 ; i < TX_PWR_CFG_IDX_COUNT; i++)"band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n" ,'5' : '2' ,'4' : '2' ,1 ) : i,"_EXT" : "" ,unsigned long ) regs[i]);static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,struct ieee80211_channel *chan,int power_level)enum nl80211_band band = chan->band;int delta;/* Warn user if bw_comp is set in EEPROM */ if (delta)"ignoring EEPROM HT40 power delta: %d\n" ,/* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit * value to 0 x3f and replace 0 x20 by 0 x21 as this is what the vendor * driver does as well , though it looks kinda wrong . * Maybe some misunderstanding of what a signed 8 - bit value is ? Maybe * the hardware has a problem handling 0 x20 , and as the code initially * used a fixed offset between HT20 and HT40 rates they had to work - * around that issue and most likely just forgot about it later on . * Maybe we should use rt2800_get_txpower_bw_comp ( ) here as well , * however , the corresponding EEPROM value is not respected by the * vendor driver , so maybe this is rather being taken care of the * TXALC and the driver doesn ' t need to handle it . . . ? * Though this is all very awkward , just do as they did , as that ' s what * board vendors expected when they populated the EEPROM . . . for (i = 0 ; i < 5 ; i++) {2 );0 x3f;if (t == 32 )0 x3f00) >> 8 ;if (t == 32 )8 );2 ) + 1 );0 x3f;if (t == 32 )16 );0 x3f00) >> 8 ;if (t == 32 )24 );16 );if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {/* HT20 */ if (data != 0 xffffffff)4 ),else {/* HT40 */ if (gdata != 0 xffffffff)4 ),/* Aparently Ralink ran out of space in the BYRATE calibration section * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x * registers . As recent 2 T chips use 8 - bit instead of 4 - bit values for * power - offsets more space would be needed . Ralink decided to keep the * EEPROM layout untouched and rather have some shared values covering * multiple bitrates . * Populate the registers not covered by the EEPROM in the same way the * vendor driver does . /* For OFDM 54MBS use value from OFDM 48MBS */ 0 ;/* For MCS 7 use value from MCS 6 */ /* For MCS 15 use value from MCS 14 */ 0 ;/* For STBC MCS 7 use value from STBC MCS 6 */ 0 ;/* TODO: temperature compensation code! */ /* * We configure transmit power using MAC TX_PWR_CFG_ { 0 , . . . , N } registers and * BBP R1 register . TX_PWR_CFG_X allow to configure per rate TX power values , * 4 bits for each rate ( tune from 0 to 15 dBm ) . BBP_R1 controls transmit power * for all rates , but allow to set only 4 discrete values : - 12 , - 6 , 0 and 6 dBm . * Reference per rate transmit power values are located in the EEPROM at * EEPROM_TXPOWER_BYRATE offset . We adjust them and BBP R1 settings according to * current conditions ( i . e . band , bandwidth , temperature , user settings ) . static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,struct ieee80211_channel *chan,int power_level)int i, is_rate_b, delta, power_ctrl;enum nl80211_band band = chan->band;/* * Calculate HT40 compensation . For 40 MHz we need to add or subtract * value read from EEPROM ( different for 2 GHz and for 5 GHz ) . /* * Calculate temperature compensation . Depends on measurement of current * TSSI ( Transmitter Signal Strength Indication ) we know TX power ( due * to temperature or maybe other factors ) is smaller or bigger than * expected . We adjust it , based on TSSI reference and boundaries values * provided in EEPROM . switch (rt2x00dev->chip.rt) {case RT2860:case RT2872:case RT2883:case RT3070:case RT3071:case RT3090:case RT3572:break ;default :/* TODO: temperature compensation code for other chips. */ break ;/* * Decrease power according to user settings , on devices with unknown * maximum tx power . For other devices we take user power_level into * consideration on rt2800_compensate_txpower ( ) . /* * BBP_R1 controls TX power for all rates , it allow to set the following * gains - 12 , - 6 , 0 , + 6 dBm by setting values 2 , 1 , 0 , 3 respectively . * * TODO : we do not use + 6 dBm option to do not increase power beyond * regulatory limit , however this could be utilized for devices with * CAPABILITY_POWER_LIMIT . if (delta <= -12 ) {2 ;12 ;else if (delta <= -6 ) {1 ;6 ;else {0 ;1 );1 , r1);for (i = 0 ; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2 ) {/* just to be safe */ if (offset > TX_PWR_CFG_4)break ;/* read the next four txpower values */ 0 : 1 ;/* * TX_PWR_CFG_0 : 1 MBS , TX_PWR_CFG_1 : 24 MBS , * TX_PWR_CFG_2 : MCS4 , TX_PWR_CFG_3 : MCS12 , * TX_PWR_CFG_4 : unknown /* * TX_PWR_CFG_0 : 2 MBS , TX_PWR_CFG_1 : 36 MBS , * TX_PWR_CFG_2 : MCS5 , TX_PWR_CFG_3 : MCS13 , * TX_PWR_CFG_4 : unknown /* * TX_PWR_CFG_0 : 5 . 5 MBS , TX_PWR_CFG_1 : 48 MBS , * TX_PWR_CFG_2 : MCS6 , TX_PWR_CFG_3 : MCS14 , * TX_PWR_CFG_4 : unknown /* * TX_PWR_CFG_0 : 11 MBS , TX_PWR_CFG_1 : 54 MBS , * TX_PWR_CFG_2 : MCS7 , TX_PWR_CFG_3 : MCS15 , * TX_PWR_CFG_4 : unknown /* read the next four txpower values */ 1 );0 ;/* * TX_PWR_CFG_0 : 6 MBS , TX_PWR_CFG_1 : MCS0 , * TX_PWR_CFG_2 : MCS8 , TX_PWR_CFG_3 : unknown , * TX_PWR_CFG_4 : unknown /* * TX_PWR_CFG_0 : 9 MBS , TX_PWR_CFG_1 : MCS1 , * TX_PWR_CFG_2 : MCS9 , TX_PWR_CFG_3 : unknown , * TX_PWR_CFG_4 : unknown /* * TX_PWR_CFG_0 : 12 MBS , TX_PWR_CFG_1 : MCS2 , * TX_PWR_CFG_2 : MCS10 , TX_PWR_CFG_3 : unknown , * TX_PWR_CFG_4 : unknown /* * TX_PWR_CFG_0 : 18 MBS , TX_PWR_CFG_1 : MCS3 , * TX_PWR_CFG_2 : MCS11 , TX_PWR_CFG_3 : unknown , * TX_PWR_CFG_4 : unknown /* next TX_PWR_CFG register */ 4 ;static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,struct ieee80211_channel *chan,int power_level)if (rt2x00_rt(rt2x00dev, RT3593) ||else if (rt2x00_rt(rt2x00dev, RT6352))else void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)unsigned long min_sleep = 0 ;/* * A voltage - controlled oscillator ( VCO ) is an electronic oscillator * designed to be controlled in oscillation frequency by a voltage * input . Maybe the temperature will affect the frequency of * oscillation to be shifted . The VCO calibration will be called * periodically to adjust the frequency to be precision . switch (rt2x00dev->chip.rf) {case RF2020:case RF3020:case RF3021:case RF3022:case RF3320:case RF3052:7 );1 );7 , rfcsr);break ;case RF3053:case RF3070:case RF3290:case RF3853:case RF5350:case RF5360:case RF5362:case RF5370:case RF5372:case RF5390:case RF5392:case RF5592:3 );1 );3 , rfcsr);1000 ;break ;case RF7620:5 , 0 x40);4 , 0 x0C);4 );1 );4 , rfcsr);2000 ;break ;default :1 , "Not supported RF chipset %x for VCO recalibration" ,return ;if (min_sleep > 0 )2 );if (rt2x00dev->rf_channel <= 14 ) {switch (rt2x00dev->default_ant.tx_chain_num) {case 3 :1 );case 2 :1 );case 1 :default :1 );break ;else {switch (rt2x00dev->default_ant.tx_chain_num) {case 3 :1 );case 2 :1 );case 1 :default :1 );break ;static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,struct rt2x00lib_conf *libconf)static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,struct rt2x00lib_conf *libconf)enum dev_state state =if (state == STATE_SLEEP) {0 );5 );1 );1 );else {0 );0 );0 );void rt2800_config(struct rt2x00_dev *rt2x00dev,struct rt2x00lib_conf *libconf,const unsigned int flags)/* Always recalculate LNA gain before changing configuration */ if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {/* * To provide correct survey data for survey - based ACS algorithm * we have to save survey data for current channel before switching . if (flags & IEEE80211_CONF_CHANGE_POWER)if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)if (flags & IEEE80211_CONF_CHANGE_PS)/* * Link tuning void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)/* * Update FCS error count from register . static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {if (rt2x00_rt(rt2x00dev, RT3070) ||0 x1c + (2 * rt2x00dev->lna_gain);else 0 x2e + rt2x00dev->lna_gain;else { /* 5GHZ band */ if (rt2x00_rt(rt2x00dev, RT3593) ||0 x20 + (rt2x00dev->lna_gain * 5 ) / 3 ;else if (rt2x00_rt(rt2x00dev, RT5592))0 x24 + (2 * rt2x00dev->lna_gain);else {if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))0 x32 + (rt2x00dev->lna_gain * 5 ) / 3 ;else 0 x3a + (rt2x00dev->lna_gain * 5 ) / 3 ;return vgc;static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,struct link_qual *qual, u8 vgc_level)if (qual->vgc_level != vgc_level) {if (rt2x00_rt(rt2x00dev, RT3572) ||66 ,else if (rt2x00_rt(rt2x00dev, RT5592)) {83 , qual->rssi > -65 ? 0 x4a : 0 x7a);66 , vgc_level);else {66 , vgc_level);void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,const u32 count)if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))return ;/* When RSSI is better than a certain threshold, increase VGC * with a chip specific value in order to improve the balance * between sensibility and noise isolation . switch (rt2x00dev->chip.rt) {case RT3572:case RT3593:if (qual->rssi > -65 ) {if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)0 x20;else 0 x10;break ;case RT3883:if (qual->rssi > -65 )0 x10;break ;case RT5592:if (qual->rssi > -65 )0 x20;break ;default :if (qual->rssi > -80 )0 x10;break ;/* * Initialization functions . static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;unsigned int i;int ret;if (ret)return ret;if (rt2x00_rt(rt2x00dev, RT6352)) {0 x01);21 );0 x01;21 , bbp);21 );0 x01);21 , bbp);0 x00);0 x0000013f);0 x00008003);0 x00000000);1600 );0 );0 );0 );0 );0 );9 );2 );if (rt2x00_rt(rt2x00dev, RT3290)) {if (rt2x00_get_field32(reg, WLAN_EN) == 1 ) {1 );if (!(rt2x00_get_field32(reg, LDO0_EN) == 1 )) {1 );3 );1 );1 );0 x27);0 x5e);0 x00);0 x17);0 x93);0 x7f);1 );if (rt2x00_rt(rt2x00dev, RT3071) ||if (rt2x00_rt(rt2x00dev, RT3290))0 x00000404);else 0 x00000400);0 x00000000);if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))0 x0000002c);else 0 x0000000f);else {0 x00000000);else if (rt2x00_rt(rt2x00dev, RT3070)) {0 x00000400);if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {0 x00000000);0 x0000002c);else {0 x00080606);0 x00000000);else if (rt2800_is_305x_soc(rt2x00dev)) {0 x00000400);0 x00000000);0 x00000030);else if (rt2x00_rt(rt2x00dev, RT3352)) {0 x00000402);0 x00080606);0 x00000000);else if (rt2x00_rt(rt2x00dev, RT3572)) {0 x00000400);0 x00080606);else if (rt2x00_rt(rt2x00dev, RT3593)) {0 x00000402);0 x00000000);if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {if (rt2x00_get_field16(eeprom,0 x0000001f);else 0 x0000000f);else {0 x00000000);else if (rt2x00_rt(rt2x00dev, RT3883)) {0 x00000402);0 x00000000);0 x00040000);0 x8000fc21);0 x00009c40);else if (rt2x00_rt(rt2x00dev, RT5390) ||0 x00000404);0 x00080606);0 x00000000);else if (rt2x00_rt(rt2x00dev, RT5592)) {0 x00000404);0 x00000000);0 x00000000);else if (rt2x00_rt(rt2x00dev, RT5350)) {0 x00000404);else if (rt2x00_rt(rt2x00dev, RT6352)) {0 x00000401);0 x000C0001);0 x00000000);0 x00000000);0 x0);0 x0);0 x6C6C666C);0 x6C6C666C);0 x3630363A);0 x3630363A);0 );0 x77754433);0 x77765543);0 x77765544);0 x77765544);0 x1010);0 x00000000);0 x00080606);32 );0 );0 );0 );0 );1 );0 );0 );9 );32 );10 );3 ;2 ;1 ;10 );10 );70 );30 );3 );3 );3 );3 );1 );0 x1f3fbf9f);2 );2 );2000 );0 );0 );1 );1 );1 );1 );0 );0 );0 );0 );3 );0 );1 );1 );1 );1 );0 );1 );0 );0 );3 );0 );1 );1 );1 );1 );0 );1 );0 );0 );0 x4004);1 );1 );0 );1 );1 );0 );1 );0 );0 );0 x4084);1 );1 );0 );1 );1 );1 );1 );1 );0 );0 x4004);1 );1 );0 );1 );1 );0 );1 );0 );0 );0 x4084);1 );1 );0 );1 );1 );1 );1 );1 );0 );0 xf40006);0 );0 );0 );0 );3 );0 );0 );0 );0 );1 1 );1 );1 );1 );1 );1 );0 );0 );88 );0 );0 x00000082 : 0 x00000002;0 x12111008);0 x16151413);7 );1 );0 x002400ca);10 and the OFDM SIFS16 . However, the original Ralink driver uses16 for both and indeed using a value of 10 for CCK SIFS results in11 g + CTS protection. Hence, use the same16 for both, CCK and OFDM SIFS.16 );16 );4 );314 );1 );0 x00000003);0 ; i < 4 ; i++)0 );0 ; i < 256 ; i++) {0 ; i < 256 ; i++)0 );0 ; i < 8 ; i++)30 );125 );125 ;3000000 ;1000000 ;0 );0 );1 );2 );3 );4 );5 );6 );8 );8 );9 );10 );11 );12 );13 );14 );8 );8 );9 );10 );11 );12 );13 );14 );0 );0 );1 );2 );0 );0 );6 ms6 << 4 );1 );1 );1 );1 );1 );0 ;; 4 ); 1 ); 4 , value); 142 , 1 ); 143 , 57 ); 0 xE0, 0 x1F, 0 X38, 0 x32, 0 x08, 0 x28, 0 x19, 0 x0A, 0 xFF, 0 x00, /* 128 ~ 137 */0 x16, 0 x10, 0 x10, 0 x0B, 0 x36, 0 x2C, 0 x26, 0 x24, 0 x42, 0 x36, /* 138 ~ 147 */0 x30, 0 x2D, 0 x4C, 0 x46, 0 x3D, 0 x40, 0 x3E, 0 x42, 0 x3D, 0 x40, /* 148 ~ 157 */0 X3C, 0 x34, 0 x2C, 0 x2F, 0 x3C, 0 x35, 0 x2E, 0 x2A, 0 x49, 0 x41, /* 158 ~ 167 */0 x36, 0 x31, 0 x30, 0 x30, 0 x0E, 0 x0D, 0 x28, 0 x21, 0 x1C, 0 x16, /* 168 ~ 177 */0 x50, 0 x4A, 0 x43, 0 x40, 0 x10, 0 x10, 0 x10, 0 x10, 0 x00, 0 x00, /* 178 ~ 187 */0 x00, 0 x00, 0 x00, 0 x00, 0 x00, 0 x00, 0 x00, 0 x00, 0 x00, 0 x00, /* 188 ~ 197 */0 x00, 0 x00, 0 x7D, 0 x14, 0 x32, 0 x2C, 0 x36, 0 x4C, 0 x43, 0 x2C, /* 198 ~ 207 */0 x2E, 0 x36, 0 x30, 0 x6E, /* 208 ~ 211 */; int i; 0 ; i < ARRAY_SIZE(glrt_table); i++) { 195 , 128 + i); 196 , glrt_table[i]); ; 65 , 0 x2C); 66 , 0 x38); 68 , 0 x0B); 69 , 0 x12); 70 , 0 x0a); 73 , 0 x10); 81 , 0 x37); 82 , 0 x62); 83 , 0 x6A); 84 , 0 x99); 86 , 0 x00); 91 , 0 x04); 92 , 0 x00); 103 , 0 x00); 105 , 0 x05); 106 , 0 x35); ; ; 138 ); ; if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1 )0 x20; if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1 )0 x02; 138 , value); 31 , 0 x08); 65 , 0 x2c); 66 , 0 x38); 69 , 0 x12); 73 , 0 x10); 70 , 0 x0a); 78 , 0 x0e); 80 , 0 x08); 82 , 0 x62); 83 , 0 x6a); 84 , 0 x99); 86 , 0 x00); 91 , 0 x04); 92 , 0 x00); 103 , 0 xc0); 105 , 0 x01); 106 , 0 x35); 65 , 0 x2c); 66 , 0 x38); if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {69 , 0 x16); 73 , 0 x12); 69 , 0 x12); 73 , 0 x10); 70 , 0 x0a); 81 , 0 x37); 82 , 0 x62); 83 , 0 x6a); if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))84 , 0 x19); 84 , 0 x99); 86 , 0 x00); 91 , 0 x04); 92 , 0 x00); 103 , 0 x00); 105 , 0 x05); 106 , 0 x35); 65 , 0 x2c); 66 , 0 x38); 69 , 0 x12); 73 , 0 x10); 70 , 0 x0a); 79 , 0 x13); 80 , 0 x05); 81 , 0 x33); 82 , 0 x62); 83 , 0 x6a); 84 , 0 x99); 86 , 0 x00); 91 , 0 x04); 92 , 0 x00); if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||103 , 0 xc0); 103 , 0 x00); 105 , 0 x05); 106 , 0 x35); if (rt2x00_rt(rt2x00dev, RT3071) ||; ; ; 31 , 0 x08); 65 , 0 x2c); 66 , 0 x38); 68 , 0 x0b); 69 , 0 x12); 73 , 0 x13); 75 , 0 x46); 76 , 0 x28); 77 , 0 x58); 70 , 0 x0a); 74 , 0 x0b); 79 , 0 x18); 80 , 0 x09); 81 , 0 x33); 82 , 0 x62); 83 , 0 x7a); 84 , 0 x9a); 86 , 0 x38); 91 , 0 x04); 92 , 0 x02); 103 , 0 xc0); 104 , 0 x92); 105 , 0 x1c); 106 , 0 x03); 128 , 0 x12); 67 , 0 x24); 143 , 0 x04); 142 , 0 x99); 150 , 0 x30); 151 , 0 x2e); 152 , 0 x20); 153 , 0 x34); 154 , 0 x40); 155 , 0 x3b); 253 , 0 x04); 47 ); 1 ); 47 , value); 5 -bit ADC for Acquisition and 8 -bit ADC for data */3 ); 1 ); 1 ); 3 , value); 3 , 0 x00); 4 , 0 x50); 31 , 0 x08); 47 , 0 x48); 65 , 0 x2c); 66 , 0 x38); 68 , 0 x0b); 69 , 0 x12); 73 , 0 x13); 75 , 0 x46); ; 0 59; 70 ,x)80 , 0 x08); 81 , 0 x37); 82 , 0 x62if 83 , 0 x7a); 84 , 0 x9a); 83 , 0 x6a); 84 , 0 x99); 86 , 0 x38); 88 , 0 x90); 91 , 0 x04); 92 , 0 x02); 103 , 0 xc0); 104 , 0 x92); if (rt2x00_rt(rt2x00dev, RT5350)) {105 , 0 x3c); 106 , 0 x03); 105 , 0 x34); 106 , 0 x05); 120 , 0 x50); 137 , 0 x0f); 163 , 0 xbd); 0 x9c40=1000 msec */179 , 0 x02); 180 , 0 x00); 182 , 0 x40); 180 , 0 x01); 182 , 0 x9c); 179 , 0 x00); 142 , 0 x04); 143 , 0 x3b); 142 , 0 x06); 143 , 0 xa0); 142 , 0 x07); 143 , 0 xa1); 142 , 0 x08); 143 , 0 xa2); 148 , 0 xc8); if (rt2x00_rt(rt2x00dev, RT5350)) {150 , 0 x40); 151 , 0 x30); 152 , 0 xa3); 154 , 0 ); 65 , 0 x2c); 66 , 0 x38); 69 , 0 x12); 73 , 0 x10); 70 , 0 x0a); 79 , 0 x13); 80 , 0 x05); 81 , 0 x33); 82 , 0 x62); 83 , 0 x6a); 84 , 0 x99); 86 , 0 x00); 91 , 0 x04); 92 , 0 x00); if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))103 , 0 xc0); 103 , 0 x00); 105 , 0 x05); 106 , 0 x35); ; 31 , 0 x08); 65 , 0 x2c); 66 , 0 x38); 69 , 0 x12); 73 , 0 x10); 70 , 0 x0a); 79 , 0 x13); 80 , 0 x05); 81 , 0 x33); 82 , 0 x62); 83 , 0 x6a); 84 , 0 x99); 86 , 0 x00); 91 , 0 x04); 92 , 0 x00); 103 , 0 xc0); 105 , 0 x05); 106 , 0 x35); ; ; 79 , 0 x13); 80 , 0 x05); 81 , 0 x33); 137 , 0 x0f); 84 , 0 x19); if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))103 , 0 xc0); ; 4 , 0 x50); 47 , 0 x48); 86 , 0 x46); 88 , 0 x90); 92 , 0 x02); 103 , 0 xc0); 104 , 0 x92); 105 , 0 x34); 106 , 0 x12); 120 , 0 x50); 137 , 0 x0f); 163 , 0 x9d); 0 x9C40=1000 msec */179 , 0 x02); 180 , 0 x00); 182 , 0 x40); 180 , 0 x01); 182 , 0 x9c); 179 , 0 x00); 142 , 0 x04); 143 , 0 x3b); 142 , 0 x06); 143 , 0 xa0); 142 , 0 x07); 143 , 0 xa1); 142 , 0 x08); 143 , 0 xa2); 148 , 0 xc8); int ant, div_mode; ; ; ; 31 , 0 x08); 65 , 0 x2c); 66 , 0 x38); 68 , 0 x0b); 69 , 0 x12); 73 , 0 x13); 75 , 0 x46); 76 , 0 x28); 77 , 0 x59); 70 , 0 x0a); 79 , 0 x13); 80 , 0 x05); 81 , 0 x33); 82 , 0 x62); 83 , 0 x7a); 84 , 0 x9a); 86 , 0 x38); if (rt2x00_rt(rt2x00dev, RT5392))88 , 0 x90); 91 , 0 x04); 92 , 0 x02); if (rt2x00_rt(rt2x00dev, RT5392)) {95 , 0 x9a); 98 , 0 x12); 103 , 0 xc0); 104 , 0 x92); 105 , 0 x3c); if (rt2x00_rt(rt2x00dev, RT5390))106 , 0 x03); if (rt2x00_rt(rt2x00dev, RT5392))106 , 0 x12); 1 ); 128 , 0 x12); if (rt2x00_rt(rt2x00dev, RT5392)) {134 , 0 xd0); 135 , 0 xf6); ; ; ; 3 ) ? 1 : 0 ; if this is a Bluetooth combo card */if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {; ; 0 ); 0 ); 0 ); 0 ); if (ant == 0 )1 ); if (ant == 1 )1 ); ; if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||150 , 0 ); /* Disable Antenna Software OFDM */ 151 , 0 ); /* Disable Antenna Software CCK */ 154 , 0 ); /* Clear previously selected antenna */ 152 ); if (ant == 0 )1 ); 0 ); 152 , value); ; int ant, div_mode; ; ; ; 105 ); 2 ); 105 , value); ; 20 , 0 x06); 31 , 0 x08); 65 , 0 x2C); 68 , 0 xDD); 69 , 0 x1A); 70 , 0 x05); 73 , 0 x13); 74 , 0 x0F); 75 , 0 x4F); 76 , 0 x28); 77 , 0 x59); 84 , 0 x9A); 86 , 0 x38); 88 , 0 x90); 91 , 0 x04); 92 , 0 x02); 95 , 0 x9a); 98 , 0 x12); 103 , 0 xC0); 104 , 0 x92); 105 , 0 x3C); 106 , 0 x35); 128 , 0 x12); 134 , 0 xD0); 135 , 0 xF6); 137 , 0 x0F); ; ; ; ; 3 ) ? 1 : 0 ; 152 ); if (ant == 0 ) {1 ); 0 ); 152 , value); if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {254 ); 1 ); 254 , value); ; 84 , 0 x19); if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))103 , 0 xc0); ; 2 stream case */105 ); 2 ); 105 , bbp); data loss and CRC errors */; 1 ); 0 x04; 1 , bbp); 3 , 0 x08); 4 , 0 x00); /* rt2800_bbp4_mac_if_ctrl? */ 6 , 0 x08); 14 , 0 x09); 15 , 0 xFF); 16 , 0 x01); 20 , 0 x06); 21 , 0 x00); 22 , 0 x00); 27 , 0 x00); 28 , 0 x00); 30 , 0 x00); 31 , 0 x48); 47 , 0 x40); 62 , 0 x00); 63 , 0 x00); 64 , 0 x00); 65 , 0 x2C); 66 , 0 x1C); 67 , 0 x20); 68 , 0 xDD); 69 , 0 x10); 70 , 0 x05); 73 , 0 x18); 74 , 0 x0F); 75 , 0 x60); 76 , 0 x44); 77 , 0 x59); 78 , 0 x1E); 79 , 0 x1C); 80 , 0 x0C); 81 , 0 x3A); 82 , 0 xB6); 83 , 0 x9A); 84 , 0 x9A); 86 , 0 x38); 88 , 0 x90); 91 , 0 x04); 92 , 0 x02); 95 , 0 x9A); 96 , 0 x00); 103 , 0 xC0); 104 , 0 x92); 105 , 0 x3C); 106 , 0 x12); 109 , 0 x00); 134 , 0 x10); 135 , 0 xA6); 137 , 0 x04); 142 , 0 x30); 143 , 0 xF7); 160 , 0 xEC); 161 , 0 xC4); 162 , 0 x77); 163 , 0 xF9); 164 , 0 x00); 165 , 0 x00); 186 , 0 x00); 187 , 0 x00); 188 , 0 x00); 186 , 0 x00); 187 , 0 x01); 188 , 0 x00); 189 , 0 x00); 91 , 0 x06); 92 , 0 x04); 93 , 0 x54); 99 , 0 x50); 148 , 0 x84); 167 , 0 x80); 178 , 0 xFF); 106 , 0 x13); 0 , 0 x00); 1 , 0 x14); 2 , 0 x20); 3 , 0 x0A); 10 , 0 x16); 11 , 0 x06); 12 , 0 x02); 13 , 0 x07); 14 , 0 x05); 15 , 0 x09); 16 , 0 x20); 17 , 0 x08); 18 , 0 x4A); 19 , 0 x00); 20 , 0 x00); 128 , 0 xE0); 129 , 0 x1F); 130 , 0 x4F); 131 , 0 x32); 132 , 0 x08); 133 , 0 x28); 134 , 0 x19); 135 , 0 x0A); 138 , 0 x16); 139 , 0 x10); 140 , 0 x10); 141 , 0 x1A); 142 , 0 x36); 143 , 0 x2C); 144 , 0 x26); 145 , 0 x24); 146 , 0 x42); 147 , 0 x40); 148 , 0 x30); 149 , 0 x29); 150 , 0 x4C); 151 , 0 x46); 152 , 0 x3D); 153 , 0 x40); 154 , 0 x3E); 155 , 0 x38); 156 , 0 x3D); 157 , 0 x2F); 158 , 0 x3C); 159 , 0 x34); 160 , 0 x2C); 161 , 0 x2F); 162 , 0 x3C); 163 , 0 x35); 164 , 0 x2E); 165 , 0 x2F); 166 , 0 x49); 167 , 0 x41); 168 , 0 x36); 169 , 0 x39); 170 , 0 x30); 171 , 0 x30); 172 , 0 x0E); 173 , 0 x0D); 174 , 0 x28); 175 , 0 x21); 176 , 0 x1C); 177 , 0 x16); 178 , 0 x50); 179 , 0 x4A); 180 , 0 x43); 181 , 0 x50); 182 , 0 x10); 183 , 0 x10); 184 , 0 x10); 185 , 0 x10); 200 , 0 x7D); 201 ,0 )203 , 0 x2C); 204 , 0 x36); 205 , 0 x4C); 206 , 0 x43); 207 , 0 x2C); 208 , 0 x2E); 209 , 0 x36); 210 , 0 x30); 211 , 0 x6E); 140 , 0 x0C); 141 , 0 x00); 142 , 0 x10); 143 , 0 x10); 144 , 0 x10); 145 , 0 x10); 146 , 0 x08); 147 , 0 x40); 148 , 0 x04); 149 , 0 x04); 150 , 0 x08); 151 , 0 x08); 152 , 0 x03); 153 , 0 x03); 154 , 0 x03); 155 , 0 x02); 156 , 0 x40); 157 , 0 x40); 158 , 0 x64); 159 , 0 x64); ; 84 , 0 x19); int i; ; ; ; if (rt2800_is_305x_soc(rt2x00dev)); ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 0 ; i < EEPROM_BBP_SIZE; i++) { ; if (eeprom != 0 xffff && eeprom != 0 x0000) {; ; ; ; ; 1 ); ; int i; ; ; ; ; 0 ; 0 x27 : 0 x07; 24 , rfcsr24); 4 ); 2 * bw40); 4 , bbp); 31 ); ; 31 , rfcsr); 22 ); 1 ); 22 , rfcsr); 24 , 0 ); 0 ; i < 100; i++) { 25 , 0 x90); 1 ); 55 ); if (passband); 24 , 0 x06); 0 ; i < 100; i++) { 25 , 0 x90); 1 ); 55 ); if ((passband - stopband) <= filter_target) {; ; ; 24 , rfcsr24); ; 24 , rfcsr24); ; int rf_reg); ; 0 x80), 1 ); ; 1 ); 0 x80), 0 ); ; ; ; ; ; if (rt2x00_rt(rt2x00dev, RT3070)) {0 x16; 0 x19; 0 x13; 0 x15; ; ; 25 & 26 values for later use in channel switching (for 3052 )25 ); 26 ); 24 , 0 ); 22 ); 0 ); 22 , rfcsr); 4 ); 0 ); 4 , bbp); ; ; ; 17 ); 0 ); if (rt2x00_rt(rt2x00dev, RT3070) ||if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))1 ); 1 : 2 ; if (drv_data->txmixer_gain_24g >= min_gain) {; 17 , rfcsr); if (rt2x00_rt(rt2x00dev, RT3090)) {and ADC1 to reduce power consumption */138 ); ; if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1 )0 ); if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1 )1 ); 138 , bbp); if (rt2x00_rt(rt2x00dev, RT3070)) {27 ); if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))3 ); 0 ); 0 ); 0 ); 0 ); 27 , rfcsr); if (rt2x00_rt(rt2x00dev, RT3071) ||1 ); 1 ); 0 ); 0 ); 1 ); 1 ); 1 , rfcsr); 15 ); 0 ); 15 , rfcsr); 20 ); 0 ); 20 , rfcsr); 21 ); 0 ); 21 , rfcsr); ; ; ; 50 ); 0 ); 50 , rfcsr); 51 ); ; ; 51 , rfcsr); 38 ); 0 ); 38 , rfcsr); 39 ); 0 ); 39 , rfcsr); 1 ); 1 ); 1 ); 1 , rfcsr); 30 ); 2 ); 30 , rfcsr); ; ; and ADC1 to reduce power consumption */138 ); ; if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1 )0 ); if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1 )1 ); 138 , reg); 38 ); 0 ); 38 , reg); 39 ); 0 ); 39 , reg); ; 30 ); 2 ); 30 , reg); 30 ); 0 , 0 x50); 1 , 0 x01); 2 , 0 xf7); 3 , 0 x75); 4 , 0 x40); 5 , 0 x03); 6 , 0 x02); 7 , 0 x50); 8 , 0 x39); 9 , 0 x0f); 10 , 0 x60); 11 , 0 x21); 12 , 0 x75); 13 , 0 x75); 14 , 0 x90); 15 , 0 x58); 16 , 0 xb3); 17 , 0 x92); 18 , 0 x2c); 19 , 0 x02); 20 , 0 xba); 21 , 0 xdb); 22 , 0 x00); 23 , 0 x31); 24 , 0 x08); 25 , 0 x01); 26 , 0 x25); 27 , 0 x23); 28 , 0 x13); 29 , 0 x83); 30 , 0 x00); 31 , 0 x00); ; ; ; this only for 3070 */30 ); 4 , 0 x40); 5 , 0 x03); 6 , 0 x02); 7 , 0 x60); 9 , 0 x0f); 10 , 0 x41); 11 , 0 x21); 12 , 0 x7b); 14 , 0 x90); 15 , 0 x58); 16 , 0 xb3); 17 , 0 x92); 18 , 0 x2c); 19 , 0 x02); 20 , 0 xba); 21 , 0 xdb); 24 , 0 x16); 25 , 0 x03); 29 , 0 x1f); if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {; 1 ); 3 ); ; if (rt2x00_rt(rt2x00dev, RT3071) ||31 , 0 x14); 6 ); 1 ); 6 , rfcsr); ; 1 ); if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||; if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))3 ); 0 ); ; ; 0 ); ; ; if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||27 , 0 x03); ; ; ; 2 ); 1 , 0 x0f); 2 , 0 x80); 3 , 0 x08); 4 , 0 x00); 6 , 0 xa0); 8 , 0 xf3); 9 , 0 x02); 10 , 0 x53); 11 , 0 x4a); 12 , 0 x46); 13 , 0 x9f); 18 , 0 x02); 22 , 0 x20); 25 , 0 x83); 26 , 0 x82); 27 , 0 x09); 29 , 0 x10); 30 , 0 x10); 31 , 0 x80); 32 , 0 x80); 33 , 0 x00); 34 , 0 x05); 35 , 0 x12); 36 , 0 x00); 38 , 0 x85); 39 , 0 x1b); 40 , 0 x0b); 41 , 0 xbb); 42 , 0 xd5); 43 , 0 x7b); 44 , 0 x0e); 45 , 0 xa2); 46 , 0 x73); 47 , 0 x00); 48 , 0 x10); 49 , 0 x98); 52 , 0 x38); 53 , 0 x00); 54 , 0 x78); 55 , 0 x43); 56 , 0 x02); 57 , 0 x80); 58 , 0 x7f); 59 , 0 x09); 60 , 0 x45); 61 , 0 xc1); 29 ); 3 ); 29 , rfcsr); ; ; int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0,; int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1,; ; 30 ); 0 , 0 xf0); 1 , 0 x23); 2 , 0 x50); 3 , 0 x18); 4 , 0 x00); 5 , 0 x00); 6 , 0 x33); 7 , 0 x00); 8 , 0 xf1); 9 , 0 x02); 10 , 0 xd2); 11 , 0 x42); 12 , 0 x1c); 13 , 0 x00); 14 , 0 x5a); 15 , 0 x00); 16 , 0 x01); 18 , 0 x45); 19 , 0 x02); 20 , 0 x00); 21 , 0 x00); 22 , 0 x00); 23 , 0 x00); 24 , 0 x00); 25 , 0 x80); 26 , 0 x00); 27 , 0 x03); 28 , 0 x03); 29 , 0 x00); 30 , 0 x10); 31 , 0 x80); 32 , 0 x80); 33 , 0 x00); 0 x01; if (tx0_ext_pa)1 ); if (tx1_ext_pa)1 ); 34 , rfcsr); 35 , 0 x03); 36 , 0 xbd); 37 , 0 x3c); 38 , 0 x5f); 39 , 0 xc5); 40 , 0 x33); 0 x52; if (!tx0_ext_pa) {1 ); 1 ); 41 , rfcsr); 0 x52; if (!tx1_ext_pa) {1 ); 1 ); 42 , rfcsr); 43 , 0 xdb); 44 , 0 xdb); 45 , 0 xdb); 46 , 0 xdd); 47 , 0 x0d); 48 , 0 x14); 49 , 0 x00); 0 x2d; if (tx0_ext_pa)1 ); if (tx1_ext_pa)1 ); 50 , rfcsr); 51 , (tx0_ext_pa ? 0 x52 : 0 x7f)); 52 , (tx0_ext_pa ? 0 xc0 : 0 x00)); 53 , (tx0_ext_pa ? 0 xd2 : 0 x52)); 54 , (tx0_ext_pa ? 0 xc0 : 0 x1b)); 55 , (tx1_ext_pa ? 0 x52 : 0 x7f)); 56 , (tx1_ext_pa ? 0 xc0 : 0 x00)); 57 , (tx0_ext_pa ? 0 x49 : 0 x52)); 58 , (tx1_ext_pa ? 0 xc0 : 0 x1b)); 59 , 0 x00); 60 , 0 x00); 61 , 0 x00); 62 , 0 x00); 63 , 0 x00); ; ; ; ; 30 ); 0 , 0 xa0); 1 , 0 xe1); 2 , 0 xf1); 3 , 0 x62); 4 , 0 x40); 5 , 0 x8b); 6 , 0 x42); 7 , 0 x34); 8 , 0 x00); 9 , 0 xc0); 10 , 0 x61); 11 , 0 x21); 12 , 0 x3b); 13 , 0 xe0); 14 , 0 x90); 15 , 0 x53); 16 , 0 xe0); 17 , 0 x94); 18 , 0 x5c); 19 , 0 x4a); 20 , 0 xb2); 21 , 0 xf6); 22 , 0 x00); 23 , 0 x14); 24 , 0 x08); 25 , 0 x3d); 26 , 0 x85); 27 , 0 x00); 28 , 0 x41); 29 , 0 x8f); 30 , 0 x20); 31 , 0 x0f); ; 0 ); ; ; if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))27 , 0 x03); ; ; ; ; 30 ); 0 , 0 x70); 1 , 0 x81); 2 , 0 xf1); 3 , 0 x02); 4 , 0 x4c); 5 , 0 x05); 6 , 0 x4a); 7 , 0 xd8); 9 , 0 xc3); 10 , 0 xf1); 11 , 0 xb9); 12 , 0 x70); 13 , 0 x65); 14 , 0 xa0); 15 , 0 x53); 16 , 0 x4c); 17 , 0 x23); 18 , 0 xac); 19 , 0 x93); 20 , 0 xb3); 21 , 0 xd0); 22 , 0 x00); 23 , 0 x3c); 24 , 0 x16); 25 , 0 x15); 26 , 0 x85); 27 , 0 x00); 28 , 0 x00); 29 , 0 x9b); 30 , 0 x09); 31 , 0 x10); 6 ); 1 ); 6 , rfcsr); ; 3 ); 1 ); ; 1 ); ; 0 ); 1 ); ; ; ; ; ; ; /* FIXME */ 105 ); if (rt2x00dev->default_ant.rx_chain_num == 1 )0 ); 1 ); 105 , bbp); ; 92 , 0 x02); 82 , 0 x82); 106 , 0 x05); 104 , 0 x92); 88 , 0 x90); 148 ,0 c8; 47 , 0 x48); 120 , 0 x50); if (txbf_enabled)163 , 0 xbd); 163 , 0 x9d); 142 , 6 ); 143 , 160 ); 142 , 7 ); 143 , 161 ); 142 , 8 ); 143 , 162 ); ADC /DAC control */31 , 0 x08); 68 , 0 x0b); 105 owerwrite? */105 , 0 x04); ; ; ; 4 and #7 function for LAN PE control */; 0 ); 0 ); ; 1 , 0 x03); 3 , 0 x80); 5 , 0 x00); 6 , 0 x40); 8 , 0 xf1); 9 , 0 x02); 10 , 0 xd3); 11 , 0 x40); 12 , 0 x4e); 13 , 0 x12); 18 , 0 x40); 22 , 0 x20); 30 , 0 x10); 31 , 0 x80); 32 , 0 x78); 33 , 0 x3b); 34 , 0 x3c); 35 , 0 xe0); 38 , 0 x86); 39 , 0 x23); 44 , 0 xd3); 45 , 0 xbb); 46 , 0 x60); 49 , 0 x8e); 50 , 0 x86); 51 , 0 x75); 52 , 0 x45); 53 , 0 x18); 54 , 0 x18); 55 , 0 x18); 56 , 0 xdb); 57 , 0 x6e); 2 ); 1 ); 2 , rfcsr); ; 18 ); 1 ); 18 , rfcsr); ; 3 ); 1 ); ; 1000 , 1500 ); ; 0 ); ; 0 x1f; 0 x2f; 25 & 26 values for later use in channel switching */25 ); 26 ); ; ; ; 0 , 0 xf0); 1 , 0 x23); 2 , 0 x50); 3 , 0 x08); 4 , 0 x49); 5 , 0 x10); 6 , 0 xe0); 7 , 0 x00); 8 , 0 xf1); 9 , 0 x02); 10 , 0 x53); 11 , 0 x4a); 12 , 0 x46); if (rt2800_clk_is_20mhz(rt2x00dev))13 , 0 x1f); 13 , 0 x9f); 14 , 0 x00); 15 , 0 x00); 16 , 0 xc0); 18 , 0 x03); 19 , 0 x00); 20 , 0 x00); 21 , 0 x00); 22 , 0 x20); 23 , 0 x00); 24 , 0 x00); 25 , 0 x80); 26 , 0 x00); 27 , 0 x03); 28 , 0 x00); 29 , 0 xd0); 30 , 0 x10); 31 , 0 x80); 32 , 0 x80); 33 , 0 x00); 34 , 0 x07); 35 , 0 x12); 36 , 0 x00); 37 , 0 x08); 38 , 0 x85); 39 , 0 x1b); 40 , 0 x0b); 41 , 0 xbb); 42 , 0 xd5); 43 , 0 x9b); 44 , 0 x0c); 45 , 0 xa6); 46 , 0 x73); 47 , 0 x00); 48 , 0 x10); 49 , 0 x80); 50 , 0 x00); 51 , 0 x00); 52 , 0 x38); 53 , 0 x00); 54 , 0 x38); 55 , 0 x43); 56 , 0 x82); 57 , 0 x00); 58 , 0 x39); 59 , 0 x0b); 60 , 0 x45); 61 , 0 xd1); 62 , 0 x00); 63 , 0 x00); ; int eco = 5 ; 2 ); 0 , 0 xe0); 1 , 0 x03); 2 , 0 x50); 3 , 0 x20); 4 , 0 x00); 5 , 0 x00); 6 , 0 x40); 7 , 0 x00); 8 , 0 x5b); 9 , 0 x08); 10 , 0 xd3); 11 , 0 x48); 12 , 0 x1a); 13 , 0 x12); 14 , 0 x00); 15 , 0 x00); 16 , 0 x00); 17 will be initialized later based on the18 , 0 x40); 19 , 0 x00); 20 , 0 x00); 21 , 0 x00); 22 , 0 x20); 23 , 0 xc0); 24 , 0 x00); 25 , 0 x00); 26 , 0 x00); 27 , 0 x00); 28 , 0 x00); 29 , 0 x00); 30 , 0 x10); 31 , 0 x80); 32 , 0 x80); 33 , 0 x00); 34 , 0 x20); 35 , 0 x00); 36 , 0 x00); 37 , 0 x00); 38 , 0 x86); 39 , 0 x23); 40 , 0 x00); 41 , 0 x00); 42 , 0 x00); 43 , 0 x00); 44 , 0 x93); 45 , 0 xbb); 46 , 0 x60); 47 , 0 x00); 48 , 0 x00); 49 , 0 x8e); 50 , 0 x86); 51 , 0 x51); 52 , 0 x05); 53 , 0 x76); 54 , 0 x76); 55 , 0 x76); 56 , 0 xdb); 57 , 0 x3e); 58 , 0 x00); 59 , 0 x00); 60 , 0 x00); 61 , 0 x00); 62 , 0 x00); 63 , 0 x00); 137 , 0 x0f); 163 , 0 x9d); 105 , 0 x05); 179 , 0 x02); 180 , 0 x00); 182 , 0 x40); 180 , 0 x01); 182 , 0 x9c); 179 , 0 x00); 142 , 0 x04); 143 , 0 x3b); 142 , 0 x06); 143 , 0 xa0); 142 , 0 x07); 143 , 0 xa1); 142 , 0 x08); 143 , 0 xa2); 148 , 0 xc8); if (eco == 5 ) {32 , 0 xd8); 33 , 0 x32); 2 ); 0 ); 1 ); 2 , rfcsr); 1 ); 0 ); 2 , rfcsr); 1 ); 1 ); 1 , rfcsr); 6 ); 0 xc0; 6 , rfcsr); 22 ); 0 x20; 22 , rfcsr); 46 ); 0 x20; 46 , rfcsr); 20 ); 0 xee; 20 , rfcsr); 2 ); 1 , 0 x0f); 2 , 0 x80); 3 , 0 x88); 5 , 0 x10); if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))6 , 0 xe0); 6 , 0 xa0); 7 , 0 x00); 10 , 0 x53); 11 , 0 x4a); 12 , 0 x46); 13 , 0 x9f); 14 , 0 x00); 15 , 0 x00); 16 , 0 x00); 18 , 0 x03); 19 , 0 x00); 20 , 0 x00); 21 , 0 x00); 22 , 0 x20); 23 , 0 x00); 24 , 0 x00); if (rt2x00_is_usb(rt2x00dev) &&25 , 0 x80); 25 , 0 xc0); 26 , 0 x00); 27 , 0 x09); 28 , 0 x00); 29 , 0 x10); 30 , 0 x10); 31 , 0 x80); 32 , 0 x80); 33 , 0 x00); 34 , 0 x07); 35 , 0 x12); 36 , 0 x00); 37 , 0 x08); 38 , 0 x85); 39 , 0 x1b); 40 , 0 x0b); 41 , 0 xbb); 42 , 0 xd2); 43 , 0 x9a); 44 , 0 x0e); 45 , 0 xa2); if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))46 , 0 x73); 46 , 0 x7b); 47 , 0 x00); 48 , 0 x10); 49 , 0 x94); 52 , 0 x38); if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))53 , 0 x00); 53 , 0 x84); 54 , 0 x78); 55 , 0 x44); if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))56 , 0 x42); 56 , 0 x22); 57 , 0 x80); 58 , 0 x7f); 59 , 0 x8f); 60 , 0 x45); if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {if (rt2x00_is_usb(rt2x00dev))61 , 0 xd1); 61 , 0 xd5); if (rt2x00_is_usb(rt2x00dev))61 , 0 xdd); 61 , 0 xb5); 62 , 0 x00); 63 , 0 x00); ; ; 2 ); 1 , 0 x17); 3 , 0 x88); 5 , 0 x10); 6 , 0 xe0); 7 , 0 x00); 10 , 0 x53); 11 , 0 x4a); 12 , 0 x46); 13 , 0 x9f); 14 , 0 x00); 15 , 0 x00); 16 , 0 x00); 18 , 0 x03); 19 , 0 x4d); 20 , 0 x00); 21 , 0 x8d); 22 , 0 x20); 23 , 0 x0b); 24 , 0 x44); 25 , 0 x80); 26 , 0 x82); 27 , 0 x09); 28 , 0 x00); 29 , 0 x10); 30 , 0 x10); 31 , 0 x80); 32 , 0 x20); 33 , 0 xC0); 34 , 0 x07); 35 , 0 x12); 36 , 0 x00); 37 , 0 x08); 38 , 0 x89); 39 , 0 x1b); 40 , 0 x0f); 41 , 0 xbb); 42 , 0 xd5); 43 , 0 x9b); 44 , 0 x0e); 45 , 0 xa2); 46 , 0 x73); 47 , 0 x0c); 48 , 0 x10); 49 , 0 x94); 50 , 0 x94); 51 , 0 x3a); 52 , 0 x48); 53 , 0 x44); 54 , 0 x38); 55 , 0 x43); 56 , 0 xa1); 57 , 0 x00); 58 , 0 x39); 59 , 0 x07); 60 , 0 x45); 61 , 0 x91); 62 , 0 x39); 63 , 0 x07); ; ; 30 ); 1 , 0 x3F); 3 , 0 x08); 5 , 0 x10); 6 , 0 xE4); 7 , 0 x00); 14 , 0 x00); 15 , 0 x00); 16 , 0 x00); 18 , 0 x03); 19 , 0 x4D); 20 , 0 x10); 21 , 0 x8D); 26 , 0 x82);28 , 0 x00);29 , 0 x10);33 , 0 xC0);34 , 0 x07);35 , 0 x12);47 , 0 x0C);53 , 0 x22);63 , 0 x07);2 , 0 x80);1 );/* Enable DC filter */ if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))103 , 0 xc0);if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))27 , 0 x03);static void rt2800_rf_self_txdc_cal(struct rt2x00_dev *rt2x00dev)0 x0);0 x0);0 xC);0 x3306);0 x3330);0 xfffff);5 , 1 );7 , 1 );5 , 1 , 0 x4);for (i = 0 ; i < 100 ; ++i) {50 , 100 );5 , 1 );if ((rfvalue & 0 x04) != 0 x4)break ;5 , 1 , rfb5r1_org);7 , 1 , 0 x4);for (i = 0 ; i < 100 ; ++i) {50 , 100 );7 , 1 );if ((rfvalue & 0 x04) != 0 x4)break ;7 , 1 , rfb7r1_org);0 x0);0 x0);static int rt2800_calcrcalibrationcode(struct rt2x00_dev *rt2x00dev, int d1, int d2)int calcode = ((d2 - d1) * 1000 ) / 43 ;if ((calcode % 10 ) >= 5 )10 ;10 );return calcode;static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev)0 ;int rcalcode;0 ;0 , d2 = 0 ;0 , 1 );0 , 34 );0 , 35 );5 , 4 );5 , 17 );5 , 18 );5 , 19 );5 , 20 );22 );47 );49 );0 x04);if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))"Wait MAC Tx Status to MAX !!!\n" );0 x08);if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))"Wait MAC Rx Status to MAX !!!\n" );0 x3004);0 x3002));5 , 4 , 0 x27);5 , 17 , 0 x80);5 , 18 , 0 x83);5 , 19 , 0 x00);5 , 20 , 0 x20);0 , 1 , 0 x00);0 , 34 , 0 x13);0 , 35 , 0 x00);0 x1);47 , 0 x04);22 , 0 x80);100 , 200 );49 );if (bytevalue > 128 )256 ;else 22 , 0 x0);0 , 35 , 0 x01);22 , 0 x80);100 , 200 );49 );if (bytevalue > 128 )256 ;else 22 , 0 x0);if (rcalcode < 0 )256 + rcalcode;else 0 , 7 , r_cal_code);22 , 0 x0);21 );0 x1;21 , bytevalue);21 );0 x1);21 , bytevalue);0 , 1 , saverfb0r1);0 , 34 , saverfb0r34);0 , 35 , saverfb0r35);5 , 4 , saverfb5r4);5 , 17 , saverfb5r17);5 , 18 , saverfb5r18);5 , 19 , saverfb5r19);5 , 20 , saverfb5r20);22 , savebbpr22);47 , savebbpr47);49 , savebbpr49);static void rt2800_rxdcoc_calibration(struct rt2x00_dev *rt2x00dev)0 ;0 ;int i;0 , 2 );0 x03;0 , 2 , rfvalue);158 , 141 );159 );0 x10;159 , bbpreg);0 x8);if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))"RF TX busy in RX RXDCOC calibration\n" );5 , 4 );7 , 4 );0 x40);0 x40);4 , 0 x64);5 , 4 , saverfb5r4);7 , 4 , saverfb7r4);158 , 140 );159 );0 x40);159 , bbpreg);0 x48;159 , bbpreg);for (i = 0 ; i < 10000 ; i++) {159 );if ((bbpreg & 0 x40) == 0 )break ;50 , 100 );159 );0 x40);159 , bbpreg);158 , 141 );159 );0 x10);159 , bbpreg);0 , 2 , saverfb0r2);static u32 rt2800_do_sqrt_accumulation(u32 si)1 << 15 ;0 ;for (i = 15 ; i >= 0 ; i = i - 1 ) {if ((root_pre * root_pre) <= si)1 ;return root;static void rt2800_rxiq_calibration(struct rt2x00_dev *rt2x00dev)0 ;int mi = 0 , mq = 0 , si = 0 , sq = 0 , riq = 0 ;int sigma_i, sigma_q, r_iq, g_rx;int g_imb;int ph_rx;0 ;0 ;0 ;0 ;0 ;0 ;0 ;0 ;static const u8 rf_vga_table[] = {0 x20, 0 x21, 0 x22, 0 x38, 0 x39, 0 x3a, 0 x3b, 0 x3c, 0 x3d, 0 x3e, 0 x3f};1 );4 );0 x0);if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))"Timeout waiting for MAC status in RXIQ calibration\n" );0 x18);0 x00;4 , bbpval);21 );1 ;21 , bbpval);0 xfe;21 , bbpval);0 x00000202);0 x00000303);if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))0 x0101);else 0 x0000);0 xf1f1);0 , 1 );0 , 2 );0 , 42 );4 , 0 );4 , 19 );5 , 3 );5 , 4 );5 , 17 );5 , 18 );5 , 19 );5 , 20 );6 , 0 );6 , 19 );7 , 3 );7 , 4 );7 , 17 );7 , 18 );7 , 19 );7 , 20 );0 , 0 x87);19 , 0 x27);3 , 0 x38);4 , 0 x38);17 , 0 x80);18 , 0 xC1);19 , 0 x60);20 , 0 x00);23 , 0 x0);24 , 0 x0);5 , 0 x0);241 );242 );241 , 0 x10);242 , 0 x84);244 , 0 x31);3 );0 x7);3 , bbpval);0 x00000004);1 );0 x00000006);1 , 200 );0 x00003376);0 x00001006);1 );if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {23 , 0 x06);24 , 0 x06);else {23 , 0 x02);24 , 0 x02);for (ch_idx = 0 ; ch_idx < 2 ; ch_idx = ch_idx + 1 ) {if (ch_idx == 0 ) {0 x1;0 , 1 , rfval);0 x11;0 , 2 , rfval);0 x10;0 , 42 , rfval);0 x00001006);1 );0 x18);0 x00;1 , bbpval);1 , 0 x00);else {0 x2;0 , 1 , rfval);0 x22;0 , 2 , rfval);0 x40;0 , 42 , rfval);0 x00002006);1 );0 x18);0 x08;1 , bbpval);1 , 0 x01);500 , 1500 );0 ;while (vga_idx < 11 ) {3 , rf_vga_table[vga_idx]);4 , rf_vga_table[vga_idx]);0 , 0 x93);for (i = 0 ; i < 10000 ; i++) {159 );if ((bbpval & 0 xff) == 0 x93)50 , 100 );else break ;if ((bbpval & 0 xff) == 0 x93) {"Fatal Error: Calibration doesn't finish" );goto restore_value;for (i = 0 ; i < 5 ; i++) {0 ;0 ;int result = 0 ;158 , 0 x1e);159 , i);158 , 0 x22);159 );24 );158 , 0 x21);159 );16 );158 , 0 x20);159 );8 );158 , 0 x1f);159 );if (i < 2 && (bbptemp & 0 x800000))0 xffffff) - 0 x1000000;else if (i == 0 )4096 ;else if (i == 1 )4096 ;else if (i == 2 )4096 ;else if (i == 3 )4096 ;else 4096 ;"RXIQ si=%d, sq=%d, riq=%d, bbpval %d, vga_idx %d" ,if (bbpval1 >= (100 * 100 ))break ;if (bbpval1 <= 100 )9 ;else if (bbpval1 <= 158 )8 ;else if (bbpval1 <= 251 )7 ;else if (bbpval1 <= 398 )6 ;else if (bbpval1 <= 630 )5 ;else if (bbpval1 <= 1000 )4 ;else if (bbpval1 <= 1584 )3 ;else if (bbpval1 <= 2511 )2 ;else 1 ;100 * (si - mi * mi));100 * (sq - mq * mq));10 * (riq - (mi * mq));"Sigma_i=%d, Sigma_q=%d, R_iq=%d" , sigma_i, sigma_q, r_iq);if (sigma_i <= 1400 && sigma_i >= 1000 &&112 &&112 &&32 && mi >= -32 &&32 && mq >= -32 ) {10 * (riq - (mi * mq));"RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n" ,1000 * sigma_q) / sigma_i;2 ) * 128 * (1000 - g_rx)) / (1000 + g_rx);2292 ) / (sigma_i * sigma_q);if (ph_rx > 20 || ph_rx < -20 ) {0 ;"RXIQ calibration FAIL" );if (g_imb > 12 || g_imb < -12 ) {0 ;"RXIQ calibration FAIL" );else {0 ;0 ;"RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n" ,"RXIQ calibration FAIL" );if (ch_idx == 0 ) {158 , 0 x37);159 , g_imb & 0 x3f);158 , 0 x35);159 , ph_rx & 0 x3f);else {158 , 0 x55);159 , g_imb & 0 x3f);158 , 0 x53);159 , ph_rx & 0 x3f);158 , 0 x3);159 );159 , (bbpval | 0 x07));158 , 0 x00);159 , 0 x00);1 , bbp1);4 , bbp4);241 , bbpr241);242 , bbpr242);244 , 0 x00);21 );0 x1;21 , bbpval);10 , 200 );0 xfe;21 , bbpval);0 , 1 , rfb0r1);0 , 2 , rfb0r2);0 , 42 , rfb0r42);4 , 0 , rfb4r0);4 , 19 , rfb4r19);5 , 3 , rfb5r3);5 , 4 , rfb5r4);5 , 17 , rfb5r17);5 , 18 , rfb5r18);5 , 19 , rfb5r19);5 , 20 , rfb5r20);6 , 0 , rfb6r0);6 , 19 , rfb6r19);7 , 3 , rfb7r3);7 , 4 , rfb7r4);7 , 17 , rfb7r17);7 , 18 , rfb7r18);7 , 19 , rfb7r19);7 , 20 , rfb7r20);0 x00000006);1 );0 x00000004);1 );1 );static void rt2800_rf_configstore(struct rt2x00_dev *rt2x00dev,struct rf_reg_pair rf_reg_record[][13 ], u8 chain)0 ;if (chain == CHAIN_0) {0 , 1 );0 ].bank = 0 ;0 ].reg = 1 ;0 ].value = rfvalue;0 , 2 );1 ].bank = 0 ;1 ].reg = 2 ;1 ].value = rfvalue;0 , 35 );2 ].bank = 0 ;2 ].reg = 35 ;2 ].value = rfvalue;0 , 42 );3 ].bank = 0 ;3 ].reg = 42 ;3 ].value = rfvalue;4 , 0 );4 ].bank = 4 ;4 ].reg = 0 ;4 ].value = rfvalue;4 , 2 );5 ].bank = 4 ;5 ].reg = 2 ;5 ].value = rfvalue;4 , 34 );6 ].bank = 4 ;6 ].reg = 34 ;6 ].value = rfvalue;5 , 3 );7 ].bank = 5 ;7 ].reg = 3 ;7 ].value = rfvalue;5 , 4 );8 ].bank = 5 ;8 ].reg = 4 ;8 ].value = rfvalue;5 , 17 );9 ].bank = 5 ;9 ].reg = 17 ;9 ].value = rfvalue;5 , 18 );10 ].bank = 5 ;10 ].reg = 18 ;10 ].value = rfvalue;5 , 19 );11 ].bank = 5 ;11 ].reg = 19 ;11 ].value = rfvalue;5 , 20 );12 ].bank = 5 ;12 ].reg = 20 ;12 ].value = rfvalue;else if (chain == CHAIN_1) {0 , 1 );0 ].bank = 0 ;0 ].reg = 1 ;0 ].value = rfvalue;0 , 2 );1 ].bank = 0 ;1 ].reg = 2 ;1 ].value = rfvalue;0 , 35 );2 ].bank = 0 ;2 ].reg = 35 ;2 ].value = rfvalue;0 , 42 );3 ].bank = 0 ;3 ].reg = 42 ;3 ].value = rfvalue;6 , 0 );4 ].bank = 6 ;4 ].reg = 0 ;4 ].value = rfvalue;6 , 2 );5 ].bank = 6 ;5 ].reg = 2 ;5 ].value = rfvalue;6 , 34 );6 ].bank = 6 ;6 ].reg = 34 ;6 ].value = rfvalue;7 , 3 );7 ].bank = 7 ;7 ].reg = 3 ;7 ].value = rfvalue;7 , 4 );8 ].bank = 7 ;8 ].reg = 4 ;8 ].value = rfvalue;7 , 17 );9 ].bank = 7 ;9 ].reg = 17 ;9 ].value = rfvalue;7 , 18 );10 ].bank = 7 ;10 ].reg = 18 ;10 ].value = rfvalue;7 , 19 );11 ].bank = 7 ;11 ].reg = 19 ;11 ].value = rfvalue;7 , 20 );12 ].bank = 7 ;12 ].reg = 20 ;12 ].value = rfvalue;else {"Unknown chain = %u\n" , chain);static void rt2800_rf_configrecover(struct rt2x00_dev *rt2x00dev,struct rf_reg_pair rf_record[][13 ])0 , record_index = 0 ;0 , rf_register = 0 , value = 0 ;for (chain_index = 0 ; chain_index < 2 ; chain_index++) {for (record_index = 0 ; record_index < 13 ; record_index++) {"bank: %d, rf_register: %d, value: %x\n" ,static void rt2800_setbbptonegenerator(struct rt2x00_dev *rt2x00dev)158 , 0 xAA);159 , 0 x00);158 , 0 xAB);159 , 0 x0A);158 , 0 xAC);159 , 0 x3F);158 , 0 xAD);159 , 0 x3F);244 , 0 x40);static u32 rt2800_do_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx, u8 read_neg)0 ;int fftout_i = 0 , fftout_q = 0 ;0 , pint = 0 ;0 ;158 , 0 x00);159 , 0 x9b);0 x9b;while (bbp == 0 x9b) {10 , 50 );159 );0 xff;158 , 0 xba);159 , tidx);159 , tidx);159 , tidx);0 x057C);16 );0 x8000) ? (fftout_i - 0 x10000) : fftout_i;0 xffff);0 x8000) ? (fftout_q - 0 x10000) : fftout_q;"I = %d, Q = %d, power = %x\n" , fftout_i, fftout_q, pint);if (read_neg) {1 ;0 x40 - tidx;0 x3f;158 , 0 xba);159 , tidxi);159 , tidxi);159 , tidxi);0 x057C);16 );0 x8000) ? (fftout_i - 0 x10000) : fftout_i;0 xffff);0 x8000) ? (fftout_q - 0 x10000) : fftout_q;1 ;return pint;static u32 rt2800_read_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx)0 ;int fftout_i = 0 , fftout_q = 0 ;0 , pint = 0 ;158 , 0 xBA);159 , tidx);159 , tidx);159 , tidx);0 x057C);16 );0 x8000) ? (fftout_i - 0 x10000) : fftout_i;0 xffff);0 x8000) ? (fftout_q - 0 x10000) : fftout_q;return pint;static void rt2800_write_dc(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc, u8 iorq, u8 dc)0 ;158 , 0 xb0);0 x80;159 , bbp);if (ch_idx == 0 )0 ) ? 0 xb1 : 0 xb2;else 0 ) ? 0 xb8 : 0 xb9;158 , bbp);159 , bbp);static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx,2 ])0 , p1 = 0 , pf = 0 ;0 , idx1 = 0 ;0 x00, 0 x00};0 x20;158 , 0 xb0);159 , 0 x80);for (bidx = 5 ; bidx >= 0 ; bidx--) {for (iorq = 0 ; iorq <= 1 ; iorq++) {if (idxf[iorq] == 0 x20) {0 x20;else {0 x3F;0 , iorq, idx0);0 x0A, 0 );5 ? 0 : ibit);0 x3F;0 , iorq, idx1);0 x0A, 0 );"alc=%u, IorQ=%u, idx_final=%2x\n" ,"p0=%x, p1=%x, pf=%x, idx_0=%x, idx_1=%x, ibit=%x\n" ,if (bidx != 5 && pf <= p0 && pf < p1) {/* no need to adjust idxf[] */; else if (p0 < p1) {0 x3F;else {0 x3F;"IorQ=%u, idx_final[%u]:%x, pf:%8x\n" ,0 , iorq, idxf[iorq]);1 ;0 ] = idxf[0 ];1 ] = idxf[1 ];static void rt2800_iq_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 *ges, u8 *pes)0 , p1 = 0 , pf = 0 ;0 , gerr = 0 , iq_err = 0 ;0 , gef = 0 ;0 x20;0 x00, touch_neg_max = 0 x00;0 , idx1 = 0 ;0 ;for (bidx = 5 ; bidx >= 1 ; bidx--) {for (gop = 0 ; gop < 2 ; gop++) {if (gop == 1 || bidx < 4 ) {if (gop == 0 )else 0 ) ? (bidx == 3 ) : (bidx == 5 );0 x0F) == 0 x08) :0 x3F) == 0 x20);if (touch_neg_max) {else {0 ) ? ((gop == 0 ) ? 0 x28 : 0 x29) :0 ) ? 0 x46 : 0 x47);158 , bbp);159 , idx0);0 x14, 1 );0 : ibit);0 ) ? (idx1 & 0 x0F) : (idx1 & 0 x3F);0 ) ? (gop == 0 ) ? 0 x28 : 0 x29 :0 ) ? 0 x46 : 0 x47;158 , bbp);159 , idx1);0 x14, 1 );"p0=%x, p1=%x, pwer_final=%x, idx0=%x, idx1=%x, iq_err=%x, gop=%d, ibit=%x\n" ,if (!(!first_search && pf <= p0 && pf < p1)) {if (p0 < p1) {else {0 ) ? (gop == 0 ) ? 0 x28 : 0 x29 :0 ) ? 0 x46 : 0 x47;158 , bbp);159 , iq_err);if (gop == 0 )else "IQCalibration pf=%8x (%2x, %2x) !\n" ,0 x0F, perr & 0 x3F);if (bidx > 0 )1 );0 x08) ? (gerr & 0 x0F) - 0 x10 : (gerr & 0 x0F);0 x20) ? (perr & 0 x3F) - 0 x40 : (perr & 0 x3F);0 x07) ? -0 x07 : (gerr > 0 x05) ? 0 x05 : gerr;1 ;2 ;0 x1f) ? -0 x1f : (perr > 0 x1d) ? 0 x1d : perr;1 ;2 ;for (gef = gsta; gef <= gend; gef = gef + 1 )for (pef = psta; pef <= pend; pef = pef + 1 ) {0 ) ? 0 x28 : 0 x46;158 , bbp);159 , gef & 0 x0F);0 ) ? 0 x29 : 0 x47;158 , bbp);159 , pef & 0 x3F);0 x14, 1 );if (gef == gsta && pef == psta) {else if (pf > p1) {"Fine IQCalibration p1=%8x pf=%8x (%2x, %2x) !\n" ,0 x0F, pef & 0 x3F);0 x0F;0 x3F;static void rt2800_rf_aux_tx0_loopback(struct rt2x00_dev *rt2x00dev)0 , 1 , 0 x21);0 , 2 , 0 x10);0 , 35 , 0 x00);0 , 42 , 0 x1b);4 , 0 , 0 x81);4 , 2 , 0 x81);4 , 34 , 0 xee);5 , 3 , 0 x2d);5 , 4 , 0 x2d);5 , 17 , 0 x80);5 , 18 , 0 xd7);5 , 19 , 0 xa2);5 , 20 , 0 x20);static void rt2800_rf_aux_tx1_loopback(struct rt2x00_dev *rt2x00dev)0 , 1 , 0 x22);0 , 2 , 0 x20);0 , 35 , 0 x00);0 , 42 , 0 x4b);6 , 0 , 0 x81);6 , 2 , 0 x81);6 , 34 , 0 xee);7 , 3 , 0 x2d);7 , 4 , 0 x2d);7 , 17 , 0 x80);7 , 18 , 0 xd7);7 , 19 , 0 xa2);7 , 20 , 0 x20);static void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev)struct rf_reg_pair rf_store[CHAIN_NUM][13 ];0 ;0 ;0 ;0 ;0 ;0 ;0 ;0 ;0 ;0 ;0 , p1 = 0 ;0 , p1_idx10 = 0 ;2 ];14 , 14 };0 , ch_idx = 0 , rf_alc_idx = 0 , idx = 0 ;static const u8 rf_gain[] = {0 x00, 0 x01, 0 x02, 0 x04, 0 x08, 0 x0c};static const u8 rfvga_gain_table[] = {0 x24, 0 x25, 0 x26, 0 x27, 0 x28, 0 x2c, 0 x2d, 0 x2e, 0 x2f, 0 x30,0 x31, 0 x38, 0 x39, 0 x3a, 0 x3b, 0 x3c, 0 x3d, 0 x3e, 0 x3F};static const u8 bbp_2324gain[] = {0 x16, 0 x14, 0 x12, 0 x10, 0 x0c, 0 x08};0 x13b8);0 x04);if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))"RF TX busy in LOFT IQ calibration\n" );0 x08);if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))"RF RX busy in LOFT IQ calibration\n" );for (ch_idx = 0 ; ch_idx < 2 ; ch_idx++)30 );0 , 39 );0 , 42 );30 , 0 x1F);0 , 39 , 0 x80);0 , 42 , 0 x5B);23 , 0 x00);24 , 0 x00);for (ch_idx = 0 ; ch_idx < 2 ; ch_idx++) {23 , 0 x00);24 , 0 x00);0 x00);0 x0000000F);0 x00000004);0 x00003306);0 x13b8, 0 x10);1 );if (ch_idx == 0 )else 1 );if (ch_idx == 0 )0 x00001004);else 0 x00002004);158 , 0 x05);159 , 0 x00);158 , 0 x01);if (ch_idx == 0 )159 , 0 x00);else 159 , 0 x01);18 ;for (rf_alc_idx = 0 ; rf_alc_idx < 3 ; rf_alc_idx++) {23 , bbp_2324gain[rf_alc_idx]);24 , bbp_2324gain[rf_alc_idx]);0 x0000F1F1);4 );12 );0 x0000F1F1);if (rf_alc_idx == 0 ) {0 , 1 , 0 x21);for (; vga_gain[ch_idx] > 0 ;2 ) {3 , rfvalue);4 , rfvalue);0 , 1 , 0 x00);0 , 0 , 0 x00);0 x0A, 0 );0 , 0 , 0 x21);0 x0A, 0 );"LOFT AGC %d %d\n" , p0, p1);if ((p0 < 7000 * 7000 ) && (p1 < (7000 * 7000 )))break ;0 , 0 , 0 x00);0 , 1 , 0 x00);"Used VGA %d %x\n" , vga_gain[ch_idx],3 , rfvalue);4 , rfvalue);for (rf_alc_idx = 0 ; rf_alc_idx < 3 ; rf_alc_idx++) {for (idx = 0 ; idx < 4 ; idx++) {158 , 0 xB0);2 ) + rf_alc_idx;159 , bbp);" ALC %2x," , bbp);158 , 0 xb1);0 x00];0 x3F;159 , bbp);" I0 %2x," , bbp);158 , 0 xb2);0 x01];0 x3F;159 , bbp);" Q0 %2x," , bbp);158 , 0 xb8);0 x00];0 x3F;159 , bbp);" I1 %2x," , bbp);158 , 0 xb9);0 x01];0 x3F;159 , bbp);" Q1 %2x\n" , bbp);23 , 0 x00);24 , 0 x00);0 x04);158 , 0 x00);159 , 0 x00);0 x00;244 , 0 x00);21 , 0 x01);1 );21 , 0 x00);0 x04);0 x00);0 x00);1 );0 x13b8, mac13b8);1 );4 );241 );242 );0 x13b8);0 x04);if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))"RF TX busy in LOFT IQ calibration\n" );0 x08);if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))"RF RX busy in LOFT IQ calibration\n" );if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {0 x00000101);0 x0000F1F1);23 , 0 x00);24 , 0 x00);if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {4 , bbpr4 & (~0 x18));21 , 0 x01);1 );21 , 0 x00);241 , 0 x14);242 , 0 x80);244 , 0 x31);else {0 x00000004);0 x00003306);1 );0 x0000000F);if (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {0 x00000000);0 x0000F1F1);0 x13b8, 0 x00000010);for (ch_idx = 0 ; ch_idx < 2 ; ch_idx++)3 , 0 x3B);4 , 0 x3B);158 , 0 x03);159 , 0 x60);158 , 0 xB0);159 , 0 x80);for (ch_idx = 0 ; ch_idx < 2 ; ch_idx++) {23 , 0 x00);24 , 0 x00);if (ch_idx == 0 ) {158 , 0 x01);159 , 0 x00);if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {0 x18);0 x00;1 , bbp);0 x00001004);else {158 , 0 x01);159 , 0 x01);if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {0 x18);0 x08;1 , bbp);0 x00002004);158 , 0 x05);159 , 0 x04);0 ) ? 0 x28 : 0 x46;158 , bbp);159 , 0 x00);if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {23 , 0 x06);24 , 0 x06);1 ;else {23 , 0 x1F);24 , 0 x1F);2 ;for (; vga_gain[ch_idx] < 19 ; vga_gain[ch_idx] = (vga_gain[ch_idx] + count_step)) {3 , rfvalue);4 , rfvalue);0 ) ? 0 x29 : 0 x47;158 , bbp);159 , 0 x00);0 x14, 0 );if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))0 x0A);0 ) ? 0 x29 : 0 x47;158 , bbp);159 , 0 x21);0 x14, 0 );if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags))0 x0A);"IQ AGC %d %d\n" , p0, p1);if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {"IQ AGC IDX 10 %d %d\n" , p0_idx10, p1_idx10);if ((p0_idx10 > 7000 * 7000 ) || (p1_idx10 > 7000 * 7000 )) {if (vga_gain[ch_idx] != 0 )1 ;break ;if ((p0 > 2500 * 2500 ) || (p1 > 2500 * 2500 ))break ;if (vga_gain[ch_idx] > 18 )18 ;"Used VGA %d %x\n" , vga_gain[ch_idx],0 ) ? 0 x29 : 0 x47;158 , bbp);159 , 0 x00);23 , 0 x00);24 , 0 x00);0 x04);158 , 0 x28);0 x0F;159 , bbp);158 , 0 x29);0 x3F;159 , bbp);158 , 0 x46);0 x0F;159 , bbp);158 , 0 x47);0 x3F;159 , bbp);if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {1 , bbpr1);241 , bbpr241);242 , bbpr242);244 , 0 x00);158 , 0 x00);159 , 0 x00);158 , 0 xB0);159 , 0 x00);30 , bbpr30);0 , 39 , rfb0r39);0 , 42 , rfb0r42);if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))4 , bbpr4);21 , 0 x01);1 );21 , 0 x00);0 x00);0 x00);1 );0 x13b8, mac13b8);static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,bool set_bw, bool is_ht40)21 );0 x1;21 , bbp_val);100 , 200 );if (set_bw) {4 );2 * is_ht40);4 , bbp_val);100 , 200 );21 );0 x1);21 , bbp_val);100 , 200 );static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)if (btxcal)0 x04);else 0 x02);0 x06);5 , 17 );0 x80;5 , 17 , rf_val);if (btxcal) {5 , 18 , 0 xC1);5 , 19 , 0 x20);5 , 20 , 0 x02);5 , 3 );0 x3F);0 x3F;5 , 3 , rf_val);5 , 4 );0 x3F);0 x3F;5 , 4 , rf_val);5 , 5 , 0 x31);else {5 , 18 , 0 xF1);5 , 19 , 0 x18);5 , 20 , 0 x02);5 , 3 );0 x3F);0 x34;5 , 3 , rf_val);5 , 4 );0 x3F);0 x34;5 , 4 , rf_val);return 0 ;static s8 rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)unsigned int cnt;0 , 0 x82);0 ;do {500 , 2000 );159 );if (bbp_val == 0 x02 || cnt == 20 )break ;while (cnt < 20 );0 x39);0 x7F;if (cal_val >= 0 x40)128 ;return cal_val;static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,bool btxcal)struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;0 , rx_agc_fc = 0 , cmm_agc_fc;0 x09, tx_filter_target_40m = 0 x02;0 x27, rx_filter_target_40m = 0 x31;int loop = 0 , is_ht40, cnt;/* Save MAC registers */ /* save BBP registers */ 23 );0 );2 );/* Save RF registers */ 5 , 0 );5 , 1 );5 , 3 );5 , 4 );5 , 5 );5 , 6 );5 , 7 );5 , 8 );5 , 17 );5 , 18 );5 , 19 );5 , 20 );5 , 37 );5 , 38 );5 , 39 );5 , 40 );5 , 41 );5 , 42 );5 , 43 );5 , 44 );5 , 45 );5 , 46 );5 , 58 );5 , 59 );5 , 0 );0 x3;5 , 0 , rf_val);5 , 1 );0 x1;5 , 1 , rf_val);0 ;do {500 , 2000 );5 , 1 );if (((rf_val & 0 x1) == 0 x00) || (cnt == 40 ))break ;while (cnt < 40 );5 , 0 );0 x3);0 x1;5 , 0 , rf_val);/* I-3 */ 23 );0 x1F);0 x10;23 , bbp_val);do {/* I-4,5,6,7,8,9 */ if (loop == 0 ) {false ;if (btxcal)else else {true ;if (btxcal)else 5 , 8 );0 x04);if (loop == 1 )0 x4;5 , 8 , rf_val);true , is_ht40);if (btxcal) {0 ;5 , 58 );0 x7F);5 , 58 , rf_val);5 , 59 );0 x7F);5 , 59 , rf_val);else {0 ;5 , 6 );0 x7F);5 , 6 , rf_val);5 , 7 );0 x7F);5 , 7 , rf_val);1000 , 2000 );2 );0 x6);2 , bbp_val);false , is_ht40);2 );0 x6;2 , bbp_val);if (btxcal) {5 , 58 );0 x7F);5 , 58 , rf_val);5 , 59 );0 x7F);5 , 59 , rf_val);else {5 , 6 );0 x7F);5 , 6 , rf_val);5 , 7 );0 x7F);5 , 7 , rf_val);500 , 1000 );false , is_ht40);if (btxcal)else if (((cal_diff > filter_target) && (cmm_agc_fc == 0 )) ||0 x3f))) {if (btxcal)0 ;else 0 ;else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0 x3f)) {if (btxcal)else goto do_cal;if (btxcal) {if (loop == 0 )else else {if (loop == 0 )else while (loop <= 1 );5 , 0 , saverfb5r00);5 , 1 , saverfb5r01);5 , 3 , saverfb5r03);5 , 4 , saverfb5r04);5 , 5 , saverfb5r05);5 , 6 , saverfb5r06);5 , 7 , saverfb5r07);5 , 8 , saverfb5r08);5 , 17 , saverfb5r17);5 , 18 , saverfb5r18);5 , 19 , saverfb5r19);5 , 20 , saverfb5r20);5 , 37 , saverfb5r37);5 , 38 , saverfb5r38);5 , 39 , saverfb5r39);5 , 40 , saverfb5r40);5 , 41 , saverfb5r41);5 , 42 , saverfb5r42);5 , 43 , saverfb5r43);5 , 44 , saverfb5r44);5 , 45 , saverfb5r45);5 , 46 , saverfb5r46);5 , 58 , saverfb5r58);5 , 59 , saverfb5r59);23 , savebbpr23);0 , savebbp159r0);2 , savebbp159r2);4 );2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));4 , bbp_val);static void rt2800_restore_rf_bbp_rt6352(struct rt2x00_dev *rt2x00dev)if (rt2x00_has_cap_external_pa(rt2x00dev)) {0 x0);0 x0);if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {14 , 0 x16);17 , 0 x23);18 , 0 x02);if (rt2x00_has_cap_external_pa(rt2x00dev)) {43 , 0 xd3);44 , 0 xb3);45 , 0 xd5);46 , 0 x27);47 , 0 x6c);48 , 0 xfc);49 , 0 x1f);54 , 0 x27);55 , 0 x66);56 , 0 xff);57 , 0 x1c);58 , 0 x20);59 , 0 x6b);60 , 0 xf7);61 , 0 x09);if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {75 , 0 x60);76 , 0 x44);79 , 0 x1c);80 , 0 x0c);82 , 0 xB6);if (rt2x00_has_cap_external_pa(rt2x00dev)) {0 x3630363a);0 x6c6c666c);0 x6c6c666c);static void rt2800_calibration_rt6352(struct rt2x00_dev *rt2x00dev)if (rt2x00_has_cap_external_pa(rt2x00dev) ||true );false );/* missing DPD calibration for internal PA devices */ if (!rt2x00_has_cap_external_pa(rt2x00dev) &&return ;if (rt2x00_has_cap_external_pa(rt2x00dev)) {0 x00000101;0 x00000101;if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {14 , 0 x66);17 , 0 x20);18 , 0 x42);if (rt2x00_has_cap_external_pa(rt2x00dev)) {43 , 0 x73);44 , 0 x73);45 , 0 x73);46 , 0 x27);47 , 0 xc8);48 , 0 xa4);49 , 0 x05);54 , 0 x27);55 , 0 xc8);56 , 0 xa4);57 , 0 x05);58 , 0 x27);59 , 0 xc8);60 , 0 xa4);61 , 0 x05);if (rt2x00_has_cap_external_pa(rt2x00dev))05 , 0 x00);if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {75 , 0 x68);76 , 0 x4c);79 , 0 x1c);80 , 0 x0c);82 , 0 xb6);if (rt2x00_has_cap_external_pa(rt2x00dev)) {0 x36303636);0 x6c6c6b6c);0 x6c6c6b6c);static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)/* Initialize RF central register to default value */ 0 , 0 x02);1 , 0 x03);2 , 0 x33);3 , 0 xFF);4 , 0 x0C);5 , 0 x40);6 , 0 x00);7 , 0 x00);8 , 0 x00);9 , 0 x00);10 , 0 x00);11 , 0 x00);12 , rt2x00dev->freq_offset);13 , 0 x00);14 , 0 x40);15 , 0 x22);16 , 0 x4C);17 , 0 x00);18 , 0 x00);19 , 0 x00);20 , 0 xA0);21 , 0 x12);22 , 0 x07);23 , 0 x13);24 , 0 xFE);25 , 0 x24);26 , 0 x7A);27 , 0 x00);28 , 0 x00);29 , 0 x05);30 , 0 x00);31 , 0 x00);32 , 0 x00);33 , 0 x00);34 , 0 x00);35 , 0 x00);36 , 0 x00);37 , 0 x00);38 , 0 x00);39 , 0 x00);40 , 0 x00);41 , 0 xD0);42 , 0 x5B);43 , 0 x00);11 , 0 x21);if (rt2800_clk_is_20mhz(rt2x00dev))13 , 0 x03);else 13 , 0 x00);14 , 0 x7C);16 , 0 x80);17 , 0 x99);18 , 0 x99);19 , 0 x09);20 , 0 x50);21 , 0 xB0);22 , 0 x00);23 , 0 x06);24 , 0 x00);25 , 0 x00);26 , 0 x5D);27 , 0 x00);28 , 0 x61);29 , 0 xB5);43 , 0 x02);28 , 0 x62);29 , 0 xAD);39 , 0 x80);/* Initialize RF channel register to default value */ 0 , 0 x03);1 , 0 x00);2 , 0 x00);3 , 0 x00);4 , 0 x00);5 , 0 x08);6 , 0 x00);7 , 0 x51);8 , 0 x53);9 , 0 x16);10 , 0 x61);11 , 0 x53);12 , 0 x22);13 , 0 x3D);14 , 0 x06);15 , 0 x13);16 , 0 x22);17 , 0 x27);18 , 0 x02);19 , 0 xA7);20 , 0 x01);21 , 0 x52);22 , 0 x80);23 , 0 xB3);24 , 0 x00);25 , 0 x00);26 , 0 x00);27 , 0 x00);28 , 0 x5C);29 , 0 x6B);30 , 0 x6B);31 , 0 x31);32 , 0 x5D);33 , 0 x00);34 , 0 xE6);35 , 0 x55);36 , 0 x00);37 , 0 xBB);38 , 0 xB3);39 , 0 xB3);40 , 0 x03);41 , 0 x00);42 , 0 x00);43 , 0 xB3);44 , 0 xD3);45 , 0 xD5);46 , 0 x07);47 , 0 x68);48 , 0 xEF);49 , 0 x1C);54 , 0 x07);55 , 0 xA8);56 , 0 x85);57 , 0 x10);58 , 0 x07);59 , 0 x6A);60 , 0 x85);61 , 0 x10);62 , 0 x1C);63 , 0 x00);6 , 45 , 0 xC5);9 , 0 x47);10 , 0 x71);11 , 0 x33);14 , 0 x0E);17 , 0 x23);19 , 0 xA4);20 , 0 x02);21 , 0 x12);28 , 0 x1C);29 , 0 xEB);32 , 0 x7D);34 , 0 xD6);36 , 0 x08);38 , 0 xB4);43 , 0 xD3);44 , 0 xB3);45 , 0 xD5);46 , 0 x27);4 , 47 , 0 x67);6 , 47 , 0 x69);48 , 0 xFF);4 , 54 , 0 x27);6 , 54 , 0 x20);55 , 0 x66);56 , 0 xFF);57 , 0 x1C);58 , 0 x20);59 , 0 x6B);60 , 0 xF7);61 , 0 x09);10 , 0 x51);14 , 0 x06);19 , 0 xA7);28 , 0 x2C);55 , 0 x64);8 , 0 x51);9 , 0 x36);11 , 0 x53);14 , 0 x16);47 , 0 x6C);48 , 0 xFC);49 , 0 x1F);54 , 0 x27);55 , 0 x66);59 , 0 x6B);/* Initialize RF channel register for DRQFN */ 43 , 0 xD3);44 , 0 xE3);45 , 0 xE5);47 , 0 x28);55 , 0 x68);56 , 0 xF7);58 , 0 x02);60 , 0 xC7);/* Initialize RF DC calibration register to default value */ 0 , 0 x47);1 , 0 x00);2 , 0 x00);3 , 0 x00);4 , 0 x00);5 , 0 x00);6 , 0 x10);7 , 0 x10);8 , 0 x04);9 , 0 x00);10 , 0 x07);11 , 0 x01);12 , 0 x07);13 , 0 x07);14 , 0 x07);15 , 0 x20);16 , 0 x22);17 , 0 x00);18 , 0 x00);19 , 0 x00);20 , 0 x00);21 , 0 xF1);22 , 0 x11);23 , 0 x02);24 , 0 x41);25 , 0 x20);26 , 0 x00);27 , 0 xD7);28 , 0 xA2);29 , 0 x20);30 , 0 x49);31 , 0 x20);32 , 0 x04);33 , 0 xF1);34 , 0 xA1);35 , 0 x01);41 , 0 x00);42 , 0 x00);43 , 0 x00);44 , 0 x00);45 , 0 x00);46 , 0 x00);47 , 0 x3E);48 , 0 x3D);49 , 0 x3E);50 , 0 x3D);51 , 0 x3E);52 , 0 x3D);53 , 0 x00);54 , 0 x00);55 , 0 x00);56 , 0 x00);57 , 0 x00);58 , 0 x10);59 , 0 x10);60 , 0 x0A);61 , 0 x00);62 , 0 x00);63 , 0 x00);3 , 0 x08);4 , 0 x04);5 , 0 x20);5 , 0 x00);17 , 0 x7C);/* Do calibration and init PA/LNA */ static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)if (rt2800_is_305x_soc(rt2x00dev)) {return ;switch (rt2x00dev->chip.rt) {case RT3070:case RT3071:case RT3090:break ;case RT3290:break ;case RT3352:break ;case RT3390:break ;case RT3883:break ;case RT3572:break ;case RT3593:break ;case RT5350:break ;case RT5390:break ;case RT5392:break ;case RT5592:break ;case RT6352:break ;int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)/* * Initialize MAC registers . if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||return -EIO;/* * Wait BBP / RF to wake up . if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))return -EIO;/* * Send signal during boot time to initialize firmware . 0 );0 );if (rt2x00_is_usb(rt2x00dev))0 );0 , 0 , 0 );1 );/* * Make sure BBP is up and running . if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))return -EIO;/* * Initialize BBP / RF registers . if (rt2x00_is_usb(rt2x00dev) &&200 );0 , 0 , 0 );10 );/* * Enable RX . 1 );0 );50 );1 );1 );1 );1 );1 );/* * Initialize LED control 0 xff,0 xff, (word >> 8 ) & 0 xff);0 xff,0 xff, (word >> 8 ) & 0 xff);0 xff,0 xff, (word >> 8 ) & 0 xff);return 0 ;void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)/* Wait for DMA, ignore error */ 0 );0 );int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)if (rt2x00_rt(rt2x00dev, RT3290))else return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)if (rt2x00_rt(rt2x00dev, RT3290)) {else {0 );1 );/* Wait until the EEPROM has been loaded */ /* Apparently the data is read from end to start */ /* The returned value is in CPU order, but eeprom is le */ 2 ] = cpu_to_le32(reg);4 ] = cpu_to_le32(reg);6 ] = cpu_to_le32(reg);int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)unsigned int i;for (i = 0 ; i < EEPROM_SIZE / sizeof (u16); i += 8 )return 0 ;static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)if (rt2x00_rt(rt2x00dev, RT3593) ||return 0 ;if ((word & 0 x00ff) != 0 x00ff)return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);return 0 ;static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)if (rt2x00_rt(rt2x00dev, RT3593) ||return 0 ;if ((word & 0 x00ff) != 0 x00ff)return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);return 0 ;static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;int retval;/* * Read the EEPROM . if (retval)return retval;/* * Start validation of the data that has been read . if (word == 0 xffff) {2 );1 );"Antenna: 0x%04x\n" , word);else if (rt2x00_rt(rt2x00dev, RT2860) ||/* * There is a max of 2 RX streams for RT28x0 series if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2 )2 );if (word == 0 xffff) {0 );0 );0 );0 );0 );0 );0 );0 );0 );0 );0 );0 );0 );0 );0 );"NIC: 0x%04x\n" , word);if ((word & 0 x00ff) == 0 x00ff) {0 );"Freq: 0x%04x\n" , word);if ((word & 0 xff00) == 0 xff00) {0 );0 x5555);0 x2221);0 xa9f8);"Led Mode: 0x%04x\n" , word);/* * During the LNA validation we are going to use * lna0 as correct value . Note that EEPROM_LNA * is never validated . if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10 )0 );if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10 )0 );if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10 )0 );if (!rt2x00_rt(rt2x00dev, RT3593) &&if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0 x00 ||0 xff)if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10 )0 );if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10 )0 );if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10 )0 );if (!rt2x00_rt(rt2x00dev, RT3593) &&if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0 x00 ||0 xff)if (rt2x00_rt(rt2x00dev, RT3593) ||if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0 x00 ||0 xff)if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0 x00 ||0 xff)return 0 ;static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)/* * Read EEPROM word for configuration . /* * Identify RF chipset by EEPROM value * RT28xx / RT30xx : defined in " EEPROM_NIC_CONF0_RF_TYPE " field * RT53xx : defined in " EEPROM_CHIP_ID " field if (rt2x00_rt(rt2x00dev, RT3290) ||else if (rt2x00_rt(rt2x00dev, RT3352))else if (rt2x00_rt(rt2x00dev, RT3883))else if (rt2x00_rt(rt2x00dev, RT5350))else if (rt2x00_rt(rt2x00dev, RT5592))else switch (rf) {case RF2820:case RF2850:case RF2720:case RF2750:case RF3020:case RF2020:case RF3021:case RF3022:case RF3052:case RF3053:case RF3070:case RF3290:case RF3320:"nvrm/.h" case RF3853:case RF5360:case RF5362:case RF5370:case RF5372:case RF5390:case RF5392:case RF5592:case RF7620:break ;default :"Invalid RF chipset 0x%04x detected\n" ,return -ENODEV;/* * Identify default antenna configuration . if (rt2x00_rt(rt2x00dev, RT3070) ||switch (value) {case 0 :case 1 :case 2 :break ;case 3 :break ;else {/* These chips have hardware RX antenna diversity */ if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||/* Unused */ /* Unused */ /* * Determine external LNA informations . if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))/* * Detect if this device has an hardware controlled radio . if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))/* * Detect if this device has Bluetooth co - existence . if (!rt2x00_rt(rt2x00dev, RT3352) &&/* * Read frequency offset and RF programming sequence . /* * Store led settings , for correct led behaviour . #ifdef CONFIG_RT2X00_LIB_LEDS#endif /* CONFIG_RT2X00_LIB_LEDS */ /* * Check if support EIRP tx power limit feature . if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) </* * Detect if device uses internal or external PA if (rt2x00_rt(rt2x00dev, RT3352) ||if (rt2x00_get_field16(eeprom,if (rt2x00_get_field16(eeprom,if (rt2x00_rt(rt2x00dev, RT6352) && eeprom != 0 && eeprom != 0 xffff) {if (!rt2x00_get_field16(eeprom,return 0 ;/* * RF value list for rt28xx * Supports : 2 . 4 GHz ( all ) & 5 . 2 GHz ( RF2850 & RF2750 ) static const struct rf_channel rf_vals[] = {1 , 0 x18402ecc, 0 x184c0786, 0 x1816b455, 0 x1800510b },2 , 0 x18402ecc, 0 x184c0786, 0 x18168a55, 0 x1800519f },3 , 0 x18402ecc, 0 x184c078a, 0 x18168a55, 0 x1800518b },4 , 0 x18402ecc, 0 x184c078a, 0 x18168a55, 0 x1800519f },5 , 0 x18402ecc, 0 x184c078e, 0 x18168a55, 0 x1800518b },6 , 0 x18402ecc, 0 x184c078e, 0 x18168a55, 0 x1800519f },7 , 0 x18402ecc, 0 x184c0792, 0 x18168a55, 0 x1800518b },8 , 0 x18402ecc, 0 x184c0792, 0 x18168a55, 0 x1800519f },9 , 0 x18402ecc, 0 x184c0796, 0 x18168a55, 0 x1800518b },10 , 0 x18402ecc, 0 x184c0796, 0 x18168a55, 0 x1800519f },11 , 0 x18402ecc, 0 x184c079a, 0 x18168a55, 0 x1800518b },12 , 0 x18402ecc, 0 x184c079a, 0 x18168a55, 0 x1800519f },13 , 0 x18402ecc, 0 x184c079e, 0 x18168a55, 0 x1800518b },14 , 0 x18402ecc, 0 x184c07a2, 0 x18168a55, 0 x18005193 },/* 802.11 UNI / HyperLan 2 */ 36 , 0 x18402ecc, 0 x184c099a, 0 x18158a55, 0 x180ed1a3 },38 , 0 x18402ecc, 0 x184c099e, 0 x18158a55, 0 x180ed193 },40 , 0 x18402ec8, 0 x184c0682, 0 x18158a55, 0 x180ed183 },44 , 0 x18402ec8, 0 x184c0682, 0 x18158a55, 0 x180ed1a3 },46 , 0 x18402ec8, 0 x184c0686, 0 x18158a55, 0 x180ed18b },48 , 0 x18402ec8, 0 x184c0686, 0 x18158a55, 0 x180ed19b },52 , 0 x18402ec8, 0 x184c068a, 0 x18158a55, 0 x180ed193 },54 , 0 x18402ec8, 0 x184c068a, 0 x18158a55, 0 x180ed1a3 },56 , 0 x18402ec8, 0 x184c068e, 0 x18158a55, 0 x180ed18b },60 , 0 x18402ec8, 0 x184c0692, 0 x18158a55, 0 x180ed183 },62 , 0 x18402ec8, 0 x184c0692, 0 x18158a55, 0 x180ed193 },64 , 0 x18402ec8, 0 x184c0692, 0 x18158a55, 0 x180ed1a3 },/* 802.11 HyperLan 2 */ 100 , 0 x18402ec8, 0 x184c06b2, 0 x18178a55, 0 x180ed783 },102 , 0 x18402ec8, 0 x184c06b2, 0 x18578a55, 0 x180ed793 },104 , 0 x18402ec8, 0 x185c06b2, 0 x18578a55, 0 x180ed1a3 },108 , 0 x18402ecc, 0 x185c0a32, 0 x18578a55, 0 x180ed193 },110 , 0 x18402ecc, 0 x184c0a36, 0 x18178a55, 0 x180ed183 },112 , 0 x18402ecc, 0 x184c0a36, 0 x18178a55, 0 x180ed19b },116 , 0 x18402ecc, 0 x184c0a3a, 0 x18178a55, 0 x180ed1a3 },118 , 0 x18402ecc, 0 x184c0a3e, 0 x18178a55, 0 x180ed193 },120 , 0 x18402ec4, 0 x184c0382, 0 x18178a55, 0 x180ed183 },124 , 0 x18402ec4, 0 x184c0382, 0 x18178a55, 0 x180ed193 },126 , 0 x18402ec4, 0 x184c0382, 0 x18178a55, 0 x180ed15b },128 , 0 x18402ec4, 0 x184c0382, 0 x18178a55, 0 x180ed1a3 },132 , 0 x18402ec4, 0 x184c0386, 0 x18178a55, 0 x180ed18b },134 , 0 x18402ec4, 0 x184c0386, 0 x18178a55, 0 x180ed193 },136 , 0 x18402ec4, 0 x184c0386, 0 x18178a55, 0 x180ed19b },140 , 0 x18402ec4, 0 x184c038a, 0 x18178a55, 0 x180ed183 },/* 802.11 UNII */ 149 , 0 x18402ec4, 0 x184c038a, 0 x18178a55, 0 x180ed1a7 },151 , 0 x18402ec4, 0 x184c038e, 0 x18178a55, 0 x180ed187 },153 , 0 x18402ec4, 0 x184c038e, 0 x18178a55, 0 x180ed18f },157 , 0 x18402ec4, 0 x184c038e, 0 x18178a55, 0 x180ed19f },159 , 0 x18402ec4, 0 x184c038e, 0 x18178a55, 0 x180ed1a7 },161 , 0 x18402ec4, 0 x184c0392, 0 x18178a55, 0 x180ed187 },165 , 0 x18402ec4, 0 x184c0392, 0 x18178a55, 0 x180ed197 },167 , 0 x18402ec4, 0 x184c03d2, 0 x18179855, 0 x1815531f },169 , 0 x18402ec4, 0 x184c03d2, 0 x18179855, 0 x18155327 },171 , 0 x18402ec4, 0 x184c03d6, 0 x18179855, 0 x18155307 },173 , 0 x18402ec4, 0 x184c03d6, 0 x18179855, 0 x1815530f },/* 802.11 Japan */ 184 , 0 x15002ccc, 0 x1500491e, 0 x1509be55, 0 x150c0a0b },188 , 0 x15002ccc, 0 x15004922, 0 x1509be55, 0 x150c0a13 },192 , 0 x15002ccc, 0 x15004926, 0 x1509be55, 0 x150c0a1b },196 , 0 x15002ccc, 0 x1500492a, 0 x1509be55, 0 x150c0a23 },208 , 0 x15002ccc, 0 x1500493a, 0 x1509be55, 0 x150c0a13 },212 , 0 x15002ccc, 0 x1500493e, 0 x1509be55, 0 x150c0a1b },216 , 0 x15002ccc, 0 x15004982, 0 x1509be55, 0 x150c0a23 },/* * RF value list for rt3xxx * Supports : 2 . 4 GHz ( all ) & 5 . 2 GHz ( RF3052 & RF3053 ) static const struct rf_channel rf_vals_3x[] = {1 , 241 , 2 , 2 },2 , 241 , 2 , 7 },3 , 242 , 2 , 2 },4 , 242 , 2 , 7 },5 , 243 , 2 , 2 },6 , 243 , 2 , 7 },7 , 244 , 2 , 2 },8 , 244 , 2 , 7 },9 , 245 , 2 , 2 },10 , 245 , 2 , 7 },11 , 246 , 2 , 2 },12 , 246 , 2 , 7 },13 , 247 , 2 , 2 },14 , 248 , 2 , 4 },/* 802.11 UNI / HyperLan 2 */ 36 , 0 x56, 0 , 4 },38 , 0 x56, 0 , 6 },40 , 0 x56, 0 , 8 },44 , 0 x57, 0 , 0 },46 , 0 x57, 0 , 2 },48 , 0 x57, 0 , 4 },52 , 0 x57, 0 , 8 },54 , 0 x57, 0 , 10 },56 , 0 x58, 0 , 0 },60 , 0 x58, 0 , 4 },62 , 0 x58, 0 , 6 },64 , 0 x58, 0 , 8 },/* 802.11 HyperLan 2 */ 100 , 0 x5b, 0 , 8 },102 , 0 x5b, 0 , 10 },104 , 0 x5c, 0 , 0 },108 , 0 x5c, 0 , 4 },110 , 0 x5c, 0 , 6 },112 , 0 x5c, 0 , 8 },116 , 0 x5d, 0 , 0 },118 , 0 x5d, 0 , 2 },120 , 0 x5d, 0 , 4 },124 , 0 x5d, 0 , 8 },126 , 0 x5d, 0 , 10 },128 , 0 x5e, 0 , 0 },132 , 0 x5e, 0 , 4 },134 , 0 x5e, 0 , 6 },136 , 0 x5e, 0 , 8 },140 , 0 x5f, 0 , 0 },/* 802.11 UNII */ 149 , 0 x5f, 0 , 9 },151 , 0 x5f, 0 , 11 },153 , 0 x60, 0 , 1 },157 , 0 x60, 0 , 5 },159 , 0 x60, 0 , 7 },161 , 0 x60, 0 , 9 },165 , 0 x61, 0 , 1 },167 , 0 x61, 0 , 3 },169 , 0 x61, 0 , 5 },171 , 0 x61, 0 , 7 },173 , 0 x61, 0 , 9 },/* * RF value list for rt3xxx with Xtal20MHz * Supports : 2 . 4 GHz ( all ) ( RF3322 ) static const struct rf_channel rf_vals_3x_xtal20[] = {1 , 0 xE2, 2 , 0 x14},2 , 0 xE3, 2 , 0 x14},3 , 0 xE4, 2 , 0 x14},4 , 0 xE5, 2 , 0 x14},5 , 0 xE6, 2 , 0 x14},6 , 0 xE7, 2 , 0 x14},7 , 0 xE8, 2 , 0 x14},8 , 0 xE9, 2 , 0 x14},9 , 0 xEA, 2 , 0 x14},10 , 0 xEB, 2 , 0 x14},11 , 0 xEC, 2 , 0 x14},12 , 0 xED, 2 , 0 x14},13 , 0 xEE, 2 , 0 x14},14 , 0 xF0, 2 , 0 x18},static const struct rf_channel rf_vals_3853[] = {1 , 241 , 6 , 2 },2 , 241 , 6 , 7 },3 , 242 , 6 , 2 },4 , 242 , 6 , 7 },5 , 243 , 6 , 2 },6 , 243 , 6 , 7 },7 , 244 , 6 , 2 },8 , 244 , 6 , 7 },9 , 245 , 6 , 2 },10 , 245 , 6 , 7 },11 , 246 , 6 , 2 },12 , 246 , 6 , 7 },13 , 247 , 6 , 2 },14 , 248 , 6 , 4 },36 , 0 x56, 8 , 4 },38 , 0 x56, 8 , 6 },40 , 0 x56, 8 , 8 },44 , 0 x57, 8 , 0 },46 , 0 x57, 8 , 2 },48 , 0 x57, 8 , 4 },52 , 0 x57, 8 , 8 },54 , 0 x57, 8 , 10 },56 , 0 x58, 8 , 0 },60 , 0 x58, 8 , 4 },62 , 0 x58, 8 , 6 },64 , 0 x58, 8 , 8 },100 , 0 x5b, 8 , 8 },102 , 0 x5b, 8 , 10 },104 , 0 x5c, 8 , 0 },108 , 0 x5c, 8 , 4 },110 , 0 x5c, 8 , 6 },112 , 0 x5c, 8 , 8 },114 , 0 x5c, 8 , 10 },116 , 0 x5d, 8 , 0 },118 , 0 x5d, 8 , 2 },120 , 0 x5d, 8 , 4 },124 , 0 x5d, 8 , 8 },126 , 0 x5d, 8 , 10 },128 , 0 x5e, 8 , 0 },132 , 0 x5e, 8 , 4 },134 , 0 x5e, 8 , 6 },136 , 0 x5e, 8 , 8 },140 , 0 x5f, 8 , 0 },149 , 0 x5f, 8 , 9 },151 , 0 x5f, 8 , 11 },153 , 0 x60, 8 , 1 },157 , 0 x60, 8 , 5 },159 , 0 x60, 8 , 7 },161 , 0 x60, 8 , 9 },165 , 0 x61, 8 , 1 },167 , 0 x61, 8 , 3 },169 , 0 x61, 8 , 5 },171 , 0 x61, 8 , 7 },173 , 0 x61, 8 , 9 },static const struct rf_channel rf_vals_5592_xtal20[] = {/* Channel, N, K, mod, R */ 1 , 482 , 4 , 10 , 3 },2 , 483 , 4 , 10 , 3 },3 , 484 , 4 , 10 , 3 },4 , 485 , 4 , 10 , 3 },5 , 486 , 4 , 10 , 3 },6 , 487 , 4 , 10 , 3 },7 , 488 , 4 , 10 , 3 },8 , 489 , 4 , 10 , 3 },9 , 490 , 4 , 10 , 3 },10 , 491 , 4 , 10 , 3 },11 , 492 , 4 , 10 , 3 },12 , 493 , 4 , 10 , 3 },13 , 494 , 4 , 10 , 3 },14 , 496 , 8 , 10 , 3 },36 , 172 , 8 , 12 , 1 },38 , 173 , 0 , 12 , 1 },40 , 173 , 4 , 12 , 1 },42 , 173 , 8 , 12 , 1 },44 , 174 , 0 , 12 , 1 },46 , 174 , 4 , 12 , 1 },48 , 174 , 8 , 12 , 1 },50 , 175 , 0 , 12 , 1 },52 , 175 , 4 , 12 , 1 },54 , 175 , 8 , 12 , 1 },56 , 176 , 0 , 12 , 1 },58 , 176 , 4 , 12 , 1 },60 , 176 , 8 , 12 , 1 },62 , 177 , 0 , 12 , 1 },64 , 177 , 4 , 12 , 1 },100 , 183 , 4 , 12 , 1 },102 , 183 , 8 , 12 , 1 },104 , 184 , 0 , 12 , 1 },106 , 184 , 4 , 12 , 1 },108 , 184 , 8 , 12 , 1 },110 , 185 , 0 , 12 , 1 },112 , 185 , 4 , 12 , 1 },114 , 185 , 8 , 12 , 1 },116 , 186 , 0 , 12 , 1 },118 , 186 , 4 , 12 , 1 },120 , 186 , 8 , 12 , 1 },122 , 187 , 0 , 12 , 1 },124 , 187 , 4 , 12 , 1 },126 , 187 , 8 , 12 , 1 },128 , 188 , 0 , 12 , 1 },130 , 188 , 4 , 12 , 1 },132 , 188 , 8 , 12 , 1 },134 , 189 , 0 , 12 , 1 },136 , 189 , 4 , 12 , 1 },138 , 189 , 8 , 12 , 1 },140 , 190 , 0 , 12 , 1 },149 , 191 , 6 , 12 , 1 },151 , 191 , 10 , 12 , 1 },153 , 192 , 2 , 12 , 1 },155 , 192 , 6 , 12 , 1 },157 , 192 , 10 , 12 , 1 },159 , 193 , 2 , 12 , 1 },161 , 193 , 6 , 12 , 1 },165 , 194 , 2 , 12 , 1 },184 , 164 , 0 , 12 , 1 },188 , 164 , 4 , 12 , 1 },192 , 165 , 8 , 12 , 1 },196 , 166 , 0 , 12 , 1 },static const struct rf_channel rf_vals_5592_xtal40[] = {/* Channel, N, K, mod, R */ 1 , 241 , 2 , 10 , 3 },2 , 241 , 7 , 10 , 3 },3 , 242 , 2 , 10 , 3 },4 , 242 , 7 , 10 , 3 },5 , 243 , 2 , 10 , 3 },6 , 243 , 7 , 10 , 3 },7 , 244 , 2 , 10 , 3 },8 , 244 , 7 , 10 , 3 },9 , 245 , 2 , 10 , 3 },10 , 245 , 7 , 10 , 3 },11 , 246 , 2 , 10 , 3 },12 , 246 , 7 , 10 , 3 },13 , 247 , 2 , 10 , 3 },14 , 248 , 4 , 10 , 3 },36 , 86 , 4 , 12 , 1 },38 , 86 , 6 , 12 , 1 },40 , 86 , 8 , 12 , 1 },42 , 86 , 10 , 12 , 1 },44 , 87 , 0 , 12 , 1 },46 , 87 , 2 , 12 , 1 },48 , 87 , 4 , 12 , 1 },50 , 87 , 6 , 12 , 1 },52 , 87 , 8 , 12 , 1 },54 , 87 , 10 , 12 , 1 },56 , 88 , 0 , 12 , 1 },58 , 88 , 2 , 12 , 1 },60 , 88 , 4 , 12 , 1 },62 , 88 , 6 , 12 , 1 },64 , 88 , 8 , 12 , 1 },100 , 91 , 8 , 12 , 1 },102 , 91 , 10 , 12 , 1 },104 , 92 , 0 , 12 , 1 },106 , 92 , 2 , 12 , 1 },108 , 92 , 4 , 12 , 1 },110 , 92 , 6 , 12 , 1 },112 , 92 , 8 , 12 , 1 },114 , 92 , 10 , 12 , 1 },116 , 93 , 0 , 12 , 1 },118 , 93 , 2 , 12 , 1 },120 , 93 , 4 , 12 , 1 },122 , 93 , 6 , 12 , 1 },124 , 93 , 8 , 12 , 1 },126 , 93 , 10 , 12 , 1 },128 , 94 , 0 , 12 , 1 },130 , 94 , 2 , 12 , 1 },132 , 94 , 4 , 12 , 1 },134 , 94 , 6 , 12 , 1 },136 , 94 , 8 , 12 , 1 },138 , 94 , 10 , 12 , 1 },140 , 95 , 0 , 12 , 1 },149 , 95 , 9 , 12 , 1 },151 , 95 , 11 , 12 , 1 },153 , 96 , 1 , 12 , 1 },155 , 96 , 3 , 12 , 1 },157 , 96 , 5 , 12 , 1 },159 , 96 , 7 , 12 , 1 },161 , 96 , 9 , 12 , 1 },165 , 97 , 1 , 12 , 1 },184 , 82 , 0 , 12 , 1 },188 , 82 , 4 , 12 , 1 },192 , 82 , 8 , 12 , 1 },196 , 83 , 0 , 12 , 1 },static const struct rf_channel rf_vals_7620[] = {1 , 0 x50, 0 x99, 0 x99, 1 },2 , 0 x50, 0 x44, 0 x44, 2 },3 , 0 x50, 0 xEE, 0 xEE, 2 },4 , 0 x50, 0 x99, 0 x99, 3 },5 , 0 x51, 0 x44, 0 x44, 0 },6 , 0 x51, 0 xEE, 0 xEE, 0 },7 , 0 x51, 0 x99, 0 x99, 1 },8 , 0 x51, 0 x44, 0 x44, 2 },9 , 0 x51, 0 xEE, 0 xEE, 2 },10 , 0 x51, 0 x99, 0 x99, 3 },11 , 0 x52, 0 x44, 0 x44, 0 },12 , 0 x52, 0 xEE, 0 xEE, 0 },13 , 0 x52, 0 x99, 0 x99, 1 },14 , 0 x52, 0 x33, 0 x33, 3 },static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)struct hw_mode_spec *spec = &rt2x00dev->spec;struct channel_info *info;unsigned int i, tx_chains, rx_chains;/* * Disable powersaving as default . /* * Change default retry settings to values corresponding more closely * to rate [ 0 ] . count setting of minstrel rate control algorithm . 2 ;2 ;/* * Initialize all hw fields . /* * Don ' t set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices * unless we are capable of sending the buffered frames out after the * DTIM transmission using rt2x00lib_beacondone . This will send out * multicast and broadcast traffic immediately instead of buffering it * infinitly and thus dropping it after some time . if (!rt2x00_is_usb(rt2x00dev))/* * As rt2800 has a global fallback table we cannot specify * more then one tx rate per frame but since the hw will * try several rates ( based on the fallback table ) we should * initialize max_report_rates to the maximum number of rates * we are going to try . Otherwise mac80211 will truncate our * reported tx rates and the rc algortihm will end up with * incorrect data . 1 ;7 ;1 ;/* * Initialize hw_mode information . switch (rt2x00dev->chip.rf) {case RF2720:case RF2820:14 ;break ;case RF2750:case RF2850:break ;case RF2020:case RF3020:case RF3021:case RF3022:case RF3070:case RF3290:case RF3320:case RF3322:case RF5350:case RF5360:case RF5362:case RF5370:case RF5372:case RF5390:case RF5392:14 ;if (rt2800_clk_is_20mhz(rt2x00dev))else break ;case RF7620:break ;case RF3052:case RF3053:break ;case RF3853:break ;case RF5592:if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {else {break ;if (WARN_ON_ONCE(!spec->channels))return -ENODEV;if (spec->num_channels > 14 )/* * Initialize HT information . if (!rt2x00_rf(rt2x00dev, RF2020))true ;else false ;if (tx_chains >= 2 )1 ) ? 3 : 2 ;4 ;if (tx_chains != rx_chains) {1 ) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;switch (rx_chains) {case 3 :2 ] = 0 xff;case 2 :1 ] = 0 xff;case 1 :0 ] = 0 xff;4 ] = 0 x1; /* MCS32 */ break ;/* * Create channel information and survey arrays sizeof (*info), GFP_KERNEL);if (!info)return -ENOMEM;sizeof (struct rt2x00_chan_survey),if (!rt2x00dev->chan_survey) {return -ENOMEM;if (rt2x00dev->default_ant.tx_chain_num > 2 )else for (i = 0 ; i < 14 ; i++) {if (default_power3)if (spec->num_channels > 14 ) {if (rt2x00dev->default_ant.tx_chain_num > 2 )else for (i = 14 ; i < spec->num_channels; i++) {14 ];14 ];if (default_power3)14 ];switch (rt2x00dev->chip.rf) {case RF2020:case RF3020:case RF3021:case RF3022:case RF3320:case RF3052:case RF3053:case RF3070:case RF3290:case RF3853:case RF5350:case RF5360:case RF5362:case RF5370:case RF5372:case RF5390:case RF5392:case RF5592:case RF7620:break ;return 0 ;static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)if (rt2x00_rt(rt2x00dev, RT3290))else switch (rt) {case RT2860:case RT2872:case RT2883:case RT3070:case RT3071:case RT3090:case RT3290:case RT3352:case RT3390:case RT3572:case RT3593:case RT3883:case RT5350:case RT5390:case RT5392:case RT5592:break ;default :"Invalid RT chipset 0x%04x, rev %04x detected\n" ,return -ENODEV;if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))return 0 ;int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)int retval;if (retval)return retval;/* * Allocate eeprom data . if (retval)return retval;if (retval)return retval;/* * Enable rfkill polling by setting GPIO direction of the * rfkill switch GPIO pin correctly . 1 );/* * Initialize hw specifications . if (retval)return retval;/* * Set device capabilities . if (!rt2x00_is_usb(rt2x00dev))/* * Set device requirements . * / if ( ! rt2x00_is_soc ( rt2x00dev ) ) _ _ set_bit ( REQUIRE_FIRMWARE , & rt2x00dev - > cap_flags ) ; _ _ set_bit ( REQUIRE_L2PAD , & rt2x00dev - > cap_flags ) ; _ _ set_bit ( REQUIRE_TXSTATUS_FIFO , & rt2x00dev - > cap_flags ) ; if ( ! rt2800_hwcrypt_disabled ( rt2x00dev ) ) _ _ set_bit ( CAPABILITY_HW_CRYPTO , & rt2x00dev - > cap_flags ) ; _ _ set_bit ( CAPABILITY_LINK_TUNING , & rt2x00dev - > cap_flags ) ; _ _ set_bit ( REQUIRE_HT_TX_DESC , & rt2x00dev - > cap_flags ) ; if ( rt2x00_is_usb ( rt2x00dev ) ) _ _ set_bit ( REQUIRE_PS_AUTOWAKE , & rt2x00dev - > cap_flags ) ; else { _ _ set_bit ( REQUIRE_DMA , & rt2x00dev - > cap_flags ) ; _ _ set_bit ( REQUIRE_TASKLET_CONTEXT , & rt2x00dev - > cap_flags ) ; } rt2x00dev - > link . watchdog = modparam_watchdog ; if (rt2x00_is_usb(rt2x00dev))if (rt2x00dev->link.watchdog) {100 );/* * Set the rssi offset . return 0 ;/* * IEEE80211 stack callback functions . void rt2800_get_key_seq(struct ieee80211_hw *hw,struct ieee80211_key_conf *key,struct ieee80211_key_seq *seq)struct rt2x00_dev *rt2x00dev = hw->priv;struct mac_iveiv_entry iveiv_entry;if (key->cipher != WLAN_CIPHER_SUITE_TKIP)return ;sizeof (iveiv_entry));0 ], 2 );4 ], 4 );int rt2800_set_rts_threshold(struct ieee80211_hw *hw, int radio_idx, u32 value)struct rt2x00_dev *rt2x00dev = hw->priv;bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);return 0 ;int rt2800_conf_tx(struct ieee80211_hw *hw,struct ieee80211_vif *vif,unsigned int link_id, u16 queue_idx,const struct ieee80211_tx_queue_params *params)struct rt2x00_dev *rt2x00dev = hw->priv;struct data_queue *queue;struct rt2x00_field32 field;int retval;/* * First pass the configuration through rt2x00lib , that will * update the queue settings and validate the input . After that * we are free to update the registers based on the value * in the queue parameter . if (retval)return retval;/* * We only need to perform additional register initialization * for WMM queues / if (queue_idx >= 4 )return 0 ;/* Update WMM TXOP register */ sizeof (u32) * (!!(queue_idx & 2 )));1 ) * 16 ;0 xffff << field.bit_offset;/* Update WMM registers */ 4 ;0 xf << field.bit_offset;/* Update EDCA registers */ sizeof (u32) * queue_idx);return 0 ;struct ieee80211_hw *hw, struct ieee80211_vif *vif)struct rt2x00_dev *rt2x00dev = hw->priv;32 ;return tsf;int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,struct ieee80211_ampdu_params *params)struct ieee80211_sta *sta = params->sta;enum ieee80211_ampdu_mlme_action action = params->action;struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;int ret = 0 ;/* * Don ' t allow aggregation for stations the hardware isn ' t aware * of because tx status reports for frames to an unknown station * always contain wcid = WCID_END + 1 and thus we can ' t distinguish * between multiple stations which leads to unwanted situations * when the hw reorders frames due to aggregation . if (sta_priv->wcid > WCID_END)return -ENOSPC;switch (action) {case IEEE80211_AMPDU_RX_START:case IEEE80211_AMPDU_RX_STOP:/* * The hw itself takes care of setting up BlockAck mechanisms . * So , we only have to allow mac80211 to nagotiate a BlockAck * agreement . Once that is done , the hw will BlockAck incoming * AMPDUs without further setup . break ;case IEEE80211_AMPDU_TX_START:break ;case IEEE80211_AMPDU_TX_STOP_CONT:case IEEE80211_AMPDU_TX_STOP_FLUSH:case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:break ;case IEEE80211_AMPDU_TX_OPERATIONAL:break ;default :struct rt2x00_dev *)hw->priv,"Unknown AMPDU action\n" );return ret;int rt2800_get_survey(struct ieee80211_hw *hw, int idx,struct survey_info *survey)struct rt2x00_dev *rt2x00dev = hw->priv;struct rt2x00_chan_survey *chan_survey =enum nl80211_band band = NL80211_BAND_2GHZ;if (idx >= rt2x00dev->bands[band].n_channels) {if (idx >= rt2x00dev->bands[band].n_channels)return -ENOENT;if (idx == 0 )1000 );1000 );1000 );if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))return 0 ;", Bartlomiej Zolnierkiewicz" );"Ralink RT2800 library" );"GPL" );
Messung V0.5 in Prozent C=89 H=94 G=91
¤ Diese beiden folgenden Angebotsgruppen bietet das Unternehmen0.698Angebot
(Wie Sie bei der Firma Beratungs- und Dienstleistungen beauftragen können 2026-10-11)
¤ *Eine klare Vorstellung vom Zielzustand
