// SPDX-License-Identifier: GPL-2.0-or-later /* Copyright ( C ) 2004 - 2009 Ivo van Doorn < IvDoorn @ gmail . com > < http : //rt2x00.serialmonkey.com> /* Module : rt61pci Abstract : rt61pci device specific routines . Supported chipsets : RT2561 , RT2561s , RT2661 . #include <linux/crc-itu-t.h>#include <linux/delay.h>#include <linux/etherdevice.h>#include <linux/kernel.h>#include <linux/module.h>#include <linux/slab.h>#include <linux/pci.h>#include <linux/eeprom_93cx6.h>#include "rt2x00.h" #include "rt2x00mmio.h" #include "rt2x00pci.h" #include "rt61pci.h" /* * Allow hardware encryption to be disabled . static bool modparam_nohwcrypt = false ;bool , 0444 );"Disable hardware encryption." );/* * Register access . * BBP and RF register require indirect register access , * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this . * These indirect registers work with busy bits , * and we will try maximal REGISTER_BUSY_COUNT times to access * the register while taking a REGISTER_BUSY_DELAY us delay * between each attempt . When the busy bit is still set at that time , * the access attempt is considered to have failed , * and we will print an error . #define WAIT_FOR_BBP(__dev, __reg) \#define WAIT_FOR_RF(__dev, __reg) \#define WAIT_FOR_MCU(__dev, __reg) \static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,const unsigned int word, const u8 value)/* * Wait until the BBP becomes available , afterwards we * can safely write the new data into the register . if (WAIT_FOR_BBP(rt2x00dev, ®)) {0 ;1 );0 );static u8 rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,const unsigned int word)/* * Wait until the BBP becomes available , afterwards we * can safely write the read request into the register . * After the data has been written , we wait until hardware * returns the correct value , if at any time the register * doesn ' t become available in time , reg will be 0 xffffffff * which means we return 0 xff to the caller . if (WAIT_FOR_BBP(rt2x00dev, ®)) {0 ;1 );1 );return value;static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,const unsigned int word, const u32 value)/* * Wait until the RF becomes available , afterwards we * can safely write the new data into the register . if (WAIT_FOR_RF(rt2x00dev, ®)) {0 ;21 );0 );1 );static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,const u8 command, const u8 token,const u8 arg0, const u8 arg1)/* * Wait until the MCU becomes available , afterwards we * can safely write the new data into the register . if (WAIT_FOR_MCU(rt2x00dev, ®)) {1 );1 );static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)struct rt2x00_dev *rt2x00dev = eeprom->data;static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)struct rt2x00_dev *rt2x00dev = eeprom->data;0 ;#ifdef CONFIG_RT2X00_LIB_DEBUGFSstatic const struct rt2x00debug rt61pci_rt2x00debug = {sizeof (u32),sizeof (u32),sizeof (u16),sizeof (u16),sizeof (u8),sizeof (u8),sizeof (u32),sizeof (u32),#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)return rt2x00_get_field32(reg, MAC_CSR13_VAL5);#ifdef CONFIG_RT2X00_LIB_LEDSstatic void rt61pci_brightness_set(struct led_classdev *led_cdev,enum led_brightness brightness)struct rt2x00_led *led =struct rt2x00_led, led_dev);unsigned int enabled = brightness != LED_OFF;unsigned int a_mode =unsigned int bg_mode =if (led->type == LED_TYPE_RADIO) {0 xff,0 xff),8 )));else if (led->type == LED_TYPE_ASSOC) {0 xff,0 xff),8 )));else if (led->type == LED_TYPE_QUALITY) {/* * The brightness is divided into 6 levels ( 0 - 5 ) , * this means we need to convert the brightness * argument into the matching level within that range . 0 xff,6 ), 0 );static int rt61pci_blink_set(struct led_classdev *led_cdev,unsigned long *delay_on,unsigned long *delay_off)struct rt2x00_led *led =struct rt2x00_led, led_dev);return 0 ;static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,struct rt2x00_led *led,enum led_type type)#endif /* CONFIG_RT2X00_LIB_LEDS */ /* * Configuration handlers . static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,struct rt2x00lib_crypto *crypto,struct ieee80211_key_conf *key)/* * Let the software handle the shared keys , * since the hardware decryption does not work reliably , * because the firmware does not know the key ' s keyidx . return -EOPNOTSUPP;static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,struct rt2x00lib_crypto *crypto,struct ieee80211_key_conf *key)struct hw_pairwise_ta_entry addr_entry;struct hw_key_entry key_entry;if (crypto->cmd == SET_KEY) {/* * rt2x00lib can ' t determine the correct free * key_idx for pairwise keys . We have 2 registers * with key valid bits . The goal is simple : read * the first register . If that is full , move to * the next register . * When both registers are full , we drop the key . * Otherwise , we use the first invalid entry . if (reg && reg == ~0 ) {32 ;if (reg && reg == ~0 )return -ENOSPC;0 ;/* * Upload key to hardware sizeof (key_entry.key));sizeof (key_entry.tx_mic));sizeof (key_entry.rx_mic));0 , sizeof (addr_entry));sizeof (key_entry));sizeof (addr_entry));/* * Enable pairwise lookup table for given BSS idx . * Without this , received frames will not be decrypted * by the hardware . 1 << crypto->bssidx);/* * The driver does not support the IV / EIV generation * in hardware . However it doesn ' t support the IV / EIV * inside the ieee80211 frame either , but requires it * to be provided separately for the descriptor . * rt2x00lib will cut the IV / EIV data out of all frames * given to us by mac80211 , but we must tell mac80211 * to generate the IV / EIV data . /* * SEC_CSR2 and SEC_CSR3 contain only single - bit fields to indicate * a particular key is valid . Because using the FIELD32 ( ) * defines directly will cause a lot of overhead , we use * a calculation to determine the correct bit directly . if (key->hw_key_idx < 32 ) {1 << key->hw_key_idx;if (crypto->cmd == SET_KEY)else if (crypto->cmd == DISABLE_KEY)else {1 << (key->hw_key_idx - 32 );if (crypto->cmd == SET_KEY)else if (crypto->cmd == DISABLE_KEY)return 0 ;static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,const unsigned int filter_flags)/* * Start configuration steps . * Note that the version error will always be dropped * and broadcast frames will always be accepted since * there is no filter for it at this time . 1 );0 );static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,struct rt2x00_intf *intf,struct rt2x00intf_conf *conf,const unsigned int flags)if (flags & CONFIG_UPDATE_TYPE) {/* * Enable synchronisation . if (flags & CONFIG_UPDATE_MAC) {1 ]);0 xff);1 ] = cpu_to_le32(reg);sizeof (conf->mac));if (flags & CONFIG_UPDATE_BSSID) {1 ]);3 );1 ] = cpu_to_le32(reg);sizeof (conf->bssid));static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,struct rt2x00lib_erp *erp,0 x32);if (changed & BSS_CHANGED_ERP_PREAMBLE) {1 );if (changed & BSS_CHANGED_BASIC_RATES)if (changed & BSS_CHANGED_BEACON_INT) {16 );if (changed & BSS_CHANGED_ERP_SLOT) {3 );static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,struct antenna_setup *ant)3 );4 );77 );/* * Configure the RX antenna . switch (ant->rx) {case ANTENNA_HW_DIVERSITY:2 );break ;case ANTENNA_A:1 );0 );if (rt2x00dev->curr_band == NL80211_BAND_5GHZ)0 );else 3 );break ;case ANTENNA_B:default :1 );0 );if (rt2x00dev->curr_band == NL80211_BAND_5GHZ)3 );else 0 );break ;77 , r77);3 , r3);4 , r4);static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,struct antenna_setup *ant)3 );4 );77 );/* * Configure the RX antenna . switch (ant->rx) {case ANTENNA_HW_DIVERSITY:2 );break ;case ANTENNA_A:1 );3 );break ;case ANTENNA_B:default :1 );0 );break ;77 , r77);3 , r3);4 , r4);static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,const int p1, const int p2)0 );0 );static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,struct antenna_setup *ant)3 );4 );77 );/* * Configure the RX antenna . switch (ant->rx) {case ANTENNA_A:1 );0 );0 , 0 );break ;case ANTENNA_HW_DIVERSITY:/* * FIXME : Antenna selection for the rf 2529 is very confusing * in the legacy driver . Just default to antenna B until the * legacy code can be properly translated into rt2x00 code . case ANTENNA_B:default :1 );3 );1 , 1 );break ;77 , r77);3 , r3);4 , r4);struct antenna_sel {/* * value [ 0 ] - > non - LNA * value [ 1 ] - > LNA 2 ];static const struct antenna_sel antenna_sel_a[] = {96 , { 0 x58, 0 x78 } },104 , { 0 x38, 0 x48 } },75 , { 0 xfe, 0 x80 } },86 , { 0 xfe, 0 x80 } },88 , { 0 xfe, 0 x80 } },35 , { 0 x60, 0 x60 } },97 , { 0 x58, 0 x58 } },98 , { 0 x58, 0 x58 } },static const struct antenna_sel antenna_sel_bg[] = {96 , { 0 x48, 0 x68 } },104 , { 0 x2c, 0 x3c } },75 , { 0 xfe, 0 x80 } },86 , { 0 xfe, 0 x80 } },88 , { 0 xfe, 0 x80 } },35 , { 0 x50, 0 x50 } },97 , { 0 x48, 0 x48 } },98 , { 0 x48, 0 x48 } },static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,struct antenna_setup *ant)const struct antenna_sel *sel;unsigned int lna;unsigned int i;/* * We should never come here because rt2x00lib is supposed * to catch this and send us the correct antenna explicitely . if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {else {for (i = 0 ; i < ARRAY_SIZE(antenna_sel_a); i++)if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))else if (rt2x00_rf(rt2x00dev, RF2527))else if (rt2x00_rf(rt2x00dev, RF2529)) {if (rt2x00_has_cap_double_antenna(rt2x00dev))else static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,struct rt2x00lib_conf *libconf)short lna_gain = 0 ;if (libconf->conf->chandef.chan->band == NL80211_BAND_2GHZ) {if (rt2x00_has_cap_external_lna_bg(rt2x00dev))14 ;else {if (rt2x00_has_cap_external_lna_a(rt2x00dev))14 ;static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,struct rf_channel *rf, const int txpower)3 );3 , r3);6 ;if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))94 , r94);1 , rf->rf1);2 , rf->rf2);3 , rf->rf3 & ~0 x00000004);4 , rf->rf4);200 );1 , rf->rf1);2 , rf->rf2);3 , rf->rf3 | 0 x00000004);4 , rf->rf4);200 );1 , rf->rf1);2 , rf->rf2);3 , rf->rf3 & ~0 x00000004);4 , rf->rf4);1 );static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,const int txpower)struct rf_channel rf;1 );2 );3 );4 );static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,struct rt2x00lib_conf *libconf)1 );0 );0 );static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,struct rt2x00lib_conf *libconf)enum dev_state state =if (state == STATE_SLEEP) {10 );1 );5 );/* We must first disable autowake before it can be enabled */ 0 );1 );0 x00000005);0 x0000001c);0 x00000060);0 xff, 0 , 0 );else {0 );0 );0 );0 );0 x00000007);0 x00000018);0 x00000020);0 xff, 0 , 0 );static void rt61pci_config(struct rt2x00_dev *rt2x00dev,struct rt2x00lib_conf *libconf,const unsigned int flags)/* Always recalculate LNA gain before changing configuration */ if (flags & IEEE80211_CONF_CHANGE_CHANNEL)if ((flags & IEEE80211_CONF_CHANGE_POWER) &&if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)if (flags & IEEE80211_CONF_CHANGE_PS)/* * Link tuning static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,struct link_qual *qual)/* * Update FCS error count from register . /* * Update False CCA count from register . static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,struct link_qual *qual, u8 vgc_level)if (qual->vgc_level != vgc_level) {17 , vgc_level);static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,struct link_qual *qual)0 x20);static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,struct link_qual *qual, const u32 count)/* * Determine r17 bounds . if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {0 x28;0 x48;if (rt2x00_has_cap_external_lna_a(rt2x00dev)) {0 x10;0 x10;else {0 x20;0 x40;if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {0 x10;0 x10;/* * If we are not associated , we should go straight to the * dynamic CCA tuning . if (!rt2x00dev->intf_associated)goto dynamic_cca_tune;/* * Special big - R17 for very short distance if (qual->rssi >= -35 ) {0 x60);return ;/* * Special big - R17 for short distance if (qual->rssi >= -58 ) {return ;/* * Special big - R17 for middle - short distance if (qual->rssi >= -66 ) {0 x10);return ;/* * Special mid - R17 for middle distance if (qual->rssi >= -74 ) {0 x08);return ;/* * Special case : Change up_bound based on the rssi . * Lower up_bound when rssi is weaker then - 74 dBm . 2 * (-74 - qual->rssi);if (low_bound > up_bound)if (qual->vgc_level > up_bound) {return ;/* * r17 does not yet exceed upper limit , continue and base * the r17 tuning on the false CCA count . if ((qual->false_cca > 512 ) && (qual->vgc_level < up_bound))else if ((qual->false_cca < 100 ) && (qual->vgc_level > low_bound))/* * Queue handlers . static void rt61pci_start_queue(struct data_queue *queue)struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;switch (queue->qid) {case QID_RX:0 );break ;case QID_BEACON:1 );1 );1 );break ;default :break ;static void rt61pci_kick_queue(struct data_queue *queue)struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;switch (queue->qid) {case QID_AC_VO:1 );break ;case QID_AC_VI:1 );break ;case QID_AC_BE:1 );break ;case QID_AC_BK:1 );break ;default :break ;static void rt61pci_stop_queue(struct data_queue *queue)struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;switch (queue->qid) {case QID_AC_VO:1 );break ;case QID_AC_VI:1 );break ;case QID_AC_BE:1 );break ;case QID_AC_BK:1 );break ;case QID_RX:1 );break ;case QID_BEACON:0 );0 );0 );/* * Wait for possibly running tbtt tasklets . break ;default :break ;/* * Firmware functions static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)char *fw_name;switch (chip) {case RT2561_PCI_ID:break ;case RT2561s_PCI_ID:break ;case RT2661_PCI_ID:break ;default :break ;return fw_name;static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,const u8 *data, const size_t len)/* * Only support 8 kb firmware files . if (len != 8192 )return FW_BAD_LENGTH;/* * The last 2 bytes in the firmware array are the crc checksum itself . * This means that we should never pass those 2 bytes to the crc * algorithm . 2 ] << 8 | data[len - 1 ]);/* * Use the crc itu - t algorithm . 0 , data, len - 2 );0 );0 );return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,const u8 *data, const size_t len)int i;/* * Wait for stable hardware . for (i = 0 ; i < 100 ; i++) {if (reg)break ;1 );if (!reg) {"Unstable hardware\n" );return -EBUSY;/* * Prepare MCU and mailbox for firmware loading . 0 ;1 );0 xffffffff);0 );0 );/* * Write firmware to device . 0 ;1 );1 );0 );0 );for (i = 0 ; i < 100 ; i++) {if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))break ;1 );if (i == 100 ) {"MCU Control register not ready\n" );return -EBUSY;/* * Hardware needs another millisecond before it is ready . 1 );/* * Reset MAC and BBP registers . 0 ;1 );1 );0 );0 );1 );return 0 ;/* * Initialization functions . static bool rt61pci_get_entry_state(struct queue_entry *entry)struct queue_entry_priv_mmio *entry_priv = entry->priv_data;if (entry->queue->qid == QID_RX) {0 );return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);else {0 );return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||static void rt61pci_clear_entry(struct queue_entry *entry)struct queue_entry_priv_mmio *entry_priv = entry->priv_data;struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);if (entry->queue->qid == QID_RX) {5 );5 , word);0 );1 );0 , word);else {0 );0 );0 );0 , word);static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)struct queue_entry_priv_mmio *entry_priv;/* * Initialize registers . 0 ].limit);1 ].limit);2 ].limit);3 ].limit);0 ].desc_size / 4 );0 ].entries[0 ].priv_data;1 ].entries[0 ].priv_data;2 ].entries[0 ].priv_data;3 ].entries[0 ].priv_data;4 );4 );0 ].priv_data;2 );2 );2 );2 );1 );1 );1 );1 );1 );return 0 ;static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)1 );0 );0 );47 ); /* CCK Signal */ 1 );30 ); /* Rssi */ 1 );42 ); /* OFDM Rate */ 1 );30 ); /* Rssi */ 1 );/* * CCK TXD BBP registers 13 );1 );12 );1 );11 );1 );10 );1 );/* * OFDM TXD BBP registers 7 );1 );6 );1 );5 );1 );59 );53 );49 );46 );44 );42 );42 );42 );0 );0 );0 );0 );0 );0 );0 x0000000f);0 x00000fff);0 );0 x0000071c);if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))return -EBUSY;0 x0000e000);/* * Invalidate all Shared Keys ( SEC_CSR0 ) , * and clear the Shared key Cipher algorithms ( SEC_CSR1 & SEC_CSR5 ) 0 x00000000);0 x00000000);0 x00000000);0 x000023b0);0 x060a100c);0 x00080606);0 x00000a08);0 x28ca4404);0 x00000200);0 xffffffff);/* * Clear all beacons * For the Beacon base registers we only need to clear * the first byte since that byte contains the VALID and OWNER * bits which ( when set to 0 ) will invalidate the entire beacon . 0 );0 );0 );0 );/* * We must clear the error counters . * These registers are cleared on read , * so we may pass a useless variable to store the value . /* * Reset MAC and BBP registers . 1 );1 );0 );0 );1 );return 0 ;static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)unsigned int i;for (i = 0 ; i < REGISTER_BUSY_COUNT; i++) {0 );if ((value != 0 xff) && (value != 0 x00))return 0 ;"BBP register access failed, aborting\n" );return -EACCES;static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)unsigned int i;if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))return -EACCES;3 , 0 x00);15 , 0 x30);21 , 0 xc8);22 , 0 x38);23 , 0 x06);24 , 0 xfe);25 , 0 x0a);26 , 0 x0d);34 , 0 x12);37 , 0 x07);39 , 0 xf8);41 , 0 x60);53 , 0 x10);54 , 0 x18);60 , 0 x10);61 , 0 x04);62 , 0 x04);75 , 0 xfe);86 , 0 xfe);88 , 0 xfe);90 , 0 x0f);99 , 0 x00);102 , 0 x16);107 , 0 x04);for (i = 0 ; i < EEPROM_BBP_SIZE; i++) {if (eeprom != 0 xffff && eeprom != 0 x0000) {return 0 ;/* * Device state switch handlers . static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,enum dev_state state)int mask = (state == STATE_RADIO_IRQ_OFF);unsigned long flags;/* * When interrupts are being enabled , the interrupt registers * should clear the register to assure a clean state . if (state == STATE_RADIO_IRQ_ON) {/* * Only toggle the interrupts bits we are going to use . * Non - checked interrupt bits are disabled by default . 0 xff);if (state == STATE_RADIO_IRQ_OFF) {/* * Ensure that all tasklets are finished . static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)/* * Initialize all registers . if (unlikely(rt61pci_init_queues(rt2x00dev) ||return -EIO;/* * Enable RX . 1 );return 0 ;static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)/* * Disable power 0 x00001818);static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)unsigned int i;bool put_to_sleep;/* * Device is not guaranteed to be in the requested state yet . * We must wait until the register indicates that the * device has entered the correct state . for (i = 0 ; i < REGISTER_BUSY_COUNT; i++) {if (state == !put_to_sleep)return 0 ;10 );return -EBUSY;static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,enum dev_state state)int retval = 0 ;switch (state) {case STATE_RADIO_ON:break ;case STATE_RADIO_OFF:break ;case STATE_RADIO_IRQ_ON:case STATE_RADIO_IRQ_OFF:break ;case STATE_DEEP_SLEEP:case STATE_SLEEP:case STATE_STANDBY:case STATE_AWAKE:break ;default :break ;if (unlikely(retval))"Device failed to enter state %d (%d)\n" ,return retval;/* * TX descriptor initialization static void rt61pci_write_tx_desc(struct queue_entry *entry,struct txentry_desc *txdesc)struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);struct queue_entry_priv_mmio *entry_priv = entry->priv_data;/* * Start writing the descriptor words . 1 );1 );1 , word);2 );2 , word);if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {3 , skbdesc->iv[0 ]);4 , skbdesc->iv[1 ]);5 );1 );5 , word);if (entry->queue->qid != QID_BEACON) {6 );6 , word);11 );11 , word);/* * Writing TXD word 0 must the last to prevent a race condition with * the device , whereby the device may take hold of the TXD before we * finished updating it . 0 );1 );1 );0 , word);/* * Register descriptor details in skb frame descriptor . /* * TX data initialization static void rt61pci_write_beacon(struct queue_entry *entry,struct txentry_desc *txdesc)struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;struct queue_entry_priv_mmio *entry_priv = entry->priv_data;unsigned int beacon_base;unsigned int padding_len;/* * Disable beaconing while we are reloading the beacon data , * otherwise we might be sending out invalid data . 0 );/* * Write the TX descriptor for the beacon . /* * Dump beacon to userspace through debugfs . /* * Write entire beacon with descriptor and padding to register . 4 ) - entry->skb->len;if (padding_len && skb_pad(entry->skb, padding_len)) {"Failure padding beacon, aborting\n" );/* skb freed by skb_pad() on failure */ return ;/* * Enable beaconing again . * * For Wi - Fi faily generated beacons between participating * stations . Set TBTT phase adaptive adjustment step to 8 us . 0 x00001008);1 );/* * Clean up beacon skb . static void rt61pci_clear_beacon(struct queue_entry *entry)struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;/* * Disable beaconing while we are reloading the beacon data , * otherwise we might be sending out invalid data . 0 );/* * Clear beacon . 0 );/* * Restore global beaconing state . /* * RX control handlers static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)switch (lna) {case 3 :90 ;break ;case 2 :74 ;break ;case 1 :64 ;break ;default :return 0 ;if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {if (lna == 3 || lna == 2 )10 ;return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;static void rt61pci_fill_rxdone(struct queue_entry *entry,struct rxdone_entry_desc *rxdesc)struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;struct queue_entry_priv_mmio *entry_priv = entry->priv_data;0 );1 );if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))if (rxdesc->cipher != CIPHER_NONE) {0 ] = _rt2x00_desc_read(entry_priv->desc, 2 );1 ] = _rt2x00_desc_read(entry_priv->desc, 3 );4 );/* * Hardware has stripped IV / EIV data from 802 . 11 frame during * decryption . It has provided the data separately but rt2x00lib * should decide if it should be reinserted . /* * The hardware has already checked the Michael Mic and has * stripped it from the frame . Signal this to mac80211 . if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)/* * Obtain the status about this packet . * When frame was received with an OFDM bitrate , * the signal is the PLCP value . If it was received with * a CCK bitrate the signal is the rate in 100 kbit / s . if (rt2x00_get_field32(word0, RXD_W0_OFDM))else if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))/* * Interrupt functions . static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)struct data_queue *queue;struct queue_entry *entry;struct queue_entry *entry_done;struct queue_entry_priv_mmio *entry_priv;struct txdone_entry_desc txdesc;int type;int index;int i;/* * TX_STA_FIFO is a stack of X entries , hence read TX_STA_FIFO * at most X times and also stop processing once the TX_STA_FIFO_VALID * flag is not set anymore . * * The legacy drivers use X = TX_RING_SIZE but state in a comment * that the TX_STA_FIFO stack has a size of 16 . We stick to our * tx ring size for now . for (i = 0 ; i < rt2x00dev->tx->limit; i++) {if (!rt2x00_get_field32(reg, STA_CSR4_VALID))break ;/* * Skip this entry when it contains an invalid * queue identication number . if (unlikely(!queue))continue ;/* * Skip this entry when it contains an invalid * index number . if (unlikely(index >= queue->limit))continue ;0 );if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||return ;while (entry != entry_done) {/* Catch up. * Just report any entries we missed as failed . "TX status report missed for entry %d\n" ,/* * Obtain the status about this packet . 0 ;switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {case 0 : /* Success, maybe with retry */ break ;case 6 : /* Failure, excessive retries */ /* this is a failed frame! */ default : /* Failure */ /* * the frame was retried at least once * - > hw used fallback rates if (txdesc.retry)static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)struct rt2x00lib_conf libconf = { .conf = &rt2x00dev->hw->conf };static inline void rt61pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,struct rt2x00_field32 irq_field)/* * Enable a single interrupt . The interrupt mask register * access needs locking . 0 );static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev *rt2x00dev,struct rt2x00_field32 irq_field)/* * Enable a single MCU interrupt . The interrupt mask register * access needs locking . 0 );static void rt61pci_txstatus_tasklet(struct tasklet_struct *t)struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))static void rt61pci_tbtt_tasklet(struct tasklet_struct *t)struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t, tbtt_tasklet);if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))static void rt61pci_rxdone_tasklet(struct tasklet_struct *t)struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,if (rt2x00mmio_rxdone(rt2x00dev))else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))static void rt61pci_autowake_tasklet(struct tasklet_struct *t)struct rt2x00_dev *rt2x00dev = from_tasklet(rt2x00dev, t,0 xffffffff);if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)struct rt2x00_dev *rt2x00dev = dev_instance;/* * Get the interrupt sources & saved to local variable . * Write register value back to clear pending interrupts . if (!reg && !reg_mcu)return IRQ_NONE;if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))return IRQ_HANDLED;/* * Schedule tasklets for interrupt handling . if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))/* * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits * for interrupts and interrupt masks we can just use the value of * INT_SOURCE_CSR to create the interrupt mask . /* * Disable all interrupts for which a tasklet was scheduled right now , * the tasklet will reenable the appropriate interrupts . return IRQ_HANDLED;/* * Device probe functions . static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)struct eeprom_93cx6 eeprom;0 ;0 ;0 ;0 ;sizeof (u16));/* * Start validation of the data that has been read . if (word == 0 xffff) {2 );0 );0 );0 );"Antenna: 0x%04x\n" , word);if (word == 0 xffff) {0 );0 );0 );0 );0 );0 );0 );"NIC: 0x%04x\n" , word);if (word == 0 xffff) {"Led: 0x%04x\n" , word);if (word == 0 xffff) {0 );0 );"Freq: 0x%04x\n" , word);if (word == 0 xffff) {0 );0 );"RSSI OFFSET BG: 0x%04x\n" , word);else {if (value < -10 || value > 10 )0 );if (value < -10 || value > 10 )0 );if (word == 0 xffff) {0 );0 );"RSSI OFFSET A: 0x%04x\n" , word);else {if (value < -10 || value > 10 )0 );if (value < -10 || value > 10 )0 );return 0 ;static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)/* * Read EEPROM word for configuration . /* * Identify RF chipset . if (!rt2x00_rf(rt2x00dev, RF5225) &&"Invalid RF chipset detected\n" );return -ENODEV;/* * Determine number of antennas . if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2 )/* * Identify default antenna configuration . /* * Read the Frame type . if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))/* * Detect if this device has a hardware controlled radio . if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))/* * Read frequency offset and RF programming sequence . if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))/* * Read external LNA informations . if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))/* * When working with a RF2529 chip without double antenna , * the antenna settings should be gathered from the NIC * eeprom word . if (rt2x00_rf(rt2x00dev, RF2529) &&if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))/* * Store led settings , for correct led behaviour . * If the eeprom value is invalid , * switch to default led mode . #ifdef CONFIG_RT2X00_LIB_LEDSif (value == LED_MODE_SIGNAL_STRENGTH)#endif /* CONFIG_RT2X00_LIB_LEDS */ return 0 ;/* * RF value list for RF5225 & RF5325 * Supports : 2 . 4 GHz & 5 . 2 GHz , rf_sequence disabled static const struct rf_channel rf_vals_noseq[] = {1 , 0 x00002ccc, 0 x00004786, 0 x00068455, 0 x000ffa0b },2 , 0 x00002ccc, 0 x00004786, 0 x00068455, 0 x000ffa1f },3 , 0 x00002ccc, 0 x0000478a, 0 x00068455, 0 x000ffa0b },4 , 0 x00002ccc, 0 x0000478a, 0 x00068455, 0 x000ffa1f },5 , 0 x00002ccc, 0 x0000478e, 0 x00068455, 0 x000ffa0b },6 , 0 x00002ccc, 0 x0000478e, 0 x00068455, 0 x000ffa1f },7 , 0 x00002ccc, 0 x00004792, 0 x00068455, 0 x000ffa0b },8 , 0 x00002ccc, 0 x00004792, 0 x00068455, 0 x000ffa1f },9 , 0 x00002ccc, 0 x00004796, 0 x00068455, 0 x000ffa0b },10 , 0 x00002ccc, 0 x00004796, 0 x00068455, 0 x000ffa1f },11 , 0 x00002ccc, 0 x0000479a, 0 x00068455, 0 x000ffa0b },12 , 0 x00002ccc, 0 x0000479a, 0 x00068455, 0 x000ffa1f },13 , 0 x00002ccc, 0 x0000479e, 0 x00068455, 0 x000ffa0b },14 , 0 x00002ccc, 0 x000047a2, 0 x00068455, 0 x000ffa13 },/* 802.11 UNI / HyperLan 2 */ 36 , 0 x00002ccc, 0 x0000499a, 0 x0009be55, 0 x000ffa23 },40 , 0 x00002ccc, 0 x000049a2, 0 x0009be55, 0 x000ffa03 },44 , 0 x00002ccc, 0 x000049a6, 0 x0009be55, 0 x000ffa0b },48 , 0 x00002ccc, 0 x000049aa, 0 x0009be55, 0 x000ffa13 },52 , 0 x00002ccc, 0 x000049ae, 0 x0009ae55, 0 x000ffa1b },56 , 0 x00002ccc, 0 x000049b2, 0 x0009ae55, 0 x000ffa23 },60 , 0 x00002ccc, 0 x000049ba, 0 x0009ae55, 0 x000ffa03 },64 , 0 x00002ccc, 0 x000049be, 0 x0009ae55, 0 x000ffa0b },/* 802.11 HyperLan 2 */ 100 , 0 x00002ccc, 0 x00004a2a, 0 x000bae55, 0 x000ffa03 },104 , 0 x00002ccc, 0 x00004a2e, 0 x000bae55, 0 x000ffa0b },108 , 0 x00002ccc, 0 x00004a32, 0 x000bae55, 0 x000ffa13 },112 , 0 x00002ccc, 0 x00004a36, 0 x000bae55, 0 x000ffa1b },116 , 0 x00002ccc, 0 x00004a3a, 0 x000bbe55, 0 x000ffa23 },120 , 0 x00002ccc, 0 x00004a82, 0 x000bbe55, 0 x000ffa03 },124 , 0 x00002ccc, 0 x00004a86, 0 x000bbe55, 0 x000ffa0b },128 , 0 x00002ccc, 0 x00004a8a, 0 x000bbe55, 0 x000ffa13 },132 , 0 x00002ccc, 0 x00004a8e, 0 x000bbe55, 0 x000ffa1b },136 , 0 x00002ccc, 0 x00004a92, 0 x000bbe55, 0 x000ffa23 },/* 802.11 UNII */ 140 , 0 x00002ccc, 0 x00004a9a, 0 x000bbe55, 0 x000ffa03 },149 , 0 x00002ccc, 0 x00004aa2, 0 x000bbe55, 0 x000ffa1f },153 , 0 x00002ccc, 0 x00004aa6, 0 x000bbe55, 0 x000ffa27 },157 , 0 x00002ccc, 0 x00004aae, 0 x000bbe55, 0 x000ffa07 },161 , 0 x00002ccc, 0 x00004ab2, 0 x000bbe55, 0 x000ffa0f },165 , 0 x00002ccc, 0 x00004ab6, 0 x000bbe55, 0 x000ffa17 },/* MMAC(Japan)J52 ch 34,38,42,46 */ 34 , 0 x00002ccc, 0 x0000499a, 0 x0009be55, 0 x000ffa0b },38 , 0 x00002ccc, 0 x0000499e, 0 x0009be55, 0 x000ffa13 },42 , 0 x00002ccc, 0 x000049a2, 0 x0009be55, 0 x000ffa1b },46 , 0 x00002ccc, 0 x000049a6, 0 x0009be55, 0 x000ffa23 },/* * RF value list for RF5225 & RF5325 * Supports : 2 . 4 GHz & 5 . 2 GHz , rf_sequence enabled static const struct rf_channel rf_vals_seq[] = {1 , 0 x00002ccc, 0 x00004786, 0 x00068455, 0 x000ffa0b },2 , 0 x00002ccc, 0 x00004786, 0 x00068455, 0 x000ffa1f },3 , 0 x00002ccc, 0 x0000478a, 0 x00068455, 0 x000ffa0b },4 , 0 x00002ccc, 0 x0000478a, 0 x00068455, 0 x000ffa1f },5 , 0 x00002ccc, 0 x0000478e, 0 x00068455, 0 x000ffa0b },6 , 0 x00002ccc, 0 x0000478e, 0 x00068455, 0 x000ffa1f },7 , 0 x00002ccc, 0 x00004792, 0 x00068455, 0 x000ffa0b },8 , 0 x00002ccc, 0 x00004792, 0 x00068455, 0 x000ffa1f },9 , 0 x00002ccc, 0 x00004796, 0 x00068455, 0 x000ffa0b },10 , 0 x00002ccc, 0 x00004796, 0 x00068455, 0 x000ffa1f },11 , 0 x00002ccc, 0 x0000479a, 0 x00068455, 0 x000ffa0b },12 , 0 x00002ccc, 0 x0000479a, 0 x00068455, 0 x000ffa1f },13 , 0 x00002ccc, 0 x0000479e, 0 x00068455, 0 x000ffa0b },14 , 0 x00002ccc, 0 x000047a2, 0 x00068455, 0 x000ffa13 },/* 802.11 UNI / HyperLan 2 */ 36 , 0 x00002cd4, 0 x0004481a, 0 x00098455, 0 x000c0a03 },40 , 0 x00002cd0, 0 x00044682, 0 x00098455, 0 x000c0a03 },44 , 0 x00002cd0, 0 x00044686, 0 x00098455, 0 x000c0a1b },48 , 0 x00002cd0, 0 x0004468e, 0 x00098655, 0 x000c0a0b },52 , 0 x00002cd0, 0 x00044692, 0 x00098855, 0 x000c0a23 },56 , 0 x00002cd0, 0 x0004469a, 0 x00098c55, 0 x000c0a13 },60 , 0 x00002cd0, 0 x000446a2, 0 x00098e55, 0 x000c0a03 },64 , 0 x00002cd0, 0 x000446a6, 0 x00099255, 0 x000c0a1b },/* 802.11 HyperLan 2 */ 100 , 0 x00002cd4, 0 x0004489a, 0 x000b9855, 0 x000c0a03 },104 , 0 x00002cd4, 0 x000448a2, 0 x000b9855, 0 x000c0a03 },108 , 0 x00002cd4, 0 x000448aa, 0 x000b9855, 0 x000c0a03 },112 , 0 x00002cd4, 0 x000448b2, 0 x000b9a55, 0 x000c0a03 },116 , 0 x00002cd4, 0 x000448ba, 0 x000b9a55, 0 x000c0a03 },120 , 0 x00002cd0, 0 x00044702, 0 x000b9a55, 0 x000c0a03 },124 , 0 x00002cd0, 0 x00044706, 0 x000b9a55, 0 x000c0a1b },128 , 0 x00002cd0, 0 x0004470e, 0 x000b9c55, 0 x000c0a0b },132 , 0 x00002cd0, 0 x00044712, 0 x000b9c55, 0 x000c0a23 },136 , 0 x00002cd0, 0 x0004471a, 0 x000b9e55, 0 x000c0a13 },/* 802.11 UNII */ 140 , 0 x00002cd0, 0 x00044722, 0 x000b9e55, 0 x000c0a03 },149 , 0 x00002cd0, 0 x0004472e, 0 x000ba255, 0 x000c0a1b },153 , 0 x00002cd0, 0 x00044736, 0 x000ba255, 0 x000c0a0b },157 , 0 x00002cd4, 0 x0004490a, 0 x000ba255, 0 x000c0a17 },161 , 0 x00002cd4, 0 x00044912, 0 x000ba255, 0 x000c0a17 },165 , 0 x00002cd4, 0 x0004491a, 0 x000ba255, 0 x000c0a17 },/* MMAC(Japan)J52 ch 34,38,42,46 */ 34 , 0 x00002ccc, 0 x0000499a, 0 x0009be55, 0 x000c0a0b },38 , 0 x00002ccc, 0 x0000499e, 0 x0009be55, 0 x000c0a13 },42 , 0 x00002ccc, 0 x000049a2, 0 x0009be55, 0 x000c0a1b },46 , 0 x00002ccc, 0 x000049a6, 0 x0009be55, 0 x000c0a23 },static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)struct hw_mode_spec *spec = &rt2x00dev->spec;struct channel_info *info;unsigned int i;/* * Disable powersaving as default . /* * Initialize all hw fields . /* * As rt61 has a global fallback table we cannot specify * more then one tx rate per frame but since the hw will * try several rates ( based on the fallback table ) we should * initialize max_report_rates to the maximum number of rates * we are going to try . Otherwise mac80211 will truncate our * reported tx rates and the rc algortihm will end up with * incorrect data . 1 ;7 ;1 ;/* * Initialize hw_mode information . if (!rt2x00_has_cap_rf_sequence(rt2x00dev)) {14 ;else {14 ;if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {/* * Create channel information array sizeof (*info), GFP_KERNEL);if (!info)return -ENOMEM;for (i = 0 ; i < 14 ; i++) {if (spec->num_channels > 14 ) {for (i = 14 ; i < spec->num_channels; i++) {14 ]);return 0 ;static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)int retval;/* * Disable power saving . 0 x00000007);/* * Allocate eeprom data . if (retval)return retval;if (retval)return retval;/* * Enable rfkill polling by setting GPIO direction of the * rfkill switch GPIO pin correctly . 1 );/* * Initialize hw specifications . if (retval)return retval;/* * This device has multiple filters for control frames , * but has no a separate filter for PS Poll frames . /* * This device requires firmware and DMA mapped skbs . if (!modparam_nohwcrypt)/* * Set the rssi offset . return 0 ;/* * IEEE80211 stack callback functions . static int rt61pci_conf_tx(struct ieee80211_hw *hw,struct ieee80211_vif *vif,unsigned int link_id, u16 queue_idx,const struct ieee80211_tx_queue_params *params)struct rt2x00_dev *rt2x00dev = hw->priv;struct data_queue *queue;struct rt2x00_field32 field;int retval;/* * First pass the configuration through rt2x00lib , that will * update the queue settings and validate the input . After that * we are free to update the registers based on the value * in the queue parameter . if (retval)return retval;/* * We only need to perform additional register initialization * for WMM queues . if (queue_idx >= 4 )return 0 ;/* Update WMM TXOP register */ sizeof (u32) * (!!(queue_idx & 2 )));1 ) * 16 ;0 xffff << field.bit_offset;/* Update WMM registers */ 4 ;0 xf << field.bit_offset;return 0 ;static u64 rt61pci_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)struct rt2x00_dev *rt2x00dev = hw->priv;32 ;return tsf;static const struct ieee80211_ops rt61pci_mac80211_ops = {static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {static void rt61pci_queue_init(struct data_queue *queue)switch (queue->qid) {case QID_RX:32 ;sizeof (struct queue_entry_priv_mmio);break ;case QID_AC_VO:case QID_AC_VI:case QID_AC_BE:case QID_AC_BK:32 ;sizeof (struct queue_entry_priv_mmio);break ;case QID_BEACON:4 ;0 ; /* No DMA required for beacons */ sizeof (struct queue_entry_priv_mmio);break ;case QID_ATIM:default :break ;static const struct rt2x00_ops rt61pci_ops = {4 ,#ifdef CONFIG_RT2X00_LIB_DEBUGFS#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ /* * RT61pci module information . static const struct pci_device_id rt61pci_device_table[] = {/* RT2561s */ 0 x1814, 0 x0301) },/* RT2561 v2 */ 0 x1814, 0 x0302) },/* RT2661 */ 0 x1814, 0 x0401) },0 , }"Ralink RT61 PCI & PCMCIA Wireless LAN driver." );"GPL" );static int rt61pci_probe(struct pci_dev *pci_dev,const struct pci_device_id *id)return rt2x00pci_probe(pci_dev, &rt61pci_ops);static struct pci_driver rt61pci_driver = {
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