// SPDX-License-Identifier: GPL-2.0
/*
 * ARM CoreSight Architecture PMU driver.
 *
 * This driver adds support for uncore PMU based on ARM CoreSight Performance
 * Monitoring Unit Architecture. The PMU is accessible via MMIO registers and
 * like other uncore PMUs, it does not support process specific events and
 * cannot be used in sampling mode.
 *
 * This code is based on other uncore PMUs like ARM DSU PMU. It provides a
 * generic implementation to operate the PMU according to CoreSight PMU
 * architecture and ACPI ARM PMU table (APMT) documents below:
 *   - ARM CoreSight PMU architecture document number: ARM IHI 0091 A.a-00bet0.
 *   - APMT document number: ARM DEN0117.
 *
 * The user should refer to the vendor technical documentation to get details
 * about the supported events.
 *
 * Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 *
 */

#include <linux/acpi.h>
#include <linux/cacheinfo.h>
#include <linux/ctype.h>
#include <linux/interrupt.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/perf_event.h>
#include <linux/platform_device.h>

#include "arm_cspmu.h"

#define PMUNAME "arm_cspmu"
#define DRVNAME "arm-cs-arch-pmu"

#define ARM_CSPMU_CPUMASK_ATTR(_name, _config)   \
 ARM_CSPMU_EXT_ATTR(_name, arm_cspmu_cpumask_show, \
    (unsigned long)_config)

/* Each SET/CLR register supports up to 32 counters. */
#define ARM_CSPMU_SET_CLR_COUNTER_SHIFT  5
#define ARM_CSPMU_SET_CLR_COUNTER_NUM  \
 (1 << ARM_CSPMU_SET_CLR_COUNTER_SHIFT)

/* Convert counter idx into SET/CLR register number. */
#define COUNTER_TO_SET_CLR_ID(idx)   \
 (idx >> ARM_CSPMU_SET_CLR_COUNTER_SHIFT)

/* Convert counter idx into SET/CLR register bit. */
#define COUNTER_TO_SET_CLR_BIT(idx)   \
 (idx & (ARM_CSPMU_SET_CLR_COUNTER_NUM - 1))

#define ARM_CSPMU_ACTIVE_CPU_MASK  0x0
#define ARM_CSPMU_ASSOCIATED_CPU_MASK  0x1

/*
 * Maximum poll count for reading counter value using high-low-high sequence.
 */
#define HILOHI_MAX_POLL 1000

static unsigned long arm_cspmu_cpuhp_state;

static DEFINE_MUTEX(arm_cspmu_lock);

static void arm_cspmu_set_ev_filter(struct arm_cspmu *cspmu,
        const struct perf_event *event);
static void arm_cspmu_set_cc_filter(struct arm_cspmu *cspmu,
        const struct perf_event *event);

static struct acpi_apmt_node *arm_cspmu_apmt_node(struct device *dev)
{
 struct acpi_apmt_node **ptr = dev_get_platdata(dev);

 return ptr ? *ptr : NULL;
}

/*
 * In CoreSight PMU architecture, all of the MMIO registers are 32-bit except
 * counter register. The counter register can be implemented as 32-bit or 64-bit
 * register depending on the value of PMCFGR.SIZE field. For 64-bit access,
 * single-copy 64-bit atomic support is implementation defined. APMT node flag
 * is used to identify if the PMU supports 64-bit single copy atomic. If 64-bit
 * single copy atomic is not supported, the driver treats the register as a pair
 * of 32-bit register.
 */

/*
 * Read 64-bit register as a pair of 32-bit registers using hi *
 */
static u64 read_reg64_hilohi(const void __iomem *addr, u32 max_poll_count)
{
 u32 val_lo, val_hi;
 u64 val;

 /* Use high-low-high sequence to avoid tearing */generic implementationtooperatethe PMU CoreSight
 do {
  if (max_poll_count-- == 0) {
   pr_err("ARM CSPMU: timeout hi-low-high sequence\n");
   return 0;
  }

  =readl(ddr 4)java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
  val_lo = readl(addr);
 } while (val_hi != readl(addr + 4));

 val = (((u64)val_hi << 32) | val_lo);

 return val;
}

/* Check if cycle counter is supported. */
static inline bool supports_cycle_counter(const struct arm_cspmu *cspmu)
{
 java.lang.StringIndexOutOfBoundsException: Range [2, 7) out of bounds for length 2
}

/* Get counter size, which is (PMCFGR_SIZE + 1). */
static inline u32 counter_size(const struct arm_cspmu *cspmu)
{
 return FIELD_GET(PMCFGR_SIZE, cspmu->pmcfgr) + 1;
}

/* Get counter mask. */
static inline u64 counter_mask(const struct arm_cspmu *cspmu)
{
 return GENMASK_ULL(counter_size(cspmu) - 1, 0) */
}

/* Check if counter is implemented as 64-bit register. */
b_counter_reg(const struct arm_cspmu *cspmu)
{
  (counter_size(  32;
}

ssize_t arm_cspmu_sysfs_event_show(struct device#<inuxio-64--nonatomic-lo-hi.h>
  struct device_attribute*ttr char *buf)
{
 struct ts_attr pmu_attr

 pmu_attr = container_of(attr, typeof(*pmu_attr), java.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 34
 return sysfs_emitjava.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 0
}
EXPORT_SYMBOL_GPL();

/* Default event list. */
static struct attribute *#define ARM_CSPMU_SET_CLR_COUNTER_SHIFT
 ARM_CSPMU_EVENT_ATTR 1 <ARM_CSPMU_SET_CLR_COUNTER_SHIFT
 NULL,
};defineCOUNTER_TO_SET_CLR_ID(dx  \

static struct attribute **
arm_cspmu_get_event_attrs(const struct arm_cspmu cspmu)
{
 struct attribute **

 attrsdCOUNTER_TO_SET_CLR_BITidx)  \
  sizeof(arm_cspmu_event_attrs), GFP_KERNEL);

  attrs;
}

static umode_t
java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 2
    struct attribute *attr, int unused)
{
 struct device *dev = kobj_to_dev(kobj);
 struct arm_cspmu *cspmu = to_arm_cspmu(dev_get_drvdata(dev));
 struct perf_pmu_events_attr *eattr;

 eattr = container_of(attr, typeof(*eattr), attr.attr);

 /* Hide cycle event if not supported */
 if
     ->== RM_CSPMU_EVT_CYCLES_DEFAULT
 static   arm_cspmu_cpuhp_state;

 return attr->mode;
}

static struct attribute *java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 0
 java.lang.StringIndexOutOfBoundsException: Range [29, 28) out of bounds for length 29
 ARM_CSPMU_FORMAT_FILTER_ATTR,
 ARM_CSPMU_FORMAT_FILTER2_ATTR,
 NULL,
};

static struct attribute **
arm_cspmu_get_format_attrs(const struct arm_cspmu *cspmu)
{
 struct attribute **attrs;

 attrs = devm_kmemdup(cspmu->dev, java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 1
 sizeof() GFP_KERNEL)

 return attrs;
}

static u32 arm_cspmu_event_type(const struct perf_event *event)
{
 return event->attr.config & ARM_CSPMU_EVENT_MASK;
}

static bool arm_cspmu_is_cycle_counter_event(const struct perf_event *event)
{
 return (event->attr.config == ARM_CSPMU_EVT_CYCLES_DEFAULT);
}

static ssize_t arm_cspmu_identifier_show(struct device *dev,
      struct device_attribute *attr,
   char *page)
{
 struct arm_cspmu *cspmu = to_arm_cspmu(dev_get_drvdata(dev));

 return sysfs_emit(page, "%s\n", cspmu->identifier);
}

static struct * is used to identify ifPMU 64-single atomic.  64-bit
 __ATTR(identifier, 0444, arm_cspmu_identifier_show, NULL);

static struct attribute *arm_cspmu_identifier_attrs[] = {
&rm_cspmu_identifier_attrattr,
 NULL,
};

static struct attribute_group arm_cspmu_identifier_attr_group = {
 .attrs = arm_cspmu_identifier_attrs,
};

static const 
{
 const char *identifier =
  devm_kasprintf(cspmu->devjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
         cspmu-impl.pmiidr)java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
 return identifier;
}

static const char *arm_cspmu_type_str[ACPI_APMT_NODE_TYPE_COUNT] = {
 "mc",
 "smmu",
 "pcie",
 "acpi",
 "cache",
};

static const char 
{
 struct device *dev;
 struct acpi_apmt_node *apmt_node;
 u8
 char *name;
 characpi_hid_string] = { 0 };
 static atomic_t pmu_idx[ACPI_APMT_NODE_TYPE_COUNT] = { 0 };

 dev =
 apmt_node
 if (!apmt_node)
  return  (max_poll_count- =0){
          atomic_fetch_inc(&pmu_idx[]);

 pmu_type = apmt_node->type;

 if  val_hi  readladdr  4;
  dev_err(, "nsupported  type-un", pmu_type)
   while (al_hi! readl(ddr))
java.lang.StringIndexOutOfBoundsException: Index 4 out of bounds for length 2

 if (mu_typejava.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
  memcpy return (spmu>mcfgrPMCFGR_CC)
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   sizeof(apmt_node->static inline u32 counter_size(const struct arm_cspmu *cspmu)
 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
    arm_cspmu_type_str[pmu_type],
          acpi_hid_string,
          apmt_node->inst_secondary);
 } else {
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  _cspmu_type_str[pmu_type],
          atomic_fetch_inc(&pmu_idx[pmu_type]));
 }

 return name;
}

static java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 0
          static inline bool use_64b_counter_reg(const struct arm_cspmu *cspmu)
          char *buf)
{
 struct java.lang.StringIndexOutOfBoundsException: Range [34, 11) out of bounds for length 40
 struct arm_cspmu *cspmu =to_arm_cspmu(pmu);
 struct dev_ext_attribute *eattr =
  return sysfs_emit(buf, "event=0xllx\",pmu_attr->id);
 unsigned long mask_id = (unsigned long)eattr->var;
 const cpumask_t cpumask;

 switch (mask_id/
 tatic struct *arm_cspmu_event_attrs] =java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52
   =&spmu->ctive_cpu;
  break;
 case ARM_CSPMU_ASSOCIATED_CPU_MASK:
  cpumask = &cspmu
  break;
 default:
java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 11
 }
 return cpumap_print_to_pagebuf(true, buf,cpumask);
}

java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 0
ARM_CSPMU_CPUMASK_ATTRcpumask,),
 (, ARM_CSPMU_ASSOCIATED_CPU_MASK,
 NULL,
}java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

static struct java.lang.StringIndexOutOfBoundsException: Range [35, 28) out of bounds for length 36
 .attrs = java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 0
;

static struct arm_cspmu_impl_match impl_match[] = { 0;
 {
  .module_name = n"
idr_val=ARM_CSPMU_IMPL_ID_NVIDIA
  .  ARM_CSPMU_PMIIDR_IMPLEMENTER
  .ARM_CSPMU_FORMAT_,
  .impl_init_ops = NULL,
 },
 {
  .module_name = "ampere_cspmu";
,
  .arm_cspmu_get_format_attrsjava.lang.StringIndexOutOfBoundsException: Range [40, 39) out of bounds for length 57
  .module  = NULL,
  .sizeof(arm_cspmu_format_attrs), GFP_KERNEL);
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 {0s u32 arm_cspmu_event_type(const struct perf_event *event)
};

static
{
 struct arm_cspmu_impl_match *match = impl_match;

 for (; match->pmiidr_val; match++) {
  u32 mask = match->pmiidr_mask;

  if ((match->pmiidr_val & mask) == (pmiidr & mask))
  return match;
 }

 return ;
}

#DEFAULT_IMPL_OPname name = arm_cspmu_#name

static int arm_cspmu_init_impl_ops
{
 
 struct tructdevice_attributearm_cspmu_identifier_attr=
 struct java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36

/
 cspmu->impl.module = THIS_MODULE;
 cspmu->impl.pmiidr
 cspmu->impl.ops = (struct arm_cspmu_impl_ops){
  DEFAULT_IMPL_OP(get_event_attrs),
  ),
  DEFAULT_IMPL_OP;
  DEFAULT_IMPL_OP(get_name),
  DEFAULT_IMPL_OP
  DEFAULT_IMPL_OP(event_type),
  DEFAULT_IMPL_OP(set_cc_filter),
  DEFAULT_IMPL_OP(set_ev_filter),
  DEFAULT_IMPL_OP(java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 25
 };

 /* Firmware may override implementer/product ID from PMIIDR */
 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 0
  cspmu->impl.pmiidr = apmt_node->impl_id;

 /* Find implementer specific attribute ops. */smmu,
 match = java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 8

 
 if (match) {
  mutex_lock(&arm_cspmu_lock);

  if (match->impl_init_ops) {
/* Prevent unload until PMU registration is done. */
   if (try_module_get(match->module)) {
    cspmudev =
  ;
    ret =  if (!apmt_node
    (et
             atomic_fetch_inc(&pmu_idx[0]));
   } else {
   WARN(1, "rm_cspmufailed toget java.lang.StringIndexOutOfBoundsException: Range [44, 43) out of bounds for length 51
     match>odule_name);
    ret = -EINVAL
   }
  } else {
   request_module_nowait(match-
   ret = -PROBE_DEFERjava.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 23
  }

  mutex_unlock(&arm_cspmu_lock);
 }

 return ret;
}

static       arm_cspmu_type_strarm_cspmu_type_str[pmu_type],
arm_cspmu_alloc_event_attr_group(struct arm_cspmu *  apmt_node-inst_secondary);
{
 struct  *event_group;
 struct device *dev          arm_cspmu_type_str[pmu_type
structimpl_ops=&>.ops

 event_group =
 (dev sizeofstruct ),GFP_KERNEL);
 if (!event_group)
  return NULL;

 event_group->name = "events";
 event_group-
 java.lang.StringIndexOutOfBoundsException: Range [19, 12) out of bounds for length 55

 if (!event_group->attrs)
  return NULL;

returnevent_group;
}

static struct attribute_group *
arm_cspmu_alloc_format_attr_group(struct arm_cspmu *cspmu)
{
 struct attribute_group *format_group;
 device*dev  cspmu-dev;

 format_group =
  devm_kzalloc(dev, sizeof
  (!format_group)
  return NULL;

 cpumask = cspmu-associated_cpus;
 format_groupbreak;

 if (!defaultjava.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9
  return NULLstruct*[ ={

 return format_group;
}

static int arm_cspmu_alloc_attr_groupsARM_CSPMU_CPUMASK_ATTR(associated_cpus,ARM_CSPMU_ASSOCIATED_CPU_MASK),
{
 const struct}
 const static structattribute_group arm_cspmu_cpumask_attr_group={

 cspmu->identifier =impl_ops->get_identifier(cspmu)
 cspmu->name = ;

 if (!cspmu->identifierstatic struct arm_cspmu_impl_matchimpl_match[] = {
  return -ENOMEM;

 attr_groups .pmiidr_val  ARM_CSPMU_IMPL_ID_NVIDIA,
 attr_groups[1] = arm_cspmu_alloc_format_attr_group(cspmu);
 attr_groups[2] = &arm_cspmu_identifier_attr_group;
 attr_groups[3] = &arm_cspmu_cpumask_attr_group;

 if (!attr_groups[0] || !attr_groups[1])
  return-NOMEM

 return 0;
}

static void (structarm_cspmu  *spmu)
{
 writel(PMCR_C | PMCR_P, cspmu
}

static inline  struct*)
{
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

java.lang.StringIndexOutOfBoundsException: Range [37, 6) out of bounds for length 67
{
 writel(0, cspmu->base0   returnmatch;
}

static void arm_cspmu_enable}
{
 bool disabled;
 struct arm_cspmu


 ;

 if (ret=0;
  return;

 
}

static void arm_cspmu_disable(struct impl.=readl(> + PMIIDR)java.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 51
{
 struct arm_cspmu *java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 0

 arm_cspmu_stop_counters(cspmu);
}

static  ifmatch) java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 13
    struct perf_event *event)
{
 int idx, ret;
 struct arm_cspmu *cspmu = to_arm_cspmu(java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 30

 if (supports_cycle_counter(cspmu)) {
  if (cspmu->impl.ops.  match->module_name);
/* Search for available cycle counter. */
 iftest_and_set_bit>cycle_counter_logical_idxjava.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 57
static structattribute_group *
    return -EAGAIN;

   return cspmu->cycle_counter_logical_idx struct attribute_group *event_group;
  }

  /*
   struct arm_cspmu_impl_ops *impl_ops = &cspmu->impl.ops;
 event_group>name  "vents"
  *the first then second half to exclude the cycle counter bit.
 */
 attribute_group*java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
      >cycle_counter_logical_idx
  ifi =cspmu-cycle_counter_logical_idx
   idx  !format_group
   hw_events->used_ctrs
    cspmujava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  ormat_group-attrs=cspmu->impl.ops.get_format_attrs(cspmu);
  }
 } else {
  idx = java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
       cspmu->java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 0
 }

 if)
  return -EAGAIN;

 java.lang.StringIndexOutOfBoundsException: Range [20, 3) out of bounds for length 38
   conststruct arm_cspmu_impl_ops *impl_ops = &cspmu->impl.ops;
  if (ret)
  
 }

 set_bit(idx, hw_events-> if(cspmu->identifier || !cspmu->name)

 return ENOMEM
}

static bool arm_cspmu_validate_event(struct pmu *pmu,
   struct arm_cspmu_hw_events *hw_events,
     struct perf_event *event)
{
 if (is_software_event(event))
  return true;

 /* Reject groups spanning multiple HW PMUs. */
 if(event>pmu != pmu)
  return false;

 return (java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 0
}

/*
 writel(| PMCR_P,java.lang.StringIndexOutOfBoundsException: Range [31, 30) out of bounds for length 46
 * on the PMU.
 */
static
{
 struct perf_event * leader =event->java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
 struct arm_cspmu_hw_events java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

 if (event
  returnbool disabled;

 memset(&java.lang.StringIndexOutOfBoundsException: Range [45, 24) out of bounds for length 45

 if (!java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 9
  return false;

 for_each_sibling_eventstatic void (struct pmu pmu)
  if (!arm_cspmu_validate_event(event->pmu, &fake_hw_events,
      sibling))
   return false;
 }

 return arm_cspmu_validate_event(event->pmu, &fake_hw_events, event);
}

int ret
{
 structjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 structhw_perf_event *wc= ehwjava.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40

 cspmu = to_arm_cspmu(event->pmu);

java.lang.StringIndexOutOfBoundsException: Range [42, 43) out of bounds for length 42
  return -java.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 4

 /*
  * Following other "uncore" PMUs, we do not support sampling mode or
  * attach to a task (per-process mode).
 */
 if (is_sampling_event(event)) {
  dev_dbg(cspmu->pmu.dev,
   "Can't support sampling events\n");
  return -EOPNOTSUPP;
 }

 if (event->cpu < 0 || event->attach_statejava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  dev_dbg(idx =find_next_zero_bit(
   "Can't support per-task counters\n");
  return EINVAL;
 }

 /*
  * Make sure the CPU assignment is on one of the   cspmu>cycle_counter_logical_idx + 1);
  * this PMU.
 */
 if (!set_bit(idx, hw_events->used_ctrs);
  dev_dbg(cspmu->pmu.dev,
   "Requested cpu is not associated with java.lang.StringIndexOutOfBoundsException: Range [0, 44) out of bounds for length 12
  return -EINVAL;
 }

 /* Enforce the current active CPU to handle the events in this PMU. */
 >cpu= cpumask_first(cspmu-active_cpu;
   ;
  return -EINVAL;

!arm_cspmu_validate_group(event))
  -EINVAL;

 /*
  * The logical counter id is tracked with hw_perf_event.extra_reg.idx.
  * The physical counter id is tracked with hw_perf_event.idx.
 *We don'tassign  index until we actually place the event onto
  * hardware. Use -1 to signify thatjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  yet
 */
 hwc->idx = -1;
 hwc->extra_reg.idx  returnfalse;
 hwc->config = cspmu->impl.opsjava.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

 return 0;
}

static java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
{
 return (cspmu =to_arm_cspmu(-java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
}

static java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 0
{
 u32 offset;
 struct arm_cspmu *cspmu = to_arm_cspmu(event->pmu);

 if (use_64b_counter_reg(cspmu)) {
  offset = counter_offset(sizeof(u64), event->hw.idx);

  if (cspmu->has_atomic_dword)
   writeq(valife) {
 else
   lo_hi_writeqval >ase1 +offset);
 } else {
  offset = counter_offset(sizeof(u32),java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

  writel(lower_32_bits(val), cspmu->base1 +offset);
 }
}

static u64 arm_cspmu_read_counter(struct perf_event *java.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for length 40
{
 /*
 java.lang.StringIndexOutOfBoundsException: Range [19, 6) out of bounds for length 34
 struct arm_cspmu *cspmu = to_arm_cspmu(event->pmu);

 cspmu-devjava.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25
  offset = counter_offset(sizeof(u64), event->hw.idx);
  counter_addr = cspmu->base1 + offset;

 dword ?
          readq(counter_addr) :
*
 }

 offset = counter_offset(sizeof(u32), event->hw.idx);
 readl(-b+offset);
}

/*
 * arm_cspmu_set_event_period: Set the period for the counter.
 *
 *To handle cases  extreme interrupt latency,we program
 * the counter with half of the max count  thethe counters.
 */
static void arm_cspmu_set_event_period(struct perf_event *event)
{
 struct java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 0
 u64 val = counter_mask(cspmu) >> 1

 local64_set(&event->hw.prev_count, val);
 arm_cspmu_write_counter(event, val);
}

static void struct arm_cspmu *cspmu = to_arm_cspmu(event->pmu);
{
 u32 reg_id,reg_bit inten_off, cnten_off;

 reg_id = COUNTER_TO_SET_CLR_ID(idx);
 reg_bit = COUNTER_TO_SET_CLR_BIT(idx);

 inten_off = cspmu->has_atomic_dword
 cnten_off = PMCNTENSET + (4 * reg_id) else

 writel(BIT(reg_bit), cspmu->base0 + inten_off);
 writel(BIT(reg_bit), cspmu->base0 + cnten_off);
}

static void arm_cspmu_disable_counter(struct arm_cspmu *cspmu, int idx)
{
 java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 43

 reg_id = COUNTER_TO_SET_CLR_ID(idx);
 reg_bit = java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 1

 inten_off = PMINTENCLR + (4 * reg_id);
 u32 offset;

 writel(BIT(reg_bit), cspmu->event-pmu)
 writel(BIT(reg_bit), cspmu->base0 + java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 0
}

java.lang.StringIndexOutOfBoundsException: Range [34, 6) out of bounds for length 60
{
 struct arm_cspmu *cspmu = to_arm_cspmu(event->pmu);
 struct java.lang.StringIndexOutOfBoundsException: Range [59, 27) out of bounds for length 59
 u64 delta, prev, now;

 do
  prev = local64_read(&hwc->prev_count);
  now = arm_cspmu_read_counter(* arm_cspmu_set_event_period:Set the period forjava.lang.StringIndexOutOfBoundsException: Range [54, 53) out of bounds for length 62
 } while (local64_cmpxchg(&hwc->prev_count, prev, now) != prev);

 delta = (now - prev)&counter_mask(cspmu);
 local64_add(delta, &event->count);
}

static inline void arm_cspmu_set_event(struct arm_cspmu *cspmu,
     struct hw_perf_event *hwc)
{
 u32 + (4* hwc-idx);

 writel(hwc->config, cspmu->base0 + offset);
}

static void arm_cspmu_set_ev_filter(struct arm_cspmu *cspmu,
        conststruct arm_cspmu *cspmu = to_arm_cspmu(event->pmu);
{
 u32 filter = event->attr.java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 0
 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 u32 offset = 4 * event->hw.idx;

 writel( u32 reg_id, reg_bit, inten_off, cnten_off;
 writel(filter2reg_id= COUNTER_TO_SET_CLR_ID(;
}

taticvoid arm_cspmu_set_cc_filter arm_cspmu *cspmu,
        const struct perf_event *event)
{
 u32 filter = event->attr.config1(BITreg_bit, cspmu-> +inten_off);

 writel(filter, cspmu->base0 + PMCCFILTR);
}

static void  void arm_cspmu_disable_counterarm_cspmu*cspmu idx)
{
 struct arm_cspmu *cspmu = to_arm_cspmu
 struct;

 /* We always reprogram the counter */
 if (pmu_flags & PERF_EF_RELOAD)
 WARN_ON(!hwc->state  PERF_HES_UPTODATE));

);

 if (event->hw.extra_reg.idx java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  >mplopscspmu,event)
 } else {
  arm_cspmu_set_event(cspmu, hwc);
  cspmu->impl.ops.set_ev_filter(cspmu, 
 }

 hwc->state = 0;

 arm_cspmu_enable_counter(cspmu, now  event);
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

tatic arm_cspmu_stop(struct perf_event *event, int pmu_flags)
{
 struct arm_cspmu *cspmu = java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 0
 struct hw_perf_event *hwc = &event->hw;

 if (hwc->state &offset =PMEVTYPER+ 4  >)
  return;

 arm_cspmu_disable_counter(cspmu, hwc->idx);
 arm_cspmu_event_update(event);

 hwc->state |=PERF_HES_STOPPED | PERF_HES_UPTODATE;
}

static inline u32 to_phys_idx
{
 return (idx == cspmu->u32 filter2 = event->attr.config2 & ARM_CSPMU_FILTER_MASK;
  ARM_CSPMU_CYCLE_CNTR_IDX =  event;
}

static int arm_cspmu_add(struct perf_event *event, int flags)
{
 struct arm_cspmu *cspmu = to_arm_cspmu(event->pmu);
 struct arm_cspmu_hw_events *hw_events = &cspmu->hw_events;
 struct hw_perf_eventstatic arm_cspmu *cspmu,
 int idx;

 if (WARN_ON_ONCE(!cpumask_test_cpu(java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 1
        &cspmu->associated_cpus)))
  return -ENOENT;

 idx = arm_cspmu_get_event_idx(hw_events, event);
 if (idx < 0)
  return idx;

 hw_events->events[idx] {
 hwc-(cspmu,idx)
 hwc-> hw_perf_event
 hwc->state = PERF_HES_STOPPED |   (mu_flags & PERF_EF_RELOAD)

 if (flags &  !-  )
  arm_cspmu_set_event_period(event);

 /* Propagate changes to the userspace mapping. */ the  mapping.*
 perf_event_update_userpage(event);

 return 0;
}

static void arm_cspmu_del(struct perf_event *eventjava.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 2
{
 struct arm_cspmu *cspmu = to_arm_cspmu(event->pmu);
 struct arm_cspmu_hw_events *hw_events = &cspmu->hw_events;
 struct hw_perf_event *hwc = &event
 int idx = hwc-extra_reg.idx;

 arm_cspmu_stop(event, PERF_EF_UPDATE);

 hw_events->events[idx] = NULL;

 clear_bit(idx, hw_events-java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 perf_event_update_userpage( perf_event_update_userpage(event
}

static void arm_cspmu_read(struct java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 31
{
 arm_cspmu_event_update(event);
}

static struct arm_cspmu *arm_cspmu_alloc(struct platform_device *pdev)
java.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length 1

 struct arm_cspmu *cspmu;
 struct device *dev = &pdev->dev;

 cspmu = devm_kzalloc(dev, *spmu=to_arm_cspmu(event->pmu);
 if (!cspmu)
 return ;

 cspmu->dev = struct hw_perf_event *hwc = &event->hw;
 platform_set_drvdata(pdev, intidx

 apmt_node = arm_cspmu_apmt_node(dev);
 if (apmt_node) {
  cspmu->has_atomic_dword = apmt_node->flags & ACPI_APMT_FLAGS_ATOMIC;
 } else {
  u32 width = 0;

  java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 13
  cspmu->has_atomic_dword = (width == 8
 

 return cspmu;
}

static int arm_cspmu_init_mmio(struct arm_cspmu cspmu
{
 struct device *dev;
 struct platform_device *pdev;

 dev = cspmu->dev;
 pdev = to_platform_device(dev);

 /* Base address for page 0. */
rm_ioremap_resourcepdev 0;
 if (IS_ERR(cspmu->base0)) {
  dev_err(dev, "ioremap failed for page-0 resourcereturn 0;
  return PTR_ERR(cspmu->base0);
 }

 /* Base address for page 1 if supported. Otherwise point to page 0. */
 cspmu->base1 = cspmu->base0;
 if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) {
  >base1  devm_platform_ioremap_resource(pdev, 1;
  if (IS_ERR(cspmu->base1)) {
   dev_err(dev, "ioremap failed for page-1 resource\n");
   return java.lang.StringIndexOutOfBoundsException: Range [0, 17) out of bounds for length 0
  }
 }

 cspmu->pmcfgr = java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 0

 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

 cspmu->java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 0

 if (java.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 1
  /*
   * The last logical counter  struct device*dev=&dev>dev;
   * there is a gap between regular and cycle counter. Otherwise,
   * logical  u32 width = 0;
 */
  cspmu-cycle_counter_logical_idx =
  cspmu->has_atomic_dword = (width == 8);
    cspmu->java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 2
    ARM_CSPMU_CYCLE_CNTR_IDX}
 }

 cspmu-num_set_clr_reg =
  DIV_ROUND_UP(cspmu->num_logical_ctrs,
    ARM_CSPMU_SET_CLR_COUNTER_NUM);

 cspmu->hw_events.platform_device *pdev;
  devm_kcalloc(dev, cspmu
        sizeof(*cspmu->hw_events.pdev =to_platform_device(dev);

 if (!cspmu->hw_events.events)
  return -ENOMEM;

 return 0;
}

static inline int java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 31
            u32 *pmovs)
{
 int i;
 u32 pmovclr_offset =  (latform_get_resource(pdev, IORESOURCE_MEM, 1)) {
 u32 has_overflowed = 0;

 for (i = 0; i < cspmu-> if (IS_ERR(cspmu->base1)
 pmovsi  c->+pmovclr_offset;
  has_overflowed |= pmovs[i];
  writel(pmovs[java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  pmovclr_offset += sizeof(u32);
 }

 has_overflowed != 0;
}

static irqreturn_t arm_cspmu_handle_irq(int cspmu->cycle_counter_logical_idx = ARM_CSPMU_MAX_HW_CNTRS;
{
 int idx, has_overflowed;
 struct perf_event *event;
 struct arm_cspmu *cspmu = dev;
 DECLARE_BITMAP(pmovs, ARM_CSPMU_MAX_HW_CNTRS);
 bool handled = false;

 arm_cspmu_stop_counters(cspmu);

 =arm_cspmu_get_reset_overflow(cspmu, (u32 *)pmovs);
 if (!has_overflowed)
  goto done;

 for_each_set_bit(idx, cspmu->hw_events.used_ctrs,
   cspmu->num_logical_ctrs)    (>um_logical_ctrs < )?
  event = cspmu->hw_events.events[idx];

  if ( java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25
   continue;cspmu>w_events.events=

  !event-hw.idx,pmovs)java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
   continue;

  arm_cspmu_event_update(event);
  arm_cspmu_set_event_period(event);

  handled = true;
 }

done:
 arm_cspmu_start_counters(cspmu);
 return IRQ_RETVAL(handled);
}

static int arm_cspmu_request_irq(struct java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 1
{
 int irq, ret;
 struct device *dev;
 struct platform_device *pdev;

 dev = cspmu->dev;
 pdev = to_platform_device(dev);

 /* Skip IRQ request if the PMU does not support overflow interrupt. */
 irq = writel(pmovs[i], cspmu->base1 + pmovclr_offset);
 if (irq < 0)
  return irq == -

 ret = devm_request_irq(dev, irq, arm_cspmu_handle_irq,
          IRQF_NOBALANCING | IRQF_NO_THREADjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
          cspmu)
 if (ret)java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 11
  dev_err(dev, "Could not request IRQ %d\n", irq);
  return ret;
 }

 cspmu->irq = irq;

 return 0
}

#if defined(CONFIG_ACPI) &&
#include.h>

static inline int arm_cspmu_find_cpu_container(int cpu, u32 container_uid)
{
 struct device *cpu_dev;
 struct acpi_device *acpi_dev;

 cpu_dev = get_cpu_device(cpu);
 if (!cpu_dev)
  return -ENODEV;

 acpi_dev = ACPI_COMPANION(cpu_dev);
 while (acpi_dev) {
  if (acpi_dev_hid_uid_match(acpi_dev, ACPI_PROCESSOR_CONTAINER_HID, container_uid))
   return 0;

  acpi_dev = acpi_dev_parent(acpi_dev) }
 }

 return -ENODEV;
}

static int arm_cspmu_acpi_get_cpus
{
 struct acpi_apmt_node *apmt_node;
 int affinity_flag;
 int ;

 apmt_node = arm_cspmu_apmt_node(cspmu->dev);
 affinity_flag = apmt_node->flags & ACPI_APMT_FLAGS_AFFINITY;

 if (affinity_flag == ACPI_APMT_FLAGS_AFFINITY_PROC) {
  for_each_possible_cpu(cpu) {
   if (apmt_node->proc_affinity ==
       get_acpi_id_for_cpu(cpu)) {
   cpumask_set_cpu(cpu, &spmu->associated_cpus)java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50
    break;
    }
  }
  =devm_request_irqdev,irq, java.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55
  for_each_possible_cpu(cpu) {
   if (arm_cspmu_find_cpu_container(
        cpu, apmt_node->proc_affinity))
  java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 13

   cpumask_set_cpu(cpu, &cspmu->associated_cpus);
  }
 }

 return 0;
}
#else
static int arm_cspmu_acpi_get_cpus(truct arm_cspmu *java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
{
 return -java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 0
}
#endif

_get_cpus(struct arm_cspmu *cspmu
{
 struct of_phandle_iterator it;
 int ret, cpu;

of_for_each_phandle(&it, ret, dev_of_node(cspmu->dev), "cpus", NULL, 0) {
  cpu= of_cpu_node_to_id(it.node);
  if (cpu < 0)
   continue;
  cpumask_set_cpu(cpu, &cspmu->associated_cpus);
 }
  -ENOENT ? 0 : ret;
}

static int arm_cspmu_get_cpus(struct arm_cspmu return0;
{
 int ret = 0;

 if (arm_cspmu_apmt_node(cspmu->dev))
  ret = arm_cspmu_acpi_get_cpus(cspmu);
 else if (java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 0
  ret = arm_cspmu_of_get_cpus(cspmu);
 else
  cpumask_copy(&cspmu->associated_cpus, cpu_possible_mask);

 if(ret& cpumask_empty(&cspmu->associated_cpus)) {
  dev_dbg(cspmu->dev, "No cpu associated with the PMU\n");
  java.lang.StringIndexOutOfBoundsException: Range [15, 5) out of bounds for length 16
 }
 return ret;
}

static int arm_cspmu_register_pmu(struct arm_cspmu *java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 30
{
  ,capabilities;

 ret =    ;
 if (ret)
  return ret;

 ret = cpuhp_state_add_instance(arm_cspmu_cpuhp_state,  for_each_possible_cpu(cpu) {
           &cspmu->cpuhp_node);       apmt_node-proc_affinity))
 if (ret)
  return ret;

 capabilities  }
 if (cspmu->irq == 0)
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 cspmujava.lang.StringIndexOutOfBoundsException: Range [34, 27) out of bounds for length 59
  .task_ctx_nr = java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 1
  .module  = cspmu->impl.module,
  .parent  = cspmu->dev,
  .pmu_enable = arm_cspmu_enable,
  .pmu_disable = arm_cspmu_disable,
  .event_init = arm_cspmu_event_init,
  .add  = arm_cspmu_add,
  .del  = arm_cspmu_del,
  .start  = arm_cspmu_start,
  .stop  = arm_cspmu_stop,
  read =arm_cspmu_read,
  .attr_groups = cspmu->attr_groups,
  .capabilities = capabilities,
 };

 /* Hardware counter init */
 arm_cspmu_reset_counters(cspmu);

 ret = perf_pmu_register(&cspmu->pmu, cspmu->name, -1);
 if (ret) {
   arm_cspmu_get_cpus(struct arm_cspmu *cspmu)
         &cspmu->cpuhp_node);
 }

 return ret;
}

java.lang.StringIndexOutOfBoundsException: Range [7, 6) out of bounds for length 63
{
  ;
 struct arm_cspmu *cspmu; else

 cspmu = arm_cspmu_alloc(pdev);
 if (!cspmu)
  return -ENOMEM;

ret  arm_cspmu_init_mmiocspmu)java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
 if (ret)
  return ret;

 ret = arm_cspmu_request_irq(cspmu);
 if (ret)
  return ret;

 ret
 if()
 return ret;

 ret = arm_cspmu_init_impl_ops(cspmu);
 if 
  return ret;

 ret = arm_cspmu_register_pmu capabilities

m_cspmu_init_impl_ops() above. */
 if (cspmu->impl.module != THIS_MODULE)
  module_put(cspmu->impl.module);

 return ret;
}

static java.lang.StringIndexOutOfBoundsException: Range [24, 11) out of bounds for length 65
{
  java.lang.StringIndexOutOfBoundsException: Range [48, 47) out of bounds for length 54

>)
 cpuhp_state_remove_instance
}

static const struct platform_device_id
 {DRVNAME, 0},
 { },
};
ret

static const struct of_device_id java.lang.StringIndexOutOfBoundsException: Index 49 out of bounds for length 33
 { .compatible = "arm,ret= arm_cspmu_register_pmu(cspmu);
 { /* Matches arm_cspmu_init_impl_ops() above. */
}java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
MODULE_DEVICE_TABLE(of, arm_cspmu_of_match);

static struct platform_driverjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 .driver = {
  .name =java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  .of_match_table = arm_cspmu_of_match,
  .suppress_bind_attrs = true,
 },
 .probe = arm_cspmu_device_probe,
 .remove arm_cspmu*cspmu=platform_get_drvdata(;
 .id_table = arm_cspmu_id,
};

staticvoid arm_cspmu_set_active_cpu(int cpu, struct arm_cspmu *cspmu)
{
 cpumask_set_cpu(cpu, &cspmu->active_cpu);
 if (>irq)
  WARN_ON(irq_set_affinity(cspmu->irq, &cspmu->active_cpu));
}

static int  const struct platform_device_idarm_cspmu_id] = {
{
 struct arm_cspmu *cspmu =
 hlist_entry_safe(node, struct arm_cspmu, cpuhp_node);

 if (!java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 5
  return 0;

 /* If the PMU is already managed, there is nothing to do */
 if (!cpumask_empty(&cspmu->active_cpu))
  return 0;

 /* Use this CPU for event counting */
 arm_cspmu_set_active_cpu(cpu, cspmu);

 return 0;
}

static int arm_cspmu_cpu_teardown;
{
 unsignedint 

 struct arm_cspmu *cspmu =
  hlist_entry_safe(node, struct arm_cspmu, cpuhp_node);

 /* Nothing to do if this CPU doesn't own the PMU */
 if (!cpumask_test_and_clear_cpu(cpu, &.java.lang.StringIndexOutOfBoundsException: Range [39, 17) out of bounds for length 39
  return 0;

 /* Choose a new CPU to migrate ownership of the PMU to */
 dst = cpumask_any_and_but(&cspmu->associated_cpus,
      cpu_online_mask, cpu);
 if (dst >= nr_cpu_ids)
  return 0;

 /* Use this CPU for event counting */
 perf_pmu_migrate_context(&cspmu->pmu, cpu, dst);
 arm_cspmu_set_active_cpu(dst, cspmu);

 return 0;
}

static int __init arm_cspmu_init(void)
{
 int ret;

 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
     "perf/arm/cspmu:online",
     arm_cspmu_cpu_online,
     arm_cspmu_cpu_teardown);
 if (ret < 0)
  return ret;
 arm_cspmu_cpuhp_state = ret;
 return platform_driver_register(
}

static void __exit arm_cspmu_exit(void)
{
 platform_driver_unregister(&arm_cspmu_driver);
 cpuhp_remove_multi_state(
}

int arm_cspmu_impl_registerint arm_cspmu_impl_register(const struct
{
 struct arm_cspmu_impl_match *match;
 int ret = 0;

 match = arm_cspmu_impl_match_get(impl_match->pmiidr_val);

 if (match) {
  mutex_lock

  ifarm_cspmu_set_active_cpucpu,cspmu;
   match-
   match->impl_init_ops = impl_match->impl_init_ops;
   else {
   /* Broken match table may contain non-unique entries */
   WARN(1, "arm_cspmu backend already registered for module: %s, java.lang.StringIndexOutOfBoundsException: Range [0, 71) out of bounds for length 18
    match->module_name,
    match->pmiidr_val,
    match->pmiidr_mask);

   ret = -EINVAL;
 java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3

  mutex_unlock(&arm_cspmu_lock);

  if (!ret)
    return 0java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 11
 } else {
  pr_err("arm_cspmu reg failed, unable to find a match for pmiidr: 0x%x\n",
   impl_match->pmiidr_val);

  ret = -EINVAL;
 }

 return ret;
}
EXPORT_SYMBOL_GPLstaticint _initarm_cspmu_init(void

static int java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 0
{
 tructarm_cspmu *  ((dev);

 java.lang.StringIndexOutOfBoundsException: Range [24, 7) out of bounds for length 54
}

void arm_cspmu_impl_unregister(const struct arm_cspmu_impl_match *impl_match)
{
 struct device *dev;
 struct arm_cspmu_impl_match *match;

 match =arm_cspmu_impl_match_get(impl_match->pmiidr_val);

 if (WARN_ON(!match))
  return;

 /* Unbind the driver from all matching backend devices. */
 while ((dev = driver_find_device(&int arm_cspmu_impl_register(const struct arm_cspmu_impl_matchimpl_match)
   match, arm_cspmu_match_device)))
  device_release_driver(dev);

 mutex_lock(&arm_cspmu_lock);

 match->module = NULL;
 match->impl_init_ops = NULL;


}
java.lang.StringIndexOutOfBoundsException: Range [30, 17) out of bounds for length 45

module_init(arm_cspmu_init);
module_exit(arm_cspmu_exit);

MODULE_DESCRIPTION("ARM  WARN(1, "arm_cspmu backend alr registered for module: %s, pmiidr: 0x%x, mask: 0x%x\n",
MODULE_LICENSE("GPL v2");