// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2024 AIROHA Inc * Author: Lorenzo Bianconi <lorenzo@kernel.org> #include <linux/bitfield.h>#include <linux/delay.h>#include <linux/io.h>#include <linux/module.h>#include <linux/of.h>#include <linux/phy/phy.h>#include <linux/platform_device.h>#include <linux/slab.h>#include "phy-airoha-pcie-regs.h" #define LEQ_LEN_CTRL_MAX_VAL 7#define FREQ_LOCK_MAX_ATTEMPT 10/* PCIe-PHY initialization time in ms needed by the hw to complete */ #define PHY_HW_INIT_TIME_MS 30enum airoha_pcie_port_gen {/** * struct airoha_pcie_phy - PCIe phy driver main structure * @dev: pointer to device * @phy: pointer to generic phy * @csr_2l: Analogic lane IO mapped register base address * @pma0: IO mapped register base address of PMA0-PCIe * @pma1: IO mapped register base address of PMA1-PCIe * @p0_xr_dtime: IO mapped register base address of port0 Tx-Rx detection time * @p1_xr_dtime: IO mapped register base address of port1 Tx-Rx detection time * @rx_aeq: IO mapped register base address of Rx AEQ training struct airoha_pcie_phy {struct device *dev;struct phy *phy;void __iomem *csr_2l;void __iomem *pma0;void __iomem *pma1;void __iomem *p0_xr_dtime;void __iomem *p1_xr_dtime;void __iomem *rx_aeq;static void airoha_phy_clear_bits(void __iomem *reg, u32 mask)static void airoha_phy_set_bits(void __iomem *reg, u32 mask)static void airoha_phy_update_bits(void __iomem *reg, u32 mask, u32 val)#define airoha_phy_update_field(reg, mask, val) \do { \"mask is not constant" ); \while (0)#define airoha_phy_csr_2l_clear_bits(pcie_phy, reg, mask) \#define airoha_phy_csr_2l_set_bits(pcie_phy, reg, mask) \#define airoha_phy_csr_2l_update_field(pcie_phy, reg, mask, val) \#define airoha_phy_pma0_clear_bits(pcie_phy, reg, mask) \#define airoha_phy_pma1_clear_bits(pcie_phy, reg, mask) \#define airoha_phy_pma0_set_bits(pcie_phy, reg, mask) \#define airoha_phy_pma1_set_bits(pcie_phy, reg, mask) \#define airoha_phy_pma0_update_field(pcie_phy, reg, mask, val) \#define airoha_phy_pma1_update_field(pcie_phy, reg, mask, val) \static void struct airoha_pcie_phy *pcie_phy,enum airoha_pcie_port_gen gen)int i;for (i = 0; i < LEQ_LEN_CTRL_MAX_VAL; i++) {if (val > fl_out_target)for (i = LEQ_LEN_CTRL_MAX_VAL; i >= 0; i--) {if (val < fl_out_target)for (i = 0; i < FREQ_LOCK_MAX_ATTEMPT; i++) {if (val & PCIE_RO_FBCK_LOCK)break ;/* turn off force mode and update band values */ if (gen == PCIE_PORT_GEN3) {else {static void struct airoha_pcie_phy *pcie_phy,enum airoha_pcie_port_gen gen)int i;for (i = 0; i < LEQ_LEN_CTRL_MAX_VAL; i++) {if (val > fl_out_target)for (i = LEQ_LEN_CTRL_MAX_VAL; i >= 0; i--) {if (val < fl_out_target)for (i = 0; i < FREQ_LOCK_MAX_ATTEMPT; i++) {if (val & PCIE_RO_FBCK_LOCK)break ;/* turn off force mode and update band values */ if (gen == PCIE_PORT_GEN3) {else {static void airoha_pcie_phy_init_default(struct airoha_pcie_phy *pcie_phy)static void airoha_pcie_phy_init_clk_out(struct airoha_pcie_phy *pcie_phy)static void airoha_pcie_phy_init_csr_2l(struct airoha_pcie_phy *pcie_phy)static void airoha_pcie_phy_init_rx(struct airoha_pcie_phy *pcie_phy)static void airoha_pcie_phy_init_jcpll(struct airoha_pcie_phy *pcie_phy)static void airoha_pcie_phy_txpll(struct airoha_pcie_phy *pcie_phy)static void airoha_pcie_phy_init_ssc_jcpll(struct airoha_pcie_phy *pcie_phy)static void struct airoha_pcie_phy *pcie_phy)static void struct airoha_pcie_phy *pcie_phy)static void airoha_pcie_phy_set_rxflow(struct airoha_pcie_phy *pcie_phy)static void airoha_pcie_phy_set_pr(struct airoha_pcie_phy *pcie_phy)static void airoha_pcie_phy_set_txflow(struct airoha_pcie_phy *pcie_phy)static void airoha_pcie_phy_set_rx_mode(struct airoha_pcie_phy *pcie_phy)static void airoha_pcie_phy_load_kflow(struct airoha_pcie_phy *pcie_phy)/** * airoha_pcie_phy_init() - Initialize the phy * @phy: the phy to be initialized * * Initialize the phy registers. * The hardware settings will be reset during suspend, it should be * reinitialized when the consumer calls phy_init() again on resume. static int airoha_pcie_phy_init(struct phy *phy)struct airoha_pcie_phy *pcie_phy = phy_get_drvdata(phy);/* Setup Tx-Rx detection time */ /* Setup Rx AEQ training time */ /* enable load FLL-K flow */ /* phase 1, no ssc for K TXPLL */ /* TX PLL settings */ /* SSC JCPLL setting */ /* Rx lan0 signal detect */ /* Rx lan1 signal detect */ /* RX FLOW */ /* TX FLOW */ /* RX mode setting */ /* Load K-Flow */ /* Wait for the PCIe PHY to complete initialization before returning */ return 0;static int airoha_pcie_phy_exit(struct phy *phy)struct airoha_pcie_phy *pcie_phy = phy_get_drvdata(phy);return 0;static const struct phy_ops airoha_pcie_phy_ops = {exit = airoha_pcie_phy_exit,static int airoha_pcie_phy_probe(struct platform_device *pdev)struct airoha_pcie_phy *pcie_phy;struct device *dev = &pdev->dev;struct phy_provider *provider;sizeof (*pcie_phy), GFP_KERNEL);if (!pcie_phy)return -ENOMEM;"csr-2l" );if (IS_ERR(pcie_phy->csr_2l))return dev_err_probe(dev, PTR_ERR(pcie_phy->csr_2l),"Failed to map phy-csr-2l base\n" );"pma0" );if (IS_ERR(pcie_phy->pma0))return dev_err_probe(dev, PTR_ERR(pcie_phy->pma0),"Failed to map phy-pma0 base\n" );"pma1" );if (IS_ERR(pcie_phy->pma1))return dev_err_probe(dev, PTR_ERR(pcie_phy->pma1),"Failed to map phy-pma1 base\n" );if (IS_ERR(pcie_phy->phy))return dev_err_probe(dev, PTR_ERR(pcie_phy->phy),"Failed to create PCIe phy\n" );"p0-xr-dtime" );if (IS_ERR(pcie_phy->p0_xr_dtime))return dev_err_probe(dev, PTR_ERR(pcie_phy->p0_xr_dtime),"Failed to map P0 Tx-Rx dtime base\n" );"p1-xr-dtime" );if (IS_ERR(pcie_phy->p1_xr_dtime))return dev_err_probe(dev, PTR_ERR(pcie_phy->p1_xr_dtime),"Failed to map P1 Tx-Rx dtime base\n" );"rx-aeq" );if (IS_ERR(pcie_phy->rx_aeq))return dev_err_probe(dev, PTR_ERR(pcie_phy->rx_aeq),"Failed to map Rx AEQ base\n" );if (IS_ERR(provider))return dev_err_probe(dev, PTR_ERR(provider),"PCIe phy probe failed\n" );return 0;static const struct of_device_id airoha_pcie_phy_of_match[] = {"airoha,en7581-pcie-phy" },/* sentinel */ } static struct platform_driver airoha_pcie_phy_driver = {"airoha-pcie-phy" ,"Airoha PCIe PHY driver" );"Lorenzo Bianconi " );"GPL" );
Messung V0.5 C=99 H=89 G=94
¤ Dauer der Verarbeitung: 0.3 Sekunden
(vorverarbeitet)
¤ *© Formatika GbR, Deutschland
