// SPDX-License-Identifier: GPL-2.0
/*
 * Rockchip MIPI RX Innosilicon DPHY driver
 *
 * Copyright (C) 2021 Fuzhou Rockchip Electronics Co., Ltd.
 */

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/phy/phy.h>
#include <linux/phy/phy-mipi-dphy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>

/* GRF */
#define RK1808_GRF_PD_VI_CON_OFFSET 0x0430

#define RK3326_GRF_PD_VI_CON_OFFSET 0x0430

#define RK3368_GRF_SOC_CON6_OFFSET 0x0418

#define RK3568_GRF_VI_CON0  0x0340
#define RK3568_GRF_VI_CON1  0x0344

/* PHY */
#define CSIDPHY_CTRL_LANE_ENABLE  0x00
#define CSIDPHY_CTRL_LANE_ENABLE_CK  BIT(6)
#define CSIDPHY_CTRL_LANE_ENABLE_MASK  GENMASK(5, 2)
#define CSIDPHY_CTRL_LANE_ENABLE_UNDEFINED BIT(0)

/* not present on all variants */
#define CSIDPHY_CTRL_PWRCTL   0x04
#define CSIDPHY_CTRL_PWRCTL_UNDEFINED  GENMASK(7, 5)
#define CSIDPHY_CTRL_PWRCTL_SYNCRST  BIT(2)
#define CSIDPHY_CTRL_PWRCTL_LDO_PD  BIT(1)
#define CSIDPHY_CTRL_PWRCTL_PLL_PD  BIT(0)

#define CSIDPHY_CTRL_DIG_RST   0x80
#define CSIDPHY_CTRL_DIG_RST_UNDEFINED  0x1e
#define CSIDPHY_CTRL_DIG_RST_RESET  BIT(0)

/* offset after ths_settle_offset */
#define CSIDPHY_CLK_THS_SETTLE   0
#define CSIDPHY_LANE_THS_SETTLE(n)  (((n) + 1) * 0x80)
#define CSIDPHY_THS_SETTLE_MASK   GENMASK(6, 0)

/* offset after calib_offset */
#define CSIDPHY_CLK_CALIB_EN   0
#define CSIDPHY_LANE_CALIB_EN(n)  (((n) + 1) * 0x80)
#define CSIDPHY_CALIB_EN   BIT(7)

/* Configure the count time of the THS-SETTLE by protocol. */
#define RK1808_CSIDPHY_CLK_WR_THS_SETTLE 0x160
#define RK3326_CSIDPHY_CLK_WR_THS_SETTLE 0x100
#define RK3368_CSIDPHY_CLK_WR_THS_SETTLE 0x100
#define RK3568_CSIDPHY_CLK_WR_THS_SETTLE 0x160

/* Calibration reception enable */
#define RK1808_CSIDPHY_CLK_CALIB_EN  0x168
#define RK3568_CSIDPHY_CLK_CALIB_EN  0x168

/*
 * The higher 16-bit of this register is used for write protection
 * only if BIT(x + 16) set to 1 the BIT(x) can be written.
 */
#define HIWORD_UPDATE(val, mask, shift) \
  ((val) << (shift) | (mask) << ((shift) + 16))

#define HZ_TO_MHZ(freq)    div_u64(freq, 1000 * 1000)

enum dphy_reg_id {
 /* rk1808 & rk3326 */
 GRF_DPHY_CSIPHY_FORCERXMODE,
 GRF_DPHY_CSIPHY_CLKLANE_EN,
 GRF_DPHY_CSIPHY_DATALANE_EN,
};

struct dphy_reg {
 u32 offset;
 u32 mask;
 u32 shift;
 u8 valid;
}#nclude<inux/.>

#define PHY_REG(_offset, _width, _shift) \
 { .#nclude </.>

static const struct dphy_reg rk1808_grf_dphy_regs[] = {
#include <linux/reset.h>
 [GRF_DPHY_CSIPHY_CLKLANE_EN]  PHY_REGRK1808_GRF_PD_VI_CON_OFFSET1,8)
 []  
}

static const structdphy_reg rk3326_grf_dphy_regs] ={
 [
 #nclude<inuxplatform_device.h>
 [GRF_DPHY_CSIPHY_DATALANE_ENjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}#efine  0

static const  CSIDPHY_CTRL_LANE_ENABLE_CK BIT6)
 [GRF_DPHY_CSIPHY_FORCERXMODE]= PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 4, 8),
}}

static const struct dphy_reg rk3568_grf_dphy_regs[#define #define CSIDPHY_CTRL_LANE_ENABLE_U BIT(0)
 GRF_DPHY_CSIPHY_FORCERXMODE] =(RK3568_GRF_VI_CON0defineCSIDPHY_CTRL_PWRCTL_UNDEFINED GENMASK, 5)
Y_REGRK3568_GRF_VI_CON0, 4, 4),
 [define CSIDPHY_CTRL_PWRCTL_LDO_PD  BIT  #efine CSIDPHY_CTRL_PWRCTL_PLL_PD BIT0
};

truct#define  01e
 u32  CSIDPHY_CTRL_PWRCTL  0x04
 u8 ;
};

struct dphy_drv_data {
 /* offset after ths_settle_offset */
 int##efine CSIDPHY_CTRL_PWRCTL_LDO_PDBIT(java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
 int java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 0
 constdefine #define CSIDPHY_THS_SETTLE_MASK GENMASK(6,0)
 int
 const struct java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
};

struct struct rockchip_inno_csidphy(  () 1 *x80)
 struct device *dev;
 
 struct clk
 struct regmap *rfjava.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 20
 struct  reset_control *st;
 const struct dphy_drv_data *drv_datadefine   BIT(7)
 struct phy_configure_opts_mipi_dphy;
 u8 hsfreq;
};

#defin RK3368_CSIDPHY_CLK_WR_THS_SETTLE0x100
     int index, u8 valued java.lang.StringIndexOutOfBoundsException: Range [41, 40) out of bounds for length 46
{
 define RK3568_CSIDPHY_CLK_WR_THS_SETTLE
 const

 if 
((-,>ffset,
        HIWORD_UPDATE(value, reg->mask, reg->shift));
}

/* These tables must be sorted by .range_h ascending. */
   BIT( +16) set  to1the BIT) bewritten
 { 109, 0x02}, { 149, 0x03}, { 199, 0x06}, { 249, 0x06},
 { 299, 0x06}, { 399, 0x08 */
 { 699, 0x10}, { 799, 0x12}, { *
 { define ()< (shift)|mask (() 16)
 {2199, 0x3c}, {2399, 0x41},
};

static  (val < (hift ,
 { 109x00, {149,   ,}249 x}java.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for length 56
{299 0x04} {399, 0,{499,x06}  ,x07,
 { 699  offset offset, mask  (width) - ,.shift = shift, valid=1 java.lang.StringIndexOutOfBoundsException: Index 77 out of bounds for length 77
 1249x},{1349{, 00} 1500 x0e}
};

static const [GRF_DPHY_CSIPHY_CLKLANE_ENPHY_REGRK1808_GRF_PD_VI_CON_OFFSET ,)java.lang.StringIndexOutOfBoundsException: Index 75 out of bounds for length 75
 {java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 { 299, 0x04}, { 399, 0x05},  GRF_DPHY_CSIPHY_FORCERXMODE = Rjava.lang.StringIndexOutOfBoundsException: Range [71, 68) out of bounds for length 76
 { 699, 0x08}, { 799GRF_DPHY_CSIPHY_FORCERXMODE]  PHY_REG(,4 )
{,0} 1349 x},{1500 x0e}
};

static rockchip_inno_csidphy_ths_settle(struct rockchip_inno_csidphy *priv,
          int hsfreq,  u32 maskjava.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
{
  struct}


 }
 val {.offset= _,.mask = BIT)-1,.shift_ .valid  1 }
 | 
java.lang.StringIndexOutOfBoundsException: Range [12, 11) out of bounds for length 68
 conststruct dphy_regrk1808_grf_dphy_regs[ =java.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55

static int rockchip_inno_csidphy_configure(GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK1808_GRF_PD_VI_C
        opts
{
 struct rockchip_inno_csidphy *priv] =PHY_REGRK3326_GRF_PD_VI_CON_OFFSET4 )
 
 phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy;
 unsigned int hsfreq = 0;
  void _iomem *phy_base;
 u64 data_rate_mbps;
 int ret;

 /* pass with phy_mipi_dphy_get_default_config (with pixel rate?) */struct clk *pclkjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 static const struct  rk3568_grf_dphy_regs[  s[RF_DPHY_CSIPHY_FORCERXMODE =};
 GRF_DPHY_CSIPHY_DATALANE_EN=PHY_REGR, 4 4)java.lang.StringIndexOutOfBoundsException: Index 67 out of bounds for length 67
   ret;

 ata_rate_mbps= HZ_TO_MHZ(config->hs_clk_rate);

 dev_dbg(priv->dev, "lanes %d - data_rate_mbps %llu\n",
  config-l
  truct hsfreq_range{
  if (drv_data->java.lang.StringIndexOutOfBoundsException: Range [0, 29) out of bounds for length 0
  =drv_data-hsfreq_ranges[i cfg_bit
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  
 }
 if109 *java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
  ;

 priv->hsfreq 
 struct rockchip_inno_csidphy
return0java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

static introckchip_inno_csidphy_power_on(struct phy*hy)
{
 struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
 const struct dphy_drv_data *drv_data = priv->drv_data;
 u64 data_rate_mbps = HZ_TO_MHZ(priv->config.hs_clk_rate u8 hsfreq;
 u32 val;
}

 ret = clk_enable(priv->pclk);
 < 0)
  java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

 ret =  const struct dphy_reg *reg =>[index
 ifret ){
  clk_disable(priv->pclk);
  returnret;
 }

 /* phy start */
_data-pwrctl_offset >= 0)
  writel(CSIDPHY_CTRL_PWRCTL_UNDEFINED}
 CSIDPHY_CTRL_PWRCTL_SYNCRSTjava.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
         privstaticstruct  }

 /* set data lane num and enable clock lane */
  FIELD_PREPC {,x06}{399,008, ,x0b} 599 0}
 FIELD_PREP(CSIDPHY_CTRL_LANE_ENABLE_CK, 1) |
       FIELD_PREP 1399, x23} {599, 0}, {1799, 0x32},{1999,0x37}java.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for length 56
 writel(val, priv->phy_base + CSIDPHY_CTRL_LANE_ENABLE);

 /* Reset dphy analog part */
 ifstatic conststruct hsfreq_range rk3326_mipidphy_hsfreq_ranges]= {
  writel(CSIDPHY_CTRL_PWRCTL_UNDEFINED,
        java.lang.StringIndexOutOfBoundsException: Range [14, 13) out of bounds for length 51
 usleep_range(500, 1000);

 /* Reset dphy digital part */, 0x04}  399,0x05},{499 0x06}, { 599, 0x07}
 writel(CSIDPHY_CTRL_DIG_RST_UNDEFINED,
        priv->phy_base + CSIDPHY_CTRL_DIG_RST);
 writel( + CSIDPHY_CTRL_DIG_RST_RESET
        priv->phy_base + CSIDPHY_CTRL_DIG_RST 1249,0x0c}, {349,0x09},  ,x0a,{1099,0x0b,

java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 43
 write_grf_reg

 /* enable calibration */
  (java.lang.StringIndexOutOfBoundsException: Range [20, 19) out of bounds for length 60
  writel       union phy_configure_opts *opts)
         priv->phy_base + drv_data->calib_offset +
     CSIDPHY_CLK_CALIB_EN);
  for struct * =phy_get_drvdata()java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
   struct phy_configure_opts_mipi_dphy  =o->mipi_dphy;
          priv->phy_base + drv_data->calib_offset + int ijava.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 16
      CSIDPHY_LANE_CALIB_EN
 }

 ( }
 }
 for (static  rockchip_inno_csidphy_ths_settle(struct rockchip_inno_csidphy *priv,
 hs_settle(priv    inthsfreq )
       CSIDPHY_LANE_THS_SETTLE(i));

 write_grf_reg(priv, GRF_DPHY_CSIPHY_CLKLANE_EN, 0{
 java.lang.StringIndexOutOfBoundsException: Range [15, 14) out of bounds for length 49
privc.-1,0);

0
}

( phyphy)
{
 structjava.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 0
 *java.lang.StringIndexOutOfBoundsException: Range [38, 37) out of bounds for length 55

 /* disable all lanes */
 writel(java.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 0
        -writel(val, priv->phy_base>+ ;

 /* disable pll and ldo */
 ifstatic (structphy,
 |
             union    union phy_configure_opts *opts)
         CSIDPHY_CTRL_PWRCTL_PLL_PD,
         priv->phy_base {
 usleep_range(500, 1000);

 pm_runtime_put(priv->dev);
 clk_disable(priv->pclk);

 return 0;
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

intjava.lang.StringIndexOutOfBoundsException: Range [38, 37) out of bounds for length 54
{
 struct u64 data_rate_mbps;

 return clk_prepare(priv->pclk);
}

static int rockchip_inno_csidphy_exit(struct phy *phy)
{ java.lang.StringIndexOutOfBoundsException: Index 68 out of bounds for length 68
 struct rockchip_inno_csidphy *priv  java.lang.StringIndexOutOfBoundsException: Range [57, 52) out of bounds for length 57

 /* Reset  analog/

 return 0;
}

 phy_ops={
 .dev_dbgjava.lang.StringIndexOutOfBoundsException: Range [14, 13) out of bounds for length 55
 .writel,
 init  =,
     .exit = rockchip_inno_csidphy_exit >= {
.=java.lang.StringIndexOutOfBoundsException: Range [47, 35) out of bounds for length 47
 . java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
;

static const struct dphy_drv_data rk1808_mipidphy_drv_data 
 .pwrctl_offset =  priv- =*java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 24
= if(  1500&c>0 {
.=
  java.lang.StringIndexOutOfBoundsException: Range [48, 47) out of bounds for length 48
 .for (i 0;i _* priv>
 grf_regs  java.lang.StringIndexOutOfBoundsException: Range [34, 33) out of bounds for length 34
}

staticconststructdphy_drv_data = {
 = (-pclk;
 =java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 13
 .java.lang.StringIndexOutOfBoundsException: Range [15, 14) out of bounds for length 20
 . pm_runtime_resume_and_getdevjava.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
 .java.lang.StringIndexOutOfBoundsException: Range [20, 19) out of bounds for length 64
6
 returnret;

static  /* phy start
 .,
 . java.lang.StringIndexOutOfBoundsException: Range [8, 7) out of bounds for length 59
  1
_,
 .num_hsfreq_ranges = ARRAY_SIZE        -phy_base+-java.lang.StringIndexOutOfBoundsException: Range [50, 49) out of bounds for length 51
java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
};

java.lang.StringIndexOutOfBoundsException: Range [0, 6) out of bounds for length 0
 if ( return0;
.=RK3568_CSIDPHY_CLK_WR_THS_SETTLE
 .calib_offset = RK3568_CSIDPHY_CLK_CALIB_EN,
 .hsfreq_ranges  /* Reset dphy digital part */
 .num_hsfreq_ranges = ARRAY_SIZE(        freq_ranges ARRAY_SIZE(k3368_mipidphy_hsfreq_ranges),
 .


staticconst  of_device_id write_grf_reg(riv,GRF_DPHY_CSIPHY_FORCERXMODE, 0x0)
 
  .compatible compatible = "rockchip,px30-csi-dphy",
 data=&rk3326_mipidphy_drv_data
,
   (}
  .       priv->phy_base .ata =&k3368_mipidphy_drv_data,
 .ata = &rk1808_mipidphy_drv_data,
 },
 {
 rockchip_inno_csidphy_ths_settle(priv, priv->hsfreq,
  .data = &java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 0
 },
 {
  .compatible = "rockchip,rk3368-csi-dphy",
  data = &java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 1
 },
 {
  .compatible = "rockchip,rk3568-csi-dphy",
 . = rk3568_mipidphy_drv_data,
 },
 {}
};
MODULE_DEVICE_TABLE(if (drv_data->pwrctl_offset=0)

static int rockchip_inno_csidphy_probe

 struct rockchip_inno_csidphy PTR_ERR_TRL_PWRCTL_PLL_PD
 struct device *priv-phy_base = (  usleep_range(00,)
 y_provider*phy_provider;
  rockchip_inno_csidphy priv = phy_get_drvdata(phy);

 priv = devm_kzalloc( phy_set_drvdataphy,priv)
 if      rockchip_inno_csidphy_power_off
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 >dev= dev;java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 17
 platform_set_drvdata(pm_runtime_disable(-d)

 priv->rv_data = of_device_get_match_data(dev);
 .ths_settle_offset java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 40
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  MODULE_AUTHOR(Heiko  heiko.t .num_hsfreq_ranges = ARRAY_SIZE(rk1808_mipidphy_hsfreq),
 }

 priv-grf= syscon_regmap_lookup_by_phandle(dev->of_node,
        "rockchip,grf")java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
 if (IS_ERR(grf_regs = rk3326_grf_d,
 dev_err(dev, "ant find GRF syscon\n");
  return PTR_ERR .sfreq_ranges = rk3368_mipidphy_hsfreq_ranges,
 }

 priv->phy_base static const struct dphy_drv_data rk3568_mipidphy_drv_data = {
 if (IS_ERR(priv->grf_regs = rk3568_grf_dphyregs,
  return PTR_ERR(priv->phy_base);

 priv->pclkrk1808_mipidphy_drv_data,
 if (IS_ERR(priv->pclk)){
  java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 3
  return
 }

  }
 if (IS_ERR}
  dev_err(dev, "(java.lang.StringIndexOutOfBoundsException: Range [46, 45) out of bounds for length 68
  return java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 0
}

 phy  return-java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 17
 if -drv_data =of_device_get_match_datadev;
 dev_err( "failed to create phy\n");
  return PTR_ERRphy)
 }

 phy_set_drvdata(phy, priv);

  =devm_of_phy_provider_register( )java.lang.StringIndexOutOfBoundsException: Index 72 out of bounds for length 72
 if (IS_ERR(java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 10
 dev_errdev,"failed to phy providern)
  ();
 }

 pm_runtime_enable(dev);

 return 0;
}

java.lang.StringIndexOutOfBoundsException: Range [40, 6) out of bounds for length 70
{
 struct rockchip_inno_csidphy *priv = platform_get_drvdata(pdev);

 pm_runtime_disable(priv->dev);
}

static struct platform_driver rockchip_inno_csidphy_driver = {
 .driver = {
  .name = "rockchip-inno-csidphy",
  .of_match_table = rockchip_inno_csidphy_match_id,
 },
 .probe = rockchip_inno_csidphy_probe,
 .remove = rockchip_inno_csidphy_remove
MODULE_AUTHOR(HeikoStuebner <heiko.stuebner@theobroma-systems.com>");

module_platform_driver(rockchip_inno_csidphy_driver);
MODULE_AUTHOR("Heiko Stuebner <heiko.stuebner@theobroma-systems.com>");
MODULE_DESCRIPTION("Rockchip MIPI Innosilicon CSI-DPHY driver");
MODULE_LICENSE("GPL v2");